2 * Marvell MMC/SD/SDIO driver
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/mbus.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21 #include <linux/irq.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <linux/of_gpio.h>
25 #include <linux/of_irq.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/pinctrl/consumer.h>
30 #include <asm/sizes.h>
31 #include <asm/unaligned.h>
32 #include <linux/platform_data/mmc-mvsdio.h>
36 #define DRIVER_NAME "mvsdio"
43 struct mmc_request
*mrq
;
45 unsigned int xfer_mode
;
48 unsigned int pio_size
;
50 unsigned int sg_frags
;
51 unsigned int ns_per_clk
;
53 unsigned int base_clock
;
54 struct timer_list timer
;
60 #define mvsd_write(offs, val) writel(val, iobase + (offs))
61 #define mvsd_read(offs) readl(iobase + (offs))
63 static int mvsd_setup_data(struct mvsd_host
*host
, struct mmc_data
*data
)
65 void __iomem
*iobase
= host
->base
;
70 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
71 * register is sometimes not set before a while when some
72 * "unusual" data block sizes are used (such as with the SWITCH
73 * command), even despite the fact that the XFER_DONE interrupt
74 * was raised. And if another data transfer starts before
75 * this bit comes to good sense (which eventually happens by
76 * itself) then the new transfer simply fails with a timeout.
78 if (!(mvsd_read(MVSD_HW_STATE
) & (1 << 13))) {
79 unsigned long t
= jiffies
+ HZ
;
80 unsigned int hw_state
, count
= 0;
82 hw_state
= mvsd_read(MVSD_HW_STATE
);
83 if (time_after(jiffies
, t
)) {
84 dev_warn(host
->dev
, "FIFO_EMPTY bit missing\n");
88 } while (!(hw_state
& (1 << 13)));
89 dev_dbg(host
->dev
, "*** wait for FIFO_EMPTY bit "
90 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
91 hw_state
, count
, jiffies
- (t
- HZ
));
94 /* If timeout=0 then maximum timeout index is used. */
95 tmout
= DIV_ROUND_UP(data
->timeout_ns
, host
->ns_per_clk
);
96 tmout
+= data
->timeout_clks
;
97 tmout_index
= fls(tmout
- 1) - 12;
100 if (tmout_index
> MVSD_HOST_CTRL_TMOUT_MAX
)
101 tmout_index
= MVSD_HOST_CTRL_TMOUT_MAX
;
103 dev_dbg(host
->dev
, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
104 (data
->flags
& MMC_DATA_READ
) ? "read" : "write",
105 (u32
)sg_virt(data
->sg
), data
->blocks
, data
->blksz
,
108 host
->ctrl
&= ~MVSD_HOST_CTRL_TMOUT_MASK
;
109 host
->ctrl
|= MVSD_HOST_CTRL_TMOUT(tmout_index
);
110 mvsd_write(MVSD_HOST_CTRL
, host
->ctrl
);
111 mvsd_write(MVSD_BLK_COUNT
, data
->blocks
);
112 mvsd_write(MVSD_BLK_SIZE
, data
->blksz
);
114 if (nodma
|| (data
->blksz
| data
->sg
->offset
) & 3) {
116 * We cannot do DMA on a buffer which offset or size
117 * is not aligned on a 4-byte boundary.
119 host
->pio_size
= data
->blocks
* data
->blksz
;
120 host
->pio_ptr
= sg_virt(data
->sg
);
122 dev_dbg(host
->dev
, "fallback to PIO for data at 0x%p size %d\n",
123 host
->pio_ptr
, host
->pio_size
);
126 dma_addr_t phys_addr
;
127 int dma_dir
= (data
->flags
& MMC_DATA_READ
) ?
128 DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
129 host
->sg_frags
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
130 data
->sg_len
, dma_dir
);
131 phys_addr
= sg_dma_address(data
->sg
);
132 mvsd_write(MVSD_SYS_ADDR_LOW
, (u32
)phys_addr
& 0xffff);
133 mvsd_write(MVSD_SYS_ADDR_HI
, (u32
)phys_addr
>> 16);
138 static void mvsd_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
140 struct mvsd_host
*host
= mmc_priv(mmc
);
141 void __iomem
*iobase
= host
->base
;
142 struct mmc_command
*cmd
= mrq
->cmd
;
143 u32 cmdreg
= 0, xfer
= 0, intr
= 0;
146 BUG_ON(host
->mrq
!= NULL
);
149 dev_dbg(host
->dev
, "cmd %d (hw state 0x%04x)\n",
150 cmd
->opcode
, mvsd_read(MVSD_HW_STATE
));
152 cmdreg
= MVSD_CMD_INDEX(cmd
->opcode
);
154 if (cmd
->flags
& MMC_RSP_BUSY
)
155 cmdreg
|= MVSD_CMD_RSP_48BUSY
;
156 else if (cmd
->flags
& MMC_RSP_136
)
157 cmdreg
|= MVSD_CMD_RSP_136
;
158 else if (cmd
->flags
& MMC_RSP_PRESENT
)
159 cmdreg
|= MVSD_CMD_RSP_48
;
161 cmdreg
|= MVSD_CMD_RSP_NONE
;
163 if (cmd
->flags
& MMC_RSP_CRC
)
164 cmdreg
|= MVSD_CMD_CHECK_CMDCRC
;
166 if (cmd
->flags
& MMC_RSP_OPCODE
)
167 cmdreg
|= MVSD_CMD_INDX_CHECK
;
169 if (cmd
->flags
& MMC_RSP_PRESENT
) {
170 cmdreg
|= MVSD_UNEXPECTED_RESP
;
171 intr
|= MVSD_NOR_UNEXP_RSP
;
175 struct mmc_data
*data
= mrq
->data
;
178 cmdreg
|= MVSD_CMD_DATA_PRESENT
| MVSD_CMD_CHECK_DATACRC16
;
179 xfer
|= MVSD_XFER_MODE_HW_WR_DATA_EN
;
180 if (data
->flags
& MMC_DATA_READ
)
181 xfer
|= MVSD_XFER_MODE_TO_HOST
;
183 pio
= mvsd_setup_data(host
, data
);
185 xfer
|= MVSD_XFER_MODE_PIO
;
186 /* PIO section of mvsd_irq has comments on those bits */
187 if (data
->flags
& MMC_DATA_WRITE
)
188 intr
|= MVSD_NOR_TX_AVAIL
;
189 else if (host
->pio_size
> 32)
190 intr
|= MVSD_NOR_RX_FIFO_8W
;
192 intr
|= MVSD_NOR_RX_READY
;
196 struct mmc_command
*stop
= data
->stop
;
199 mvsd_write(MVSD_AUTOCMD12_ARG_LOW
, stop
->arg
& 0xffff);
200 mvsd_write(MVSD_AUTOCMD12_ARG_HI
, stop
->arg
>> 16);
202 if (stop
->flags
& MMC_RSP_BUSY
)
203 cmd12reg
|= MVSD_AUTOCMD12_BUSY
;
204 if (stop
->flags
& MMC_RSP_OPCODE
)
205 cmd12reg
|= MVSD_AUTOCMD12_INDX_CHECK
;
206 cmd12reg
|= MVSD_AUTOCMD12_INDEX(stop
->opcode
);
207 mvsd_write(MVSD_AUTOCMD12_CMD
, cmd12reg
);
209 xfer
|= MVSD_XFER_MODE_AUTO_CMD12
;
210 intr
|= MVSD_NOR_AUTOCMD12_DONE
;
212 intr
|= MVSD_NOR_XFER_DONE
;
215 intr
|= MVSD_NOR_CMD_DONE
;
218 mvsd_write(MVSD_ARG_LOW
, cmd
->arg
& 0xffff);
219 mvsd_write(MVSD_ARG_HI
, cmd
->arg
>> 16);
221 spin_lock_irqsave(&host
->lock
, flags
);
223 host
->xfer_mode
&= MVSD_XFER_MODE_INT_CHK_EN
;
224 host
->xfer_mode
|= xfer
;
225 mvsd_write(MVSD_XFER_MODE
, host
->xfer_mode
);
227 mvsd_write(MVSD_NOR_INTR_STATUS
, ~MVSD_NOR_CARD_INT
);
228 mvsd_write(MVSD_ERR_INTR_STATUS
, 0xffff);
229 mvsd_write(MVSD_CMD
, cmdreg
);
231 host
->intr_en
&= MVSD_NOR_CARD_INT
;
232 host
->intr_en
|= intr
| MVSD_NOR_ERROR
;
233 mvsd_write(MVSD_NOR_INTR_EN
, host
->intr_en
);
234 mvsd_write(MVSD_ERR_INTR_EN
, 0xffff);
236 mod_timer(&host
->timer
, jiffies
+ 5 * HZ
);
238 spin_unlock_irqrestore(&host
->lock
, flags
);
241 static u32
mvsd_finish_cmd(struct mvsd_host
*host
, struct mmc_command
*cmd
,
244 void __iomem
*iobase
= host
->base
;
246 if (cmd
->flags
& MMC_RSP_136
) {
247 unsigned int response
[8], i
;
248 for (i
= 0; i
< 8; i
++)
249 response
[i
] = mvsd_read(MVSD_RSP(i
));
250 cmd
->resp
[0] = ((response
[0] & 0x03ff) << 22) |
251 ((response
[1] & 0xffff) << 6) |
252 ((response
[2] & 0xfc00) >> 10);
253 cmd
->resp
[1] = ((response
[2] & 0x03ff) << 22) |
254 ((response
[3] & 0xffff) << 6) |
255 ((response
[4] & 0xfc00) >> 10);
256 cmd
->resp
[2] = ((response
[4] & 0x03ff) << 22) |
257 ((response
[5] & 0xffff) << 6) |
258 ((response
[6] & 0xfc00) >> 10);
259 cmd
->resp
[3] = ((response
[6] & 0x03ff) << 22) |
260 ((response
[7] & 0x3fff) << 8);
261 } else if (cmd
->flags
& MMC_RSP_PRESENT
) {
262 unsigned int response
[3], i
;
263 for (i
= 0; i
< 3; i
++)
264 response
[i
] = mvsd_read(MVSD_RSP(i
));
265 cmd
->resp
[0] = ((response
[2] & 0x003f) << (8 - 8)) |
266 ((response
[1] & 0xffff) << (14 - 8)) |
267 ((response
[0] & 0x03ff) << (30 - 8));
268 cmd
->resp
[1] = ((response
[0] & 0xfc00) >> 10);
273 if (err_status
& MVSD_ERR_CMD_TIMEOUT
) {
274 cmd
->error
= -ETIMEDOUT
;
275 } else if (err_status
& (MVSD_ERR_CMD_CRC
| MVSD_ERR_CMD_ENDBIT
|
276 MVSD_ERR_CMD_INDEX
| MVSD_ERR_CMD_STARTBIT
)) {
277 cmd
->error
= -EILSEQ
;
279 err_status
&= ~(MVSD_ERR_CMD_TIMEOUT
| MVSD_ERR_CMD_CRC
|
280 MVSD_ERR_CMD_ENDBIT
| MVSD_ERR_CMD_INDEX
|
281 MVSD_ERR_CMD_STARTBIT
);
286 static u32
mvsd_finish_data(struct mvsd_host
*host
, struct mmc_data
*data
,
289 void __iomem
*iobase
= host
->base
;
292 host
->pio_ptr
= NULL
;
295 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, host
->sg_frags
,
296 (data
->flags
& MMC_DATA_READ
) ?
297 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
300 if (err_status
& MVSD_ERR_DATA_TIMEOUT
)
301 data
->error
= -ETIMEDOUT
;
302 else if (err_status
& (MVSD_ERR_DATA_CRC
| MVSD_ERR_DATA_ENDBIT
))
303 data
->error
= -EILSEQ
;
304 else if (err_status
& MVSD_ERR_XFER_SIZE
)
305 data
->error
= -EBADE
;
306 err_status
&= ~(MVSD_ERR_DATA_TIMEOUT
| MVSD_ERR_DATA_CRC
|
307 MVSD_ERR_DATA_ENDBIT
| MVSD_ERR_XFER_SIZE
);
309 dev_dbg(host
->dev
, "data done: blocks_left=%d, bytes_left=%d\n",
310 mvsd_read(MVSD_CURR_BLK_LEFT
), mvsd_read(MVSD_CURR_BYTE_LEFT
));
312 (data
->blocks
- mvsd_read(MVSD_CURR_BLK_LEFT
)) * data
->blksz
;
313 /* We can't be sure about the last block when errors are detected */
314 if (data
->bytes_xfered
&& data
->error
)
315 data
->bytes_xfered
-= data
->blksz
;
317 /* Handle Auto cmd 12 response */
319 unsigned int response
[3], i
;
320 for (i
= 0; i
< 3; i
++)
321 response
[i
] = mvsd_read(MVSD_AUTO_RSP(i
));
322 data
->stop
->resp
[0] = ((response
[2] & 0x003f) << (8 - 8)) |
323 ((response
[1] & 0xffff) << (14 - 8)) |
324 ((response
[0] & 0x03ff) << (30 - 8));
325 data
->stop
->resp
[1] = ((response
[0] & 0xfc00) >> 10);
326 data
->stop
->resp
[2] = 0;
327 data
->stop
->resp
[3] = 0;
329 if (err_status
& MVSD_ERR_AUTOCMD12
) {
330 u32 err_cmd12
= mvsd_read(MVSD_AUTOCMD12_ERR_STATUS
);
331 dev_dbg(host
->dev
, "c12err 0x%04x\n", err_cmd12
);
332 if (err_cmd12
& MVSD_AUTOCMD12_ERR_NOTEXE
)
333 data
->stop
->error
= -ENOEXEC
;
334 else if (err_cmd12
& MVSD_AUTOCMD12_ERR_TIMEOUT
)
335 data
->stop
->error
= -ETIMEDOUT
;
337 data
->stop
->error
= -EILSEQ
;
338 err_status
&= ~MVSD_ERR_AUTOCMD12
;
345 static irqreturn_t
mvsd_irq(int irq
, void *dev
)
347 struct mvsd_host
*host
= dev
;
348 void __iomem
*iobase
= host
->base
;
349 u32 intr_status
, intr_done_mask
;
352 intr_status
= mvsd_read(MVSD_NOR_INTR_STATUS
);
353 dev_dbg(host
->dev
, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
354 intr_status
, mvsd_read(MVSD_NOR_INTR_EN
),
355 mvsd_read(MVSD_HW_STATE
));
358 * It looks like, SDIO IP can issue one late, spurious irq
359 * although all irqs should be disabled. To work around this,
360 * bail out early, if we didn't expect any irqs to occur.
362 if (!mvsd_read(MVSD_NOR_INTR_EN
) && !mvsd_read(MVSD_ERR_INTR_EN
)) {
363 dev_dbg(host
->dev
, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n",
364 mvsd_read(MVSD_NOR_INTR_STATUS
),
365 mvsd_read(MVSD_NOR_INTR_EN
),
366 mvsd_read(MVSD_ERR_INTR_STATUS
),
367 mvsd_read(MVSD_ERR_INTR_EN
));
371 spin_lock(&host
->lock
);
373 /* PIO handling, if needed. Messy business... */
374 if (host
->pio_size
&&
375 (intr_status
& host
->intr_en
&
376 (MVSD_NOR_RX_READY
| MVSD_NOR_RX_FIFO_8W
))) {
377 u16
*p
= host
->pio_ptr
;
378 int s
= host
->pio_size
;
379 while (s
>= 32 && (intr_status
& MVSD_NOR_RX_FIFO_8W
)) {
380 readsw(iobase
+ MVSD_FIFO
, p
, 16);
383 intr_status
= mvsd_read(MVSD_NOR_INTR_STATUS
);
386 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
387 * doesn't appear to assert when there is exactly 32 bytes
388 * (8 words) left to fetch in a transfer.
391 while (s
>= 4 && (intr_status
& MVSD_NOR_RX_READY
)) {
392 put_unaligned(mvsd_read(MVSD_FIFO
), p
++);
393 put_unaligned(mvsd_read(MVSD_FIFO
), p
++);
395 intr_status
= mvsd_read(MVSD_NOR_INTR_STATUS
);
397 if (s
&& s
< 4 && (intr_status
& MVSD_NOR_RX_READY
)) {
399 val
[0] = mvsd_read(MVSD_FIFO
);
400 val
[1] = mvsd_read(MVSD_FIFO
);
401 memcpy(p
, ((void *)&val
) + 4 - s
, s
);
403 intr_status
= mvsd_read(MVSD_NOR_INTR_STATUS
);
407 ~(MVSD_NOR_RX_READY
| MVSD_NOR_RX_FIFO_8W
);
408 mvsd_write(MVSD_NOR_INTR_EN
, host
->intr_en
);
409 } else if (host
->intr_en
& MVSD_NOR_RX_FIFO_8W
) {
410 host
->intr_en
&= ~MVSD_NOR_RX_FIFO_8W
;
411 host
->intr_en
|= MVSD_NOR_RX_READY
;
412 mvsd_write(MVSD_NOR_INTR_EN
, host
->intr_en
);
415 dev_dbg(host
->dev
, "pio %d intr 0x%04x hw_state 0x%04x\n",
416 s
, intr_status
, mvsd_read(MVSD_HW_STATE
));
420 } else if (host
->pio_size
&&
421 (intr_status
& host
->intr_en
&
422 (MVSD_NOR_TX_AVAIL
| MVSD_NOR_TX_FIFO_8W
))) {
423 u16
*p
= host
->pio_ptr
;
424 int s
= host
->pio_size
;
426 * The TX_FIFO_8W bit is unreliable. When set, bursting
427 * 16 halfwords all at once in the FIFO drops data. Actually
428 * TX_AVAIL does go off after only one word is pushed even if
429 * TX_FIFO_8W remains set.
431 while (s
>= 4 && (intr_status
& MVSD_NOR_TX_AVAIL
)) {
432 mvsd_write(MVSD_FIFO
, get_unaligned(p
++));
433 mvsd_write(MVSD_FIFO
, get_unaligned(p
++));
435 intr_status
= mvsd_read(MVSD_NOR_INTR_STATUS
);
438 if (s
&& (intr_status
& MVSD_NOR_TX_AVAIL
)) {
440 memcpy(((void *)&val
) + 4 - s
, p
, s
);
441 mvsd_write(MVSD_FIFO
, val
[0]);
442 mvsd_write(MVSD_FIFO
, val
[1]);
444 intr_status
= mvsd_read(MVSD_NOR_INTR_STATUS
);
448 ~(MVSD_NOR_TX_AVAIL
| MVSD_NOR_TX_FIFO_8W
);
449 mvsd_write(MVSD_NOR_INTR_EN
, host
->intr_en
);
452 dev_dbg(host
->dev
, "pio %d intr 0x%04x hw_state 0x%04x\n",
453 s
, intr_status
, mvsd_read(MVSD_HW_STATE
));
459 mvsd_write(MVSD_NOR_INTR_STATUS
, intr_status
);
461 intr_done_mask
= MVSD_NOR_CARD_INT
| MVSD_NOR_RX_READY
|
462 MVSD_NOR_RX_FIFO_8W
| MVSD_NOR_TX_FIFO_8W
;
463 if (intr_status
& host
->intr_en
& ~intr_done_mask
) {
464 struct mmc_request
*mrq
= host
->mrq
;
465 struct mmc_command
*cmd
= mrq
->cmd
;
468 del_timer(&host
->timer
);
471 host
->intr_en
&= MVSD_NOR_CARD_INT
;
472 mvsd_write(MVSD_NOR_INTR_EN
, host
->intr_en
);
473 mvsd_write(MVSD_ERR_INTR_EN
, 0);
475 spin_unlock(&host
->lock
);
477 if (intr_status
& MVSD_NOR_UNEXP_RSP
) {
478 cmd
->error
= -EPROTO
;
479 } else if (intr_status
& MVSD_NOR_ERROR
) {
480 err_status
= mvsd_read(MVSD_ERR_INTR_STATUS
);
481 dev_dbg(host
->dev
, "err 0x%04x\n", err_status
);
484 err_status
= mvsd_finish_cmd(host
, cmd
, err_status
);
486 err_status
= mvsd_finish_data(host
, mrq
->data
, err_status
);
488 dev_err(host
->dev
, "unhandled error status %#04x\n",
490 cmd
->error
= -ENOMSG
;
493 mmc_request_done(host
->mmc
, mrq
);
496 spin_unlock(&host
->lock
);
498 if (intr_status
& MVSD_NOR_CARD_INT
) {
499 mmc_signal_sdio_irq(host
->mmc
);
506 dev_err(host
->dev
, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
507 intr_status
, host
->intr_en
, host
->pio_size
);
511 static void mvsd_timeout_timer(unsigned long data
)
513 struct mvsd_host
*host
= (struct mvsd_host
*)data
;
514 void __iomem
*iobase
= host
->base
;
515 struct mmc_request
*mrq
;
518 spin_lock_irqsave(&host
->lock
, flags
);
521 dev_err(host
->dev
, "Timeout waiting for hardware interrupt.\n");
522 dev_err(host
->dev
, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
523 mvsd_read(MVSD_HW_STATE
),
524 mvsd_read(MVSD_NOR_INTR_STATUS
),
525 mvsd_read(MVSD_NOR_INTR_EN
));
529 mvsd_write(MVSD_SW_RESET
, MVSD_SW_RESET_NOW
);
531 host
->xfer_mode
&= MVSD_XFER_MODE_INT_CHK_EN
;
532 mvsd_write(MVSD_XFER_MODE
, host
->xfer_mode
);
534 host
->intr_en
&= MVSD_NOR_CARD_INT
;
535 mvsd_write(MVSD_NOR_INTR_EN
, host
->intr_en
);
536 mvsd_write(MVSD_ERR_INTR_EN
, 0);
537 mvsd_write(MVSD_ERR_INTR_STATUS
, 0xffff);
539 mrq
->cmd
->error
= -ETIMEDOUT
;
540 mvsd_finish_cmd(host
, mrq
->cmd
, 0);
542 mrq
->data
->error
= -ETIMEDOUT
;
543 mvsd_finish_data(host
, mrq
->data
, 0);
546 spin_unlock_irqrestore(&host
->lock
, flags
);
549 mmc_request_done(host
->mmc
, mrq
);
552 static void mvsd_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
554 struct mvsd_host
*host
= mmc_priv(mmc
);
555 void __iomem
*iobase
= host
->base
;
558 spin_lock_irqsave(&host
->lock
, flags
);
560 host
->xfer_mode
|= MVSD_XFER_MODE_INT_CHK_EN
;
561 host
->intr_en
|= MVSD_NOR_CARD_INT
;
563 host
->xfer_mode
&= ~MVSD_XFER_MODE_INT_CHK_EN
;
564 host
->intr_en
&= ~MVSD_NOR_CARD_INT
;
566 mvsd_write(MVSD_XFER_MODE
, host
->xfer_mode
);
567 mvsd_write(MVSD_NOR_INTR_EN
, host
->intr_en
);
568 spin_unlock_irqrestore(&host
->lock
, flags
);
571 static void mvsd_power_up(struct mvsd_host
*host
)
573 void __iomem
*iobase
= host
->base
;
574 dev_dbg(host
->dev
, "power up\n");
575 mvsd_write(MVSD_NOR_INTR_EN
, 0);
576 mvsd_write(MVSD_ERR_INTR_EN
, 0);
577 mvsd_write(MVSD_SW_RESET
, MVSD_SW_RESET_NOW
);
578 mvsd_write(MVSD_XFER_MODE
, 0);
579 mvsd_write(MVSD_NOR_STATUS_EN
, 0xffff);
580 mvsd_write(MVSD_ERR_STATUS_EN
, 0xffff);
581 mvsd_write(MVSD_NOR_INTR_STATUS
, 0xffff);
582 mvsd_write(MVSD_ERR_INTR_STATUS
, 0xffff);
585 static void mvsd_power_down(struct mvsd_host
*host
)
587 void __iomem
*iobase
= host
->base
;
588 dev_dbg(host
->dev
, "power down\n");
589 mvsd_write(MVSD_NOR_INTR_EN
, 0);
590 mvsd_write(MVSD_ERR_INTR_EN
, 0);
591 mvsd_write(MVSD_SW_RESET
, MVSD_SW_RESET_NOW
);
592 mvsd_write(MVSD_XFER_MODE
, MVSD_XFER_MODE_STOP_CLK
);
593 mvsd_write(MVSD_NOR_STATUS_EN
, 0);
594 mvsd_write(MVSD_ERR_STATUS_EN
, 0);
595 mvsd_write(MVSD_NOR_INTR_STATUS
, 0xffff);
596 mvsd_write(MVSD_ERR_INTR_STATUS
, 0xffff);
599 static void mvsd_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
601 struct mvsd_host
*host
= mmc_priv(mmc
);
602 void __iomem
*iobase
= host
->base
;
605 if (ios
->power_mode
== MMC_POWER_UP
)
608 if (ios
->clock
== 0) {
609 mvsd_write(MVSD_XFER_MODE
, MVSD_XFER_MODE_STOP_CLK
);
610 mvsd_write(MVSD_CLK_DIV
, MVSD_BASE_DIV_MAX
);
612 dev_dbg(host
->dev
, "clock off\n");
613 } else if (ios
->clock
!= host
->clock
) {
614 u32 m
= DIV_ROUND_UP(host
->base_clock
, ios
->clock
) - 1;
615 if (m
> MVSD_BASE_DIV_MAX
)
616 m
= MVSD_BASE_DIV_MAX
;
617 mvsd_write(MVSD_CLK_DIV
, m
);
618 host
->clock
= ios
->clock
;
619 host
->ns_per_clk
= 1000000000 / (host
->base_clock
/ (m
+1));
620 dev_dbg(host
->dev
, "clock=%d (%d), div=0x%04x\n",
621 ios
->clock
, host
->base_clock
/ (m
+1), m
);
624 /* default transfer mode */
625 ctrl_reg
|= MVSD_HOST_CTRL_BIG_ENDIAN
;
626 ctrl_reg
&= ~MVSD_HOST_CTRL_LSB_FIRST
;
628 /* default to maximum timeout */
629 ctrl_reg
|= MVSD_HOST_CTRL_TMOUT_MASK
;
630 ctrl_reg
|= MVSD_HOST_CTRL_TMOUT_EN
;
632 if (ios
->bus_mode
== MMC_BUSMODE_PUSHPULL
)
633 ctrl_reg
|= MVSD_HOST_CTRL_PUSH_PULL_EN
;
635 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
636 ctrl_reg
|= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS
;
639 * The HI_SPEED_EN bit is causing trouble with many (but not all)
640 * high speed SD, SDHC and SDIO cards. Not enabling that bit
641 * makes all cards work. So let's just ignore that bit for now
642 * and revisit this issue if problems for not enabling this bit
646 if (ios
->timing
== MMC_TIMING_MMC_HS
||
647 ios
->timing
== MMC_TIMING_SD_HS
)
648 ctrl_reg
|= MVSD_HOST_CTRL_HI_SPEED_EN
;
651 host
->ctrl
= ctrl_reg
;
652 mvsd_write(MVSD_HOST_CTRL
, ctrl_reg
);
653 dev_dbg(host
->dev
, "ctrl 0x%04x: %s %s %s\n", ctrl_reg
,
654 (ctrl_reg
& MVSD_HOST_CTRL_PUSH_PULL_EN
) ?
655 "push-pull" : "open-drain",
656 (ctrl_reg
& MVSD_HOST_CTRL_DATA_WIDTH_4_BITS
) ?
657 "4bit-width" : "1bit-width",
658 (ctrl_reg
& MVSD_HOST_CTRL_HI_SPEED_EN
) ?
661 if (ios
->power_mode
== MMC_POWER_OFF
)
662 mvsd_power_down(host
);
665 static const struct mmc_host_ops mvsd_ops
= {
666 .request
= mvsd_request
,
667 .get_ro
= mmc_gpio_get_ro
,
668 .set_ios
= mvsd_set_ios
,
669 .enable_sdio_irq
= mvsd_enable_sdio_irq
,
673 mv_conf_mbus_windows(struct mvsd_host
*host
,
674 const struct mbus_dram_target_info
*dram
)
676 void __iomem
*iobase
= host
->base
;
679 for (i
= 0; i
< 4; i
++) {
680 writel(0, iobase
+ MVSD_WINDOW_CTRL(i
));
681 writel(0, iobase
+ MVSD_WINDOW_BASE(i
));
684 for (i
= 0; i
< dram
->num_cs
; i
++) {
685 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
686 writel(((cs
->size
- 1) & 0xffff0000) |
687 (cs
->mbus_attr
<< 8) |
688 (dram
->mbus_dram_target_id
<< 4) | 1,
689 iobase
+ MVSD_WINDOW_CTRL(i
));
690 writel(cs
->base
, iobase
+ MVSD_WINDOW_BASE(i
));
694 static int mvsd_probe(struct platform_device
*pdev
)
696 struct device_node
*np
= pdev
->dev
.of_node
;
697 struct mmc_host
*mmc
= NULL
;
698 struct mvsd_host
*host
= NULL
;
699 const struct mbus_dram_target_info
*dram
;
702 struct pinctrl
*pinctrl
;
704 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
705 irq
= platform_get_irq(pdev
, 0);
709 mmc
= mmc_alloc_host(sizeof(struct mvsd_host
), &pdev
->dev
);
715 host
= mmc_priv(mmc
);
717 host
->dev
= &pdev
->dev
;
719 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
721 dev_warn(&pdev
->dev
, "no pins associated\n");
724 * Some non-DT platforms do not pass a clock, and the clock
725 * frequency is passed through platform_data. On DT platforms,
726 * a clock must always be passed, even if there is no gatable
727 * clock associated to the SDIO interface (it can simply be a
730 host
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
731 if (!IS_ERR(host
->clk
))
732 clk_prepare_enable(host
->clk
);
734 mmc
->ops
= &mvsd_ops
;
736 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
738 mmc
->f_min
= DIV_ROUND_UP(host
->base_clock
, MVSD_BASE_DIV_MAX
);
739 mmc
->f_max
= MVSD_CLOCKRATE_MAX
;
741 mmc
->max_blk_size
= 2048;
742 mmc
->max_blk_count
= 65535;
745 mmc
->max_seg_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
746 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
749 if (IS_ERR(host
->clk
)) {
750 dev_err(&pdev
->dev
, "DT platforms must have a clock associated\n");
755 host
->base_clock
= clk_get_rate(host
->clk
) / 2;
756 ret
= mmc_of_parse(mmc
);
760 const struct mvsdio_platform_data
*mvsd_data
;
762 mvsd_data
= pdev
->dev
.platform_data
;
767 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_SDIO_IRQ
|
768 MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
769 host
->base_clock
= mvsd_data
->clock
/ 2;
770 /* GPIO 0 regarded as invalid for backward compatibility */
771 if (mvsd_data
->gpio_card_detect
&&
772 gpio_is_valid(mvsd_data
->gpio_card_detect
)) {
773 ret
= mmc_gpio_request_cd(mmc
,
774 mvsd_data
->gpio_card_detect
,
779 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
782 if (mvsd_data
->gpio_write_protect
&&
783 gpio_is_valid(mvsd_data
->gpio_write_protect
))
784 mmc_gpio_request_ro(mmc
, mvsd_data
->gpio_write_protect
);
788 mmc
->f_max
= maxfreq
;
790 spin_lock_init(&host
->lock
);
792 host
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
793 if (IS_ERR(host
->base
)) {
794 ret
= PTR_ERR(host
->base
);
798 /* (Re-)program MBUS remapping windows if we are asked to. */
799 dram
= mv_mbus_dram_info();
801 mv_conf_mbus_windows(host
, dram
);
803 mvsd_power_down(host
);
805 ret
= devm_request_irq(&pdev
->dev
, irq
, mvsd_irq
, 0, DRIVER_NAME
, host
);
807 dev_err(&pdev
->dev
, "cannot assign irq %d\n", irq
);
811 setup_timer(&host
->timer
, mvsd_timeout_timer
, (unsigned long)host
);
812 platform_set_drvdata(pdev
, mmc
);
813 ret
= mmc_add_host(mmc
);
817 if (!(mmc
->caps
& MMC_CAP_NEEDS_POLL
))
818 dev_dbg(&pdev
->dev
, "using GPIO for card detection\n");
820 dev_dbg(&pdev
->dev
, "lacking card detect (fall back to polling)\n");
826 mmc_gpio_free_cd(mmc
);
827 mmc_gpio_free_ro(mmc
);
828 if (!IS_ERR(host
->clk
))
829 clk_disable_unprepare(host
->clk
);
836 static int mvsd_remove(struct platform_device
*pdev
)
838 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
840 struct mvsd_host
*host
= mmc_priv(mmc
);
842 mmc_gpio_free_cd(mmc
);
843 mmc_gpio_free_ro(mmc
);
844 mmc_remove_host(mmc
);
845 del_timer_sync(&host
->timer
);
846 mvsd_power_down(host
);
848 if (!IS_ERR(host
->clk
))
849 clk_disable_unprepare(host
->clk
);
855 static const struct of_device_id mvsdio_dt_ids
[] = {
856 { .compatible
= "marvell,orion-sdio" },
859 MODULE_DEVICE_TABLE(of
, mvsdio_dt_ids
);
861 static struct platform_driver mvsd_driver
= {
863 .remove
= mvsd_remove
,
866 .of_match_table
= mvsdio_dt_ids
,
870 module_platform_driver(mvsd_driver
);
872 /* maximum card clock frequency (default 50MHz) */
873 module_param(maxfreq
, int, 0);
875 /* force PIO transfers all the time */
876 module_param(nodma
, int, 0);
878 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
879 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
880 MODULE_LICENSE("GPL");
881 MODULE_ALIAS("platform:mvsdio");