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Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
31 #include <linux/of.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/omap-dmaengine.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/core.h>
38 #include <linux/mmc/mmc.h>
39 #include <linux/mmc/slot-gpio.h>
40 #include <linux/io.h>
41 #include <linux/irq.h>
42 #include <linux/gpio.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/pinctrl/consumer.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/pm_wakeirq.h>
47 #include <linux/platform_data/hsmmc-omap.h>
48
49 /* OMAP HSMMC Host Controller Registers */
50 #define OMAP_HSMMC_SYSSTATUS 0x0014
51 #define OMAP_HSMMC_CON 0x002C
52 #define OMAP_HSMMC_SDMASA 0x0100
53 #define OMAP_HSMMC_BLK 0x0104
54 #define OMAP_HSMMC_ARG 0x0108
55 #define OMAP_HSMMC_CMD 0x010C
56 #define OMAP_HSMMC_RSP10 0x0110
57 #define OMAP_HSMMC_RSP32 0x0114
58 #define OMAP_HSMMC_RSP54 0x0118
59 #define OMAP_HSMMC_RSP76 0x011C
60 #define OMAP_HSMMC_DATA 0x0120
61 #define OMAP_HSMMC_PSTATE 0x0124
62 #define OMAP_HSMMC_HCTL 0x0128
63 #define OMAP_HSMMC_SYSCTL 0x012C
64 #define OMAP_HSMMC_STAT 0x0130
65 #define OMAP_HSMMC_IE 0x0134
66 #define OMAP_HSMMC_ISE 0x0138
67 #define OMAP_HSMMC_AC12 0x013C
68 #define OMAP_HSMMC_CAPA 0x0140
69
70 #define VS18 (1 << 26)
71 #define VS30 (1 << 25)
72 #define HSS (1 << 21)
73 #define SDVS18 (0x5 << 9)
74 #define SDVS30 (0x6 << 9)
75 #define SDVS33 (0x7 << 9)
76 #define SDVS_MASK 0x00000E00
77 #define SDVSCLR 0xFFFFF1FF
78 #define SDVSDET 0x00000400
79 #define AUTOIDLE 0x1
80 #define SDBP (1 << 8)
81 #define DTO 0xe
82 #define ICE 0x1
83 #define ICS 0x2
84 #define CEN (1 << 2)
85 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
86 #define CLKD_MASK 0x0000FFC0
87 #define CLKD_SHIFT 6
88 #define DTO_MASK 0x000F0000
89 #define DTO_SHIFT 16
90 #define INIT_STREAM (1 << 1)
91 #define ACEN_ACMD23 (2 << 2)
92 #define DP_SELECT (1 << 21)
93 #define DDIR (1 << 4)
94 #define DMAE 0x1
95 #define MSBS (1 << 5)
96 #define BCE (1 << 1)
97 #define FOUR_BIT (1 << 1)
98 #define HSPE (1 << 2)
99 #define IWE (1 << 24)
100 #define DDR (1 << 19)
101 #define CLKEXTFREE (1 << 16)
102 #define CTPL (1 << 11)
103 #define DW8 (1 << 5)
104 #define OD 0x1
105 #define STAT_CLEAR 0xFFFFFFFF
106 #define INIT_STREAM_CMD 0x00000000
107 #define DUAL_VOLT_OCR_BIT 7
108 #define SRC (1 << 25)
109 #define SRD (1 << 26)
110 #define SOFTRESET (1 << 1)
111
112 /* PSTATE */
113 #define DLEV_DAT(x) (1 << (20 + (x)))
114
115 /* Interrupt masks for IE and ISE register */
116 #define CC_EN (1 << 0)
117 #define TC_EN (1 << 1)
118 #define BWR_EN (1 << 4)
119 #define BRR_EN (1 << 5)
120 #define CIRQ_EN (1 << 8)
121 #define ERR_EN (1 << 15)
122 #define CTO_EN (1 << 16)
123 #define CCRC_EN (1 << 17)
124 #define CEB_EN (1 << 18)
125 #define CIE_EN (1 << 19)
126 #define DTO_EN (1 << 20)
127 #define DCRC_EN (1 << 21)
128 #define DEB_EN (1 << 22)
129 #define ACE_EN (1 << 24)
130 #define CERR_EN (1 << 28)
131 #define BADA_EN (1 << 29)
132
133 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
134 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
135 BRR_EN | BWR_EN | TC_EN | CC_EN)
136
137 #define CNI (1 << 7)
138 #define ACIE (1 << 4)
139 #define ACEB (1 << 3)
140 #define ACCE (1 << 2)
141 #define ACTO (1 << 1)
142 #define ACNE (1 << 0)
143
144 #define MMC_AUTOSUSPEND_DELAY 100
145 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
146 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
147 #define OMAP_MMC_MIN_CLOCK 400000
148 #define OMAP_MMC_MAX_CLOCK 52000000
149 #define DRIVER_NAME "omap_hsmmc"
150
151 #define VDD_1V8 1800000 /* 180000 uV */
152 #define VDD_3V0 3000000 /* 300000 uV */
153 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
154
155 /*
156 * One controller can have multiple slots, like on some omap boards using
157 * omap.c controller driver. Luckily this is not currently done on any known
158 * omap_hsmmc.c device.
159 */
160 #define mmc_pdata(host) host->pdata
161
162 /*
163 * MMC Host controller read/write API's
164 */
165 #define OMAP_HSMMC_READ(base, reg) \
166 __raw_readl((base) + OMAP_HSMMC_##reg)
167
168 #define OMAP_HSMMC_WRITE(base, reg, val) \
169 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
170
171 struct omap_hsmmc_next {
172 unsigned int dma_len;
173 s32 cookie;
174 };
175
176 struct omap_hsmmc_host {
177 struct device *dev;
178 struct mmc_host *mmc;
179 struct mmc_request *mrq;
180 struct mmc_command *cmd;
181 struct mmc_data *data;
182 struct clk *fclk;
183 struct clk *dbclk;
184 /*
185 * vcc == configured supply
186 * vcc_aux == optional
187 * - MMC1, supply for DAT4..DAT7
188 * - MMC2/MMC2, external level shifter voltage supply, for
189 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
190 */
191 struct regulator *vcc;
192 struct regulator *vcc_aux;
193 struct regulator *pbias;
194 bool pbias_enabled;
195 void __iomem *base;
196 resource_size_t mapbase;
197 spinlock_t irq_lock; /* Prevent races with irq handler */
198 unsigned int dma_len;
199 unsigned int dma_sg_idx;
200 unsigned char bus_mode;
201 unsigned char power_mode;
202 int suspended;
203 u32 con;
204 u32 hctl;
205 u32 sysctl;
206 u32 capa;
207 int irq;
208 int wake_irq;
209 int use_dma, dma_ch;
210 struct dma_chan *tx_chan;
211 struct dma_chan *rx_chan;
212 int response_busy;
213 int context_loss;
214 int protect_card;
215 int reqs_blocked;
216 int use_reg;
217 int req_in_progress;
218 unsigned long clk_rate;
219 unsigned int flags;
220 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
221 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
222 struct omap_hsmmc_next next_data;
223 struct omap_hsmmc_platform_data *pdata;
224
225 /* return MMC cover switch state, can be NULL if not supported.
226 *
227 * possible return values:
228 * 0 - closed
229 * 1 - open
230 */
231 int (*get_cover_state)(struct device *dev);
232
233 int (*card_detect)(struct device *dev);
234 };
235
236 struct omap_mmc_of_data {
237 u32 reg_offset;
238 u8 controller_flags;
239 };
240
241 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
242
243 static int omap_hsmmc_card_detect(struct device *dev)
244 {
245 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
246
247 return mmc_gpio_get_cd(host->mmc);
248 }
249
250 static int omap_hsmmc_get_cover_state(struct device *dev)
251 {
252 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
253
254 return mmc_gpio_get_cd(host->mmc);
255 }
256
257 #ifdef CONFIG_REGULATOR
258
259 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
260 {
261 struct omap_hsmmc_host *host =
262 platform_get_drvdata(to_platform_device(dev));
263 int ret = 0;
264
265 /*
266 * If we don't see a Vcc regulator, assume it's a fixed
267 * voltage always-on regulator.
268 */
269 if (!host->vcc)
270 return 0;
271
272 if (mmc_pdata(host)->before_set_reg)
273 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
274
275 if (host->pbias) {
276 if (host->pbias_enabled == 1) {
277 ret = regulator_disable(host->pbias);
278 if (!ret)
279 host->pbias_enabled = 0;
280 }
281 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
282 }
283
284 /*
285 * Assume Vcc regulator is used only to power the card ... OMAP
286 * VDDS is used to power the pins, optionally with a transceiver to
287 * support cards using voltages other than VDDS (1.8V nominal). When a
288 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
289 *
290 * In some cases this regulator won't support enable/disable;
291 * e.g. it's a fixed rail for a WLAN chip.
292 *
293 * In other cases vcc_aux switches interface power. Example, for
294 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
295 * chips/cards need an interface voltage rail too.
296 */
297 if (power_on) {
298 if (host->vcc)
299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0 && host->vcc)
304 ret = mmc_regulator_set_ocr(host->mmc,
305 host->vcc, 0);
306 }
307 } else {
308 /* Shut down the rail */
309 if (host->vcc_aux)
310 ret = regulator_disable(host->vcc_aux);
311 if (host->vcc) {
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
314 host->vcc, 0);
315 }
316 }
317
318 if (host->pbias) {
319 if (vdd <= VDD_165_195)
320 ret = regulator_set_voltage(host->pbias, VDD_1V8,
321 VDD_1V8);
322 else
323 ret = regulator_set_voltage(host->pbias, VDD_3V0,
324 VDD_3V0);
325 if (ret < 0)
326 goto error_set_power;
327
328 if (host->pbias_enabled == 0) {
329 ret = regulator_enable(host->pbias);
330 if (!ret)
331 host->pbias_enabled = 1;
332 }
333 }
334
335 if (mmc_pdata(host)->after_set_reg)
336 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
337
338 error_set_power:
339 return ret;
340 }
341
342 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
343 {
344 struct regulator *reg;
345 int ocr_value = 0;
346
347 reg = devm_regulator_get(host->dev, "vmmc");
348 if (IS_ERR(reg)) {
349 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
350 PTR_ERR(reg));
351 return PTR_ERR(reg);
352 } else {
353 host->vcc = reg;
354 ocr_value = mmc_regulator_get_ocrmask(reg);
355 if (!mmc_pdata(host)->ocr_mask) {
356 mmc_pdata(host)->ocr_mask = ocr_value;
357 } else {
358 if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
359 dev_err(host->dev, "ocrmask %x is not supported\n",
360 mmc_pdata(host)->ocr_mask);
361 mmc_pdata(host)->ocr_mask = 0;
362 return -EINVAL;
363 }
364 }
365 }
366 mmc_pdata(host)->set_power = omap_hsmmc_set_power;
367
368 /* Allow an aux regulator */
369 reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
370 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
371
372 reg = devm_regulator_get_optional(host->dev, "pbias");
373 host->pbias = IS_ERR(reg) ? NULL : reg;
374
375 /* For eMMC do not power off when not in sleep state */
376 if (mmc_pdata(host)->no_regulator_off_init)
377 return 0;
378 /*
379 * To disable boot_on regulator, enable regulator
380 * to increase usecount and then disable it.
381 */
382 if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
383 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
384 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
385
386 mmc_pdata(host)->set_power(host->dev, 1, vdd);
387 mmc_pdata(host)->set_power(host->dev, 0, 0);
388 }
389
390 return 0;
391 }
392
393 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
394 {
395 mmc_pdata(host)->set_power = NULL;
396 }
397
398 static inline int omap_hsmmc_have_reg(void)
399 {
400 return 1;
401 }
402
403 #else
404
405 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
406 {
407 return -EINVAL;
408 }
409
410 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
411 {
412 }
413
414 static inline int omap_hsmmc_have_reg(void)
415 {
416 return 0;
417 }
418
419 #endif
420
421 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
422
423 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
424 struct omap_hsmmc_host *host,
425 struct omap_hsmmc_platform_data *pdata)
426 {
427 int ret;
428
429 if (gpio_is_valid(pdata->gpio_cod)) {
430 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
431 if (ret)
432 return ret;
433
434 host->get_cover_state = omap_hsmmc_get_cover_state;
435 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
436 } else if (gpio_is_valid(pdata->gpio_cd)) {
437 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
438 if (ret)
439 return ret;
440
441 host->card_detect = omap_hsmmc_card_detect;
442 }
443
444 if (gpio_is_valid(pdata->gpio_wp)) {
445 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
446 if (ret)
447 return ret;
448 }
449
450 return 0;
451 }
452
453 /*
454 * Start clock to the card
455 */
456 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
457 {
458 OMAP_HSMMC_WRITE(host->base, SYSCTL,
459 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
460 }
461
462 /*
463 * Stop clock to the card
464 */
465 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
466 {
467 OMAP_HSMMC_WRITE(host->base, SYSCTL,
468 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
469 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
470 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
471 }
472
473 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
474 struct mmc_command *cmd)
475 {
476 u32 irq_mask = INT_EN_MASK;
477 unsigned long flags;
478
479 if (host->use_dma)
480 irq_mask &= ~(BRR_EN | BWR_EN);
481
482 /* Disable timeout for erases */
483 if (cmd->opcode == MMC_ERASE)
484 irq_mask &= ~DTO_EN;
485
486 spin_lock_irqsave(&host->irq_lock, flags);
487 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
488 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
489
490 /* latch pending CIRQ, but don't signal MMC core */
491 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
492 irq_mask |= CIRQ_EN;
493 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
494 spin_unlock_irqrestore(&host->irq_lock, flags);
495 }
496
497 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
498 {
499 u32 irq_mask = 0;
500 unsigned long flags;
501
502 spin_lock_irqsave(&host->irq_lock, flags);
503 /* no transfer running but need to keep cirq if enabled */
504 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
505 irq_mask |= CIRQ_EN;
506 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
507 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
508 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
509 spin_unlock_irqrestore(&host->irq_lock, flags);
510 }
511
512 /* Calculate divisor for the given clock frequency */
513 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
514 {
515 u16 dsor = 0;
516
517 if (ios->clock) {
518 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
519 if (dsor > CLKD_MAX)
520 dsor = CLKD_MAX;
521 }
522
523 return dsor;
524 }
525
526 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
527 {
528 struct mmc_ios *ios = &host->mmc->ios;
529 unsigned long regval;
530 unsigned long timeout;
531 unsigned long clkdiv;
532
533 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
534
535 omap_hsmmc_stop_clock(host);
536
537 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
538 regval = regval & ~(CLKD_MASK | DTO_MASK);
539 clkdiv = calc_divisor(host, ios);
540 regval = regval | (clkdiv << 6) | (DTO << 16);
541 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
542 OMAP_HSMMC_WRITE(host->base, SYSCTL,
543 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
544
545 /* Wait till the ICS bit is set */
546 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
547 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
548 && time_before(jiffies, timeout))
549 cpu_relax();
550
551 /*
552 * Enable High-Speed Support
553 * Pre-Requisites
554 * - Controller should support High-Speed-Enable Bit
555 * - Controller should not be using DDR Mode
556 * - Controller should advertise that it supports High Speed
557 * in capabilities register
558 * - MMC/SD clock coming out of controller > 25MHz
559 */
560 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
561 (ios->timing != MMC_TIMING_MMC_DDR52) &&
562 (ios->timing != MMC_TIMING_UHS_DDR50) &&
563 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
564 regval = OMAP_HSMMC_READ(host->base, HCTL);
565 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
566 regval |= HSPE;
567 else
568 regval &= ~HSPE;
569
570 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
571 }
572
573 omap_hsmmc_start_clock(host);
574 }
575
576 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
577 {
578 struct mmc_ios *ios = &host->mmc->ios;
579 u32 con;
580
581 con = OMAP_HSMMC_READ(host->base, CON);
582 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
583 ios->timing == MMC_TIMING_UHS_DDR50)
584 con |= DDR; /* configure in DDR mode */
585 else
586 con &= ~DDR;
587 switch (ios->bus_width) {
588 case MMC_BUS_WIDTH_8:
589 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
590 break;
591 case MMC_BUS_WIDTH_4:
592 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
593 OMAP_HSMMC_WRITE(host->base, HCTL,
594 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
595 break;
596 case MMC_BUS_WIDTH_1:
597 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
598 OMAP_HSMMC_WRITE(host->base, HCTL,
599 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
600 break;
601 }
602 }
603
604 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
605 {
606 struct mmc_ios *ios = &host->mmc->ios;
607 u32 con;
608
609 con = OMAP_HSMMC_READ(host->base, CON);
610 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
611 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
612 else
613 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
614 }
615
616 #ifdef CONFIG_PM
617
618 /*
619 * Restore the MMC host context, if it was lost as result of a
620 * power state change.
621 */
622 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
623 {
624 struct mmc_ios *ios = &host->mmc->ios;
625 u32 hctl, capa;
626 unsigned long timeout;
627
628 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
629 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
630 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
631 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
632 return 0;
633
634 host->context_loss++;
635
636 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
637 if (host->power_mode != MMC_POWER_OFF &&
638 (1 << ios->vdd) <= MMC_VDD_23_24)
639 hctl = SDVS18;
640 else
641 hctl = SDVS30;
642 capa = VS30 | VS18;
643 } else {
644 hctl = SDVS18;
645 capa = VS18;
646 }
647
648 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
649 hctl |= IWE;
650
651 OMAP_HSMMC_WRITE(host->base, HCTL,
652 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
653
654 OMAP_HSMMC_WRITE(host->base, CAPA,
655 OMAP_HSMMC_READ(host->base, CAPA) | capa);
656
657 OMAP_HSMMC_WRITE(host->base, HCTL,
658 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
659
660 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
661 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
662 && time_before(jiffies, timeout))
663 ;
664
665 OMAP_HSMMC_WRITE(host->base, ISE, 0);
666 OMAP_HSMMC_WRITE(host->base, IE, 0);
667 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
668
669 /* Do not initialize card-specific things if the power is off */
670 if (host->power_mode == MMC_POWER_OFF)
671 goto out;
672
673 omap_hsmmc_set_bus_width(host);
674
675 omap_hsmmc_set_clock(host);
676
677 omap_hsmmc_set_bus_mode(host);
678
679 out:
680 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
681 host->context_loss);
682 return 0;
683 }
684
685 /*
686 * Save the MMC host context (store the number of power state changes so far).
687 */
688 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
689 {
690 host->con = OMAP_HSMMC_READ(host->base, CON);
691 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
692 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
693 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
694 }
695
696 #else
697
698 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
699 {
700 return 0;
701 }
702
703 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
704 {
705 }
706
707 #endif
708
709 /*
710 * Send init stream sequence to card
711 * before sending IDLE command
712 */
713 static void send_init_stream(struct omap_hsmmc_host *host)
714 {
715 int reg = 0;
716 unsigned long timeout;
717
718 if (host->protect_card)
719 return;
720
721 disable_irq(host->irq);
722
723 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
724 OMAP_HSMMC_WRITE(host->base, CON,
725 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
726 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
727
728 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
729 while ((reg != CC_EN) && time_before(jiffies, timeout))
730 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
731
732 OMAP_HSMMC_WRITE(host->base, CON,
733 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
734
735 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
736 OMAP_HSMMC_READ(host->base, STAT);
737
738 enable_irq(host->irq);
739 }
740
741 static inline
742 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
743 {
744 int r = 1;
745
746 if (host->get_cover_state)
747 r = host->get_cover_state(host->dev);
748 return r;
749 }
750
751 static ssize_t
752 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
753 char *buf)
754 {
755 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
756 struct omap_hsmmc_host *host = mmc_priv(mmc);
757
758 return sprintf(buf, "%s\n",
759 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
760 }
761
762 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
763
764 static ssize_t
765 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
766 char *buf)
767 {
768 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
769 struct omap_hsmmc_host *host = mmc_priv(mmc);
770
771 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
772 }
773
774 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
775
776 /*
777 * Configure the response type and send the cmd.
778 */
779 static void
780 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
781 struct mmc_data *data)
782 {
783 int cmdreg = 0, resptype = 0, cmdtype = 0;
784
785 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
786 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
787 host->cmd = cmd;
788
789 omap_hsmmc_enable_irq(host, cmd);
790
791 host->response_busy = 0;
792 if (cmd->flags & MMC_RSP_PRESENT) {
793 if (cmd->flags & MMC_RSP_136)
794 resptype = 1;
795 else if (cmd->flags & MMC_RSP_BUSY) {
796 resptype = 3;
797 host->response_busy = 1;
798 } else
799 resptype = 2;
800 }
801
802 /*
803 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
804 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
805 * a val of 0x3, rest 0x0.
806 */
807 if (cmd == host->mrq->stop)
808 cmdtype = 0x3;
809
810 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
811
812 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
813 host->mrq->sbc) {
814 cmdreg |= ACEN_ACMD23;
815 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
816 }
817 if (data) {
818 cmdreg |= DP_SELECT | MSBS | BCE;
819 if (data->flags & MMC_DATA_READ)
820 cmdreg |= DDIR;
821 else
822 cmdreg &= ~(DDIR);
823 }
824
825 if (host->use_dma)
826 cmdreg |= DMAE;
827
828 host->req_in_progress = 1;
829
830 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
831 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
832 }
833
834 static int
835 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
836 {
837 if (data->flags & MMC_DATA_WRITE)
838 return DMA_TO_DEVICE;
839 else
840 return DMA_FROM_DEVICE;
841 }
842
843 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
844 struct mmc_data *data)
845 {
846 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
847 }
848
849 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
850 {
851 int dma_ch;
852 unsigned long flags;
853
854 spin_lock_irqsave(&host->irq_lock, flags);
855 host->req_in_progress = 0;
856 dma_ch = host->dma_ch;
857 spin_unlock_irqrestore(&host->irq_lock, flags);
858
859 omap_hsmmc_disable_irq(host);
860 /* Do not complete the request if DMA is still in progress */
861 if (mrq->data && host->use_dma && dma_ch != -1)
862 return;
863 host->mrq = NULL;
864 mmc_request_done(host->mmc, mrq);
865 pm_runtime_mark_last_busy(host->dev);
866 pm_runtime_put_autosuspend(host->dev);
867 }
868
869 /*
870 * Notify the transfer complete to MMC core
871 */
872 static void
873 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
874 {
875 if (!data) {
876 struct mmc_request *mrq = host->mrq;
877
878 /* TC before CC from CMD6 - don't know why, but it happens */
879 if (host->cmd && host->cmd->opcode == 6 &&
880 host->response_busy) {
881 host->response_busy = 0;
882 return;
883 }
884
885 omap_hsmmc_request_done(host, mrq);
886 return;
887 }
888
889 host->data = NULL;
890
891 if (!data->error)
892 data->bytes_xfered += data->blocks * (data->blksz);
893 else
894 data->bytes_xfered = 0;
895
896 if (data->stop && (data->error || !host->mrq->sbc))
897 omap_hsmmc_start_command(host, data->stop, NULL);
898 else
899 omap_hsmmc_request_done(host, data->mrq);
900 }
901
902 /*
903 * Notify the core about command completion
904 */
905 static void
906 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
907 {
908 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
909 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
910 host->cmd = NULL;
911 omap_hsmmc_start_dma_transfer(host);
912 omap_hsmmc_start_command(host, host->mrq->cmd,
913 host->mrq->data);
914 return;
915 }
916
917 host->cmd = NULL;
918
919 if (cmd->flags & MMC_RSP_PRESENT) {
920 if (cmd->flags & MMC_RSP_136) {
921 /* response type 2 */
922 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
923 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
924 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
925 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
926 } else {
927 /* response types 1, 1b, 3, 4, 5, 6 */
928 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
929 }
930 }
931 if ((host->data == NULL && !host->response_busy) || cmd->error)
932 omap_hsmmc_request_done(host, host->mrq);
933 }
934
935 /*
936 * DMA clean up for command errors
937 */
938 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
939 {
940 int dma_ch;
941 unsigned long flags;
942
943 host->data->error = errno;
944
945 spin_lock_irqsave(&host->irq_lock, flags);
946 dma_ch = host->dma_ch;
947 host->dma_ch = -1;
948 spin_unlock_irqrestore(&host->irq_lock, flags);
949
950 if (host->use_dma && dma_ch != -1) {
951 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
952
953 dmaengine_terminate_all(chan);
954 dma_unmap_sg(chan->device->dev,
955 host->data->sg, host->data->sg_len,
956 omap_hsmmc_get_dma_dir(host, host->data));
957
958 host->data->host_cookie = 0;
959 }
960 host->data = NULL;
961 }
962
963 /*
964 * Readable error output
965 */
966 #ifdef CONFIG_MMC_DEBUG
967 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
968 {
969 /* --- means reserved bit without definition at documentation */
970 static const char *omap_hsmmc_status_bits[] = {
971 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
972 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
973 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
974 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
975 };
976 char res[256];
977 char *buf = res;
978 int len, i;
979
980 len = sprintf(buf, "MMC IRQ 0x%x :", status);
981 buf += len;
982
983 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
984 if (status & (1 << i)) {
985 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
986 buf += len;
987 }
988
989 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
990 }
991 #else
992 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
993 u32 status)
994 {
995 }
996 #endif /* CONFIG_MMC_DEBUG */
997
998 /*
999 * MMC controller internal state machines reset
1000 *
1001 * Used to reset command or data internal state machines, using respectively
1002 * SRC or SRD bit of SYSCTL register
1003 * Can be called from interrupt context
1004 */
1005 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1006 unsigned long bit)
1007 {
1008 unsigned long i = 0;
1009 unsigned long limit = MMC_TIMEOUT_US;
1010
1011 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1012 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1013
1014 /*
1015 * OMAP4 ES2 and greater has an updated reset logic.
1016 * Monitor a 0->1 transition first
1017 */
1018 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1019 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1020 && (i++ < limit))
1021 udelay(1);
1022 }
1023 i = 0;
1024
1025 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1026 (i++ < limit))
1027 udelay(1);
1028
1029 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1030 dev_err(mmc_dev(host->mmc),
1031 "Timeout waiting on controller reset in %s\n",
1032 __func__);
1033 }
1034
1035 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1036 int err, int end_cmd)
1037 {
1038 if (end_cmd) {
1039 omap_hsmmc_reset_controller_fsm(host, SRC);
1040 if (host->cmd)
1041 host->cmd->error = err;
1042 }
1043
1044 if (host->data) {
1045 omap_hsmmc_reset_controller_fsm(host, SRD);
1046 omap_hsmmc_dma_cleanup(host, err);
1047 } else if (host->mrq && host->mrq->cmd)
1048 host->mrq->cmd->error = err;
1049 }
1050
1051 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1052 {
1053 struct mmc_data *data;
1054 int end_cmd = 0, end_trans = 0;
1055 int error = 0;
1056
1057 data = host->data;
1058 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1059
1060 if (status & ERR_EN) {
1061 omap_hsmmc_dbg_report_irq(host, status);
1062
1063 if (status & (CTO_EN | CCRC_EN))
1064 end_cmd = 1;
1065 if (host->data || host->response_busy) {
1066 end_trans = !end_cmd;
1067 host->response_busy = 0;
1068 }
1069 if (status & (CTO_EN | DTO_EN))
1070 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1071 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1072 BADA_EN))
1073 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1074
1075 if (status & ACE_EN) {
1076 u32 ac12;
1077 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1078 if (!(ac12 & ACNE) && host->mrq->sbc) {
1079 end_cmd = 1;
1080 if (ac12 & ACTO)
1081 error = -ETIMEDOUT;
1082 else if (ac12 & (ACCE | ACEB | ACIE))
1083 error = -EILSEQ;
1084 host->mrq->sbc->error = error;
1085 hsmmc_command_incomplete(host, error, end_cmd);
1086 }
1087 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1088 }
1089 }
1090
1091 OMAP_HSMMC_WRITE(host->base, STAT, status);
1092 if (end_cmd || ((status & CC_EN) && host->cmd))
1093 omap_hsmmc_cmd_done(host, host->cmd);
1094 if ((end_trans || (status & TC_EN)) && host->mrq)
1095 omap_hsmmc_xfer_done(host, data);
1096 }
1097
1098 /*
1099 * MMC controller IRQ handler
1100 */
1101 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1102 {
1103 struct omap_hsmmc_host *host = dev_id;
1104 int status;
1105
1106 status = OMAP_HSMMC_READ(host->base, STAT);
1107 while (status & (INT_EN_MASK | CIRQ_EN)) {
1108 if (host->req_in_progress)
1109 omap_hsmmc_do_irq(host, status);
1110
1111 if (status & CIRQ_EN)
1112 mmc_signal_sdio_irq(host->mmc);
1113
1114 /* Flush posted write */
1115 status = OMAP_HSMMC_READ(host->base, STAT);
1116 }
1117
1118 return IRQ_HANDLED;
1119 }
1120
1121 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1122 {
1123 unsigned long i;
1124
1125 OMAP_HSMMC_WRITE(host->base, HCTL,
1126 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1127 for (i = 0; i < loops_per_jiffy; i++) {
1128 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1129 break;
1130 cpu_relax();
1131 }
1132 }
1133
1134 /*
1135 * Switch MMC interface voltage ... only relevant for MMC1.
1136 *
1137 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1138 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1139 * Some chips, like eMMC ones, use internal transceivers.
1140 */
1141 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1142 {
1143 u32 reg_val = 0;
1144 int ret;
1145
1146 /* Disable the clocks */
1147 pm_runtime_put_sync(host->dev);
1148 if (host->dbclk)
1149 clk_disable_unprepare(host->dbclk);
1150
1151 /* Turn the power off */
1152 ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1153
1154 /* Turn the power ON with given VDD 1.8 or 3.0v */
1155 if (!ret)
1156 ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1157 pm_runtime_get_sync(host->dev);
1158 if (host->dbclk)
1159 clk_prepare_enable(host->dbclk);
1160
1161 if (ret != 0)
1162 goto err;
1163
1164 OMAP_HSMMC_WRITE(host->base, HCTL,
1165 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1166 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1167
1168 /*
1169 * If a MMC dual voltage card is detected, the set_ios fn calls
1170 * this fn with VDD bit set for 1.8V. Upon card removal from the
1171 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1172 *
1173 * Cope with a bit of slop in the range ... per data sheets:
1174 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1175 * but recommended values are 1.71V to 1.89V
1176 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1177 * but recommended values are 2.7V to 3.3V
1178 *
1179 * Board setup code shouldn't permit anything very out-of-range.
1180 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1181 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1182 */
1183 if ((1 << vdd) <= MMC_VDD_23_24)
1184 reg_val |= SDVS18;
1185 else
1186 reg_val |= SDVS30;
1187
1188 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1189 set_sd_bus_power(host);
1190
1191 return 0;
1192 err:
1193 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1194 return ret;
1195 }
1196
1197 /* Protect the card while the cover is open */
1198 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1199 {
1200 if (!host->get_cover_state)
1201 return;
1202
1203 host->reqs_blocked = 0;
1204 if (host->get_cover_state(host->dev)) {
1205 if (host->protect_card) {
1206 dev_info(host->dev, "%s: cover is closed, "
1207 "card is now accessible\n",
1208 mmc_hostname(host->mmc));
1209 host->protect_card = 0;
1210 }
1211 } else {
1212 if (!host->protect_card) {
1213 dev_info(host->dev, "%s: cover is open, "
1214 "card is now inaccessible\n",
1215 mmc_hostname(host->mmc));
1216 host->protect_card = 1;
1217 }
1218 }
1219 }
1220
1221 /*
1222 * irq handler when (cell-phone) cover is mounted/removed
1223 */
1224 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1225 {
1226 struct omap_hsmmc_host *host = dev_id;
1227
1228 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1229
1230 omap_hsmmc_protect_card(host);
1231 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1232 return IRQ_HANDLED;
1233 }
1234
1235 static void omap_hsmmc_dma_callback(void *param)
1236 {
1237 struct omap_hsmmc_host *host = param;
1238 struct dma_chan *chan;
1239 struct mmc_data *data;
1240 int req_in_progress;
1241
1242 spin_lock_irq(&host->irq_lock);
1243 if (host->dma_ch < 0) {
1244 spin_unlock_irq(&host->irq_lock);
1245 return;
1246 }
1247
1248 data = host->mrq->data;
1249 chan = omap_hsmmc_get_dma_chan(host, data);
1250 if (!data->host_cookie)
1251 dma_unmap_sg(chan->device->dev,
1252 data->sg, data->sg_len,
1253 omap_hsmmc_get_dma_dir(host, data));
1254
1255 req_in_progress = host->req_in_progress;
1256 host->dma_ch = -1;
1257 spin_unlock_irq(&host->irq_lock);
1258
1259 /* If DMA has finished after TC, complete the request */
1260 if (!req_in_progress) {
1261 struct mmc_request *mrq = host->mrq;
1262
1263 host->mrq = NULL;
1264 mmc_request_done(host->mmc, mrq);
1265 pm_runtime_mark_last_busy(host->dev);
1266 pm_runtime_put_autosuspend(host->dev);
1267 }
1268 }
1269
1270 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1271 struct mmc_data *data,
1272 struct omap_hsmmc_next *next,
1273 struct dma_chan *chan)
1274 {
1275 int dma_len;
1276
1277 if (!next && data->host_cookie &&
1278 data->host_cookie != host->next_data.cookie) {
1279 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1280 " host->next_data.cookie %d\n",
1281 __func__, data->host_cookie, host->next_data.cookie);
1282 data->host_cookie = 0;
1283 }
1284
1285 /* Check if next job is already prepared */
1286 if (next || data->host_cookie != host->next_data.cookie) {
1287 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1288 omap_hsmmc_get_dma_dir(host, data));
1289
1290 } else {
1291 dma_len = host->next_data.dma_len;
1292 host->next_data.dma_len = 0;
1293 }
1294
1295
1296 if (dma_len == 0)
1297 return -EINVAL;
1298
1299 if (next) {
1300 next->dma_len = dma_len;
1301 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1302 } else
1303 host->dma_len = dma_len;
1304
1305 return 0;
1306 }
1307
1308 /*
1309 * Routine to configure and start DMA for the MMC card
1310 */
1311 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1312 struct mmc_request *req)
1313 {
1314 struct dma_slave_config cfg;
1315 struct dma_async_tx_descriptor *tx;
1316 int ret = 0, i;
1317 struct mmc_data *data = req->data;
1318 struct dma_chan *chan;
1319
1320 /* Sanity check: all the SG entries must be aligned by block size. */
1321 for (i = 0; i < data->sg_len; i++) {
1322 struct scatterlist *sgl;
1323
1324 sgl = data->sg + i;
1325 if (sgl->length % data->blksz)
1326 return -EINVAL;
1327 }
1328 if ((data->blksz % 4) != 0)
1329 /* REVISIT: The MMC buffer increments only when MSB is written.
1330 * Return error for blksz which is non multiple of four.
1331 */
1332 return -EINVAL;
1333
1334 BUG_ON(host->dma_ch != -1);
1335
1336 chan = omap_hsmmc_get_dma_chan(host, data);
1337
1338 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1339 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1340 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1341 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1342 cfg.src_maxburst = data->blksz / 4;
1343 cfg.dst_maxburst = data->blksz / 4;
1344
1345 ret = dmaengine_slave_config(chan, &cfg);
1346 if (ret)
1347 return ret;
1348
1349 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1350 if (ret)
1351 return ret;
1352
1353 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1354 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1355 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1356 if (!tx) {
1357 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1358 /* FIXME: cleanup */
1359 return -1;
1360 }
1361
1362 tx->callback = omap_hsmmc_dma_callback;
1363 tx->callback_param = host;
1364
1365 /* Does not fail */
1366 dmaengine_submit(tx);
1367
1368 host->dma_ch = 1;
1369
1370 return 0;
1371 }
1372
1373 static void set_data_timeout(struct omap_hsmmc_host *host,
1374 unsigned int timeout_ns,
1375 unsigned int timeout_clks)
1376 {
1377 unsigned int timeout, cycle_ns;
1378 uint32_t reg, clkd, dto = 0;
1379
1380 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1381 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1382 if (clkd == 0)
1383 clkd = 1;
1384
1385 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1386 timeout = timeout_ns / cycle_ns;
1387 timeout += timeout_clks;
1388 if (timeout) {
1389 while ((timeout & 0x80000000) == 0) {
1390 dto += 1;
1391 timeout <<= 1;
1392 }
1393 dto = 31 - dto;
1394 timeout <<= 1;
1395 if (timeout && dto)
1396 dto += 1;
1397 if (dto >= 13)
1398 dto -= 13;
1399 else
1400 dto = 0;
1401 if (dto > 14)
1402 dto = 14;
1403 }
1404
1405 reg &= ~DTO_MASK;
1406 reg |= dto << DTO_SHIFT;
1407 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1408 }
1409
1410 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1411 {
1412 struct mmc_request *req = host->mrq;
1413 struct dma_chan *chan;
1414
1415 if (!req->data)
1416 return;
1417 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1418 | (req->data->blocks << 16));
1419 set_data_timeout(host, req->data->timeout_ns,
1420 req->data->timeout_clks);
1421 chan = omap_hsmmc_get_dma_chan(host, req->data);
1422 dma_async_issue_pending(chan);
1423 }
1424
1425 /*
1426 * Configure block length for MMC/SD cards and initiate the transfer.
1427 */
1428 static int
1429 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1430 {
1431 int ret;
1432 host->data = req->data;
1433
1434 if (req->data == NULL) {
1435 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1436 /*
1437 * Set an arbitrary 100ms data timeout for commands with
1438 * busy signal.
1439 */
1440 if (req->cmd->flags & MMC_RSP_BUSY)
1441 set_data_timeout(host, 100000000U, 0);
1442 return 0;
1443 }
1444
1445 if (host->use_dma) {
1446 ret = omap_hsmmc_setup_dma_transfer(host, req);
1447 if (ret != 0) {
1448 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1449 return ret;
1450 }
1451 }
1452 return 0;
1453 }
1454
1455 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1456 int err)
1457 {
1458 struct omap_hsmmc_host *host = mmc_priv(mmc);
1459 struct mmc_data *data = mrq->data;
1460
1461 if (host->use_dma && data->host_cookie) {
1462 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1463
1464 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1465 omap_hsmmc_get_dma_dir(host, data));
1466 data->host_cookie = 0;
1467 }
1468 }
1469
1470 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1471 bool is_first_req)
1472 {
1473 struct omap_hsmmc_host *host = mmc_priv(mmc);
1474
1475 if (mrq->data->host_cookie) {
1476 mrq->data->host_cookie = 0;
1477 return ;
1478 }
1479
1480 if (host->use_dma) {
1481 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1482
1483 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1484 &host->next_data, c))
1485 mrq->data->host_cookie = 0;
1486 }
1487 }
1488
1489 /*
1490 * Request function. for read/write operation
1491 */
1492 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1493 {
1494 struct omap_hsmmc_host *host = mmc_priv(mmc);
1495 int err;
1496
1497 BUG_ON(host->req_in_progress);
1498 BUG_ON(host->dma_ch != -1);
1499 pm_runtime_get_sync(host->dev);
1500 if (host->protect_card) {
1501 if (host->reqs_blocked < 3) {
1502 /*
1503 * Ensure the controller is left in a consistent
1504 * state by resetting the command and data state
1505 * machines.
1506 */
1507 omap_hsmmc_reset_controller_fsm(host, SRD);
1508 omap_hsmmc_reset_controller_fsm(host, SRC);
1509 host->reqs_blocked += 1;
1510 }
1511 req->cmd->error = -EBADF;
1512 if (req->data)
1513 req->data->error = -EBADF;
1514 req->cmd->retries = 0;
1515 mmc_request_done(mmc, req);
1516 pm_runtime_mark_last_busy(host->dev);
1517 pm_runtime_put_autosuspend(host->dev);
1518 return;
1519 } else if (host->reqs_blocked)
1520 host->reqs_blocked = 0;
1521 WARN_ON(host->mrq != NULL);
1522 host->mrq = req;
1523 host->clk_rate = clk_get_rate(host->fclk);
1524 err = omap_hsmmc_prepare_data(host, req);
1525 if (err) {
1526 req->cmd->error = err;
1527 if (req->data)
1528 req->data->error = err;
1529 host->mrq = NULL;
1530 mmc_request_done(mmc, req);
1531 pm_runtime_mark_last_busy(host->dev);
1532 pm_runtime_put_autosuspend(host->dev);
1533 return;
1534 }
1535 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1536 omap_hsmmc_start_command(host, req->sbc, NULL);
1537 return;
1538 }
1539
1540 omap_hsmmc_start_dma_transfer(host);
1541 omap_hsmmc_start_command(host, req->cmd, req->data);
1542 }
1543
1544 /* Routine to configure clock values. Exposed API to core */
1545 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1546 {
1547 struct omap_hsmmc_host *host = mmc_priv(mmc);
1548 int do_send_init_stream = 0;
1549
1550 pm_runtime_get_sync(host->dev);
1551
1552 if (ios->power_mode != host->power_mode) {
1553 switch (ios->power_mode) {
1554 case MMC_POWER_OFF:
1555 mmc_pdata(host)->set_power(host->dev, 0, 0);
1556 break;
1557 case MMC_POWER_UP:
1558 mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1559 break;
1560 case MMC_POWER_ON:
1561 do_send_init_stream = 1;
1562 break;
1563 }
1564 host->power_mode = ios->power_mode;
1565 }
1566
1567 /* FIXME: set registers based only on changes to ios */
1568
1569 omap_hsmmc_set_bus_width(host);
1570
1571 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1572 /* Only MMC1 can interface at 3V without some flavor
1573 * of external transceiver; but they all handle 1.8V.
1574 */
1575 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1576 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1577 /*
1578 * The mmc_select_voltage fn of the core does
1579 * not seem to set the power_mode to
1580 * MMC_POWER_UP upon recalculating the voltage.
1581 * vdd 1.8v.
1582 */
1583 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1584 dev_dbg(mmc_dev(host->mmc),
1585 "Switch operation failed\n");
1586 }
1587 }
1588
1589 omap_hsmmc_set_clock(host);
1590
1591 if (do_send_init_stream)
1592 send_init_stream(host);
1593
1594 omap_hsmmc_set_bus_mode(host);
1595
1596 pm_runtime_put_autosuspend(host->dev);
1597 }
1598
1599 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1600 {
1601 struct omap_hsmmc_host *host = mmc_priv(mmc);
1602
1603 if (!host->card_detect)
1604 return -ENOSYS;
1605 return host->card_detect(host->dev);
1606 }
1607
1608 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1609 {
1610 struct omap_hsmmc_host *host = mmc_priv(mmc);
1611
1612 if (mmc_pdata(host)->init_card)
1613 mmc_pdata(host)->init_card(card);
1614 }
1615
1616 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1617 {
1618 struct omap_hsmmc_host *host = mmc_priv(mmc);
1619 u32 irq_mask, con;
1620 unsigned long flags;
1621
1622 spin_lock_irqsave(&host->irq_lock, flags);
1623
1624 con = OMAP_HSMMC_READ(host->base, CON);
1625 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1626 if (enable) {
1627 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1628 irq_mask |= CIRQ_EN;
1629 con |= CTPL | CLKEXTFREE;
1630 } else {
1631 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1632 irq_mask &= ~CIRQ_EN;
1633 con &= ~(CTPL | CLKEXTFREE);
1634 }
1635 OMAP_HSMMC_WRITE(host->base, CON, con);
1636 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1637
1638 /*
1639 * if enable, piggy back detection on current request
1640 * but always disable immediately
1641 */
1642 if (!host->req_in_progress || !enable)
1643 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1644
1645 /* flush posted write */
1646 OMAP_HSMMC_READ(host->base, IE);
1647
1648 spin_unlock_irqrestore(&host->irq_lock, flags);
1649 }
1650
1651 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1652 {
1653 int ret;
1654
1655 /*
1656 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1657 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1658 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1659 * with functional clock disabled.
1660 */
1661 if (!host->dev->of_node || !host->wake_irq)
1662 return -ENODEV;
1663
1664 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1665 if (ret) {
1666 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1667 goto err;
1668 }
1669
1670 /*
1671 * Some omaps don't have wake-up path from deeper idle states
1672 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1673 */
1674 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1675 struct pinctrl *p = devm_pinctrl_get(host->dev);
1676 if (!p) {
1677 ret = -ENODEV;
1678 goto err_free_irq;
1679 }
1680 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1681 dev_info(host->dev, "missing default pinctrl state\n");
1682 devm_pinctrl_put(p);
1683 ret = -EINVAL;
1684 goto err_free_irq;
1685 }
1686
1687 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1688 dev_info(host->dev, "missing idle pinctrl state\n");
1689 devm_pinctrl_put(p);
1690 ret = -EINVAL;
1691 goto err_free_irq;
1692 }
1693 devm_pinctrl_put(p);
1694 }
1695
1696 OMAP_HSMMC_WRITE(host->base, HCTL,
1697 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1698 return 0;
1699
1700 err_free_irq:
1701 dev_pm_clear_wake_irq(host->dev);
1702 err:
1703 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1704 host->wake_irq = 0;
1705 return ret;
1706 }
1707
1708 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1709 {
1710 u32 hctl, capa, value;
1711
1712 /* Only MMC1 supports 3.0V */
1713 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1714 hctl = SDVS30;
1715 capa = VS30 | VS18;
1716 } else {
1717 hctl = SDVS18;
1718 capa = VS18;
1719 }
1720
1721 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1722 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1723
1724 value = OMAP_HSMMC_READ(host->base, CAPA);
1725 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1726
1727 /* Set SD bus power bit */
1728 set_sd_bus_power(host);
1729 }
1730
1731 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1732 unsigned int direction, int blk_size)
1733 {
1734 /* This controller can't do multiblock reads due to hw bugs */
1735 if (direction == MMC_DATA_READ)
1736 return 1;
1737
1738 return blk_size;
1739 }
1740
1741 static struct mmc_host_ops omap_hsmmc_ops = {
1742 .post_req = omap_hsmmc_post_req,
1743 .pre_req = omap_hsmmc_pre_req,
1744 .request = omap_hsmmc_request,
1745 .set_ios = omap_hsmmc_set_ios,
1746 .get_cd = omap_hsmmc_get_cd,
1747 .get_ro = mmc_gpio_get_ro,
1748 .init_card = omap_hsmmc_init_card,
1749 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1750 };
1751
1752 #ifdef CONFIG_DEBUG_FS
1753
1754 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1755 {
1756 struct mmc_host *mmc = s->private;
1757 struct omap_hsmmc_host *host = mmc_priv(mmc);
1758
1759 seq_printf(s, "mmc%d:\n", mmc->index);
1760 seq_printf(s, "sdio irq mode\t%s\n",
1761 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1762
1763 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1764 seq_printf(s, "sdio irq \t%s\n",
1765 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1766 : "disabled");
1767 }
1768 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1769
1770 pm_runtime_get_sync(host->dev);
1771 seq_puts(s, "\nregs:\n");
1772 seq_printf(s, "CON:\t\t0x%08x\n",
1773 OMAP_HSMMC_READ(host->base, CON));
1774 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1775 OMAP_HSMMC_READ(host->base, PSTATE));
1776 seq_printf(s, "HCTL:\t\t0x%08x\n",
1777 OMAP_HSMMC_READ(host->base, HCTL));
1778 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1779 OMAP_HSMMC_READ(host->base, SYSCTL));
1780 seq_printf(s, "IE:\t\t0x%08x\n",
1781 OMAP_HSMMC_READ(host->base, IE));
1782 seq_printf(s, "ISE:\t\t0x%08x\n",
1783 OMAP_HSMMC_READ(host->base, ISE));
1784 seq_printf(s, "CAPA:\t\t0x%08x\n",
1785 OMAP_HSMMC_READ(host->base, CAPA));
1786
1787 pm_runtime_mark_last_busy(host->dev);
1788 pm_runtime_put_autosuspend(host->dev);
1789
1790 return 0;
1791 }
1792
1793 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1794 {
1795 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1796 }
1797
1798 static const struct file_operations mmc_regs_fops = {
1799 .open = omap_hsmmc_regs_open,
1800 .read = seq_read,
1801 .llseek = seq_lseek,
1802 .release = single_release,
1803 };
1804
1805 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1806 {
1807 if (mmc->debugfs_root)
1808 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1809 mmc, &mmc_regs_fops);
1810 }
1811
1812 #else
1813
1814 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1815 {
1816 }
1817
1818 #endif
1819
1820 #ifdef CONFIG_OF
1821 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1822 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1823 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1824 };
1825
1826 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1827 .reg_offset = 0x100,
1828 };
1829 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1830 .reg_offset = 0x100,
1831 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1832 };
1833
1834 static const struct of_device_id omap_mmc_of_match[] = {
1835 {
1836 .compatible = "ti,omap2-hsmmc",
1837 },
1838 {
1839 .compatible = "ti,omap3-pre-es3-hsmmc",
1840 .data = &omap3_pre_es3_mmc_of_data,
1841 },
1842 {
1843 .compatible = "ti,omap3-hsmmc",
1844 },
1845 {
1846 .compatible = "ti,omap4-hsmmc",
1847 .data = &omap4_mmc_of_data,
1848 },
1849 {
1850 .compatible = "ti,am33xx-hsmmc",
1851 .data = &am33xx_mmc_of_data,
1852 },
1853 {},
1854 };
1855 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1856
1857 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1858 {
1859 struct omap_hsmmc_platform_data *pdata;
1860 struct device_node *np = dev->of_node;
1861
1862 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1863 if (!pdata)
1864 return ERR_PTR(-ENOMEM); /* out of memory */
1865
1866 if (of_find_property(np, "ti,dual-volt", NULL))
1867 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1868
1869 pdata->gpio_cd = -EINVAL;
1870 pdata->gpio_cod = -EINVAL;
1871 pdata->gpio_wp = -EINVAL;
1872
1873 if (of_find_property(np, "ti,non-removable", NULL)) {
1874 pdata->nonremovable = true;
1875 pdata->no_regulator_off_init = true;
1876 }
1877
1878 if (of_find_property(np, "ti,needs-special-reset", NULL))
1879 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1880
1881 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1882 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1883
1884 return pdata;
1885 }
1886 #else
1887 static inline struct omap_hsmmc_platform_data
1888 *of_get_hsmmc_pdata(struct device *dev)
1889 {
1890 return ERR_PTR(-EINVAL);
1891 }
1892 #endif
1893
1894 static int omap_hsmmc_probe(struct platform_device *pdev)
1895 {
1896 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1897 struct mmc_host *mmc;
1898 struct omap_hsmmc_host *host = NULL;
1899 struct resource *res;
1900 int ret, irq;
1901 const struct of_device_id *match;
1902 dma_cap_mask_t mask;
1903 unsigned tx_req, rx_req;
1904 const struct omap_mmc_of_data *data;
1905 void __iomem *base;
1906
1907 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1908 if (match) {
1909 pdata = of_get_hsmmc_pdata(&pdev->dev);
1910
1911 if (IS_ERR(pdata))
1912 return PTR_ERR(pdata);
1913
1914 if (match->data) {
1915 data = match->data;
1916 pdata->reg_offset = data->reg_offset;
1917 pdata->controller_flags |= data->controller_flags;
1918 }
1919 }
1920
1921 if (pdata == NULL) {
1922 dev_err(&pdev->dev, "Platform Data is missing\n");
1923 return -ENXIO;
1924 }
1925
1926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1927 irq = platform_get_irq(pdev, 0);
1928 if (res == NULL || irq < 0)
1929 return -ENXIO;
1930
1931 base = devm_ioremap_resource(&pdev->dev, res);
1932 if (IS_ERR(base))
1933 return PTR_ERR(base);
1934
1935 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1936 if (!mmc) {
1937 ret = -ENOMEM;
1938 goto err;
1939 }
1940
1941 ret = mmc_of_parse(mmc);
1942 if (ret)
1943 goto err1;
1944
1945 host = mmc_priv(mmc);
1946 host->mmc = mmc;
1947 host->pdata = pdata;
1948 host->dev = &pdev->dev;
1949 host->use_dma = 1;
1950 host->dma_ch = -1;
1951 host->irq = irq;
1952 host->mapbase = res->start + pdata->reg_offset;
1953 host->base = base + pdata->reg_offset;
1954 host->power_mode = MMC_POWER_OFF;
1955 host->next_data.cookie = 1;
1956 host->pbias_enabled = 0;
1957
1958 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
1959 if (ret)
1960 goto err_gpio;
1961
1962 platform_set_drvdata(pdev, host);
1963
1964 if (pdev->dev.of_node)
1965 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1966
1967 mmc->ops = &omap_hsmmc_ops;
1968
1969 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1970
1971 if (pdata->max_freq > 0)
1972 mmc->f_max = pdata->max_freq;
1973 else if (mmc->f_max == 0)
1974 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1975
1976 spin_lock_init(&host->irq_lock);
1977
1978 host->fclk = devm_clk_get(&pdev->dev, "fck");
1979 if (IS_ERR(host->fclk)) {
1980 ret = PTR_ERR(host->fclk);
1981 host->fclk = NULL;
1982 goto err1;
1983 }
1984
1985 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1986 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1987 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
1988 }
1989
1990 device_init_wakeup(&pdev->dev, true);
1991 pm_runtime_enable(host->dev);
1992 pm_runtime_get_sync(host->dev);
1993 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1994 pm_runtime_use_autosuspend(host->dev);
1995
1996 omap_hsmmc_context_save(host);
1997
1998 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1999 /*
2000 * MMC can still work without debounce clock.
2001 */
2002 if (IS_ERR(host->dbclk)) {
2003 host->dbclk = NULL;
2004 } else if (clk_prepare_enable(host->dbclk) != 0) {
2005 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2006 host->dbclk = NULL;
2007 }
2008
2009 /* Since we do only SG emulation, we can have as many segs
2010 * as we want. */
2011 mmc->max_segs = 1024;
2012
2013 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2014 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2015 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2016 mmc->max_seg_size = mmc->max_req_size;
2017
2018 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2019 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2020
2021 mmc->caps |= mmc_pdata(host)->caps;
2022 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2023 mmc->caps |= MMC_CAP_4_BIT_DATA;
2024
2025 if (mmc_pdata(host)->nonremovable)
2026 mmc->caps |= MMC_CAP_NONREMOVABLE;
2027
2028 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2029
2030 omap_hsmmc_conf_bus_power(host);
2031
2032 if (!pdev->dev.of_node) {
2033 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2034 if (!res) {
2035 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2036 ret = -ENXIO;
2037 goto err_irq;
2038 }
2039 tx_req = res->start;
2040
2041 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2042 if (!res) {
2043 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2044 ret = -ENXIO;
2045 goto err_irq;
2046 }
2047 rx_req = res->start;
2048 }
2049
2050 dma_cap_zero(mask);
2051 dma_cap_set(DMA_SLAVE, mask);
2052
2053 host->rx_chan =
2054 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2055 &rx_req, &pdev->dev, "rx");
2056
2057 if (!host->rx_chan) {
2058 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2059 ret = -ENXIO;
2060 goto err_irq;
2061 }
2062
2063 host->tx_chan =
2064 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2065 &tx_req, &pdev->dev, "tx");
2066
2067 if (!host->tx_chan) {
2068 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2069 ret = -ENXIO;
2070 goto err_irq;
2071 }
2072
2073 /* Request IRQ for MMC operations */
2074 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2075 mmc_hostname(mmc), host);
2076 if (ret) {
2077 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2078 goto err_irq;
2079 }
2080
2081 if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2082 ret = omap_hsmmc_reg_get(host);
2083 if (ret)
2084 goto err_irq;
2085 host->use_reg = 1;
2086 }
2087
2088 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2089
2090 omap_hsmmc_disable_irq(host);
2091
2092 /*
2093 * For now, only support SDIO interrupt if we have a separate
2094 * wake-up interrupt configured from device tree. This is because
2095 * the wake-up interrupt is needed for idle state and some
2096 * platforms need special quirks. And we don't want to add new
2097 * legacy mux platform init code callbacks any longer as we
2098 * are moving to DT based booting anyways.
2099 */
2100 ret = omap_hsmmc_configure_wake_irq(host);
2101 if (!ret)
2102 mmc->caps |= MMC_CAP_SDIO_IRQ;
2103
2104 omap_hsmmc_protect_card(host);
2105
2106 mmc_add_host(mmc);
2107
2108 if (mmc_pdata(host)->name != NULL) {
2109 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2110 if (ret < 0)
2111 goto err_slot_name;
2112 }
2113 if (host->get_cover_state) {
2114 ret = device_create_file(&mmc->class_dev,
2115 &dev_attr_cover_switch);
2116 if (ret < 0)
2117 goto err_slot_name;
2118 }
2119
2120 omap_hsmmc_debugfs(mmc);
2121 pm_runtime_mark_last_busy(host->dev);
2122 pm_runtime_put_autosuspend(host->dev);
2123
2124 return 0;
2125
2126 err_slot_name:
2127 mmc_remove_host(mmc);
2128 if (host->use_reg)
2129 omap_hsmmc_reg_put(host);
2130 err_irq:
2131 device_init_wakeup(&pdev->dev, false);
2132 if (host->tx_chan)
2133 dma_release_channel(host->tx_chan);
2134 if (host->rx_chan)
2135 dma_release_channel(host->rx_chan);
2136 pm_runtime_put_sync(host->dev);
2137 pm_runtime_disable(host->dev);
2138 if (host->dbclk)
2139 clk_disable_unprepare(host->dbclk);
2140 err1:
2141 err_gpio:
2142 mmc_free_host(mmc);
2143 err:
2144 return ret;
2145 }
2146
2147 static int omap_hsmmc_remove(struct platform_device *pdev)
2148 {
2149 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2150
2151 pm_runtime_get_sync(host->dev);
2152 mmc_remove_host(host->mmc);
2153 if (host->use_reg)
2154 omap_hsmmc_reg_put(host);
2155
2156 if (host->tx_chan)
2157 dma_release_channel(host->tx_chan);
2158 if (host->rx_chan)
2159 dma_release_channel(host->rx_chan);
2160
2161 pm_runtime_put_sync(host->dev);
2162 pm_runtime_disable(host->dev);
2163 device_init_wakeup(&pdev->dev, false);
2164 if (host->dbclk)
2165 clk_disable_unprepare(host->dbclk);
2166
2167 mmc_free_host(host->mmc);
2168
2169 return 0;
2170 }
2171
2172 #ifdef CONFIG_PM_SLEEP
2173 static int omap_hsmmc_suspend(struct device *dev)
2174 {
2175 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2176
2177 if (!host)
2178 return 0;
2179
2180 pm_runtime_get_sync(host->dev);
2181
2182 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2183 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2184 OMAP_HSMMC_WRITE(host->base, IE, 0);
2185 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2186 OMAP_HSMMC_WRITE(host->base, HCTL,
2187 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2188 }
2189
2190 if (host->dbclk)
2191 clk_disable_unprepare(host->dbclk);
2192
2193 pm_runtime_put_sync(host->dev);
2194 return 0;
2195 }
2196
2197 /* Routine to resume the MMC device */
2198 static int omap_hsmmc_resume(struct device *dev)
2199 {
2200 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2201
2202 if (!host)
2203 return 0;
2204
2205 pm_runtime_get_sync(host->dev);
2206
2207 if (host->dbclk)
2208 clk_prepare_enable(host->dbclk);
2209
2210 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2211 omap_hsmmc_conf_bus_power(host);
2212
2213 omap_hsmmc_protect_card(host);
2214 pm_runtime_mark_last_busy(host->dev);
2215 pm_runtime_put_autosuspend(host->dev);
2216 return 0;
2217 }
2218 #endif
2219
2220 static int omap_hsmmc_runtime_suspend(struct device *dev)
2221 {
2222 struct omap_hsmmc_host *host;
2223 unsigned long flags;
2224 int ret = 0;
2225
2226 host = platform_get_drvdata(to_platform_device(dev));
2227 omap_hsmmc_context_save(host);
2228 dev_dbg(dev, "disabled\n");
2229
2230 spin_lock_irqsave(&host->irq_lock, flags);
2231 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2232 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2233 /* disable sdio irq handling to prevent race */
2234 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2235 OMAP_HSMMC_WRITE(host->base, IE, 0);
2236
2237 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2238 /*
2239 * dat1 line low, pending sdio irq
2240 * race condition: possible irq handler running on
2241 * multi-core, abort
2242 */
2243 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2244 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2245 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2246 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2247 pm_runtime_mark_last_busy(dev);
2248 ret = -EBUSY;
2249 goto abort;
2250 }
2251
2252 pinctrl_pm_select_idle_state(dev);
2253 } else {
2254 pinctrl_pm_select_idle_state(dev);
2255 }
2256
2257 abort:
2258 spin_unlock_irqrestore(&host->irq_lock, flags);
2259 return ret;
2260 }
2261
2262 static int omap_hsmmc_runtime_resume(struct device *dev)
2263 {
2264 struct omap_hsmmc_host *host;
2265 unsigned long flags;
2266
2267 host = platform_get_drvdata(to_platform_device(dev));
2268 omap_hsmmc_context_restore(host);
2269 dev_dbg(dev, "enabled\n");
2270
2271 spin_lock_irqsave(&host->irq_lock, flags);
2272 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2273 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2274
2275 pinctrl_pm_select_default_state(host->dev);
2276
2277 /* irq lost, if pinmux incorrect */
2278 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2279 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2280 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2281 } else {
2282 pinctrl_pm_select_default_state(host->dev);
2283 }
2284 spin_unlock_irqrestore(&host->irq_lock, flags);
2285 return 0;
2286 }
2287
2288 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2289 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2290 .runtime_suspend = omap_hsmmc_runtime_suspend,
2291 .runtime_resume = omap_hsmmc_runtime_resume,
2292 };
2293
2294 static struct platform_driver omap_hsmmc_driver = {
2295 .probe = omap_hsmmc_probe,
2296 .remove = omap_hsmmc_remove,
2297 .driver = {
2298 .name = DRIVER_NAME,
2299 .pm = &omap_hsmmc_dev_pm_ops,
2300 .of_match_table = of_match_ptr(omap_mmc_of_match),
2301 },
2302 };
2303
2304 module_platform_driver(omap_hsmmc_driver);
2305 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2306 MODULE_LICENSE("GPL");
2307 MODULE_ALIAS("platform:" DRIVER_NAME);
2308 MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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