1 /* Realtek PCI-Express SD/MMC Card Interface driver
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/highmem.h>
25 #include <linux/delay.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/sd.h>
31 #include <linux/mmc/card.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <asm/unaligned.h>
35 struct realtek_pci_sdmmc
{
36 struct platform_device
*pdev
;
39 struct mmc_request
*mrq
;
40 struct workqueue_struct
*workq
;
41 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
43 struct work_struct work
;
44 struct mutex host_mutex
;
53 #define SDMMC_POWER_ON 1
54 #define SDMMC_POWER_OFF 0
56 unsigned int sg_count
;
58 unsigned int cookie_sg_count
;
62 static inline struct device
*sdmmc_dev(struct realtek_pci_sdmmc
*host
)
64 return &(host
->pdev
->dev
);
67 static inline void sd_clear_error(struct realtek_pci_sdmmc
*host
)
69 rtsx_pci_write_register(host
->pcr
, CARD_STOP
,
70 SD_STOP
| SD_CLR_ERR
, SD_STOP
| SD_CLR_ERR
);
74 static void sd_print_debug_regs(struct realtek_pci_sdmmc
*host
)
76 struct rtsx_pcr
*pcr
= host
->pcr
;
80 /* Print SD host internal registers */
81 rtsx_pci_init_cmd(pcr
);
82 for (i
= 0xFDA0; i
<= 0xFDAE; i
++)
83 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, i
, 0, 0);
84 for (i
= 0xFD52; i
<= 0xFD69; i
++)
85 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, i
, 0, 0);
86 rtsx_pci_send_cmd(pcr
, 100);
88 ptr
= rtsx_pci_get_cmd_data(pcr
);
89 for (i
= 0xFDA0; i
<= 0xFDAE; i
++)
90 dev_dbg(sdmmc_dev(host
), "0x%04X: 0x%02x\n", i
, *(ptr
++));
91 for (i
= 0xFD52; i
<= 0xFD69; i
++)
92 dev_dbg(sdmmc_dev(host
), "0x%04X: 0x%02x\n", i
, *(ptr
++));
95 #define sd_print_debug_regs(host)
99 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
101 * @pre: if called in pre_req()
103 * 0 - do dma_map_sg()
106 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc
*host
,
107 struct mmc_data
*data
, bool pre
)
109 struct rtsx_pcr
*pcr
= host
->pcr
;
110 int read
= data
->flags
& MMC_DATA_READ
;
112 int using_cookie
= 0;
114 if (!pre
&& data
->host_cookie
&& data
->host_cookie
!= host
->cookie
) {
115 dev_err(sdmmc_dev(host
),
116 "error: data->host_cookie = %d, host->cookie = %d\n",
117 data
->host_cookie
, host
->cookie
);
118 data
->host_cookie
= 0;
121 if (pre
|| data
->host_cookie
!= host
->cookie
) {
122 count
= rtsx_pci_dma_map_sg(pcr
, data
->sg
, data
->sg_len
, read
);
124 count
= host
->cookie_sg_count
;
129 host
->cookie_sg_count
= count
;
130 if (++host
->cookie
< 0)
132 data
->host_cookie
= host
->cookie
;
134 host
->sg_count
= count
;
140 static void sdmmc_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
143 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
144 struct mmc_data
*data
= mrq
->data
;
146 if (data
->host_cookie
) {
147 dev_err(sdmmc_dev(host
),
148 "error: reset data->host_cookie = %d\n",
150 data
->host_cookie
= 0;
153 sd_pre_dma_transfer(host
, data
, true);
154 dev_dbg(sdmmc_dev(host
), "pre dma sg: %d\n", host
->cookie_sg_count
);
157 static void sdmmc_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
160 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
161 struct rtsx_pcr
*pcr
= host
->pcr
;
162 struct mmc_data
*data
= mrq
->data
;
163 int read
= data
->flags
& MMC_DATA_READ
;
165 rtsx_pci_dma_unmap_sg(pcr
, data
->sg
, data
->sg_len
, read
);
166 data
->host_cookie
= 0;
169 static int sd_read_data(struct realtek_pci_sdmmc
*host
, u8
*cmd
, u16 byte_cnt
,
170 u8
*buf
, int buf_len
, int timeout
)
172 struct rtsx_pcr
*pcr
= host
->pcr
;
176 dev_dbg(sdmmc_dev(host
), "%s: SD/MMC CMD%d\n", __func__
, cmd
[0] - 0x40);
181 if ((cmd
[0] & 0x3F) == MMC_SEND_TUNING_BLOCK
)
182 trans_mode
= SD_TM_AUTO_TUNING
;
184 trans_mode
= SD_TM_NORMAL_READ
;
186 rtsx_pci_init_cmd(pcr
);
188 for (i
= 0; i
< 5; i
++)
189 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CMD0
+ i
, 0xFF, cmd
[i
]);
191 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, (u8
)byte_cnt
);
192 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BYTE_CNT_H
,
193 0xFF, (u8
)(byte_cnt
>> 8));
194 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
, 0xFF, 1);
195 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
, 0xFF, 0);
197 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
198 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
|
199 SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7
| SD_RSP_LEN_6
);
200 if (trans_mode
!= SD_TM_AUTO_TUNING
)
201 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
202 CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
204 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_TRANSFER
,
205 0xFF, trans_mode
| SD_TRANSFER_START
);
206 rtsx_pci_add_cmd(pcr
, CHECK_REG_CMD
, SD_TRANSFER
,
207 SD_TRANSFER_END
, SD_TRANSFER_END
);
209 err
= rtsx_pci_send_cmd(pcr
, timeout
);
211 sd_print_debug_regs(host
);
212 dev_dbg(sdmmc_dev(host
),
213 "rtsx_pci_send_cmd fail (err = %d)\n", err
);
217 if (buf
&& buf_len
) {
218 err
= rtsx_pci_read_ppbuf(pcr
, buf
, buf_len
);
220 dev_dbg(sdmmc_dev(host
),
221 "rtsx_pci_read_ppbuf fail (err = %d)\n", err
);
229 static int sd_write_data(struct realtek_pci_sdmmc
*host
, u8
*cmd
, u16 byte_cnt
,
230 u8
*buf
, int buf_len
, int timeout
)
232 struct rtsx_pcr
*pcr
= host
->pcr
;
239 if (buf
&& buf_len
) {
240 err
= rtsx_pci_write_ppbuf(pcr
, buf
, buf_len
);
242 dev_dbg(sdmmc_dev(host
),
243 "rtsx_pci_write_ppbuf fail (err = %d)\n", err
);
248 trans_mode
= cmd
? SD_TM_AUTO_WRITE_2
: SD_TM_AUTO_WRITE_3
;
249 rtsx_pci_init_cmd(pcr
);
252 dev_dbg(sdmmc_dev(host
), "%s: SD/MMC CMD %d\n", __func__
,
255 for (i
= 0; i
< 5; i
++)
256 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
257 SD_CMD0
+ i
, 0xFF, cmd
[i
]);
260 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, (u8
)byte_cnt
);
261 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BYTE_CNT_H
,
262 0xFF, (u8
)(byte_cnt
>> 8));
263 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
, 0xFF, 1);
264 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
, 0xFF, 0);
266 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
267 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
|
268 SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7
| SD_RSP_LEN_6
);
270 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
271 trans_mode
| SD_TRANSFER_START
);
272 rtsx_pci_add_cmd(pcr
, CHECK_REG_CMD
, SD_TRANSFER
,
273 SD_TRANSFER_END
, SD_TRANSFER_END
);
275 err
= rtsx_pci_send_cmd(pcr
, timeout
);
277 sd_print_debug_regs(host
);
278 dev_dbg(sdmmc_dev(host
),
279 "rtsx_pci_send_cmd fail (err = %d)\n", err
);
286 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc
*host
,
287 struct mmc_command
*cmd
)
289 struct rtsx_pcr
*pcr
= host
->pcr
;
290 u8 cmd_idx
= (u8
)cmd
->opcode
;
299 bool clock_toggled
= false;
301 dev_dbg(sdmmc_dev(host
), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
302 __func__
, cmd_idx
, arg
);
311 switch (mmc_resp_type(cmd
)) {
313 rsp_type
= SD_RSP_TYPE_R0
;
317 rsp_type
= SD_RSP_TYPE_R1
;
319 case MMC_RSP_R1
& ~MMC_RSP_CRC
:
320 rsp_type
= SD_RSP_TYPE_R1
| SD_NO_CHECK_CRC7
;
323 rsp_type
= SD_RSP_TYPE_R1b
;
326 rsp_type
= SD_RSP_TYPE_R2
;
330 rsp_type
= SD_RSP_TYPE_R3
;
333 dev_dbg(sdmmc_dev(host
), "cmd->flag is not valid\n");
338 if (rsp_type
== SD_RSP_TYPE_R1b
)
341 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
342 err
= rtsx_pci_write_register(pcr
, SD_BUS_STAT
,
343 0xFF, SD_CLK_TOGGLE_EN
);
347 clock_toggled
= true;
350 rtsx_pci_init_cmd(pcr
);
352 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CMD0
, 0xFF, 0x40 | cmd_idx
);
353 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CMD1
, 0xFF, (u8
)(arg
>> 24));
354 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CMD2
, 0xFF, (u8
)(arg
>> 16));
355 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CMD3
, 0xFF, (u8
)(arg
>> 8));
356 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CMD4
, 0xFF, (u8
)arg
);
358 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG2
, 0xFF, rsp_type
);
359 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
360 0x01, PINGPONG_BUFFER
);
361 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_TRANSFER
,
362 0xFF, SD_TM_CMD_RSP
| SD_TRANSFER_START
);
363 rtsx_pci_add_cmd(pcr
, CHECK_REG_CMD
, SD_TRANSFER
,
364 SD_TRANSFER_END
| SD_STAT_IDLE
,
365 SD_TRANSFER_END
| SD_STAT_IDLE
);
367 if (rsp_type
== SD_RSP_TYPE_R2
) {
368 /* Read data from ping-pong buffer */
369 for (i
= PPBUF_BASE2
; i
< PPBUF_BASE2
+ 16; i
++)
370 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, (u16
)i
, 0, 0);
372 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
373 /* Read data from SD_CMDx registers */
374 for (i
= SD_CMD0
; i
<= SD_CMD4
; i
++)
375 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, (u16
)i
, 0, 0);
379 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, SD_STAT1
, 0, 0);
381 err
= rtsx_pci_send_cmd(pcr
, timeout
);
383 sd_print_debug_regs(host
);
384 sd_clear_error(host
);
385 dev_dbg(sdmmc_dev(host
),
386 "rtsx_pci_send_cmd error (err = %d)\n", err
);
390 if (rsp_type
== SD_RSP_TYPE_R0
) {
395 /* Eliminate returned value of CHECK_REG_CMD */
396 ptr
= rtsx_pci_get_cmd_data(pcr
) + 1;
398 /* Check (Start,Transmission) bit of Response */
399 if ((ptr
[0] & 0xC0) != 0) {
401 dev_dbg(sdmmc_dev(host
), "Invalid response bit\n");
406 if (!(rsp_type
& SD_NO_CHECK_CRC7
)) {
407 if (ptr
[stat_idx
] & SD_CRC7_ERR
) {
409 dev_dbg(sdmmc_dev(host
), "CRC7 error\n");
414 if (rsp_type
== SD_RSP_TYPE_R2
) {
416 * The controller offloads the last byte {CRC-7, end bit 1'b1}
417 * of response type R2. Assign dummy CRC, 0, and end bit to the
418 * byte(ptr[16], goes into the LSB of resp[3] later).
422 for (i
= 0; i
< 4; i
++) {
423 cmd
->resp
[i
] = get_unaligned_be32(ptr
+ 1 + i
* 4);
424 dev_dbg(sdmmc_dev(host
), "cmd->resp[%d] = 0x%08x\n",
428 cmd
->resp
[0] = get_unaligned_be32(ptr
+ 1);
429 dev_dbg(sdmmc_dev(host
), "cmd->resp[0] = 0x%08x\n",
436 if (err
&& clock_toggled
)
437 rtsx_pci_write_register(pcr
, SD_BUS_STAT
,
438 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
441 static int sd_rw_multi(struct realtek_pci_sdmmc
*host
, struct mmc_request
*mrq
)
443 struct rtsx_pcr
*pcr
= host
->pcr
;
444 struct mmc_host
*mmc
= host
->mmc
;
445 struct mmc_card
*card
= mmc
->card
;
446 struct mmc_data
*data
= mrq
->data
;
447 int uhs
= mmc_card_uhs(card
);
448 int read
= (data
->flags
& MMC_DATA_READ
) ? 1 : 0;
451 size_t data_len
= data
->blksz
* data
->blocks
;
454 cfg2
= SD_CALCULATE_CRC7
| SD_CHECK_CRC16
|
455 SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7
| SD_RSP_LEN_0
;
456 trans_mode
= SD_TM_AUTO_READ_3
;
458 cfg2
= SD_NO_CALCULATE_CRC7
| SD_CHECK_CRC16
|
459 SD_NO_WAIT_BUSY_END
| SD_NO_CHECK_CRC7
| SD_RSP_LEN_0
;
460 trans_mode
= SD_TM_AUTO_WRITE_3
;
464 cfg2
|= SD_NO_CHECK_WAIT_CRC_TO
;
466 rtsx_pci_init_cmd(pcr
);
468 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, 0x00);
469 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BYTE_CNT_H
, 0xFF, 0x02);
470 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
,
471 0xFF, (u8
)data
->blocks
);
472 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
,
473 0xFF, (u8
)(data
->blocks
>> 8));
475 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, IRQSTAT0
,
476 DMA_DONE_INT
, DMA_DONE_INT
);
477 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, DMATC3
,
478 0xFF, (u8
)(data_len
>> 24));
479 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, DMATC2
,
480 0xFF, (u8
)(data_len
>> 16));
481 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, DMATC1
,
482 0xFF, (u8
)(data_len
>> 8));
483 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, DMATC0
, 0xFF, (u8
)data_len
);
485 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, DMACTL
,
486 0x03 | DMA_PACK_SIZE_MASK
,
487 DMA_DIR_FROM_CARD
| DMA_EN
| DMA_512
);
489 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, DMACTL
,
490 0x03 | DMA_PACK_SIZE_MASK
,
491 DMA_DIR_TO_CARD
| DMA_EN
| DMA_512
);
494 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
497 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG2
, 0xFF, cfg2
);
498 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
499 trans_mode
| SD_TRANSFER_START
);
500 rtsx_pci_add_cmd(pcr
, CHECK_REG_CMD
, SD_TRANSFER
,
501 SD_TRANSFER_END
, SD_TRANSFER_END
);
503 rtsx_pci_send_cmd_no_wait(pcr
);
505 err
= rtsx_pci_dma_transfer(pcr
, data
->sg
, host
->sg_count
, read
, 10000);
507 sd_clear_error(host
);
514 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc
*host
)
516 rtsx_pci_write_register(host
->pcr
, SD_CFG1
,
517 SD_CLK_DIVIDE_MASK
, SD_CLK_DIVIDE_128
);
520 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc
*host
)
522 rtsx_pci_write_register(host
->pcr
, SD_CFG1
,
523 SD_CLK_DIVIDE_MASK
, SD_CLK_DIVIDE_0
);
526 static void sd_normal_rw(struct realtek_pci_sdmmc
*host
,
527 struct mmc_request
*mrq
)
529 struct mmc_command
*cmd
= mrq
->cmd
;
530 struct mmc_data
*data
= mrq
->data
;
533 _cmd
[0] = 0x40 | (u8
)cmd
->opcode
;
534 put_unaligned_be32(cmd
->arg
, (u32
*)(&_cmd
[1]));
536 buf
= kzalloc(data
->blksz
, GFP_NOIO
);
538 cmd
->error
= -ENOMEM
;
542 if (data
->flags
& MMC_DATA_READ
) {
543 if (host
->initial_mode
)
544 sd_disable_initial_mode(host
);
546 cmd
->error
= sd_read_data(host
, _cmd
, (u16
)data
->blksz
, buf
,
549 if (host
->initial_mode
)
550 sd_enable_initial_mode(host
);
552 sg_copy_from_buffer(data
->sg
, data
->sg_len
, buf
, data
->blksz
);
554 sg_copy_to_buffer(data
->sg
, data
->sg_len
, buf
, data
->blksz
);
556 cmd
->error
= sd_write_data(host
, _cmd
, (u16
)data
->blksz
, buf
,
563 static int sd_change_phase(struct realtek_pci_sdmmc
*host
,
564 u8 sample_point
, bool rx
)
566 struct rtsx_pcr
*pcr
= host
->pcr
;
569 dev_dbg(sdmmc_dev(host
), "%s(%s): sample_point = %d\n",
570 __func__
, rx
? "RX" : "TX", sample_point
);
572 rtsx_pci_init_cmd(pcr
);
574 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
, CHANGE_CLK
, CHANGE_CLK
);
576 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
577 SD_VPRX_CTL
, 0x1F, sample_point
);
579 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
580 SD_VPTX_CTL
, 0x1F, sample_point
);
581 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
, PHASE_NOT_RESET
, 0);
582 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
583 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
584 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
, CHANGE_CLK
, 0);
585 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG1
, SD_ASYNC_FIFO_NOT_RST
, 0);
587 err
= rtsx_pci_send_cmd(pcr
, 100);
594 static inline u32
test_phase_bit(u32 phase_map
, unsigned int bit
)
596 bit
%= RTSX_PHASE_MAX
;
597 return phase_map
& (1 << bit
);
600 static int sd_get_phase_len(u32 phase_map
, unsigned int start_bit
)
604 for (i
= 0; i
< RTSX_PHASE_MAX
; i
++) {
605 if (test_phase_bit(phase_map
, start_bit
+ i
) == 0)
608 return RTSX_PHASE_MAX
;
611 static u8
sd_search_final_phase(struct realtek_pci_sdmmc
*host
, u32 phase_map
)
613 int start
= 0, len
= 0;
614 int start_final
= 0, len_final
= 0;
615 u8 final_phase
= 0xFF;
617 if (phase_map
== 0) {
618 dev_err(sdmmc_dev(host
), "phase error: [map:%x]\n", phase_map
);
622 while (start
< RTSX_PHASE_MAX
) {
623 len
= sd_get_phase_len(phase_map
, start
);
624 if (len_final
< len
) {
628 start
+= len
? len
: 1;
631 final_phase
= (start_final
+ len_final
/ 2) % RTSX_PHASE_MAX
;
632 dev_dbg(sdmmc_dev(host
), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
633 phase_map
, len_final
, final_phase
);
638 static void sd_wait_data_idle(struct realtek_pci_sdmmc
*host
)
643 for (i
= 0; i
< 100; i
++) {
644 err
= rtsx_pci_read_register(host
->pcr
, SD_DATA_STATE
, &val
);
645 if (val
& SD_DATA_IDLE
)
652 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc
*host
,
653 u8 opcode
, u8 sample_point
)
658 err
= sd_change_phase(host
, sample_point
, true);
662 cmd
[0] = 0x40 | opcode
;
663 err
= sd_read_data(host
, cmd
, 0x40, NULL
, 0, 100);
665 /* Wait till SD DATA IDLE */
666 sd_wait_data_idle(host
);
667 sd_clear_error(host
);
674 static int sd_tuning_phase(struct realtek_pci_sdmmc
*host
,
675 u8 opcode
, u32
*phase_map
)
678 u32 raw_phase_map
= 0;
680 for (i
= 0; i
< RTSX_PHASE_MAX
; i
++) {
681 err
= sd_tuning_rx_cmd(host
, opcode
, (u8
)i
);
683 raw_phase_map
|= 1 << i
;
687 *phase_map
= raw_phase_map
;
692 static int sd_tuning_rx(struct realtek_pci_sdmmc
*host
, u8 opcode
)
695 u32 raw_phase_map
[RX_TUNING_CNT
] = {0}, phase_map
;
698 for (i
= 0; i
< RX_TUNING_CNT
; i
++) {
699 err
= sd_tuning_phase(host
, opcode
, &(raw_phase_map
[i
]));
703 if (raw_phase_map
[i
] == 0)
707 phase_map
= 0xFFFFFFFF;
708 for (i
= 0; i
< RX_TUNING_CNT
; i
++) {
709 dev_dbg(sdmmc_dev(host
), "RX raw_phase_map[%d] = 0x%08x\n",
710 i
, raw_phase_map
[i
]);
711 phase_map
&= raw_phase_map
[i
];
713 dev_dbg(sdmmc_dev(host
), "RX phase_map = 0x%08x\n", phase_map
);
716 final_phase
= sd_search_final_phase(host
, phase_map
);
717 if (final_phase
== 0xFF)
720 err
= sd_change_phase(host
, final_phase
, true);
730 static inline int sd_rw_cmd(struct mmc_command
*cmd
)
732 return mmc_op_multi(cmd
->opcode
) ||
733 (cmd
->opcode
== MMC_READ_SINGLE_BLOCK
) ||
734 (cmd
->opcode
== MMC_WRITE_BLOCK
);
737 static void sd_request(struct work_struct
*work
)
739 struct realtek_pci_sdmmc
*host
= container_of(work
,
740 struct realtek_pci_sdmmc
, work
);
741 struct rtsx_pcr
*pcr
= host
->pcr
;
743 struct mmc_host
*mmc
= host
->mmc
;
744 struct mmc_request
*mrq
= host
->mrq
;
745 struct mmc_command
*cmd
= mrq
->cmd
;
746 struct mmc_data
*data
= mrq
->data
;
748 unsigned int data_size
= 0;
752 cmd
->error
= -ENOMEDIUM
;
756 err
= rtsx_pci_card_exclusive_check(host
->pcr
, RTSX_SD_CARD
);
762 mutex_lock(&pcr
->pcr_mutex
);
764 rtsx_pci_start_run(pcr
);
766 rtsx_pci_switch_clock(pcr
, host
->clock
, host
->ssc_depth
,
767 host
->initial_mode
, host
->double_clk
, host
->vpclk
);
768 rtsx_pci_write_register(pcr
, CARD_SELECT
, 0x07, SD_MOD_SEL
);
769 rtsx_pci_write_register(pcr
, CARD_SHARE_MODE
,
770 CARD_SHARE_MASK
, CARD_SHARE_48_SD
);
772 mutex_lock(&host
->host_mutex
);
774 mutex_unlock(&host
->host_mutex
);
777 data_size
= data
->blocks
* data
->blksz
;
779 if (!data_size
|| sd_rw_cmd(cmd
)) {
780 sd_send_cmd_get_rsp(host
, cmd
);
782 if (!cmd
->error
&& data_size
) {
783 sd_rw_multi(host
, mrq
);
784 if (!host
->using_cookie
)
785 sdmmc_post_req(host
->mmc
, host
->mrq
, 0);
787 if (mmc_op_multi(cmd
->opcode
) && mrq
->stop
)
788 sd_send_cmd_get_rsp(host
, mrq
->stop
);
791 sd_normal_rw(host
, mrq
);
795 if (cmd
->error
|| data
->error
)
796 data
->bytes_xfered
= 0;
798 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
801 mutex_unlock(&pcr
->pcr_mutex
);
805 dev_dbg(sdmmc_dev(host
), "cmd->error = %d\n", cmd
->error
);
807 mutex_lock(&host
->host_mutex
);
809 mutex_unlock(&host
->host_mutex
);
811 mmc_request_done(mmc
, mrq
);
814 static void sdmmc_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
816 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
817 struct mmc_data
*data
= mrq
->data
;
819 mutex_lock(&host
->host_mutex
);
821 mutex_unlock(&host
->host_mutex
);
823 if (sd_rw_cmd(mrq
->cmd
))
824 host
->using_cookie
= sd_pre_dma_transfer(host
, data
, false);
826 queue_work(host
->workq
, &host
->work
);
829 static int sd_set_bus_width(struct realtek_pci_sdmmc
*host
,
830 unsigned char bus_width
)
834 [MMC_BUS_WIDTH_1
] = SD_BUS_WIDTH_1BIT
,
835 [MMC_BUS_WIDTH_4
] = SD_BUS_WIDTH_4BIT
,
836 [MMC_BUS_WIDTH_8
] = SD_BUS_WIDTH_8BIT
,
839 if (bus_width
<= MMC_BUS_WIDTH_8
)
840 err
= rtsx_pci_write_register(host
->pcr
, SD_CFG1
,
841 0x03, width
[bus_width
]);
846 static int sd_power_on(struct realtek_pci_sdmmc
*host
)
848 struct rtsx_pcr
*pcr
= host
->pcr
;
851 if (host
->power_state
== SDMMC_POWER_ON
)
854 rtsx_pci_init_cmd(pcr
);
855 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_SELECT
, 0x07, SD_MOD_SEL
);
856 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_SHARE_MODE
,
857 CARD_SHARE_MASK
, CARD_SHARE_48_SD
);
858 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
,
859 SD_CLK_EN
, SD_CLK_EN
);
860 err
= rtsx_pci_send_cmd(pcr
, 100);
864 err
= rtsx_pci_card_pull_ctl_enable(pcr
, RTSX_SD_CARD
);
868 err
= rtsx_pci_card_power_on(pcr
, RTSX_SD_CARD
);
872 err
= rtsx_pci_write_register(pcr
, CARD_OE
, SD_OUTPUT_EN
, SD_OUTPUT_EN
);
876 host
->power_state
= SDMMC_POWER_ON
;
880 static int sd_power_off(struct realtek_pci_sdmmc
*host
)
882 struct rtsx_pcr
*pcr
= host
->pcr
;
885 host
->power_state
= SDMMC_POWER_OFF
;
887 rtsx_pci_init_cmd(pcr
);
889 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
, SD_CLK_EN
, 0);
890 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_OE
, SD_OUTPUT_EN
, 0);
892 err
= rtsx_pci_send_cmd(pcr
, 100);
896 err
= rtsx_pci_card_power_off(pcr
, RTSX_SD_CARD
);
900 return rtsx_pci_card_pull_ctl_disable(pcr
, RTSX_SD_CARD
);
903 static int sd_set_power_mode(struct realtek_pci_sdmmc
*host
,
904 unsigned char power_mode
)
908 if (power_mode
== MMC_POWER_OFF
)
909 err
= sd_power_off(host
);
911 err
= sd_power_on(host
);
916 static int sd_set_timing(struct realtek_pci_sdmmc
*host
, unsigned char timing
)
918 struct rtsx_pcr
*pcr
= host
->pcr
;
921 rtsx_pci_init_cmd(pcr
);
924 case MMC_TIMING_UHS_SDR104
:
925 case MMC_TIMING_UHS_SDR50
:
926 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG1
,
927 0x0C | SD_ASYNC_FIFO_NOT_RST
,
928 SD_30_MODE
| SD_ASYNC_FIFO_NOT_RST
);
929 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
930 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
931 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_SOURCE
, 0xFF,
932 CRC_VAR_CLK0
| SD30_FIX_CLK
| SAMPLE_VAR_CLK1
);
933 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
, CLK_LOW_FREQ
, 0);
936 case MMC_TIMING_MMC_DDR52
:
937 case MMC_TIMING_UHS_DDR50
:
938 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG1
,
939 0x0C | SD_ASYNC_FIFO_NOT_RST
,
940 SD_DDR_MODE
| SD_ASYNC_FIFO_NOT_RST
);
941 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
942 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
943 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_SOURCE
, 0xFF,
944 CRC_VAR_CLK0
| SD30_FIX_CLK
| SAMPLE_VAR_CLK1
);
945 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
, CLK_LOW_FREQ
, 0);
946 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_PUSH_POINT_CTL
,
947 DDR_VAR_TX_CMD_DAT
, DDR_VAR_TX_CMD_DAT
);
948 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_SAMPLE_POINT_CTL
,
949 DDR_VAR_RX_DAT
| DDR_VAR_RX_CMD
,
950 DDR_VAR_RX_DAT
| DDR_VAR_RX_CMD
);
953 case MMC_TIMING_MMC_HS
:
954 case MMC_TIMING_SD_HS
:
955 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_CFG1
,
957 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
958 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
959 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_SOURCE
, 0xFF,
960 CRC_FIX_CLK
| SD30_VAR_CLK0
| SAMPLE_VAR_CLK1
);
961 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
, CLK_LOW_FREQ
, 0);
962 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_PUSH_POINT_CTL
,
963 SD20_TX_SEL_MASK
, SD20_TX_14_AHEAD
);
964 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_SAMPLE_POINT_CTL
,
965 SD20_RX_SEL_MASK
, SD20_RX_14_DELAY
);
969 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
970 SD_CFG1
, 0x0C, SD_20_MODE
);
971 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
972 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
973 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_SOURCE
, 0xFF,
974 CRC_FIX_CLK
| SD30_VAR_CLK0
| SAMPLE_VAR_CLK1
);
975 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
, CLK_LOW_FREQ
, 0);
976 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
977 SD_PUSH_POINT_CTL
, 0xFF, 0);
978 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_SAMPLE_POINT_CTL
,
979 SD20_RX_SEL_MASK
, SD20_RX_POS_EDGE
);
983 err
= rtsx_pci_send_cmd(pcr
, 100);
988 static void sdmmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
990 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
991 struct rtsx_pcr
*pcr
= host
->pcr
;
996 if (rtsx_pci_card_exclusive_check(host
->pcr
, RTSX_SD_CARD
))
999 mutex_lock(&pcr
->pcr_mutex
);
1001 rtsx_pci_start_run(pcr
);
1003 sd_set_bus_width(host
, ios
->bus_width
);
1004 sd_set_power_mode(host
, ios
->power_mode
);
1005 sd_set_timing(host
, ios
->timing
);
1007 host
->vpclk
= false;
1008 host
->double_clk
= true;
1010 switch (ios
->timing
) {
1011 case MMC_TIMING_UHS_SDR104
:
1012 case MMC_TIMING_UHS_SDR50
:
1013 host
->ssc_depth
= RTSX_SSC_DEPTH_2M
;
1015 host
->double_clk
= false;
1017 case MMC_TIMING_MMC_DDR52
:
1018 case MMC_TIMING_UHS_DDR50
:
1019 case MMC_TIMING_UHS_SDR25
:
1020 host
->ssc_depth
= RTSX_SSC_DEPTH_1M
;
1023 host
->ssc_depth
= RTSX_SSC_DEPTH_500K
;
1027 host
->initial_mode
= (ios
->clock
<= 1000000) ? true : false;
1029 host
->clock
= ios
->clock
;
1030 rtsx_pci_switch_clock(pcr
, ios
->clock
, host
->ssc_depth
,
1031 host
->initial_mode
, host
->double_clk
, host
->vpclk
);
1033 mutex_unlock(&pcr
->pcr_mutex
);
1036 static int sdmmc_get_ro(struct mmc_host
*mmc
)
1038 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
1039 struct rtsx_pcr
*pcr
= host
->pcr
;
1046 mutex_lock(&pcr
->pcr_mutex
);
1048 rtsx_pci_start_run(pcr
);
1050 /* Check SD mechanical write-protect switch */
1051 val
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
1052 dev_dbg(sdmmc_dev(host
), "%s: RTSX_BIPR = 0x%08x\n", __func__
, val
);
1053 if (val
& SD_WRITE_PROTECT
)
1056 mutex_unlock(&pcr
->pcr_mutex
);
1061 static int sdmmc_get_cd(struct mmc_host
*mmc
)
1063 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
1064 struct rtsx_pcr
*pcr
= host
->pcr
;
1071 mutex_lock(&pcr
->pcr_mutex
);
1073 rtsx_pci_start_run(pcr
);
1075 /* Check SD card detect */
1076 val
= rtsx_pci_card_exist(pcr
);
1077 dev_dbg(sdmmc_dev(host
), "%s: RTSX_BIPR = 0x%08x\n", __func__
, val
);
1081 mutex_unlock(&pcr
->pcr_mutex
);
1086 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc
*host
)
1088 struct rtsx_pcr
*pcr
= host
->pcr
;
1092 /* Reference to Signal Voltage Switch Sequence in SD spec.
1093 * Wait for a period of time so that the card can drive SD_CMD and
1094 * SD_DAT[3:0] to low after sending back CMD11 response.
1098 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1099 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1100 * abort the voltage switch sequence;
1102 err
= rtsx_pci_read_register(pcr
, SD_BUS_STAT
, &stat
);
1106 if (stat
& (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
1107 SD_DAT1_STATUS
| SD_DAT0_STATUS
))
1110 /* Stop toggle SD clock */
1111 err
= rtsx_pci_write_register(pcr
, SD_BUS_STAT
,
1112 0xFF, SD_CLK_FORCE_STOP
);
1119 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc
*host
)
1121 struct rtsx_pcr
*pcr
= host
->pcr
;
1125 /* Wait 1.8V output of voltage regulator in card stable */
1128 /* Toggle SD clock again */
1129 err
= rtsx_pci_write_register(pcr
, SD_BUS_STAT
, 0xFF, SD_CLK_TOGGLE_EN
);
1133 /* Wait for a period of time so that the card can drive
1134 * SD_DAT[3:0] to high at 1.8V
1138 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1139 err
= rtsx_pci_read_register(pcr
, SD_BUS_STAT
, &stat
);
1143 mask
= SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
1144 SD_DAT1_STATUS
| SD_DAT0_STATUS
;
1145 val
= SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
1146 SD_DAT1_STATUS
| SD_DAT0_STATUS
;
1147 if ((stat
& mask
) != val
) {
1148 dev_dbg(sdmmc_dev(host
),
1149 "%s: SD_BUS_STAT = 0x%x\n", __func__
, stat
);
1150 rtsx_pci_write_register(pcr
, SD_BUS_STAT
,
1151 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
1152 rtsx_pci_write_register(pcr
, CARD_CLK_EN
, 0xFF, 0);
1159 static int sdmmc_switch_voltage(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1161 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
1162 struct rtsx_pcr
*pcr
= host
->pcr
;
1166 dev_dbg(sdmmc_dev(host
), "%s: signal_voltage = %d\n",
1167 __func__
, ios
->signal_voltage
);
1172 err
= rtsx_pci_card_exclusive_check(host
->pcr
, RTSX_SD_CARD
);
1176 mutex_lock(&pcr
->pcr_mutex
);
1178 rtsx_pci_start_run(pcr
);
1180 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
)
1181 voltage
= OUTPUT_3V3
;
1183 voltage
= OUTPUT_1V8
;
1185 if (voltage
== OUTPUT_1V8
) {
1186 err
= sd_wait_voltage_stable_1(host
);
1191 err
= rtsx_pci_switch_output_voltage(pcr
, voltage
);
1195 if (voltage
== OUTPUT_1V8
) {
1196 err
= sd_wait_voltage_stable_2(host
);
1202 /* Stop toggle SD clock in idle */
1203 err
= rtsx_pci_write_register(pcr
, SD_BUS_STAT
,
1204 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
1206 mutex_unlock(&pcr
->pcr_mutex
);
1211 static int sdmmc_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1213 struct realtek_pci_sdmmc
*host
= mmc_priv(mmc
);
1214 struct rtsx_pcr
*pcr
= host
->pcr
;
1220 err
= rtsx_pci_card_exclusive_check(host
->pcr
, RTSX_SD_CARD
);
1224 mutex_lock(&pcr
->pcr_mutex
);
1226 rtsx_pci_start_run(pcr
);
1228 /* Set initial TX phase */
1229 switch (mmc
->ios
.timing
) {
1230 case MMC_TIMING_UHS_SDR104
:
1231 err
= sd_change_phase(host
, SDR104_TX_PHASE(pcr
), false);
1234 case MMC_TIMING_UHS_SDR50
:
1235 err
= sd_change_phase(host
, SDR50_TX_PHASE(pcr
), false);
1238 case MMC_TIMING_UHS_DDR50
:
1239 err
= sd_change_phase(host
, DDR50_TX_PHASE(pcr
), false);
1249 /* Tuning RX phase */
1250 if ((mmc
->ios
.timing
== MMC_TIMING_UHS_SDR104
) ||
1251 (mmc
->ios
.timing
== MMC_TIMING_UHS_SDR50
))
1252 err
= sd_tuning_rx(host
, opcode
);
1253 else if (mmc
->ios
.timing
== MMC_TIMING_UHS_DDR50
)
1254 err
= sd_change_phase(host
, DDR50_RX_PHASE(pcr
), true);
1257 mutex_unlock(&pcr
->pcr_mutex
);
1262 static const struct mmc_host_ops realtek_pci_sdmmc_ops
= {
1263 .pre_req
= sdmmc_pre_req
,
1264 .post_req
= sdmmc_post_req
,
1265 .request
= sdmmc_request
,
1266 .set_ios
= sdmmc_set_ios
,
1267 .get_ro
= sdmmc_get_ro
,
1268 .get_cd
= sdmmc_get_cd
,
1269 .start_signal_voltage_switch
= sdmmc_switch_voltage
,
1270 .execute_tuning
= sdmmc_execute_tuning
,
1273 static void init_extra_caps(struct realtek_pci_sdmmc
*host
)
1275 struct mmc_host
*mmc
= host
->mmc
;
1276 struct rtsx_pcr
*pcr
= host
->pcr
;
1278 dev_dbg(sdmmc_dev(host
), "pcr->extra_caps = 0x%x\n", pcr
->extra_caps
);
1280 if (pcr
->extra_caps
& EXTRA_CAPS_SD_SDR50
)
1281 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
1282 if (pcr
->extra_caps
& EXTRA_CAPS_SD_SDR104
)
1283 mmc
->caps
|= MMC_CAP_UHS_SDR104
;
1284 if (pcr
->extra_caps
& EXTRA_CAPS_SD_DDR50
)
1285 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
1286 if (pcr
->extra_caps
& EXTRA_CAPS_MMC_HSDDR
)
1287 mmc
->caps
|= MMC_CAP_1_8V_DDR
;
1288 if (pcr
->extra_caps
& EXTRA_CAPS_MMC_8BIT
)
1289 mmc
->caps
|= MMC_CAP_8_BIT_DATA
;
1292 static void realtek_init_host(struct realtek_pci_sdmmc
*host
)
1294 struct mmc_host
*mmc
= host
->mmc
;
1296 mmc
->f_min
= 250000;
1297 mmc
->f_max
= 208000000;
1298 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
| MMC_VDD_165_195
;
1299 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_SD_HIGHSPEED
|
1300 MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_BUS_WIDTH_TEST
|
1301 MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
1302 mmc
->caps2
= MMC_CAP2_NO_PRESCAN_POWERUP
| MMC_CAP2_FULL_PWR_CYCLE
;
1303 mmc
->max_current_330
= 400;
1304 mmc
->max_current_180
= 800;
1305 mmc
->ops
= &realtek_pci_sdmmc_ops
;
1307 init_extra_caps(host
);
1309 mmc
->max_segs
= 256;
1310 mmc
->max_seg_size
= 65536;
1311 mmc
->max_blk_size
= 512;
1312 mmc
->max_blk_count
= 65535;
1313 mmc
->max_req_size
= 524288;
1316 static void rtsx_pci_sdmmc_card_event(struct platform_device
*pdev
)
1318 struct realtek_pci_sdmmc
*host
= platform_get_drvdata(pdev
);
1320 mmc_detect_change(host
->mmc
, 0);
1323 static int rtsx_pci_sdmmc_drv_probe(struct platform_device
*pdev
)
1325 struct mmc_host
*mmc
;
1326 struct realtek_pci_sdmmc
*host
;
1327 struct rtsx_pcr
*pcr
;
1328 struct pcr_handle
*handle
= pdev
->dev
.platform_data
;
1337 dev_dbg(&(pdev
->dev
), ": Realtek PCI-E SDMMC controller found\n");
1339 mmc
= mmc_alloc_host(sizeof(*host
), &pdev
->dev
);
1343 host
= mmc_priv(mmc
);
1344 host
->workq
= create_singlethread_workqueue(SDMMC_WORKQ_NAME
);
1352 host
->power_state
= SDMMC_POWER_OFF
;
1353 INIT_WORK(&host
->work
, sd_request
);
1354 platform_set_drvdata(pdev
, host
);
1355 pcr
->slots
[RTSX_SD_CARD
].p_dev
= pdev
;
1356 pcr
->slots
[RTSX_SD_CARD
].card_event
= rtsx_pci_sdmmc_card_event
;
1358 mutex_init(&host
->host_mutex
);
1360 realtek_init_host(host
);
1367 static int rtsx_pci_sdmmc_drv_remove(struct platform_device
*pdev
)
1369 struct realtek_pci_sdmmc
*host
= platform_get_drvdata(pdev
);
1370 struct rtsx_pcr
*pcr
;
1371 struct mmc_host
*mmc
;
1377 pcr
->slots
[RTSX_SD_CARD
].p_dev
= NULL
;
1378 pcr
->slots
[RTSX_SD_CARD
].card_event
= NULL
;
1381 cancel_work_sync(&host
->work
);
1383 mutex_lock(&host
->host_mutex
);
1385 dev_dbg(&(pdev
->dev
),
1386 "%s: Controller removed during transfer\n",
1389 rtsx_pci_complete_unfinished_transfer(pcr
);
1391 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1392 if (host
->mrq
->stop
)
1393 host
->mrq
->stop
->error
= -ENOMEDIUM
;
1394 mmc_request_done(mmc
, host
->mrq
);
1396 mutex_unlock(&host
->host_mutex
);
1398 mmc_remove_host(mmc
);
1401 flush_workqueue(host
->workq
);
1402 destroy_workqueue(host
->workq
);
1407 dev_dbg(&(pdev
->dev
),
1408 ": Realtek PCI-E SDMMC controller has been removed\n");
1413 static struct platform_device_id rtsx_pci_sdmmc_ids
[] = {
1415 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
1420 MODULE_DEVICE_TABLE(platform
, rtsx_pci_sdmmc_ids
);
1422 static struct platform_driver rtsx_pci_sdmmc_driver
= {
1423 .probe
= rtsx_pci_sdmmc_drv_probe
,
1424 .remove
= rtsx_pci_sdmmc_drv_remove
,
1425 .id_table
= rtsx_pci_sdmmc_ids
,
1427 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
1430 module_platform_driver(rtsx_pci_sdmmc_driver
);
1432 MODULE_LICENSE("GPL");
1433 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1434 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");