projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...
[deliverable/linux.git] / drivers / mmc / host / sdhci-esdhc-imx.c
1 /*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include "sdhci-pltfm.h"
32 #include "sdhci-esdhc.h"
33
34 #define ESDHC_CTRL_D3CD 0x08
35 /* VENDOR SPEC register */
36 #define ESDHC_VENDOR_SPEC 0xc0
37 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
38 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
39 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
40 #define ESDHC_WTMK_LVL 0x44
41 #define ESDHC_MIX_CTRL 0x48
42 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
43 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
44 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
45 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
46 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
47 /* Bits 3 and 6 are not SDHCI standard definitions */
48 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
49 /* Tuning bits */
50 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
51
52 /* dll control register */
53 #define ESDHC_DLL_CTRL 0x60
54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
56
57 /* tune control register */
58 #define ESDHC_TUNE_CTRL_STATUS 0x68
59 #define ESDHC_TUNE_CTRL_STEP 1
60 #define ESDHC_TUNE_CTRL_MIN 0
61 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
62
63 #define ESDHC_TUNING_CTRL 0xcc
64 #define ESDHC_STD_TUNING_EN (1 << 24)
65 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
66 #define ESDHC_TUNING_START_TAP 0x1
67
68 #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64
69
70 /* pinctrl state */
71 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
72 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
73
74 /*
75 * Our interpretation of the SDHCI_HOST_CONTROL register
76 */
77 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
78 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
79 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
80
81 /*
82 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
83 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
84 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
85 * Define this macro DMA error INT for fsl eSDHC
86 */
87 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
88
89 /*
90 * The CMDTYPE of the CMD register (offset 0xE) should be set to
91 * "11" when the STOP CMD12 is issued on imx53 to abort one
92 * open ended multi-blk IO. Otherwise the TC INT wouldn't
93 * be generated.
94 * In exact block transfer, the controller doesn't complete the
95 * operations automatically as required at the end of the
96 * transfer and remains on hold if the abort command is not sent.
97 * As a result, the TC flag is not asserted and SW received timeout
98 * exeception. Bit1 of Vendor Spec registor is used to fix it.
99 */
100 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
101 /*
102 * The flag enables the workaround for ESDHC errata ENGcm07207 which
103 * affects i.MX25 and i.MX35.
104 */
105 #define ESDHC_FLAG_ENGCM07207 BIT(2)
106 /*
107 * The flag tells that the ESDHC controller is an USDHC block that is
108 * integrated on the i.MX6 series.
109 */
110 #define ESDHC_FLAG_USDHC BIT(3)
111 /* The IP supports manual tuning process */
112 #define ESDHC_FLAG_MAN_TUNING BIT(4)
113 /* The IP supports standard tuning process */
114 #define ESDHC_FLAG_STD_TUNING BIT(5)
115 /* The IP has SDHCI_CAPABILITIES_1 register */
116 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
117
118 struct esdhc_soc_data {
119 u32 flags;
120 };
121
122 static struct esdhc_soc_data esdhc_imx25_data = {
123 .flags = ESDHC_FLAG_ENGCM07207,
124 };
125
126 static struct esdhc_soc_data esdhc_imx35_data = {
127 .flags = ESDHC_FLAG_ENGCM07207,
128 };
129
130 static struct esdhc_soc_data esdhc_imx51_data = {
131 .flags = 0,
132 };
133
134 static struct esdhc_soc_data esdhc_imx53_data = {
135 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
136 };
137
138 static struct esdhc_soc_data usdhc_imx6q_data = {
139 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
140 };
141
142 static struct esdhc_soc_data usdhc_imx6sl_data = {
143 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
144 | ESDHC_FLAG_HAVE_CAP1,
145 };
146
147 struct pltfm_imx_data {
148 u32 scratchpad;
149 struct pinctrl *pinctrl;
150 struct pinctrl_state *pins_default;
151 struct pinctrl_state *pins_100mhz;
152 struct pinctrl_state *pins_200mhz;
153 const struct esdhc_soc_data *socdata;
154 struct esdhc_platform_data boarddata;
155 struct clk *clk_ipg;
156 struct clk *clk_ahb;
157 struct clk *clk_per;
158 enum {
159 NO_CMD_PENDING, /* no multiblock command pending*/
160 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
161 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
162 } multiblock_status;
163 u32 is_ddr;
164 };
165
166 static struct platform_device_id imx_esdhc_devtype[] = {
167 {
168 .name = "sdhci-esdhc-imx25",
169 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
170 }, {
171 .name = "sdhci-esdhc-imx35",
172 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
173 }, {
174 .name = "sdhci-esdhc-imx51",
175 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
176 }, {
177 /* sentinel */
178 }
179 };
180 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
181
182 static const struct of_device_id imx_esdhc_dt_ids[] = {
183 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
184 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
185 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
186 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
187 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
188 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
189 { /* sentinel */ }
190 };
191 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
192
193 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
194 {
195 return data->socdata == &esdhc_imx25_data;
196 }
197
198 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
199 {
200 return data->socdata == &esdhc_imx53_data;
201 }
202
203 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
204 {
205 return data->socdata == &usdhc_imx6q_data;
206 }
207
208 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
209 {
210 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
211 }
212
213 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
214 {
215 void __iomem *base = host->ioaddr + (reg & ~0x3);
216 u32 shift = (reg & 0x3) * 8;
217
218 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
219 }
220
221 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
222 {
223 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
224 struct pltfm_imx_data *imx_data = pltfm_host->priv;
225 u32 val = readl(host->ioaddr + reg);
226
227 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
228 u32 fsl_prss = val;
229 /* save the least 20 bits */
230 val = fsl_prss & 0x000FFFFF;
231 /* move dat[0-3] bits */
232 val |= (fsl_prss & 0x0F000000) >> 4;
233 /* move cmd line bit */
234 val |= (fsl_prss & 0x00800000) << 1;
235 }
236
237 if (unlikely(reg == SDHCI_CAPABILITIES)) {
238 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
239 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
240 val &= 0xffff0000;
241
242 /* In FSL esdhc IC module, only bit20 is used to indicate the
243 * ADMA2 capability of esdhc, but this bit is messed up on
244 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
245 * don't actually support ADMA2). So set the BROKEN_ADMA
246 * uirk on MX25/35 platforms.
247 */
248
249 if (val & SDHCI_CAN_DO_ADMA1) {
250 val &= ~SDHCI_CAN_DO_ADMA1;
251 val |= SDHCI_CAN_DO_ADMA2;
252 }
253 }
254
255 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
256 if (esdhc_is_usdhc(imx_data)) {
257 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
258 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
259 else
260 /* imx6q/dl does not have cap_1 register, fake one */
261 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
262 | SDHCI_SUPPORT_SDR50
263 | SDHCI_USE_SDR50_TUNING;
264 }
265 }
266
267 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
268 val = 0;
269 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
270 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
271 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
272 }
273
274 if (unlikely(reg == SDHCI_INT_STATUS)) {
275 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
276 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
277 val |= SDHCI_INT_ADMA_ERROR;
278 }
279
280 /*
281 * mask off the interrupt we get in response to the manually
282 * sent CMD12
283 */
284 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
285 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
286 val &= ~SDHCI_INT_RESPONSE;
287 writel(SDHCI_INT_RESPONSE, host->ioaddr +
288 SDHCI_INT_STATUS);
289 imx_data->multiblock_status = NO_CMD_PENDING;
290 }
291 }
292
293 return val;
294 }
295
296 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
297 {
298 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
299 struct pltfm_imx_data *imx_data = pltfm_host->priv;
300 u32 data;
301
302 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
303 if (val & SDHCI_INT_CARD_INT) {
304 /*
305 * Clear and then set D3CD bit to avoid missing the
306 * card interrupt. This is a eSDHC controller problem
307 * so we need to apply the following workaround: clear
308 * and set D3CD bit will make eSDHC re-sample the card
309 * interrupt. In case a card interrupt was lost,
310 * re-sample it by the following steps.
311 */
312 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
313 data &= ~ESDHC_CTRL_D3CD;
314 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
315 data |= ESDHC_CTRL_D3CD;
316 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
317 }
318 }
319
320 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
321 && (reg == SDHCI_INT_STATUS)
322 && (val & SDHCI_INT_DATA_END))) {
323 u32 v;
324 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
325 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
326 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
327
328 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
329 {
330 /* send a manual CMD12 with RESPTYP=none */
331 data = MMC_STOP_TRANSMISSION << 24 |
332 SDHCI_CMD_ABORTCMD << 16;
333 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
334 imx_data->multiblock_status = WAIT_FOR_INT;
335 }
336 }
337
338 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
339 if (val & SDHCI_INT_ADMA_ERROR) {
340 val &= ~SDHCI_INT_ADMA_ERROR;
341 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
342 }
343 }
344
345 writel(val, host->ioaddr + reg);
346 }
347
348 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
349 {
350 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
351 struct pltfm_imx_data *imx_data = pltfm_host->priv;
352 u16 ret = 0;
353 u32 val;
354
355 if (unlikely(reg == SDHCI_HOST_VERSION)) {
356 reg ^= 2;
357 if (esdhc_is_usdhc(imx_data)) {
358 /*
359 * The usdhc register returns a wrong host version.
360 * Correct it here.
361 */
362 return SDHCI_SPEC_300;
363 }
364 }
365
366 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
367 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
368 if (val & ESDHC_VENDOR_SPEC_VSELECT)
369 ret |= SDHCI_CTRL_VDD_180;
370
371 if (esdhc_is_usdhc(imx_data)) {
372 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
373 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
374 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
375 /* the std tuning bits is in ACMD12_ERR for imx6sl */
376 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
377 }
378
379 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
380 ret |= SDHCI_CTRL_EXEC_TUNING;
381 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
382 ret |= SDHCI_CTRL_TUNED_CLK;
383
384 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
385
386 return ret;
387 }
388
389 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
390 if (esdhc_is_usdhc(imx_data)) {
391 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
392 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
393 /* Swap AC23 bit */
394 if (m & ESDHC_MIX_CTRL_AC23EN) {
395 ret &= ~ESDHC_MIX_CTRL_AC23EN;
396 ret |= SDHCI_TRNS_AUTO_CMD23;
397 }
398 } else {
399 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
400 }
401
402 return ret;
403 }
404
405 return readw(host->ioaddr + reg);
406 }
407
408 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
409 {
410 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
411 struct pltfm_imx_data *imx_data = pltfm_host->priv;
412 u32 new_val = 0;
413
414 switch (reg) {
415 case SDHCI_CLOCK_CONTROL:
416 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
417 if (val & SDHCI_CLOCK_CARD_EN)
418 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
419 else
420 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
421 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
422 return;
423 case SDHCI_HOST_CONTROL2:
424 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
425 if (val & SDHCI_CTRL_VDD_180)
426 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
427 else
428 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
429 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
430 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
431 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
432 if (val & SDHCI_CTRL_TUNED_CLK)
433 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
434 else
435 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
436 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
437 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
438 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
439 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
440 if (val & SDHCI_CTRL_TUNED_CLK) {
441 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
442 } else {
443 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
444 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
445 }
446
447 if (val & SDHCI_CTRL_EXEC_TUNING) {
448 v |= ESDHC_MIX_CTRL_EXE_TUNE;
449 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
450 } else {
451 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
452 }
453
454 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
455 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
456 }
457 return;
458 case SDHCI_TRANSFER_MODE:
459 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
460 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
461 && (host->cmd->data->blocks > 1)
462 && (host->cmd->data->flags & MMC_DATA_READ)) {
463 u32 v;
464 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
465 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
466 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
467 }
468
469 if (esdhc_is_usdhc(imx_data)) {
470 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
471 /* Swap AC23 bit */
472 if (val & SDHCI_TRNS_AUTO_CMD23) {
473 val &= ~SDHCI_TRNS_AUTO_CMD23;
474 val |= ESDHC_MIX_CTRL_AC23EN;
475 }
476 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
477 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
478 } else {
479 /*
480 * Postpone this write, we must do it together with a
481 * command write that is down below.
482 */
483 imx_data->scratchpad = val;
484 }
485 return;
486 case SDHCI_COMMAND:
487 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
488 val |= SDHCI_CMD_ABORTCMD;
489
490 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
491 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
492 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
493
494 if (esdhc_is_usdhc(imx_data))
495 writel(val << 16,
496 host->ioaddr + SDHCI_TRANSFER_MODE);
497 else
498 writel(val << 16 | imx_data->scratchpad,
499 host->ioaddr + SDHCI_TRANSFER_MODE);
500 return;
501 case SDHCI_BLOCK_SIZE:
502 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
503 break;
504 }
505 esdhc_clrset_le(host, 0xffff, val, reg);
506 }
507
508 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
509 {
510 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
511 struct pltfm_imx_data *imx_data = pltfm_host->priv;
512 u32 new_val;
513 u32 mask;
514
515 switch (reg) {
516 case SDHCI_POWER_CONTROL:
517 /*
518 * FSL put some DMA bits here
519 * If your board has a regulator, code should be here
520 */
521 return;
522 case SDHCI_HOST_CONTROL:
523 /* FSL messed up here, so we need to manually compose it. */
524 new_val = val & SDHCI_CTRL_LED;
525 /* ensure the endianness */
526 new_val |= ESDHC_HOST_CONTROL_LE;
527 /* bits 8&9 are reserved on mx25 */
528 if (!is_imx25_esdhc(imx_data)) {
529 /* DMA mode bits are shifted */
530 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
531 }
532
533 /*
534 * Do not touch buswidth bits here. This is done in
535 * esdhc_pltfm_bus_width.
536 * Do not touch the D3CD bit either which is used for the
537 * SDIO interrupt errata workaround.
538 */
539 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
540
541 esdhc_clrset_le(host, mask, new_val, reg);
542 return;
543 }
544 esdhc_clrset_le(host, 0xff, val, reg);
545
546 /*
547 * The esdhc has a design violation to SDHC spec which tells
548 * that software reset should not affect card detection circuit.
549 * But esdhc clears its SYSCTL register bits [0..2] during the
550 * software reset. This will stop those clocks that card detection
551 * circuit relies on. To work around it, we turn the clocks on back
552 * to keep card detection circuit functional.
553 */
554 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
555 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
556 /*
557 * The reset on usdhc fails to clear MIX_CTRL register.
558 * Do it manually here.
559 */
560 if (esdhc_is_usdhc(imx_data)) {
561 /* the tuning bits should be kept during reset */
562 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
563 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
564 host->ioaddr + ESDHC_MIX_CTRL);
565 imx_data->is_ddr = 0;
566 }
567 }
568 }
569
570 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
571 {
572 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
573 struct pltfm_imx_data *imx_data = pltfm_host->priv;
574 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
575
576 if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock))
577 return boarddata->f_max;
578 else
579 return pltfm_host->clock;
580 }
581
582 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
583 {
584 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
585
586 return pltfm_host->clock / 256 / 16;
587 }
588
589 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
590 unsigned int clock)
591 {
592 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
593 struct pltfm_imx_data *imx_data = pltfm_host->priv;
594 unsigned int host_clock = pltfm_host->clock;
595 int pre_div = 2;
596 int div = 1;
597 u32 temp, val;
598
599 if (clock == 0) {
600 host->mmc->actual_clock = 0;
601
602 if (esdhc_is_usdhc(imx_data)) {
603 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
604 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
605 host->ioaddr + ESDHC_VENDOR_SPEC);
606 }
607 return;
608 }
609
610 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
611 pre_div = 1;
612
613 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
614 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
615 | ESDHC_CLOCK_MASK);
616 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
617
618 while (host_clock / pre_div / 16 > clock && pre_div < 256)
619 pre_div *= 2;
620
621 while (host_clock / pre_div / div > clock && div < 16)
622 div++;
623
624 host->mmc->actual_clock = host_clock / pre_div / div;
625 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
626 clock, host->mmc->actual_clock);
627
628 if (imx_data->is_ddr)
629 pre_div >>= 2;
630 else
631 pre_div >>= 1;
632 div--;
633
634 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
635 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
636 | (div << ESDHC_DIVIDER_SHIFT)
637 | (pre_div << ESDHC_PREDIV_SHIFT));
638 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
639
640 if (esdhc_is_usdhc(imx_data)) {
641 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
642 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
643 host->ioaddr + ESDHC_VENDOR_SPEC);
644 }
645
646 mdelay(1);
647 }
648
649 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
650 {
651 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
652 struct pltfm_imx_data *imx_data = pltfm_host->priv;
653 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
654
655 switch (boarddata->wp_type) {
656 case ESDHC_WP_GPIO:
657 return mmc_gpio_get_ro(host->mmc);
658 case ESDHC_WP_CONTROLLER:
659 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
660 SDHCI_WRITE_PROTECT);
661 case ESDHC_WP_NONE:
662 break;
663 }
664
665 return -ENOSYS;
666 }
667
668 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
669 {
670 u32 ctrl;
671
672 switch (width) {
673 case MMC_BUS_WIDTH_8:
674 ctrl = ESDHC_CTRL_8BITBUS;
675 break;
676 case MMC_BUS_WIDTH_4:
677 ctrl = ESDHC_CTRL_4BITBUS;
678 break;
679 default:
680 ctrl = 0;
681 break;
682 }
683
684 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
685 SDHCI_HOST_CONTROL);
686 }
687
688 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
689 {
690 u32 reg;
691
692 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
693 mdelay(1);
694
695 /* This is balanced by the runtime put in sdhci_tasklet_finish */
696 pm_runtime_get_sync(host->mmc->parent);
697 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
698 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
699 ESDHC_MIX_CTRL_FBCLK_SEL;
700 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
701 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
702 dev_dbg(mmc_dev(host->mmc),
703 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
704 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
705 }
706
707 static void esdhc_request_done(struct mmc_request *mrq)
708 {
709 complete(&mrq->completion);
710 }
711
712 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
713 struct scatterlist *sg)
714 {
715 struct mmc_command cmd = {0};
716 struct mmc_request mrq = {NULL};
717 struct mmc_data data = {0};
718
719 cmd.opcode = opcode;
720 cmd.arg = 0;
721 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
722
723 data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
724 data.blocks = 1;
725 data.flags = MMC_DATA_READ;
726 data.sg = sg;
727 data.sg_len = 1;
728
729 mrq.cmd = &cmd;
730 mrq.cmd->mrq = &mrq;
731 mrq.data = &data;
732 mrq.data->mrq = &mrq;
733 mrq.cmd->data = mrq.data;
734
735 mrq.done = esdhc_request_done;
736 init_completion(&(mrq.completion));
737
738 spin_lock_irq(&host->lock);
739 host->mrq = &mrq;
740
741 sdhci_send_command(host, mrq.cmd);
742
743 spin_unlock_irq(&host->lock);
744
745 wait_for_completion(&mrq.completion);
746
747 if (cmd.error)
748 return cmd.error;
749 if (data.error)
750 return data.error;
751
752 return 0;
753 }
754
755 static void esdhc_post_tuning(struct sdhci_host *host)
756 {
757 u32 reg;
758
759 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
760 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
761 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
762 }
763
764 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
765 {
766 struct scatterlist sg;
767 char *tuning_pattern;
768 int min, max, avg, ret;
769
770 tuning_pattern = kmalloc(ESDHC_TUNING_BLOCK_PATTERN_LEN, GFP_KERNEL);
771 if (!tuning_pattern)
772 return -ENOMEM;
773
774 sg_init_one(&sg, tuning_pattern, ESDHC_TUNING_BLOCK_PATTERN_LEN);
775
776 /* find the mininum delay first which can pass tuning */
777 min = ESDHC_TUNE_CTRL_MIN;
778 while (min < ESDHC_TUNE_CTRL_MAX) {
779 esdhc_prepare_tuning(host, min);
780 if (!esdhc_send_tuning_cmd(host, opcode, &sg))
781 break;
782 min += ESDHC_TUNE_CTRL_STEP;
783 }
784
785 /* find the maxinum delay which can not pass tuning */
786 max = min + ESDHC_TUNE_CTRL_STEP;
787 while (max < ESDHC_TUNE_CTRL_MAX) {
788 esdhc_prepare_tuning(host, max);
789 if (esdhc_send_tuning_cmd(host, opcode, &sg)) {
790 max -= ESDHC_TUNE_CTRL_STEP;
791 break;
792 }
793 max += ESDHC_TUNE_CTRL_STEP;
794 }
795
796 /* use average delay to get the best timing */
797 avg = (min + max) / 2;
798 esdhc_prepare_tuning(host, avg);
799 ret = esdhc_send_tuning_cmd(host, opcode, &sg);
800 esdhc_post_tuning(host);
801
802 kfree(tuning_pattern);
803
804 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
805 ret ? "failed" : "passed", avg, ret);
806
807 return ret;
808 }
809
810 static int esdhc_change_pinstate(struct sdhci_host *host,
811 unsigned int uhs)
812 {
813 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
814 struct pltfm_imx_data *imx_data = pltfm_host->priv;
815 struct pinctrl_state *pinctrl;
816
817 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
818
819 if (IS_ERR(imx_data->pinctrl) ||
820 IS_ERR(imx_data->pins_default) ||
821 IS_ERR(imx_data->pins_100mhz) ||
822 IS_ERR(imx_data->pins_200mhz))
823 return -EINVAL;
824
825 switch (uhs) {
826 case MMC_TIMING_UHS_SDR50:
827 pinctrl = imx_data->pins_100mhz;
828 break;
829 case MMC_TIMING_UHS_SDR104:
830 case MMC_TIMING_MMC_HS200:
831 pinctrl = imx_data->pins_200mhz;
832 break;
833 default:
834 /* back to default state for other legacy timing */
835 pinctrl = imx_data->pins_default;
836 }
837
838 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
839 }
840
841 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
842 {
843 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
844 struct pltfm_imx_data *imx_data = pltfm_host->priv;
845 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
846
847 switch (timing) {
848 case MMC_TIMING_UHS_SDR12:
849 case MMC_TIMING_UHS_SDR25:
850 case MMC_TIMING_UHS_SDR50:
851 case MMC_TIMING_UHS_SDR104:
852 case MMC_TIMING_MMC_HS200:
853 break;
854 case MMC_TIMING_UHS_DDR50:
855 case MMC_TIMING_MMC_DDR52:
856 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
857 ESDHC_MIX_CTRL_DDREN,
858 host->ioaddr + ESDHC_MIX_CTRL);
859 imx_data->is_ddr = 1;
860 if (boarddata->delay_line) {
861 u32 v;
862 v = boarddata->delay_line <<
863 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
864 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
865 if (is_imx53_esdhc(imx_data))
866 v <<= 1;
867 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
868 }
869 break;
870 }
871
872 esdhc_change_pinstate(host, timing);
873 }
874
875 static void esdhc_reset(struct sdhci_host *host, u8 mask)
876 {
877 sdhci_reset(host, mask);
878
879 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
880 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
881 }
882
883 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
884 {
885 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
886 struct pltfm_imx_data *imx_data = pltfm_host->priv;
887
888 return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
889 }
890
891 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
892 {
893 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
894 struct pltfm_imx_data *imx_data = pltfm_host->priv;
895
896 /* use maximum timeout counter */
897 sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
898 SDHCI_TIMEOUT_CONTROL);
899 }
900
901 static struct sdhci_ops sdhci_esdhc_ops = {
902 .read_l = esdhc_readl_le,
903 .read_w = esdhc_readw_le,
904 .write_l = esdhc_writel_le,
905 .write_w = esdhc_writew_le,
906 .write_b = esdhc_writeb_le,
907 .set_clock = esdhc_pltfm_set_clock,
908 .get_max_clock = esdhc_pltfm_get_max_clock,
909 .get_min_clock = esdhc_pltfm_get_min_clock,
910 .get_max_timeout_count = esdhc_get_max_timeout_count,
911 .get_ro = esdhc_pltfm_get_ro,
912 .set_timeout = esdhc_set_timeout,
913 .set_bus_width = esdhc_pltfm_set_bus_width,
914 .set_uhs_signaling = esdhc_set_uhs_signaling,
915 .reset = esdhc_reset,
916 };
917
918 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
919 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
920 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
921 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
922 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
923 .ops = &sdhci_esdhc_ops,
924 };
925
926 #ifdef CONFIG_OF
927 static int
928 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
929 struct esdhc_platform_data *boarddata)
930 {
931 struct device_node *np = pdev->dev.of_node;
932
933 if (!np)
934 return -ENODEV;
935
936 if (of_get_property(np, "non-removable", NULL))
937 boarddata->cd_type = ESDHC_CD_PERMANENT;
938
939 if (of_get_property(np, "fsl,cd-controller", NULL))
940 boarddata->cd_type = ESDHC_CD_CONTROLLER;
941
942 if (of_get_property(np, "fsl,wp-controller", NULL))
943 boarddata->wp_type = ESDHC_WP_CONTROLLER;
944
945 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
946 if (gpio_is_valid(boarddata->cd_gpio))
947 boarddata->cd_type = ESDHC_CD_GPIO;
948
949 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
950 if (gpio_is_valid(boarddata->wp_gpio))
951 boarddata->wp_type = ESDHC_WP_GPIO;
952
953 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
954
955 of_property_read_u32(np, "max-frequency", &boarddata->f_max);
956
957 if (of_find_property(np, "no-1-8-v", NULL))
958 boarddata->support_vsel = false;
959 else
960 boarddata->support_vsel = true;
961
962 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
963 boarddata->delay_line = 0;
964
965 return 0;
966 }
967 #else
968 static inline int
969 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
970 struct esdhc_platform_data *boarddata)
971 {
972 return -ENODEV;
973 }
974 #endif
975
976 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
977 {
978 const struct of_device_id *of_id =
979 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
980 struct sdhci_pltfm_host *pltfm_host;
981 struct sdhci_host *host;
982 struct esdhc_platform_data *boarddata;
983 int err;
984 struct pltfm_imx_data *imx_data;
985
986 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
987 if (IS_ERR(host))
988 return PTR_ERR(host);
989
990 pltfm_host = sdhci_priv(host);
991
992 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
993 if (!imx_data) {
994 err = -ENOMEM;
995 goto free_sdhci;
996 }
997
998 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
999 pdev->id_entry->driver_data;
1000 pltfm_host->priv = imx_data;
1001
1002 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1003 if (IS_ERR(imx_data->clk_ipg)) {
1004 err = PTR_ERR(imx_data->clk_ipg);
1005 goto free_sdhci;
1006 }
1007
1008 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1009 if (IS_ERR(imx_data->clk_ahb)) {
1010 err = PTR_ERR(imx_data->clk_ahb);
1011 goto free_sdhci;
1012 }
1013
1014 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1015 if (IS_ERR(imx_data->clk_per)) {
1016 err = PTR_ERR(imx_data->clk_per);
1017 goto free_sdhci;
1018 }
1019
1020 pltfm_host->clk = imx_data->clk_per;
1021 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1022 clk_prepare_enable(imx_data->clk_per);
1023 clk_prepare_enable(imx_data->clk_ipg);
1024 clk_prepare_enable(imx_data->clk_ahb);
1025
1026 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1027 if (IS_ERR(imx_data->pinctrl)) {
1028 err = PTR_ERR(imx_data->pinctrl);
1029 goto disable_clk;
1030 }
1031
1032 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1033 PINCTRL_STATE_DEFAULT);
1034 if (IS_ERR(imx_data->pins_default)) {
1035 err = PTR_ERR(imx_data->pins_default);
1036 dev_err(mmc_dev(host->mmc), "could not get default state\n");
1037 goto disable_clk;
1038 }
1039
1040 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1041
1042 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1043 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1044 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1045 | SDHCI_QUIRK_BROKEN_ADMA;
1046
1047 /*
1048 * The imx6q ROM code will change the default watermark level setting
1049 * to something insane. Change it back here.
1050 */
1051 if (esdhc_is_usdhc(imx_data)) {
1052 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1053 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1054 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1055 }
1056
1057 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1058 sdhci_esdhc_ops.platform_execute_tuning =
1059 esdhc_executing_tuning;
1060
1061 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1062 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1063 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1064 host->ioaddr + ESDHC_TUNING_CTRL);
1065
1066 boarddata = &imx_data->boarddata;
1067 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
1068 if (!host->mmc->parent->platform_data) {
1069 dev_err(mmc_dev(host->mmc), "no board data!\n");
1070 err = -EINVAL;
1071 goto disable_clk;
1072 }
1073 imx_data->boarddata = *((struct esdhc_platform_data *)
1074 host->mmc->parent->platform_data);
1075 }
1076
1077 /* write_protect */
1078 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1079 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1080 if (err) {
1081 dev_err(mmc_dev(host->mmc),
1082 "failed to request write-protect gpio!\n");
1083 goto disable_clk;
1084 }
1085 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1086 }
1087
1088 /* card_detect */
1089 switch (boarddata->cd_type) {
1090 case ESDHC_CD_GPIO:
1091 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1092 if (err) {
1093 dev_err(mmc_dev(host->mmc),
1094 "failed to request card-detect gpio!\n");
1095 goto disable_clk;
1096 }
1097 /* fall through */
1098
1099 case ESDHC_CD_CONTROLLER:
1100 /* we have a working card_detect back */
1101 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1102 break;
1103
1104 case ESDHC_CD_PERMANENT:
1105 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1106 break;
1107
1108 case ESDHC_CD_NONE:
1109 break;
1110 }
1111
1112 switch (boarddata->max_bus_width) {
1113 case 8:
1114 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1115 break;
1116 case 4:
1117 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1118 break;
1119 case 1:
1120 default:
1121 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1122 break;
1123 }
1124
1125 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1126 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
1127 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1128 ESDHC_PINCTRL_STATE_100MHZ);
1129 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1130 ESDHC_PINCTRL_STATE_200MHZ);
1131 if (IS_ERR(imx_data->pins_100mhz) ||
1132 IS_ERR(imx_data->pins_200mhz)) {
1133 dev_warn(mmc_dev(host->mmc),
1134 "could not get ultra high speed state, work on normal mode\n");
1135 /* fall back to not support uhs by specify no 1.8v quirk */
1136 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1137 }
1138 } else {
1139 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1140 }
1141
1142 err = sdhci_add_host(host);
1143 if (err)
1144 goto disable_clk;
1145
1146 pm_runtime_set_active(&pdev->dev);
1147 pm_runtime_enable(&pdev->dev);
1148 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1149 pm_runtime_use_autosuspend(&pdev->dev);
1150 pm_suspend_ignore_children(&pdev->dev, 1);
1151
1152 return 0;
1153
1154 disable_clk:
1155 clk_disable_unprepare(imx_data->clk_per);
1156 clk_disable_unprepare(imx_data->clk_ipg);
1157 clk_disable_unprepare(imx_data->clk_ahb);
1158 free_sdhci:
1159 sdhci_pltfm_free(pdev);
1160 return err;
1161 }
1162
1163 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1164 {
1165 struct sdhci_host *host = platform_get_drvdata(pdev);
1166 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1167 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1168 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1169
1170 sdhci_remove_host(host, dead);
1171
1172 pm_runtime_dont_use_autosuspend(&pdev->dev);
1173 pm_runtime_disable(&pdev->dev);
1174
1175 if (!IS_ENABLED(CONFIG_PM_RUNTIME)) {
1176 clk_disable_unprepare(imx_data->clk_per);
1177 clk_disable_unprepare(imx_data->clk_ipg);
1178 clk_disable_unprepare(imx_data->clk_ahb);
1179 }
1180
1181 sdhci_pltfm_free(pdev);
1182
1183 return 0;
1184 }
1185
1186 #ifdef CONFIG_PM_RUNTIME
1187 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1188 {
1189 struct sdhci_host *host = dev_get_drvdata(dev);
1190 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1191 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1192 int ret;
1193
1194 ret = sdhci_runtime_suspend_host(host);
1195
1196 if (!sdhci_sdio_irq_enabled(host)) {
1197 clk_disable_unprepare(imx_data->clk_per);
1198 clk_disable_unprepare(imx_data->clk_ipg);
1199 }
1200 clk_disable_unprepare(imx_data->clk_ahb);
1201
1202 return ret;
1203 }
1204
1205 static int sdhci_esdhc_runtime_resume(struct device *dev)
1206 {
1207 struct sdhci_host *host = dev_get_drvdata(dev);
1208 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1209 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1210
1211 if (!sdhci_sdio_irq_enabled(host)) {
1212 clk_prepare_enable(imx_data->clk_per);
1213 clk_prepare_enable(imx_data->clk_ipg);
1214 }
1215 clk_prepare_enable(imx_data->clk_ahb);
1216
1217 return sdhci_runtime_resume_host(host);
1218 }
1219 #endif
1220
1221 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1222 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1223 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1224 sdhci_esdhc_runtime_resume, NULL)
1225 };
1226
1227 static struct platform_driver sdhci_esdhc_imx_driver = {
1228 .driver = {
1229 .name = "sdhci-esdhc-imx",
1230 .of_match_table = imx_esdhc_dt_ids,
1231 .pm = &sdhci_esdhc_pmops,
1232 },
1233 .id_table = imx_esdhc_devtype,
1234 .probe = sdhci_esdhc_imx_probe,
1235 .remove = sdhci_esdhc_imx_remove,
1236 };
1237
1238 module_platform_driver(sdhci_esdhc_imx_driver);
1239
1240 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1241 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1242 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.069632 seconds and 5 git commands to generate.