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mmc: sdhci-esdhci-imx: disable DLL delay line settings explicitly
[deliverable/linux.git] / drivers / mmc / host / sdhci-esdhc-imx.c
1 /*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <kernel@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include "sdhci-pltfm.h"
32 #include "sdhci-esdhc.h"
33
34 #define ESDHC_CTRL_D3CD 0x08
35 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
36 /* VENDOR SPEC register */
37 #define ESDHC_VENDOR_SPEC 0xc0
38 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
39 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
40 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
41 #define ESDHC_WTMK_LVL 0x44
42 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
43 #define ESDHC_MIX_CTRL 0x48
44 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
45 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
46 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
47 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
48 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
49 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
50 /* Bits 3 and 6 are not SDHCI standard definitions */
51 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
52 /* Tuning bits */
53 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
54
55 /* dll control register */
56 #define ESDHC_DLL_CTRL 0x60
57 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
58 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
59
60 /* tune control register */
61 #define ESDHC_TUNE_CTRL_STATUS 0x68
62 #define ESDHC_TUNE_CTRL_STEP 1
63 #define ESDHC_TUNE_CTRL_MIN 0
64 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
65
66 /* strobe dll register */
67 #define ESDHC_STROBE_DLL_CTRL 0x70
68 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
69 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
70 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
71
72 #define ESDHC_STROBE_DLL_STATUS 0x74
73 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
74 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
75
76 #define ESDHC_TUNING_CTRL 0xcc
77 #define ESDHC_STD_TUNING_EN (1 << 24)
78 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
79 #define ESDHC_TUNING_START_TAP 0x1
80 #define ESDHC_TUNING_STEP_MASK 0x00070000
81 #define ESDHC_TUNING_STEP_SHIFT 16
82
83 /* pinctrl state */
84 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
85 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
86
87 /*
88 * Our interpretation of the SDHCI_HOST_CONTROL register
89 */
90 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
91 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
92 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
93
94 /*
95 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
96 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
97 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
98 * Define this macro DMA error INT for fsl eSDHC
99 */
100 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
101
102 /*
103 * The CMDTYPE of the CMD register (offset 0xE) should be set to
104 * "11" when the STOP CMD12 is issued on imx53 to abort one
105 * open ended multi-blk IO. Otherwise the TC INT wouldn't
106 * be generated.
107 * In exact block transfer, the controller doesn't complete the
108 * operations automatically as required at the end of the
109 * transfer and remains on hold if the abort command is not sent.
110 * As a result, the TC flag is not asserted and SW received timeout
111 * exeception. Bit1 of Vendor Spec registor is used to fix it.
112 */
113 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
114 /*
115 * The flag enables the workaround for ESDHC errata ENGcm07207 which
116 * affects i.MX25 and i.MX35.
117 */
118 #define ESDHC_FLAG_ENGCM07207 BIT(2)
119 /*
120 * The flag tells that the ESDHC controller is an USDHC block that is
121 * integrated on the i.MX6 series.
122 */
123 #define ESDHC_FLAG_USDHC BIT(3)
124 /* The IP supports manual tuning process */
125 #define ESDHC_FLAG_MAN_TUNING BIT(4)
126 /* The IP supports standard tuning process */
127 #define ESDHC_FLAG_STD_TUNING BIT(5)
128 /* The IP has SDHCI_CAPABILITIES_1 register */
129 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
130 /*
131 * The IP has errata ERR004536
132 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
133 * when reading data from the card
134 */
135 #define ESDHC_FLAG_ERR004536 BIT(7)
136 /* The IP supports HS200 mode */
137 #define ESDHC_FLAG_HS200 BIT(8)
138 /* The IP supports HS400 mode */
139 #define ESDHC_FLAG_HS400 BIT(9)
140
141 /* A higher clock ferquency than this rate requires strobell dll control */
142 #define ESDHC_STROBE_DLL_CLK_FREQ 100000000
143
144 struct esdhc_soc_data {
145 u32 flags;
146 };
147
148 static struct esdhc_soc_data esdhc_imx25_data = {
149 .flags = ESDHC_FLAG_ENGCM07207,
150 };
151
152 static struct esdhc_soc_data esdhc_imx35_data = {
153 .flags = ESDHC_FLAG_ENGCM07207,
154 };
155
156 static struct esdhc_soc_data esdhc_imx51_data = {
157 .flags = 0,
158 };
159
160 static struct esdhc_soc_data esdhc_imx53_data = {
161 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
162 };
163
164 static struct esdhc_soc_data usdhc_imx6q_data = {
165 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
166 };
167
168 static struct esdhc_soc_data usdhc_imx6sl_data = {
169 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
170 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
171 | ESDHC_FLAG_HS200,
172 };
173
174 static struct esdhc_soc_data usdhc_imx6sx_data = {
175 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
176 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
177 };
178
179 static struct esdhc_soc_data usdhc_imx7d_data = {
180 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
181 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
182 | ESDHC_FLAG_HS400,
183 };
184
185 struct pltfm_imx_data {
186 u32 scratchpad;
187 struct pinctrl *pinctrl;
188 struct pinctrl_state *pins_default;
189 struct pinctrl_state *pins_100mhz;
190 struct pinctrl_state *pins_200mhz;
191 const struct esdhc_soc_data *socdata;
192 struct esdhc_platform_data boarddata;
193 struct clk *clk_ipg;
194 struct clk *clk_ahb;
195 struct clk *clk_per;
196 enum {
197 NO_CMD_PENDING, /* no multiblock command pending*/
198 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
199 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
200 } multiblock_status;
201 u32 is_ddr;
202 };
203
204 static const struct platform_device_id imx_esdhc_devtype[] = {
205 {
206 .name = "sdhci-esdhc-imx25",
207 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
208 }, {
209 .name = "sdhci-esdhc-imx35",
210 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
211 }, {
212 .name = "sdhci-esdhc-imx51",
213 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
214 }, {
215 /* sentinel */
216 }
217 };
218 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
219
220 static const struct of_device_id imx_esdhc_dt_ids[] = {
221 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
222 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
223 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
224 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
225 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
226 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
227 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
228 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
229 { /* sentinel */ }
230 };
231 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
232
233 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
234 {
235 return data->socdata == &esdhc_imx25_data;
236 }
237
238 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
239 {
240 return data->socdata == &esdhc_imx53_data;
241 }
242
243 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
244 {
245 return data->socdata == &usdhc_imx6q_data;
246 }
247
248 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
249 {
250 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
251 }
252
253 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
254 {
255 void __iomem *base = host->ioaddr + (reg & ~0x3);
256 u32 shift = (reg & 0x3) * 8;
257
258 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
259 }
260
261 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
262 {
263 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
264 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
265 u32 val = readl(host->ioaddr + reg);
266
267 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
268 u32 fsl_prss = val;
269 /* save the least 20 bits */
270 val = fsl_prss & 0x000FFFFF;
271 /* move dat[0-3] bits */
272 val |= (fsl_prss & 0x0F000000) >> 4;
273 /* move cmd line bit */
274 val |= (fsl_prss & 0x00800000) << 1;
275 }
276
277 if (unlikely(reg == SDHCI_CAPABILITIES)) {
278 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
279 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
280 val &= 0xffff0000;
281
282 /* In FSL esdhc IC module, only bit20 is used to indicate the
283 * ADMA2 capability of esdhc, but this bit is messed up on
284 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
285 * don't actually support ADMA2). So set the BROKEN_ADMA
286 * uirk on MX25/35 platforms.
287 */
288
289 if (val & SDHCI_CAN_DO_ADMA1) {
290 val &= ~SDHCI_CAN_DO_ADMA1;
291 val |= SDHCI_CAN_DO_ADMA2;
292 }
293 }
294
295 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
296 if (esdhc_is_usdhc(imx_data)) {
297 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
298 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
299 else
300 /* imx6q/dl does not have cap_1 register, fake one */
301 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
302 | SDHCI_SUPPORT_SDR50
303 | SDHCI_USE_SDR50_TUNING;
304
305 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
306 val |= SDHCI_SUPPORT_HS400;
307 }
308 }
309
310 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
311 val = 0;
312 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
313 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
314 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
315 }
316
317 if (unlikely(reg == SDHCI_INT_STATUS)) {
318 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
319 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
320 val |= SDHCI_INT_ADMA_ERROR;
321 }
322
323 /*
324 * mask off the interrupt we get in response to the manually
325 * sent CMD12
326 */
327 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
328 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
329 val &= ~SDHCI_INT_RESPONSE;
330 writel(SDHCI_INT_RESPONSE, host->ioaddr +
331 SDHCI_INT_STATUS);
332 imx_data->multiblock_status = NO_CMD_PENDING;
333 }
334 }
335
336 return val;
337 }
338
339 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
340 {
341 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
342 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
343 u32 data;
344
345 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
346 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
347 /*
348 * Clear and then set D3CD bit to avoid missing the
349 * card interrupt. This is a eSDHC controller problem
350 * so we need to apply the following workaround: clear
351 * and set D3CD bit will make eSDHC re-sample the card
352 * interrupt. In case a card interrupt was lost,
353 * re-sample it by the following steps.
354 */
355 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
356 data &= ~ESDHC_CTRL_D3CD;
357 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
358 data |= ESDHC_CTRL_D3CD;
359 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
360 }
361
362 if (val & SDHCI_INT_ADMA_ERROR) {
363 val &= ~SDHCI_INT_ADMA_ERROR;
364 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
365 }
366 }
367
368 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
369 && (reg == SDHCI_INT_STATUS)
370 && (val & SDHCI_INT_DATA_END))) {
371 u32 v;
372 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
373 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
374 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
375
376 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
377 {
378 /* send a manual CMD12 with RESPTYP=none */
379 data = MMC_STOP_TRANSMISSION << 24 |
380 SDHCI_CMD_ABORTCMD << 16;
381 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
382 imx_data->multiblock_status = WAIT_FOR_INT;
383 }
384 }
385
386 writel(val, host->ioaddr + reg);
387 }
388
389 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
390 {
391 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
392 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
393 u16 ret = 0;
394 u32 val;
395
396 if (unlikely(reg == SDHCI_HOST_VERSION)) {
397 reg ^= 2;
398 if (esdhc_is_usdhc(imx_data)) {
399 /*
400 * The usdhc register returns a wrong host version.
401 * Correct it here.
402 */
403 return SDHCI_SPEC_300;
404 }
405 }
406
407 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
408 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
409 if (val & ESDHC_VENDOR_SPEC_VSELECT)
410 ret |= SDHCI_CTRL_VDD_180;
411
412 if (esdhc_is_usdhc(imx_data)) {
413 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
414 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
415 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
416 /* the std tuning bits is in ACMD12_ERR for imx6sl */
417 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
418 }
419
420 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
421 ret |= SDHCI_CTRL_EXEC_TUNING;
422 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
423 ret |= SDHCI_CTRL_TUNED_CLK;
424
425 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
426
427 return ret;
428 }
429
430 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
431 if (esdhc_is_usdhc(imx_data)) {
432 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
433 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
434 /* Swap AC23 bit */
435 if (m & ESDHC_MIX_CTRL_AC23EN) {
436 ret &= ~ESDHC_MIX_CTRL_AC23EN;
437 ret |= SDHCI_TRNS_AUTO_CMD23;
438 }
439 } else {
440 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
441 }
442
443 return ret;
444 }
445
446 return readw(host->ioaddr + reg);
447 }
448
449 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
450 {
451 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
452 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
453 u32 new_val = 0;
454
455 switch (reg) {
456 case SDHCI_CLOCK_CONTROL:
457 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
458 if (val & SDHCI_CLOCK_CARD_EN)
459 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
460 else
461 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
462 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
463 return;
464 case SDHCI_HOST_CONTROL2:
465 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
466 if (val & SDHCI_CTRL_VDD_180)
467 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
468 else
469 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
470 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
471 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
472 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
473 if (val & SDHCI_CTRL_TUNED_CLK)
474 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
475 else
476 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
477 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
478 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
479 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
480 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
481 u32 tuning_ctrl;
482 if (val & SDHCI_CTRL_TUNED_CLK) {
483 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
484 } else {
485 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
486 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
487 }
488
489 if (val & SDHCI_CTRL_EXEC_TUNING) {
490 v |= ESDHC_MIX_CTRL_EXE_TUNE;
491 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
492 tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL);
493 tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP;
494 if (imx_data->boarddata.tuning_step) {
495 tuning_ctrl &= ~ESDHC_TUNING_STEP_MASK;
496 tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
497 }
498 writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
499 } else {
500 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
501 }
502
503 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
504 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
505 }
506 return;
507 case SDHCI_TRANSFER_MODE:
508 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
509 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
510 && (host->cmd->data->blocks > 1)
511 && (host->cmd->data->flags & MMC_DATA_READ)) {
512 u32 v;
513 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
514 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
515 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
516 }
517
518 if (esdhc_is_usdhc(imx_data)) {
519 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
520 /* Swap AC23 bit */
521 if (val & SDHCI_TRNS_AUTO_CMD23) {
522 val &= ~SDHCI_TRNS_AUTO_CMD23;
523 val |= ESDHC_MIX_CTRL_AC23EN;
524 }
525 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
526 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
527 } else {
528 /*
529 * Postpone this write, we must do it together with a
530 * command write that is down below.
531 */
532 imx_data->scratchpad = val;
533 }
534 return;
535 case SDHCI_COMMAND:
536 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
537 val |= SDHCI_CMD_ABORTCMD;
538
539 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
540 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
541 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
542
543 if (esdhc_is_usdhc(imx_data))
544 writel(val << 16,
545 host->ioaddr + SDHCI_TRANSFER_MODE);
546 else
547 writel(val << 16 | imx_data->scratchpad,
548 host->ioaddr + SDHCI_TRANSFER_MODE);
549 return;
550 case SDHCI_BLOCK_SIZE:
551 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
552 break;
553 }
554 esdhc_clrset_le(host, 0xffff, val, reg);
555 }
556
557 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
558 {
559 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
560 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
561 u32 new_val;
562 u32 mask;
563
564 switch (reg) {
565 case SDHCI_POWER_CONTROL:
566 /*
567 * FSL put some DMA bits here
568 * If your board has a regulator, code should be here
569 */
570 return;
571 case SDHCI_HOST_CONTROL:
572 /* FSL messed up here, so we need to manually compose it. */
573 new_val = val & SDHCI_CTRL_LED;
574 /* ensure the endianness */
575 new_val |= ESDHC_HOST_CONTROL_LE;
576 /* bits 8&9 are reserved on mx25 */
577 if (!is_imx25_esdhc(imx_data)) {
578 /* DMA mode bits are shifted */
579 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
580 }
581
582 /*
583 * Do not touch buswidth bits here. This is done in
584 * esdhc_pltfm_bus_width.
585 * Do not touch the D3CD bit either which is used for the
586 * SDIO interrupt errata workaround.
587 */
588 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
589
590 esdhc_clrset_le(host, mask, new_val, reg);
591 return;
592 }
593 esdhc_clrset_le(host, 0xff, val, reg);
594
595 /*
596 * The esdhc has a design violation to SDHC spec which tells
597 * that software reset should not affect card detection circuit.
598 * But esdhc clears its SYSCTL register bits [0..2] during the
599 * software reset. This will stop those clocks that card detection
600 * circuit relies on. To work around it, we turn the clocks on back
601 * to keep card detection circuit functional.
602 */
603 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
604 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
605 /*
606 * The reset on usdhc fails to clear MIX_CTRL register.
607 * Do it manually here.
608 */
609 if (esdhc_is_usdhc(imx_data)) {
610 /* the tuning bits should be kept during reset */
611 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
612 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
613 host->ioaddr + ESDHC_MIX_CTRL);
614 imx_data->is_ddr = 0;
615 }
616 }
617 }
618
619 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
620 {
621 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
622
623 return pltfm_host->clock;
624 }
625
626 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
627 {
628 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
629
630 return pltfm_host->clock / 256 / 16;
631 }
632
633 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
634 unsigned int clock)
635 {
636 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
637 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
638 unsigned int host_clock = pltfm_host->clock;
639 int pre_div = 2;
640 int div = 1;
641 u32 temp, val;
642
643 if (clock == 0) {
644 host->mmc->actual_clock = 0;
645
646 if (esdhc_is_usdhc(imx_data)) {
647 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
648 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
649 host->ioaddr + ESDHC_VENDOR_SPEC);
650 }
651 return;
652 }
653
654 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
655 pre_div = 1;
656
657 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
658 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
659 | ESDHC_CLOCK_MASK);
660 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
661
662 while (host_clock / pre_div / 16 > clock && pre_div < 256)
663 pre_div *= 2;
664
665 while (host_clock / pre_div / div > clock && div < 16)
666 div++;
667
668 host->mmc->actual_clock = host_clock / pre_div / div;
669 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
670 clock, host->mmc->actual_clock);
671
672 if (imx_data->is_ddr)
673 pre_div >>= 2;
674 else
675 pre_div >>= 1;
676 div--;
677
678 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
679 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
680 | (div << ESDHC_DIVIDER_SHIFT)
681 | (pre_div << ESDHC_PREDIV_SHIFT));
682 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
683
684 if (esdhc_is_usdhc(imx_data)) {
685 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
686 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
687 host->ioaddr + ESDHC_VENDOR_SPEC);
688 }
689
690 mdelay(1);
691 }
692
693 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
694 {
695 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
696 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
697 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
698
699 switch (boarddata->wp_type) {
700 case ESDHC_WP_GPIO:
701 return mmc_gpio_get_ro(host->mmc);
702 case ESDHC_WP_CONTROLLER:
703 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
704 SDHCI_WRITE_PROTECT);
705 case ESDHC_WP_NONE:
706 break;
707 }
708
709 return -ENOSYS;
710 }
711
712 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
713 {
714 u32 ctrl;
715
716 switch (width) {
717 case MMC_BUS_WIDTH_8:
718 ctrl = ESDHC_CTRL_8BITBUS;
719 break;
720 case MMC_BUS_WIDTH_4:
721 ctrl = ESDHC_CTRL_4BITBUS;
722 break;
723 default:
724 ctrl = 0;
725 break;
726 }
727
728 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
729 SDHCI_HOST_CONTROL);
730 }
731
732 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
733 {
734 u32 reg;
735
736 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
737 mdelay(1);
738
739 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
740 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
741 ESDHC_MIX_CTRL_FBCLK_SEL;
742 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
743 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
744 dev_dbg(mmc_dev(host->mmc),
745 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
746 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
747 }
748
749 static void esdhc_post_tuning(struct sdhci_host *host)
750 {
751 u32 reg;
752
753 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
754 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
755 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
756 }
757
758 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
759 {
760 int min, max, avg, ret;
761
762 /* find the mininum delay first which can pass tuning */
763 min = ESDHC_TUNE_CTRL_MIN;
764 while (min < ESDHC_TUNE_CTRL_MAX) {
765 esdhc_prepare_tuning(host, min);
766 if (!mmc_send_tuning(host->mmc, opcode, NULL))
767 break;
768 min += ESDHC_TUNE_CTRL_STEP;
769 }
770
771 /* find the maxinum delay which can not pass tuning */
772 max = min + ESDHC_TUNE_CTRL_STEP;
773 while (max < ESDHC_TUNE_CTRL_MAX) {
774 esdhc_prepare_tuning(host, max);
775 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
776 max -= ESDHC_TUNE_CTRL_STEP;
777 break;
778 }
779 max += ESDHC_TUNE_CTRL_STEP;
780 }
781
782 /* use average delay to get the best timing */
783 avg = (min + max) / 2;
784 esdhc_prepare_tuning(host, avg);
785 ret = mmc_send_tuning(host->mmc, opcode, NULL);
786 esdhc_post_tuning(host);
787
788 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
789 ret ? "failed" : "passed", avg, ret);
790
791 return ret;
792 }
793
794 static int esdhc_change_pinstate(struct sdhci_host *host,
795 unsigned int uhs)
796 {
797 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
798 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
799 struct pinctrl_state *pinctrl;
800
801 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
802
803 if (IS_ERR(imx_data->pinctrl) ||
804 IS_ERR(imx_data->pins_default) ||
805 IS_ERR(imx_data->pins_100mhz) ||
806 IS_ERR(imx_data->pins_200mhz))
807 return -EINVAL;
808
809 switch (uhs) {
810 case MMC_TIMING_UHS_SDR50:
811 pinctrl = imx_data->pins_100mhz;
812 break;
813 case MMC_TIMING_UHS_SDR104:
814 case MMC_TIMING_MMC_HS200:
815 case MMC_TIMING_MMC_HS400:
816 pinctrl = imx_data->pins_200mhz;
817 break;
818 default:
819 /* back to default state for other legacy timing */
820 pinctrl = imx_data->pins_default;
821 }
822
823 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
824 }
825
826 /*
827 * For HS400 eMMC, there is a data_strobe line, this signal is generated
828 * by the device and used for data output and CRC status response output
829 * in HS400 mode. The frequency of this signal follows the frequency of
830 * CLK generated by host. Host receive the data which is aligned to the
831 * edge of data_strobe line. Due to the time delay between CLK line and
832 * data_strobe line, if the delay time is larger than one clock cycle,
833 * then CLK and data_strobe line will misaligned, read error shows up.
834 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
835 * host should config the delay target.
836 */
837 static void esdhc_set_strobe_dll(struct sdhci_host *host)
838 {
839 u32 v;
840
841 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
842 /* force a reset on strobe dll */
843 writel(ESDHC_STROBE_DLL_CTRL_RESET,
844 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
845 /*
846 * enable strobe dll ctrl and adjust the delay target
847 * for the uSDHC loopback read clock
848 */
849 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
850 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
851 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
852 /* wait 1us to make sure strobe dll status register stable */
853 udelay(1);
854 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
855 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
856 dev_warn(mmc_dev(host->mmc),
857 "warning! HS400 strobe DLL status REF not lock!\n");
858 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
859 dev_warn(mmc_dev(host->mmc),
860 "warning! HS400 strobe DLL status SLV not lock!\n");
861 }
862 }
863
864 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
865 {
866 u32 m;
867 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
868 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
869 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
870
871 /* disable ddr mode and disable HS400 mode */
872 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
873 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
874 imx_data->is_ddr = 0;
875
876 switch (timing) {
877 case MMC_TIMING_UHS_SDR12:
878 case MMC_TIMING_UHS_SDR25:
879 case MMC_TIMING_UHS_SDR50:
880 case MMC_TIMING_UHS_SDR104:
881 case MMC_TIMING_MMC_HS200:
882 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
883 break;
884 case MMC_TIMING_UHS_DDR50:
885 case MMC_TIMING_MMC_DDR52:
886 m |= ESDHC_MIX_CTRL_DDREN;
887 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
888 imx_data->is_ddr = 1;
889 if (boarddata->delay_line) {
890 u32 v;
891 v = boarddata->delay_line <<
892 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
893 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
894 if (is_imx53_esdhc(imx_data))
895 v <<= 1;
896 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
897 }
898 break;
899 case MMC_TIMING_MMC_HS400:
900 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
901 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
902 imx_data->is_ddr = 1;
903 esdhc_set_strobe_dll(host);
904 break;
905 }
906
907 esdhc_change_pinstate(host, timing);
908 }
909
910 static void esdhc_reset(struct sdhci_host *host, u8 mask)
911 {
912 sdhci_reset(host, mask);
913
914 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
915 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
916 }
917
918 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
919 {
920 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
921 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
922
923 return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
924 }
925
926 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
927 {
928 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
929 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
930
931 /* use maximum timeout counter */
932 sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
933 SDHCI_TIMEOUT_CONTROL);
934 }
935
936 static struct sdhci_ops sdhci_esdhc_ops = {
937 .read_l = esdhc_readl_le,
938 .read_w = esdhc_readw_le,
939 .write_l = esdhc_writel_le,
940 .write_w = esdhc_writew_le,
941 .write_b = esdhc_writeb_le,
942 .set_clock = esdhc_pltfm_set_clock,
943 .get_max_clock = esdhc_pltfm_get_max_clock,
944 .get_min_clock = esdhc_pltfm_get_min_clock,
945 .get_max_timeout_count = esdhc_get_max_timeout_count,
946 .get_ro = esdhc_pltfm_get_ro,
947 .set_timeout = esdhc_set_timeout,
948 .set_bus_width = esdhc_pltfm_set_bus_width,
949 .set_uhs_signaling = esdhc_set_uhs_signaling,
950 .reset = esdhc_reset,
951 };
952
953 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
954 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
955 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
956 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
957 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
958 .ops = &sdhci_esdhc_ops,
959 };
960
961 #ifdef CONFIG_OF
962 static int
963 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
964 struct sdhci_host *host,
965 struct pltfm_imx_data *imx_data)
966 {
967 struct device_node *np = pdev->dev.of_node;
968 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
969 int ret;
970
971 if (of_get_property(np, "fsl,wp-controller", NULL))
972 boarddata->wp_type = ESDHC_WP_CONTROLLER;
973
974 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
975 if (gpio_is_valid(boarddata->wp_gpio))
976 boarddata->wp_type = ESDHC_WP_GPIO;
977
978 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
979
980 if (of_find_property(np, "no-1-8-v", NULL))
981 boarddata->support_vsel = false;
982 else
983 boarddata->support_vsel = true;
984
985 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
986 boarddata->delay_line = 0;
987
988 mmc_of_parse_voltage(np, &host->ocr_mask);
989
990 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
991 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
992 !IS_ERR(imx_data->pins_default)) {
993 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
994 ESDHC_PINCTRL_STATE_100MHZ);
995 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
996 ESDHC_PINCTRL_STATE_200MHZ);
997 if (IS_ERR(imx_data->pins_100mhz) ||
998 IS_ERR(imx_data->pins_200mhz)) {
999 dev_warn(mmc_dev(host->mmc),
1000 "could not get ultra high speed state, work on normal mode\n");
1001 /*
1002 * fall back to not support uhs by specify no 1.8v quirk
1003 */
1004 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1005 }
1006 } else {
1007 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1008 }
1009
1010 /* call to generic mmc_of_parse to support additional capabilities */
1011 ret = mmc_of_parse(host->mmc);
1012 if (ret)
1013 return ret;
1014
1015 if (mmc_gpio_get_cd(host->mmc) >= 0)
1016 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1017
1018 return 0;
1019 }
1020 #else
1021 static inline int
1022 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1023 struct sdhci_host *host,
1024 struct pltfm_imx_data *imx_data)
1025 {
1026 return -ENODEV;
1027 }
1028 #endif
1029
1030 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1031 struct sdhci_host *host,
1032 struct pltfm_imx_data *imx_data)
1033 {
1034 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1035 int err;
1036
1037 if (!host->mmc->parent->platform_data) {
1038 dev_err(mmc_dev(host->mmc), "no board data!\n");
1039 return -EINVAL;
1040 }
1041
1042 imx_data->boarddata = *((struct esdhc_platform_data *)
1043 host->mmc->parent->platform_data);
1044 /* write_protect */
1045 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1046 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1047 if (err) {
1048 dev_err(mmc_dev(host->mmc),
1049 "failed to request write-protect gpio!\n");
1050 return err;
1051 }
1052 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1053 }
1054
1055 /* card_detect */
1056 switch (boarddata->cd_type) {
1057 case ESDHC_CD_GPIO:
1058 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1059 if (err) {
1060 dev_err(mmc_dev(host->mmc),
1061 "failed to request card-detect gpio!\n");
1062 return err;
1063 }
1064 /* fall through */
1065
1066 case ESDHC_CD_CONTROLLER:
1067 /* we have a working card_detect back */
1068 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1069 break;
1070
1071 case ESDHC_CD_PERMANENT:
1072 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1073 break;
1074
1075 case ESDHC_CD_NONE:
1076 break;
1077 }
1078
1079 switch (boarddata->max_bus_width) {
1080 case 8:
1081 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1082 break;
1083 case 4:
1084 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1085 break;
1086 case 1:
1087 default:
1088 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1089 break;
1090 }
1091
1092 return 0;
1093 }
1094
1095 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1096 {
1097 const struct of_device_id *of_id =
1098 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1099 struct sdhci_pltfm_host *pltfm_host;
1100 struct sdhci_host *host;
1101 int err;
1102 struct pltfm_imx_data *imx_data;
1103
1104 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1105 sizeof(*imx_data));
1106 if (IS_ERR(host))
1107 return PTR_ERR(host);
1108
1109 pltfm_host = sdhci_priv(host);
1110
1111 imx_data = sdhci_pltfm_priv(pltfm_host);
1112
1113 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1114 pdev->id_entry->driver_data;
1115
1116 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1117 if (IS_ERR(imx_data->clk_ipg)) {
1118 err = PTR_ERR(imx_data->clk_ipg);
1119 goto free_sdhci;
1120 }
1121
1122 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1123 if (IS_ERR(imx_data->clk_ahb)) {
1124 err = PTR_ERR(imx_data->clk_ahb);
1125 goto free_sdhci;
1126 }
1127
1128 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1129 if (IS_ERR(imx_data->clk_per)) {
1130 err = PTR_ERR(imx_data->clk_per);
1131 goto free_sdhci;
1132 }
1133
1134 pltfm_host->clk = imx_data->clk_per;
1135 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1136 clk_prepare_enable(imx_data->clk_per);
1137 clk_prepare_enable(imx_data->clk_ipg);
1138 clk_prepare_enable(imx_data->clk_ahb);
1139
1140 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1141 if (IS_ERR(imx_data->pinctrl)) {
1142 err = PTR_ERR(imx_data->pinctrl);
1143 goto disable_clk;
1144 }
1145
1146 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1147 PINCTRL_STATE_DEFAULT);
1148 if (IS_ERR(imx_data->pins_default))
1149 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1150
1151 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1152 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1153 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1154 | SDHCI_QUIRK_BROKEN_ADMA;
1155
1156 /*
1157 * The imx6q ROM code will change the default watermark level setting
1158 * to something insane. Change it back here.
1159 */
1160 if (esdhc_is_usdhc(imx_data)) {
1161 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1162
1163 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1164 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1165
1166 /*
1167 * ROM code will change the bit burst_length_enable setting
1168 * to zero if this usdhc is choosed to boot system. Change
1169 * it back here, otherwise it will impact the performance a
1170 * lot. This bit is used to enable/disable the burst length
1171 * for the external AHB2AXI bridge, it's usefully especially
1172 * for INCR transfer because without burst length indicator,
1173 * the AHB2AXI bridge does not know the burst length in
1174 * advance. And without burst length indicator, AHB INCR
1175 * transfer can only be converted to singles on the AXI side.
1176 */
1177 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1178 | ESDHC_BURST_LEN_EN_INCR,
1179 host->ioaddr + SDHCI_HOST_CONTROL);
1180
1181 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1182 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1183
1184 /*
1185 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1186 * TO1.1, it's harmless for MX6SL
1187 */
1188 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1189 host->ioaddr + 0x6c);
1190
1191 /* disable DLL_CTRL delay line settings */
1192 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1193 }
1194
1195 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1196 sdhci_esdhc_ops.platform_execute_tuning =
1197 esdhc_executing_tuning;
1198
1199 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1200 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1201 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1202 host->ioaddr + ESDHC_TUNING_CTRL);
1203
1204 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1205 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1206
1207 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1208 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1209
1210 if (of_id)
1211 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1212 else
1213 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1214 if (err)
1215 goto disable_clk;
1216
1217 err = sdhci_add_host(host);
1218 if (err)
1219 goto disable_clk;
1220
1221 pm_runtime_set_active(&pdev->dev);
1222 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1223 pm_runtime_use_autosuspend(&pdev->dev);
1224 pm_suspend_ignore_children(&pdev->dev, 1);
1225 pm_runtime_enable(&pdev->dev);
1226
1227 return 0;
1228
1229 disable_clk:
1230 clk_disable_unprepare(imx_data->clk_per);
1231 clk_disable_unprepare(imx_data->clk_ipg);
1232 clk_disable_unprepare(imx_data->clk_ahb);
1233 free_sdhci:
1234 sdhci_pltfm_free(pdev);
1235 return err;
1236 }
1237
1238 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1239 {
1240 struct sdhci_host *host = platform_get_drvdata(pdev);
1241 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1242 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1243 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1244
1245 pm_runtime_get_sync(&pdev->dev);
1246 pm_runtime_disable(&pdev->dev);
1247 pm_runtime_put_noidle(&pdev->dev);
1248
1249 sdhci_remove_host(host, dead);
1250
1251 clk_disable_unprepare(imx_data->clk_per);
1252 clk_disable_unprepare(imx_data->clk_ipg);
1253 clk_disable_unprepare(imx_data->clk_ahb);
1254
1255 sdhci_pltfm_free(pdev);
1256
1257 return 0;
1258 }
1259
1260 #ifdef CONFIG_PM
1261 static int sdhci_esdhc_suspend(struct device *dev)
1262 {
1263 return sdhci_pltfm_suspend(dev);
1264 }
1265
1266 static int sdhci_esdhc_resume(struct device *dev)
1267 {
1268 struct sdhci_host *host = dev_get_drvdata(dev);
1269 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1270 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1271
1272 /* restore watermark setting in case it's lost in low power mode */
1273 if (esdhc_is_usdhc(imx_data))
1274 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1275
1276 return sdhci_pltfm_resume(dev);
1277 }
1278
1279 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1280 {
1281 struct sdhci_host *host = dev_get_drvdata(dev);
1282 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1283 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1284 int ret;
1285
1286 ret = sdhci_runtime_suspend_host(host);
1287
1288 if (!sdhci_sdio_irq_enabled(host)) {
1289 clk_disable_unprepare(imx_data->clk_per);
1290 clk_disable_unprepare(imx_data->clk_ipg);
1291 }
1292 clk_disable_unprepare(imx_data->clk_ahb);
1293
1294 return ret;
1295 }
1296
1297 static int sdhci_esdhc_runtime_resume(struct device *dev)
1298 {
1299 struct sdhci_host *host = dev_get_drvdata(dev);
1300 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1301 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1302
1303 if (!sdhci_sdio_irq_enabled(host)) {
1304 clk_prepare_enable(imx_data->clk_per);
1305 clk_prepare_enable(imx_data->clk_ipg);
1306 }
1307 clk_prepare_enable(imx_data->clk_ahb);
1308
1309 return sdhci_runtime_resume_host(host);
1310 }
1311 #endif
1312
1313 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1314 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1315 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1316 sdhci_esdhc_runtime_resume, NULL)
1317 };
1318
1319 static struct platform_driver sdhci_esdhc_imx_driver = {
1320 .driver = {
1321 .name = "sdhci-esdhc-imx",
1322 .of_match_table = imx_esdhc_dt_ids,
1323 .pm = &sdhci_esdhc_pmops,
1324 },
1325 .id_table = imx_esdhc_devtype,
1326 .probe = sdhci_esdhc_imx_probe,
1327 .remove = sdhci_esdhc_imx_remove,
1328 };
1329
1330 module_platform_driver(sdhci_esdhc_imx_driver);
1331
1332 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1333 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1334 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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