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Merge git://git.kernel.org/pub/scm/linux/kernel/git/aia21/ntfs
[deliverable/linux.git] / drivers / mmc / host / sdhci-msm.c
1 /*
2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
3 *
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/slab.h>
22
23 #include "sdhci-pltfm.h"
24
25 #define CORE_HC_MODE 0x78
26 #define HC_MODE_EN 0x1
27 #define CORE_POWER 0x0
28 #define CORE_SW_RST BIT(7)
29
30 #define MAX_PHASES 16
31 #define CORE_DLL_LOCK BIT(7)
32 #define CORE_DLL_EN BIT(16)
33 #define CORE_CDR_EN BIT(17)
34 #define CORE_CK_OUT_EN BIT(18)
35 #define CORE_CDR_EXT_EN BIT(19)
36 #define CORE_DLL_PDN BIT(29)
37 #define CORE_DLL_RST BIT(30)
38 #define CORE_DLL_CONFIG 0x100
39 #define CORE_DLL_STATUS 0x108
40
41 #define CORE_VENDOR_SPEC 0x10c
42 #define CORE_CLK_PWRSAVE BIT(1)
43
44 #define CDR_SELEXT_SHIFT 20
45 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
46 #define CMUX_SHIFT_PHASE_SHIFT 24
47 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
48
49 struct sdhci_msm_host {
50 struct platform_device *pdev;
51 void __iomem *core_mem; /* MSM SDCC mapped address */
52 struct clk *clk; /* main SD/MMC bus clock */
53 struct clk *pclk; /* SDHC peripheral bus clock */
54 struct clk *bus_clk; /* SDHC bus voter clock */
55 struct mmc_host *mmc;
56 struct sdhci_pltfm_data sdhci_msm_pdata;
57 };
58
59 /* Platform specific tuning */
60 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
61 {
62 u32 wait_cnt = 50;
63 u8 ck_out_en;
64 struct mmc_host *mmc = host->mmc;
65
66 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
67 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
68 CORE_CK_OUT_EN);
69
70 while (ck_out_en != poll) {
71 if (--wait_cnt == 0) {
72 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
73 mmc_hostname(mmc), poll);
74 return -ETIMEDOUT;
75 }
76 udelay(1);
77
78 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
79 CORE_CK_OUT_EN);
80 }
81
82 return 0;
83 }
84
85 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
86 {
87 int rc;
88 static const u8 grey_coded_phase_table[] = {
89 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
90 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
91 };
92 unsigned long flags;
93 u32 config;
94 struct mmc_host *mmc = host->mmc;
95
96 spin_lock_irqsave(&host->lock, flags);
97
98 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
99 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
100 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
101 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
102
103 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
104 rc = msm_dll_poll_ck_out_en(host, 0);
105 if (rc)
106 goto err_out;
107
108 /*
109 * Write the selected DLL clock output phase (0 ... 15)
110 * to CDR_SELEXT bit field of DLL_CONFIG register.
111 */
112 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
113 config &= ~CDR_SELEXT_MASK;
114 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
115 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
116
117 /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
118 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
119 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
120
121 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
122 rc = msm_dll_poll_ck_out_en(host, 1);
123 if (rc)
124 goto err_out;
125
126 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
127 config |= CORE_CDR_EN;
128 config &= ~CORE_CDR_EXT_EN;
129 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
130 goto out;
131
132 err_out:
133 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
134 mmc_hostname(mmc), phase);
135 out:
136 spin_unlock_irqrestore(&host->lock, flags);
137 return rc;
138 }
139
140 /*
141 * Find out the greatest range of consecuitive selected
142 * DLL clock output phases that can be used as sampling
143 * setting for SD3.0 UHS-I card read operation (in SDR104
144 * timing mode) or for eMMC4.5 card read operation (in HS200
145 * timing mode).
146 * Select the 3/4 of the range and configure the DLL with the
147 * selected DLL clock output phase.
148 */
149
150 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
151 u8 *phase_table, u8 total_phases)
152 {
153 int ret;
154 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
155 u8 phases_per_row[MAX_PHASES] = { 0 };
156 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
157 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
158 bool phase_0_found = false, phase_15_found = false;
159 struct mmc_host *mmc = host->mmc;
160
161 if (!total_phases || (total_phases > MAX_PHASES)) {
162 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
163 mmc_hostname(mmc), total_phases);
164 return -EINVAL;
165 }
166
167 for (cnt = 0; cnt < total_phases; cnt++) {
168 ranges[row_index][col_index] = phase_table[cnt];
169 phases_per_row[row_index] += 1;
170 col_index++;
171
172 if ((cnt + 1) == total_phases) {
173 continue;
174 /* check if next phase in phase_table is consecutive or not */
175 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
176 row_index++;
177 col_index = 0;
178 }
179 }
180
181 if (row_index >= MAX_PHASES)
182 return -EINVAL;
183
184 /* Check if phase-0 is present in first valid window? */
185 if (!ranges[0][0]) {
186 phase_0_found = true;
187 phase_0_raw_index = 0;
188 /* Check if cycle exist between 2 valid windows */
189 for (cnt = 1; cnt <= row_index; cnt++) {
190 if (phases_per_row[cnt]) {
191 for (i = 0; i < phases_per_row[cnt]; i++) {
192 if (ranges[cnt][i] == 15) {
193 phase_15_found = true;
194 phase_15_raw_index = cnt;
195 break;
196 }
197 }
198 }
199 }
200 }
201
202 /* If 2 valid windows form cycle then merge them as single window */
203 if (phase_0_found && phase_15_found) {
204 /* number of phases in raw where phase 0 is present */
205 u8 phases_0 = phases_per_row[phase_0_raw_index];
206 /* number of phases in raw where phase 15 is present */
207 u8 phases_15 = phases_per_row[phase_15_raw_index];
208
209 if (phases_0 + phases_15 >= MAX_PHASES)
210 /*
211 * If there are more than 1 phase windows then total
212 * number of phases in both the windows should not be
213 * more than or equal to MAX_PHASES.
214 */
215 return -EINVAL;
216
217 /* Merge 2 cyclic windows */
218 i = phases_15;
219 for (cnt = 0; cnt < phases_0; cnt++) {
220 ranges[phase_15_raw_index][i] =
221 ranges[phase_0_raw_index][cnt];
222 if (++i >= MAX_PHASES)
223 break;
224 }
225
226 phases_per_row[phase_0_raw_index] = 0;
227 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
228 }
229
230 for (cnt = 0; cnt <= row_index; cnt++) {
231 if (phases_per_row[cnt] > curr_max) {
232 curr_max = phases_per_row[cnt];
233 selected_row_index = cnt;
234 }
235 }
236
237 i = (curr_max * 3) / 4;
238 if (i)
239 i--;
240
241 ret = ranges[selected_row_index][i];
242
243 if (ret >= MAX_PHASES) {
244 ret = -EINVAL;
245 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
246 mmc_hostname(mmc), ret);
247 }
248
249 return ret;
250 }
251
252 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
253 {
254 u32 mclk_freq = 0, config;
255
256 /* Program the MCLK value to MCLK_FREQ bit field */
257 if (host->clock <= 112000000)
258 mclk_freq = 0;
259 else if (host->clock <= 125000000)
260 mclk_freq = 1;
261 else if (host->clock <= 137000000)
262 mclk_freq = 2;
263 else if (host->clock <= 150000000)
264 mclk_freq = 3;
265 else if (host->clock <= 162000000)
266 mclk_freq = 4;
267 else if (host->clock <= 175000000)
268 mclk_freq = 5;
269 else if (host->clock <= 187000000)
270 mclk_freq = 6;
271 else if (host->clock <= 200000000)
272 mclk_freq = 7;
273
274 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
275 config &= ~CMUX_SHIFT_PHASE_MASK;
276 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
277 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
278 }
279
280 /* Initialize the DLL (Programmable Delay Line) */
281 static int msm_init_cm_dll(struct sdhci_host *host)
282 {
283 struct mmc_host *mmc = host->mmc;
284 int wait_cnt = 50;
285 unsigned long flags;
286
287 spin_lock_irqsave(&host->lock, flags);
288
289 /*
290 * Make sure that clock is always enabled when DLL
291 * tuning is in progress. Keeping PWRSAVE ON may
292 * turn off the clock.
293 */
294 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
295 & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
296
297 /* Write 1 to DLL_RST bit of DLL_CONFIG register */
298 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
299 | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
300
301 /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
302 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
303 | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
304 msm_cm_dll_set_freq(host);
305
306 /* Write 0 to DLL_RST bit of DLL_CONFIG register */
307 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
308 & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
309
310 /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
311 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
312 & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
313
314 /* Set DLL_EN bit to 1. */
315 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
316 | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
317
318 /* Set CK_OUT_EN bit to 1. */
319 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
320 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
321
322 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
323 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
324 CORE_DLL_LOCK)) {
325 /* max. wait for 50us sec for LOCK bit to be set */
326 if (--wait_cnt == 0) {
327 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
328 mmc_hostname(mmc));
329 spin_unlock_irqrestore(&host->lock, flags);
330 return -ETIMEDOUT;
331 }
332 udelay(1);
333 }
334
335 spin_unlock_irqrestore(&host->lock, flags);
336 return 0;
337 }
338
339 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
340 {
341 int tuning_seq_cnt = 3;
342 u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
343 const u8 *tuning_block_pattern = tuning_blk_pattern_4bit;
344 int size = sizeof(tuning_blk_pattern_4bit);
345 int rc;
346 struct mmc_host *mmc = host->mmc;
347 struct mmc_ios ios = host->mmc->ios;
348
349 /*
350 * Tuning is required for SDR104, HS200 and HS400 cards and
351 * if clock frequency is greater than 100MHz in these modes.
352 */
353 if (host->clock <= 100 * 1000 * 1000 ||
354 !((ios.timing == MMC_TIMING_MMC_HS200) ||
355 (ios.timing == MMC_TIMING_UHS_SDR104)))
356 return 0;
357
358 if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) &&
359 (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) {
360 tuning_block_pattern = tuning_blk_pattern_8bit;
361 size = sizeof(tuning_blk_pattern_8bit);
362 }
363
364 data_buf = kmalloc(size, GFP_KERNEL);
365 if (!data_buf)
366 return -ENOMEM;
367
368 retry:
369 /* First of all reset the tuning block */
370 rc = msm_init_cm_dll(host);
371 if (rc)
372 goto out;
373
374 phase = 0;
375 do {
376 struct mmc_command cmd = { 0 };
377 struct mmc_data data = { 0 };
378 struct mmc_request mrq = {
379 .cmd = &cmd,
380 .data = &data
381 };
382 struct scatterlist sg;
383
384 /* Set the phase in delay line hw block */
385 rc = msm_config_cm_dll_phase(host, phase);
386 if (rc)
387 goto out;
388
389 cmd.opcode = opcode;
390 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
391
392 data.blksz = size;
393 data.blocks = 1;
394 data.flags = MMC_DATA_READ;
395 data.timeout_ns = NSEC_PER_SEC; /* 1 second */
396
397 data.sg = &sg;
398 data.sg_len = 1;
399 sg_init_one(&sg, data_buf, size);
400 memset(data_buf, 0, size);
401 mmc_wait_for_req(mmc, &mrq);
402
403 if (!cmd.error && !data.error &&
404 !memcmp(data_buf, tuning_block_pattern, size)) {
405 /* Tuning is successful at this tuning point */
406 tuned_phases[tuned_phase_cnt++] = phase;
407 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
408 mmc_hostname(mmc), phase);
409 }
410 } while (++phase < ARRAY_SIZE(tuned_phases));
411
412 if (tuned_phase_cnt) {
413 rc = msm_find_most_appropriate_phase(host, tuned_phases,
414 tuned_phase_cnt);
415 if (rc < 0)
416 goto out;
417 else
418 phase = rc;
419
420 /*
421 * Finally set the selected phase in delay
422 * line hw block.
423 */
424 rc = msm_config_cm_dll_phase(host, phase);
425 if (rc)
426 goto out;
427 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
428 mmc_hostname(mmc), phase);
429 } else {
430 if (--tuning_seq_cnt)
431 goto retry;
432 /* Tuning failed */
433 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
434 mmc_hostname(mmc));
435 rc = -EIO;
436 }
437
438 out:
439 kfree(data_buf);
440 return rc;
441 }
442
443 static const struct of_device_id sdhci_msm_dt_match[] = {
444 { .compatible = "qcom,sdhci-msm-v4" },
445 {},
446 };
447
448 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
449
450 static struct sdhci_ops sdhci_msm_ops = {
451 .platform_execute_tuning = sdhci_msm_execute_tuning,
452 .reset = sdhci_reset,
453 .set_clock = sdhci_set_clock,
454 .set_bus_width = sdhci_set_bus_width,
455 .set_uhs_signaling = sdhci_set_uhs_signaling,
456 };
457
458 static int sdhci_msm_probe(struct platform_device *pdev)
459 {
460 struct sdhci_host *host;
461 struct sdhci_pltfm_host *pltfm_host;
462 struct sdhci_msm_host *msm_host;
463 struct resource *core_memres;
464 int ret;
465 u16 host_version;
466
467 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
468 if (!msm_host)
469 return -ENOMEM;
470
471 msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops;
472 host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0);
473 if (IS_ERR(host))
474 return PTR_ERR(host);
475
476 pltfm_host = sdhci_priv(host);
477 pltfm_host->priv = msm_host;
478 msm_host->mmc = host->mmc;
479 msm_host->pdev = pdev;
480
481 ret = mmc_of_parse(host->mmc);
482 if (ret)
483 goto pltfm_free;
484
485 sdhci_get_of_property(pdev);
486
487 /* Setup SDCC bus voter clock. */
488 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
489 if (!IS_ERR(msm_host->bus_clk)) {
490 /* Vote for max. clk rate for max. performance */
491 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
492 if (ret)
493 goto pltfm_free;
494 ret = clk_prepare_enable(msm_host->bus_clk);
495 if (ret)
496 goto pltfm_free;
497 }
498
499 /* Setup main peripheral bus clock */
500 msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
501 if (IS_ERR(msm_host->pclk)) {
502 ret = PTR_ERR(msm_host->pclk);
503 dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
504 goto bus_clk_disable;
505 }
506
507 ret = clk_prepare_enable(msm_host->pclk);
508 if (ret)
509 goto bus_clk_disable;
510
511 /* Setup SDC MMC clock */
512 msm_host->clk = devm_clk_get(&pdev->dev, "core");
513 if (IS_ERR(msm_host->clk)) {
514 ret = PTR_ERR(msm_host->clk);
515 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
516 goto pclk_disable;
517 }
518
519 ret = clk_prepare_enable(msm_host->clk);
520 if (ret)
521 goto pclk_disable;
522
523 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
524 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
525
526 if (IS_ERR(msm_host->core_mem)) {
527 dev_err(&pdev->dev, "Failed to remap registers\n");
528 ret = PTR_ERR(msm_host->core_mem);
529 goto clk_disable;
530 }
531
532 /* Reset the core and Enable SDHC mode */
533 writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
534 CORE_SW_RST, msm_host->core_mem + CORE_POWER);
535
536 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
537 usleep_range(1000, 5000);
538 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
539 dev_err(&pdev->dev, "Stuck in reset\n");
540 ret = -ETIMEDOUT;
541 goto clk_disable;
542 }
543
544 /* Set HC_MODE_EN bit in HC_MODE register */
545 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
546
547 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
548 host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;
549
550 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
551 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
552 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
553 SDHCI_VENDOR_VER_SHIFT));
554
555 ret = sdhci_add_host(host);
556 if (ret)
557 goto clk_disable;
558
559 return 0;
560
561 clk_disable:
562 clk_disable_unprepare(msm_host->clk);
563 pclk_disable:
564 clk_disable_unprepare(msm_host->pclk);
565 bus_clk_disable:
566 if (!IS_ERR(msm_host->bus_clk))
567 clk_disable_unprepare(msm_host->bus_clk);
568 pltfm_free:
569 sdhci_pltfm_free(pdev);
570 return ret;
571 }
572
573 static int sdhci_msm_remove(struct platform_device *pdev)
574 {
575 struct sdhci_host *host = platform_get_drvdata(pdev);
576 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
577 struct sdhci_msm_host *msm_host = pltfm_host->priv;
578 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
579 0xffffffff);
580
581 sdhci_remove_host(host, dead);
582 sdhci_pltfm_free(pdev);
583 clk_disable_unprepare(msm_host->clk);
584 clk_disable_unprepare(msm_host->pclk);
585 if (!IS_ERR(msm_host->bus_clk))
586 clk_disable_unprepare(msm_host->bus_clk);
587 return 0;
588 }
589
590 static struct platform_driver sdhci_msm_driver = {
591 .probe = sdhci_msm_probe,
592 .remove = sdhci_msm_remove,
593 .driver = {
594 .name = "sdhci_msm",
595 .of_match_table = sdhci_msm_dt_match,
596 },
597 };
598
599 module_platform_driver(sdhci_msm_driver);
600
601 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
602 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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