drivers/mmc/host/sdhci-pxav3.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Mingwei Wang <mwwang@marvell.com>
   6  *              Philip Rakity <prakity@marvell.com>
   7  *              Mark Brown <markb@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/slot-gpio.h>
  28 #include <linux/platform_data/pxa_sdhci.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_gpio.h>
  35
  36 #include "sdhci.h"
  37 #include "sdhci-pltfm.h"
  38
  39 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
  40 #define SDCLK_SEL       0x100
  41 #define SDCLK_DELAY_SHIFT       9
  42 #define SDCLK_DELAY_MASK        0x1f
  43
  44 #define SD_CFG_FIFO_PARAM       0x100
  45 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
  46 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
  47 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
  48
  49 #define SD_SPI_MODE          0x108
  50 #define SD_CE_ATA_1          0x10C
  51
  52 #define SD_CE_ATA_2          0x10E
  53 #define SDCE_MISC_INT           (1<<2)
  54 #define SDCE_MISC_INT_EN        (1<<1)
  55
  56 static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
  57 {
  58         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
  59         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  60
  61         if (mask == SDHCI_RESET_ALL) {
  62                 /*
  63                  * tune timing of read data/command when crc error happen
  64                  * no performance impact
  65                  */
  66                 if (pdata && 0 != pdata->clk_delay_cycles) {
  67                         u16 tmp;
  68
  69                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  70                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
  71                                 << SDCLK_DELAY_SHIFT;
  72                         tmp |= SDCLK_SEL;
  73                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  74                 }
  75         }
  76 }
  77
  78 #define MAX_WAIT_COUNT 5
  79 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
  80 {
  81         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  82         struct sdhci_pxa *pxa = pltfm_host->priv;
  83         u16 tmp;
  84         int count;
  85
  86         if (pxa->power_mode == MMC_POWER_UP
  87                         && power_mode == MMC_POWER_ON) {
  88
  89                 dev_dbg(mmc_dev(host->mmc),
  90                                 "%s: slot->power_mode = %d,"
  91                                 "ios->power_mode = %d\n",
  92                                 __func__,
  93                                 pxa->power_mode,
  94                                 power_mode);
  95
  96                 /* set we want notice of when 74 clocks are sent */
  97                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
  98                 tmp |= SDCE_MISC_INT_EN;
  99                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 100
 101                 /* start sending the 74 clocks */
 102                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
 103                 tmp |= SDCFG_GEN_PAD_CLK_ON;
 104                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
 105
 106                 /* slowest speed is about 100KHz or 10usec per clock */
 107                 udelay(740);
 108                 count = 0;
 109
 110                 while (count++ < MAX_WAIT_COUNT) {
 111                         if ((readw(host->ioaddr + SD_CE_ATA_2)
 112                                                 & SDCE_MISC_INT) == 0)
 113                                 break;
 114                         udelay(10);
 115                 }
 116
 117                 if (count == MAX_WAIT_COUNT)
 118                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
 119
 120                 /* clear the interrupt bit if posted */
 121                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 122                 tmp |= SDCE_MISC_INT;
 123                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 124         }
 125         pxa->power_mode = power_mode;
 126 }
 127
 128 static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 129 {
 130         u16 ctrl_2;
 131
 132         /*
 133          * Set V18_EN -- UHS modes do not work without this.
 134          * does not change signaling voltage
 135          */
 136         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 137
 138         /* Select Bus Speed Mode for host */
 139         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 140         switch (uhs) {
 141         case MMC_TIMING_UHS_SDR12:
 142                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 143                 break;
 144         case MMC_TIMING_UHS_SDR25:
 145                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 146                 break;
 147         case MMC_TIMING_UHS_SDR50:
 148                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
 149                 break;
 150         case MMC_TIMING_UHS_SDR104:
 151                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
 152                 break;
 153         case MMC_TIMING_UHS_DDR50:
 154                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
 155                 break;
 156         }
 157
 158         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 159         dev_dbg(mmc_dev(host->mmc),
 160                 "%s uhs = %d, ctrl_2 = %04X\n",
 161                 __func__, uhs, ctrl_2);
 162
 163         return 0;
 164 }
 165
 166 static u32 pxav3_get_max_clock(struct sdhci_host *host)
 167 {
 168         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 169
 170         return clk_get_rate(pltfm_host->clk);
 171 }
 172
 173 static struct sdhci_ops pxav3_sdhci_ops = {
 174         .platform_reset_exit = pxav3_set_private_registers,
 175         .set_uhs_signaling = pxav3_set_uhs_signaling,
 176         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
 177         .get_max_clock = pxav3_get_max_clock,
 178 };
 179
 180 #ifdef CONFIG_OF
 181 static const struct of_device_id sdhci_pxav3_of_match[] = {
 182         {
 183                 .compatible = "mrvl,pxav3-mmc",
 184         },
 185         {},
 186 };
 187 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
 188
 189 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 190 {
 191         struct sdhci_pxa_platdata *pdata;
 192         struct device_node *np = dev->of_node;
 193         u32 bus_width;
 194         u32 clk_delay_cycles;
 195         enum of_gpio_flags gpio_flags;
 196
 197         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 198         if (!pdata)
 199                 return NULL;
 200
 201         if (of_find_property(np, "non-removable", NULL))
 202                 pdata->flags |= PXA_FLAG_CARD_PERMANENT;
 203
 204         of_property_read_u32(np, "bus-width", &bus_width);
 205         if (bus_width == 8)
 206                 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
 207
 208         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
 209         if (clk_delay_cycles > 0)
 210                 pdata->clk_delay_cycles = clk_delay_cycles;
 211
 212         pdata->ext_cd_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &gpio_flags);
 213         if (gpio_flags != OF_GPIO_ACTIVE_LOW)
 214                 pdata->host_caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
 215
 216         return pdata;
 217 }
 218 #else
 219 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 220 {
 221         return NULL;
 222 }
 223 #endif
 224
 225 static int sdhci_pxav3_probe(struct platform_device *pdev)
 226 {
 227         struct sdhci_pltfm_host *pltfm_host;
 228         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 229         struct device *dev = &pdev->dev;
 230         struct sdhci_host *host = NULL;
 231         struct sdhci_pxa *pxa = NULL;
 232         const struct of_device_id *match;
 233
 234         int ret;
 235         struct clk *clk;
 236
 237         pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
 238         if (!pxa)
 239                 return -ENOMEM;
 240
 241         host = sdhci_pltfm_init(pdev, NULL);
 242         if (IS_ERR(host)) {
 243                 kfree(pxa);
 244                 return PTR_ERR(host);
 245         }
 246         pltfm_host = sdhci_priv(host);
 247         pltfm_host->priv = pxa;
 248
 249         clk = clk_get(dev, NULL);
 250         if (IS_ERR(clk)) {
 251                 dev_err(dev, "failed to get io clock\n");
 252                 ret = PTR_ERR(clk);
 253                 goto err_clk_get;
 254         }
 255         pltfm_host->clk = clk;
 256         clk_prepare_enable(clk);
 257
 258         host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
 259                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 260                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
 261                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 262
 263         /* enable 1/8V DDR capable */
 264         host->mmc->caps |= MMC_CAP_1_8V_DDR;
 265
 266         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 267         if (match)
 268                 pdata = pxav3_get_mmc_pdata(dev);
 269
 270         if (pdata) {
 271                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
 272                         /* on-chip device */
 273                         host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 274                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 275                 }
 276
 277                 /* If slot design supports 8 bit data, indicate this to MMC. */
 278                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 279                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 280
 281                 if (pdata->quirks)
 282                         host->quirks |= pdata->quirks;
 283                 if (pdata->quirks2)
 284                         host->quirks2 |= pdata->quirks2;
 285                 if (pdata->host_caps)
 286                         host->mmc->caps |= pdata->host_caps;
 287                 if (pdata->host_caps2)
 288                         host->mmc->caps2 |= pdata->host_caps2;
 289                 if (pdata->pm_caps)
 290                         host->mmc->pm_caps |= pdata->pm_caps;
 291
 292                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
 293                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
 294                         if (ret) {
 295                                 dev_err(mmc_dev(host->mmc),
 296                                         "failed to allocate card detect gpio\n");
 297                                 goto err_cd_req;
 298                         }
 299                 }
 300         }
 301
 302         host->ops = &pxav3_sdhci_ops;
 303
 304         sdhci_get_of_property(pdev);
 305
 306         ret = sdhci_add_host(host);
 307         if (ret) {
 308                 dev_err(&pdev->dev, "failed to add host\n");
 309                 goto err_add_host;
 310         }
 311
 312         platform_set_drvdata(pdev, host);
 313
 314         return 0;
 315
 316 err_add_host:
 317         clk_disable_unprepare(clk);
 318         clk_put(clk);
 319         mmc_gpio_free_cd(host->mmc);
 320 err_cd_req:
 321 err_clk_get:
 322         sdhci_pltfm_free(pdev);
 323         kfree(pxa);
 324         return ret;
 325 }
 326
 327 static int sdhci_pxav3_remove(struct platform_device *pdev)
 328 {
 329         struct sdhci_host *host = platform_get_drvdata(pdev);
 330         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 331         struct sdhci_pxa *pxa = pltfm_host->priv;
 332         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 333
 334         sdhci_remove_host(host, 1);
 335
 336         clk_disable_unprepare(pltfm_host->clk);
 337         clk_put(pltfm_host->clk);
 338
 339         if (gpio_is_valid(pdata->ext_cd_gpio))
 340                 mmc_gpio_free_cd(host->mmc);
 341
 342         sdhci_pltfm_free(pdev);
 343         kfree(pxa);
 344
 345         platform_set_drvdata(pdev, NULL);
 346
 347         return 0;
 348 }
 349
 350 static struct platform_driver sdhci_pxav3_driver = {
 351         .driver         = {
 352                 .name   = "sdhci-pxav3",
 353 #ifdef CONFIG_OF
 354                 .of_match_table = sdhci_pxav3_of_match,
 355 #endif
 356                 .owner  = THIS_MODULE,
 357                 .pm     = SDHCI_PLTFM_PMOPS,
 358         },
 359         .probe          = sdhci_pxav3_probe,
 360         .remove         = sdhci_pxav3_remove,
 361 };
 362
 363 module_platform_driver(sdhci_pxav3_driver);
 364
 365 MODULE_DESCRIPTION("SDHCI driver for pxav3");
 366 MODULE_AUTHOR("Marvell International Ltd.");
 367 MODULE_LICENSE("GPL v2");
 368