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Merge branch 'fix/rt5645' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data,
58 struct sdhci_host_next *next);
59 static int sdhci_do_get_cd(struct sdhci_host *host);
60
61 #ifdef CONFIG_PM
62 static int sdhci_runtime_pm_get(struct sdhci_host *host);
63 static int sdhci_runtime_pm_put(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
65 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66 #else
67 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
68 {
69 return 0;
70 }
71 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
72 {
73 return 0;
74 }
75 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76 {
77 }
78 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79 {
80 }
81 #endif
82
83 static void sdhci_dumpregs(struct sdhci_host *host)
84 {
85 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
86 mmc_hostname(host->mmc));
87
88 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
89 sdhci_readl(host, SDHCI_DMA_ADDRESS),
90 sdhci_readw(host, SDHCI_HOST_VERSION));
91 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
92 sdhci_readw(host, SDHCI_BLOCK_SIZE),
93 sdhci_readw(host, SDHCI_BLOCK_COUNT));
94 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
95 sdhci_readl(host, SDHCI_ARGUMENT),
96 sdhci_readw(host, SDHCI_TRANSFER_MODE));
97 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
98 sdhci_readl(host, SDHCI_PRESENT_STATE),
99 sdhci_readb(host, SDHCI_HOST_CONTROL));
100 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
101 sdhci_readb(host, SDHCI_POWER_CONTROL),
102 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
103 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
104 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
105 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
106 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
107 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
108 sdhci_readl(host, SDHCI_INT_STATUS));
109 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
110 sdhci_readl(host, SDHCI_INT_ENABLE),
111 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
112 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
113 sdhci_readw(host, SDHCI_ACMD12_ERR),
114 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
115 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
116 sdhci_readl(host, SDHCI_CAPABILITIES),
117 sdhci_readl(host, SDHCI_CAPABILITIES_1));
118 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
119 sdhci_readw(host, SDHCI_COMMAND),
120 sdhci_readl(host, SDHCI_MAX_CURRENT));
121 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
122 sdhci_readw(host, SDHCI_HOST_CONTROL2));
123
124 if (host->flags & SDHCI_USE_ADMA) {
125 if (host->flags & SDHCI_USE_64_BIT_DMA)
126 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
127 readl(host->ioaddr + SDHCI_ADMA_ERROR),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 else
131 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_ADMA_ERROR),
133 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
134 }
135
136 pr_debug(DRIVER_NAME ": ===========================================\n");
137 }
138
139 /*****************************************************************************\
140 * *
141 * Low level functions *
142 * *
143 \*****************************************************************************/
144
145 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146 {
147 u32 present;
148
149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
150 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
151 return;
152
153 if (enable) {
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
156
157 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
158 SDHCI_INT_CARD_INSERT;
159 } else {
160 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
161 }
162
163 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
164 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
165 }
166
167 static void sdhci_enable_card_detection(struct sdhci_host *host)
168 {
169 sdhci_set_card_detection(host, true);
170 }
171
172 static void sdhci_disable_card_detection(struct sdhci_host *host)
173 {
174 sdhci_set_card_detection(host, false);
175 }
176
177 void sdhci_reset(struct sdhci_host *host, u8 mask)
178 {
179 unsigned long timeout;
180
181 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
182
183 if (mask & SDHCI_RESET_ALL) {
184 host->clock = 0;
185 /* Reset-all turns off SD Bus Power */
186 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
187 sdhci_runtime_pm_bus_off(host);
188 }
189
190 /* Wait max 100 ms */
191 timeout = 100;
192
193 /* hw clears the bit when it's done */
194 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
195 if (timeout == 0) {
196 pr_err("%s: Reset 0x%x never completed.\n",
197 mmc_hostname(host->mmc), (int)mask);
198 sdhci_dumpregs(host);
199 return;
200 }
201 timeout--;
202 mdelay(1);
203 }
204 }
205 EXPORT_SYMBOL_GPL(sdhci_reset);
206
207 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208 {
209 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
210 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
211 SDHCI_CARD_PRESENT))
212 return;
213 }
214
215 host->ops->reset(host, mask);
216
217 if (mask & SDHCI_RESET_ALL) {
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if (host->ops->enable_dma)
220 host->ops->enable_dma(host);
221 }
222
223 /* Resetting the controller clears many */
224 host->preset_enabled = false;
225 }
226 }
227
228 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
229
230 static void sdhci_init(struct sdhci_host *host, int soft)
231 {
232 if (soft)
233 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
234 else
235 sdhci_do_reset(host, SDHCI_RESET_ALL);
236
237 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
238 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
239 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
240 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
241 SDHCI_INT_RESPONSE;
242
243 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
244 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
245
246 if (soft) {
247 /* force clock reconfiguration */
248 host->clock = 0;
249 sdhci_set_ios(host->mmc, &host->mmc->ios);
250 }
251 }
252
253 static void sdhci_reinit(struct sdhci_host *host)
254 {
255 sdhci_init(host, 0);
256 sdhci_enable_card_detection(host);
257 }
258
259 static void sdhci_activate_led(struct sdhci_host *host)
260 {
261 u8 ctrl;
262
263 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
264 ctrl |= SDHCI_CTRL_LED;
265 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
266 }
267
268 static void sdhci_deactivate_led(struct sdhci_host *host)
269 {
270 u8 ctrl;
271
272 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
273 ctrl &= ~SDHCI_CTRL_LED;
274 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
275 }
276
277 #ifdef SDHCI_USE_LEDS_CLASS
278 static void sdhci_led_control(struct led_classdev *led,
279 enum led_brightness brightness)
280 {
281 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
282 unsigned long flags;
283
284 spin_lock_irqsave(&host->lock, flags);
285
286 if (host->runtime_suspended)
287 goto out;
288
289 if (brightness == LED_OFF)
290 sdhci_deactivate_led(host);
291 else
292 sdhci_activate_led(host);
293 out:
294 spin_unlock_irqrestore(&host->lock, flags);
295 }
296 #endif
297
298 /*****************************************************************************\
299 * *
300 * Core functions *
301 * *
302 \*****************************************************************************/
303
304 static void sdhci_read_block_pio(struct sdhci_host *host)
305 {
306 unsigned long flags;
307 size_t blksize, len, chunk;
308 u32 uninitialized_var(scratch);
309 u8 *buf;
310
311 DBG("PIO reading\n");
312
313 blksize = host->data->blksz;
314 chunk = 0;
315
316 local_irq_save(flags);
317
318 while (blksize) {
319 BUG_ON(!sg_miter_next(&host->sg_miter));
320
321 len = min(host->sg_miter.length, blksize);
322
323 blksize -= len;
324 host->sg_miter.consumed = len;
325
326 buf = host->sg_miter.addr;
327
328 while (len) {
329 if (chunk == 0) {
330 scratch = sdhci_readl(host, SDHCI_BUFFER);
331 chunk = 4;
332 }
333
334 *buf = scratch & 0xFF;
335
336 buf++;
337 scratch >>= 8;
338 chunk--;
339 len--;
340 }
341 }
342
343 sg_miter_stop(&host->sg_miter);
344
345 local_irq_restore(flags);
346 }
347
348 static void sdhci_write_block_pio(struct sdhci_host *host)
349 {
350 unsigned long flags;
351 size_t blksize, len, chunk;
352 u32 scratch;
353 u8 *buf;
354
355 DBG("PIO writing\n");
356
357 blksize = host->data->blksz;
358 chunk = 0;
359 scratch = 0;
360
361 local_irq_save(flags);
362
363 while (blksize) {
364 BUG_ON(!sg_miter_next(&host->sg_miter));
365
366 len = min(host->sg_miter.length, blksize);
367
368 blksize -= len;
369 host->sg_miter.consumed = len;
370
371 buf = host->sg_miter.addr;
372
373 while (len) {
374 scratch |= (u32)*buf << (chunk * 8);
375
376 buf++;
377 chunk++;
378 len--;
379
380 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
381 sdhci_writel(host, scratch, SDHCI_BUFFER);
382 chunk = 0;
383 scratch = 0;
384 }
385 }
386 }
387
388 sg_miter_stop(&host->sg_miter);
389
390 local_irq_restore(flags);
391 }
392
393 static void sdhci_transfer_pio(struct sdhci_host *host)
394 {
395 u32 mask;
396
397 BUG_ON(!host->data);
398
399 if (host->blocks == 0)
400 return;
401
402 if (host->data->flags & MMC_DATA_READ)
403 mask = SDHCI_DATA_AVAILABLE;
404 else
405 mask = SDHCI_SPACE_AVAILABLE;
406
407 /*
408 * Some controllers (JMicron JMB38x) mess up the buffer bits
409 * for transfers < 4 bytes. As long as it is just one block,
410 * we can ignore the bits.
411 */
412 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
413 (host->data->blocks == 1))
414 mask = ~0;
415
416 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
417 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
418 udelay(100);
419
420 if (host->data->flags & MMC_DATA_READ)
421 sdhci_read_block_pio(host);
422 else
423 sdhci_write_block_pio(host);
424
425 host->blocks--;
426 if (host->blocks == 0)
427 break;
428 }
429
430 DBG("PIO transfer complete.\n");
431 }
432
433 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
434 {
435 local_irq_save(*flags);
436 return kmap_atomic(sg_page(sg)) + sg->offset;
437 }
438
439 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
440 {
441 kunmap_atomic(buffer);
442 local_irq_restore(*flags);
443 }
444
445 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
446 dma_addr_t addr, int len, unsigned cmd)
447 {
448 struct sdhci_adma2_64_desc *dma_desc = desc;
449
450 /* 32-bit and 64-bit descriptors have these members in same position */
451 dma_desc->cmd = cpu_to_le16(cmd);
452 dma_desc->len = cpu_to_le16(len);
453 dma_desc->addr_lo = cpu_to_le32((u32)addr);
454
455 if (host->flags & SDHCI_USE_64_BIT_DMA)
456 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
457 }
458
459 static void sdhci_adma_mark_end(void *desc)
460 {
461 struct sdhci_adma2_64_desc *dma_desc = desc;
462
463 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
464 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
465 }
466
467 static int sdhci_adma_table_pre(struct sdhci_host *host,
468 struct mmc_data *data)
469 {
470 int direction;
471
472 void *desc;
473 void *align;
474 dma_addr_t addr;
475 dma_addr_t align_addr;
476 int len, offset;
477
478 struct scatterlist *sg;
479 int i;
480 char *buffer;
481 unsigned long flags;
482
483 /*
484 * The spec does not specify endianness of descriptor table.
485 * We currently guess that it is LE.
486 */
487
488 if (data->flags & MMC_DATA_READ)
489 direction = DMA_FROM_DEVICE;
490 else
491 direction = DMA_TO_DEVICE;
492
493 host->align_addr = dma_map_single(mmc_dev(host->mmc),
494 host->align_buffer, host->align_buffer_sz, direction);
495 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
496 goto fail;
497 BUG_ON(host->align_addr & host->align_mask);
498
499 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
500 if (host->sg_count < 0)
501 goto unmap_align;
502
503 desc = host->adma_table;
504 align = host->align_buffer;
505
506 align_addr = host->align_addr;
507
508 for_each_sg(data->sg, sg, host->sg_count, i) {
509 addr = sg_dma_address(sg);
510 len = sg_dma_len(sg);
511
512 /*
513 * The SDHCI specification states that ADMA
514 * addresses must be 32-bit aligned. If they
515 * aren't, then we use a bounce buffer for
516 * the (up to three) bytes that screw up the
517 * alignment.
518 */
519 offset = (host->align_sz - (addr & host->align_mask)) &
520 host->align_mask;
521 if (offset) {
522 if (data->flags & MMC_DATA_WRITE) {
523 buffer = sdhci_kmap_atomic(sg, &flags);
524 memcpy(align, buffer, offset);
525 sdhci_kunmap_atomic(buffer, &flags);
526 }
527
528 /* tran, valid */
529 sdhci_adma_write_desc(host, desc, align_addr, offset,
530 ADMA2_TRAN_VALID);
531
532 BUG_ON(offset > 65536);
533
534 align += host->align_sz;
535 align_addr += host->align_sz;
536
537 desc += host->desc_sz;
538
539 addr += offset;
540 len -= offset;
541 }
542
543 BUG_ON(len > 65536);
544
545 /* tran, valid */
546 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
547 desc += host->desc_sz;
548
549 /*
550 * If this triggers then we have a calculation bug
551 * somewhere. :/
552 */
553 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
554 }
555
556 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
557 /*
558 * Mark the last descriptor as the terminating descriptor
559 */
560 if (desc != host->adma_table) {
561 desc -= host->desc_sz;
562 sdhci_adma_mark_end(desc);
563 }
564 } else {
565 /*
566 * Add a terminating entry.
567 */
568
569 /* nop, end, valid */
570 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
571 }
572
573 /*
574 * Resync align buffer as we might have changed it.
575 */
576 if (data->flags & MMC_DATA_WRITE) {
577 dma_sync_single_for_device(mmc_dev(host->mmc),
578 host->align_addr, host->align_buffer_sz, direction);
579 }
580
581 return 0;
582
583 unmap_align:
584 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
585 host->align_buffer_sz, direction);
586 fail:
587 return -EINVAL;
588 }
589
590 static void sdhci_adma_table_post(struct sdhci_host *host,
591 struct mmc_data *data)
592 {
593 int direction;
594
595 struct scatterlist *sg;
596 int i, size;
597 void *align;
598 char *buffer;
599 unsigned long flags;
600 bool has_unaligned;
601
602 if (data->flags & MMC_DATA_READ)
603 direction = DMA_FROM_DEVICE;
604 else
605 direction = DMA_TO_DEVICE;
606
607 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
608 host->align_buffer_sz, direction);
609
610 /* Do a quick scan of the SG list for any unaligned mappings */
611 has_unaligned = false;
612 for_each_sg(data->sg, sg, host->sg_count, i)
613 if (sg_dma_address(sg) & host->align_mask) {
614 has_unaligned = true;
615 break;
616 }
617
618 if (has_unaligned && data->flags & MMC_DATA_READ) {
619 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
620 data->sg_len, direction);
621
622 align = host->align_buffer;
623
624 for_each_sg(data->sg, sg, host->sg_count, i) {
625 if (sg_dma_address(sg) & host->align_mask) {
626 size = host->align_sz -
627 (sg_dma_address(sg) & host->align_mask);
628
629 buffer = sdhci_kmap_atomic(sg, &flags);
630 memcpy(buffer, align, size);
631 sdhci_kunmap_atomic(buffer, &flags);
632
633 align += host->align_sz;
634 }
635 }
636 }
637
638 if (!data->host_cookie)
639 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
640 data->sg_len, direction);
641 }
642
643 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
644 {
645 u8 count;
646 struct mmc_data *data = cmd->data;
647 unsigned target_timeout, current_timeout;
648
649 /*
650 * If the host controller provides us with an incorrect timeout
651 * value, just skip the check and use 0xE. The hardware may take
652 * longer to time out, but that's much better than having a too-short
653 * timeout value.
654 */
655 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
656 return 0xE;
657
658 /* Unspecified timeout, assume max */
659 if (!data && !cmd->busy_timeout)
660 return 0xE;
661
662 /* timeout in us */
663 if (!data)
664 target_timeout = cmd->busy_timeout * 1000;
665 else {
666 target_timeout = data->timeout_ns / 1000;
667 if (host->clock)
668 target_timeout += data->timeout_clks / host->clock;
669 }
670
671 /*
672 * Figure out needed cycles.
673 * We do this in steps in order to fit inside a 32 bit int.
674 * The first step is the minimum timeout, which will have a
675 * minimum resolution of 6 bits:
676 * (1) 2^13*1000 > 2^22,
677 * (2) host->timeout_clk < 2^16
678 * =>
679 * (1) / (2) > 2^6
680 */
681 count = 0;
682 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
683 while (current_timeout < target_timeout) {
684 count++;
685 current_timeout <<= 1;
686 if (count >= 0xF)
687 break;
688 }
689
690 if (count >= 0xF) {
691 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
692 mmc_hostname(host->mmc), count, cmd->opcode);
693 count = 0xE;
694 }
695
696 return count;
697 }
698
699 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
700 {
701 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
702 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
703
704 if (host->flags & SDHCI_REQ_USE_DMA)
705 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
706 else
707 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
708
709 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
710 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
711 }
712
713 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
714 {
715 u8 count;
716
717 if (host->ops->set_timeout) {
718 host->ops->set_timeout(host, cmd);
719 } else {
720 count = sdhci_calc_timeout(host, cmd);
721 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
722 }
723 }
724
725 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
726 {
727 u8 ctrl;
728 struct mmc_data *data = cmd->data;
729 int ret;
730
731 WARN_ON(host->data);
732
733 if (data || (cmd->flags & MMC_RSP_BUSY))
734 sdhci_set_timeout(host, cmd);
735
736 if (!data)
737 return;
738
739 /* Sanity checks */
740 BUG_ON(data->blksz * data->blocks > 524288);
741 BUG_ON(data->blksz > host->mmc->max_blk_size);
742 BUG_ON(data->blocks > 65535);
743
744 host->data = data;
745 host->data_early = 0;
746 host->data->bytes_xfered = 0;
747
748 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
749 host->flags |= SDHCI_REQ_USE_DMA;
750
751 /*
752 * FIXME: This doesn't account for merging when mapping the
753 * scatterlist.
754 */
755 if (host->flags & SDHCI_REQ_USE_DMA) {
756 int broken, i;
757 struct scatterlist *sg;
758
759 broken = 0;
760 if (host->flags & SDHCI_USE_ADMA) {
761 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
762 broken = 1;
763 } else {
764 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
765 broken = 1;
766 }
767
768 if (unlikely(broken)) {
769 for_each_sg(data->sg, sg, data->sg_len, i) {
770 if (sg->length & 0x3) {
771 DBG("Reverting to PIO because of "
772 "transfer size (%d)\n",
773 sg->length);
774 host->flags &= ~SDHCI_REQ_USE_DMA;
775 break;
776 }
777 }
778 }
779 }
780
781 /*
782 * The assumption here being that alignment is the same after
783 * translation to device address space.
784 */
785 if (host->flags & SDHCI_REQ_USE_DMA) {
786 int broken, i;
787 struct scatterlist *sg;
788
789 broken = 0;
790 if (host->flags & SDHCI_USE_ADMA) {
791 /*
792 * As we use 3 byte chunks to work around
793 * alignment problems, we need to check this
794 * quirk.
795 */
796 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
797 broken = 1;
798 } else {
799 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
800 broken = 1;
801 }
802
803 if (unlikely(broken)) {
804 for_each_sg(data->sg, sg, data->sg_len, i) {
805 if (sg->offset & 0x3) {
806 DBG("Reverting to PIO because of "
807 "bad alignment\n");
808 host->flags &= ~SDHCI_REQ_USE_DMA;
809 break;
810 }
811 }
812 }
813 }
814
815 if (host->flags & SDHCI_REQ_USE_DMA) {
816 if (host->flags & SDHCI_USE_ADMA) {
817 ret = sdhci_adma_table_pre(host, data);
818 if (ret) {
819 /*
820 * This only happens when someone fed
821 * us an invalid request.
822 */
823 WARN_ON(1);
824 host->flags &= ~SDHCI_REQ_USE_DMA;
825 } else {
826 sdhci_writel(host, host->adma_addr,
827 SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
832 }
833 } else {
834 int sg_cnt;
835
836 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
837 if (sg_cnt <= 0) {
838 /*
839 * This only happens when someone fed
840 * us an invalid request.
841 */
842 WARN_ON(1);
843 host->flags &= ~SDHCI_REQ_USE_DMA;
844 } else {
845 WARN_ON(sg_cnt != 1);
846 sdhci_writel(host, sg_dma_address(data->sg),
847 SDHCI_DMA_ADDRESS);
848 }
849 }
850 }
851
852 /*
853 * Always adjust the DMA selection as some controllers
854 * (e.g. JMicron) can't do PIO properly when the selection
855 * is ADMA.
856 */
857 if (host->version >= SDHCI_SPEC_200) {
858 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
859 ctrl &= ~SDHCI_CTRL_DMA_MASK;
860 if ((host->flags & SDHCI_REQ_USE_DMA) &&
861 (host->flags & SDHCI_USE_ADMA)) {
862 if (host->flags & SDHCI_USE_64_BIT_DMA)
863 ctrl |= SDHCI_CTRL_ADMA64;
864 else
865 ctrl |= SDHCI_CTRL_ADMA32;
866 } else {
867 ctrl |= SDHCI_CTRL_SDMA;
868 }
869 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
870 }
871
872 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
873 int flags;
874
875 flags = SG_MITER_ATOMIC;
876 if (host->data->flags & MMC_DATA_READ)
877 flags |= SG_MITER_TO_SG;
878 else
879 flags |= SG_MITER_FROM_SG;
880 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
881 host->blocks = data->blocks;
882 }
883
884 sdhci_set_transfer_irqs(host);
885
886 /* Set the DMA boundary value and block size */
887 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
888 data->blksz), SDHCI_BLOCK_SIZE);
889 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
890 }
891
892 static void sdhci_set_transfer_mode(struct sdhci_host *host,
893 struct mmc_command *cmd)
894 {
895 u16 mode = 0;
896 struct mmc_data *data = cmd->data;
897
898 if (data == NULL) {
899 if (host->quirks2 &
900 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
901 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
902 } else {
903 /* clear Auto CMD settings for no data CMDs */
904 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
905 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
906 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
907 }
908 return;
909 }
910
911 WARN_ON(!host->data);
912
913 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
914 mode = SDHCI_TRNS_BLK_CNT_EN;
915
916 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
917 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
918 /*
919 * If we are sending CMD23, CMD12 never gets sent
920 * on successful completion (so no Auto-CMD12).
921 */
922 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
923 (cmd->opcode != SD_IO_RW_EXTENDED))
924 mode |= SDHCI_TRNS_AUTO_CMD12;
925 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
926 mode |= SDHCI_TRNS_AUTO_CMD23;
927 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
928 }
929 }
930
931 if (data->flags & MMC_DATA_READ)
932 mode |= SDHCI_TRNS_READ;
933 if (host->flags & SDHCI_REQ_USE_DMA)
934 mode |= SDHCI_TRNS_DMA;
935
936 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
937 }
938
939 static void sdhci_finish_data(struct sdhci_host *host)
940 {
941 struct mmc_data *data;
942
943 BUG_ON(!host->data);
944
945 data = host->data;
946 host->data = NULL;
947
948 if (host->flags & SDHCI_REQ_USE_DMA) {
949 if (host->flags & SDHCI_USE_ADMA)
950 sdhci_adma_table_post(host, data);
951 else {
952 if (!data->host_cookie)
953 dma_unmap_sg(mmc_dev(host->mmc),
954 data->sg, data->sg_len,
955 (data->flags & MMC_DATA_READ) ?
956 DMA_FROM_DEVICE : DMA_TO_DEVICE);
957 }
958 }
959
960 /*
961 * The specification states that the block count register must
962 * be updated, but it does not specify at what point in the
963 * data flow. That makes the register entirely useless to read
964 * back so we have to assume that nothing made it to the card
965 * in the event of an error.
966 */
967 if (data->error)
968 data->bytes_xfered = 0;
969 else
970 data->bytes_xfered = data->blksz * data->blocks;
971
972 /*
973 * Need to send CMD12 if -
974 * a) open-ended multiblock transfer (no CMD23)
975 * b) error in multiblock transfer
976 */
977 if (data->stop &&
978 (data->error ||
979 !host->mrq->sbc)) {
980
981 /*
982 * The controller needs a reset of internal state machines
983 * upon error conditions.
984 */
985 if (data->error) {
986 sdhci_do_reset(host, SDHCI_RESET_CMD);
987 sdhci_do_reset(host, SDHCI_RESET_DATA);
988 }
989
990 sdhci_send_command(host, data->stop);
991 } else
992 tasklet_schedule(&host->finish_tasklet);
993 }
994
995 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
996 {
997 int flags;
998 u32 mask;
999 unsigned long timeout;
1000
1001 WARN_ON(host->cmd);
1002
1003 /* Wait max 10 ms */
1004 timeout = 10;
1005
1006 mask = SDHCI_CMD_INHIBIT;
1007 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1008 mask |= SDHCI_DATA_INHIBIT;
1009
1010 /* We shouldn't wait for data inihibit for stop commands, even
1011 though they might use busy signaling */
1012 if (host->mrq->data && (cmd == host->mrq->data->stop))
1013 mask &= ~SDHCI_DATA_INHIBIT;
1014
1015 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1016 if (timeout == 0) {
1017 pr_err("%s: Controller never released "
1018 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1019 sdhci_dumpregs(host);
1020 cmd->error = -EIO;
1021 tasklet_schedule(&host->finish_tasklet);
1022 return;
1023 }
1024 timeout--;
1025 mdelay(1);
1026 }
1027
1028 timeout = jiffies;
1029 if (!cmd->data && cmd->busy_timeout > 9000)
1030 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1031 else
1032 timeout += 10 * HZ;
1033 mod_timer(&host->timer, timeout);
1034
1035 host->cmd = cmd;
1036 host->busy_handle = 0;
1037
1038 sdhci_prepare_data(host, cmd);
1039
1040 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1041
1042 sdhci_set_transfer_mode(host, cmd);
1043
1044 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1045 pr_err("%s: Unsupported response type!\n",
1046 mmc_hostname(host->mmc));
1047 cmd->error = -EINVAL;
1048 tasklet_schedule(&host->finish_tasklet);
1049 return;
1050 }
1051
1052 if (!(cmd->flags & MMC_RSP_PRESENT))
1053 flags = SDHCI_CMD_RESP_NONE;
1054 else if (cmd->flags & MMC_RSP_136)
1055 flags = SDHCI_CMD_RESP_LONG;
1056 else if (cmd->flags & MMC_RSP_BUSY)
1057 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1058 else
1059 flags = SDHCI_CMD_RESP_SHORT;
1060
1061 if (cmd->flags & MMC_RSP_CRC)
1062 flags |= SDHCI_CMD_CRC;
1063 if (cmd->flags & MMC_RSP_OPCODE)
1064 flags |= SDHCI_CMD_INDEX;
1065
1066 /* CMD19 is special in that the Data Present Select should be set */
1067 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1068 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1069 flags |= SDHCI_CMD_DATA;
1070
1071 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1072 }
1073 EXPORT_SYMBOL_GPL(sdhci_send_command);
1074
1075 static void sdhci_finish_command(struct sdhci_host *host)
1076 {
1077 int i;
1078
1079 BUG_ON(host->cmd == NULL);
1080
1081 if (host->cmd->flags & MMC_RSP_PRESENT) {
1082 if (host->cmd->flags & MMC_RSP_136) {
1083 /* CRC is stripped so we need to do some shifting. */
1084 for (i = 0;i < 4;i++) {
1085 host->cmd->resp[i] = sdhci_readl(host,
1086 SDHCI_RESPONSE + (3-i)*4) << 8;
1087 if (i != 3)
1088 host->cmd->resp[i] |=
1089 sdhci_readb(host,
1090 SDHCI_RESPONSE + (3-i)*4-1);
1091 }
1092 } else {
1093 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1094 }
1095 }
1096
1097 host->cmd->error = 0;
1098
1099 /* Finished CMD23, now send actual command. */
1100 if (host->cmd == host->mrq->sbc) {
1101 host->cmd = NULL;
1102 sdhci_send_command(host, host->mrq->cmd);
1103 } else {
1104
1105 /* Processed actual command. */
1106 if (host->data && host->data_early)
1107 sdhci_finish_data(host);
1108
1109 if (!host->cmd->data)
1110 tasklet_schedule(&host->finish_tasklet);
1111
1112 host->cmd = NULL;
1113 }
1114 }
1115
1116 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1117 {
1118 u16 preset = 0;
1119
1120 switch (host->timing) {
1121 case MMC_TIMING_UHS_SDR12:
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1123 break;
1124 case MMC_TIMING_UHS_SDR25:
1125 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1126 break;
1127 case MMC_TIMING_UHS_SDR50:
1128 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1129 break;
1130 case MMC_TIMING_UHS_SDR104:
1131 case MMC_TIMING_MMC_HS200:
1132 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1133 break;
1134 case MMC_TIMING_UHS_DDR50:
1135 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1136 break;
1137 case MMC_TIMING_MMC_HS400:
1138 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1139 break;
1140 default:
1141 pr_warn("%s: Invalid UHS-I mode selected\n",
1142 mmc_hostname(host->mmc));
1143 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1144 break;
1145 }
1146 return preset;
1147 }
1148
1149 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1150 {
1151 int div = 0; /* Initialized for compiler warning */
1152 int real_div = div, clk_mul = 1;
1153 u16 clk = 0;
1154 unsigned long timeout;
1155
1156 host->mmc->actual_clock = 0;
1157
1158 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1159
1160 if (clock == 0)
1161 return;
1162
1163 if (host->version >= SDHCI_SPEC_300) {
1164 if (host->preset_enabled) {
1165 u16 pre_val;
1166
1167 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1168 pre_val = sdhci_get_preset_value(host);
1169 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1170 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1171 if (host->clk_mul &&
1172 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1173 clk = SDHCI_PROG_CLOCK_MODE;
1174 real_div = div + 1;
1175 clk_mul = host->clk_mul;
1176 } else {
1177 real_div = max_t(int, 1, div << 1);
1178 }
1179 goto clock_set;
1180 }
1181
1182 /*
1183 * Check if the Host Controller supports Programmable Clock
1184 * Mode.
1185 */
1186 if (host->clk_mul) {
1187 for (div = 1; div <= 1024; div++) {
1188 if ((host->max_clk * host->clk_mul / div)
1189 <= clock)
1190 break;
1191 }
1192 /*
1193 * Set Programmable Clock Mode in the Clock
1194 * Control register.
1195 */
1196 clk = SDHCI_PROG_CLOCK_MODE;
1197 real_div = div;
1198 clk_mul = host->clk_mul;
1199 div--;
1200 } else {
1201 /* Version 3.00 divisors must be a multiple of 2. */
1202 if (host->max_clk <= clock)
1203 div = 1;
1204 else {
1205 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1206 div += 2) {
1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
1210 }
1211 real_div = div;
1212 div >>= 1;
1213 }
1214 } else {
1215 /* Version 2.00 divisors must be a power of 2. */
1216 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1217 if ((host->max_clk / div) <= clock)
1218 break;
1219 }
1220 real_div = div;
1221 div >>= 1;
1222 }
1223
1224 clock_set:
1225 if (real_div)
1226 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1227 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1228 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1229 << SDHCI_DIVIDER_HI_SHIFT;
1230 clk |= SDHCI_CLOCK_INT_EN;
1231 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1232
1233 /* Wait max 20 ms */
1234 timeout = 20;
1235 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1236 & SDHCI_CLOCK_INT_STABLE)) {
1237 if (timeout == 0) {
1238 pr_err("%s: Internal clock never "
1239 "stabilised.\n", mmc_hostname(host->mmc));
1240 sdhci_dumpregs(host);
1241 return;
1242 }
1243 timeout--;
1244 mdelay(1);
1245 }
1246
1247 clk |= SDHCI_CLOCK_CARD_EN;
1248 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1249 }
1250 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1251
1252 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1253 unsigned short vdd)
1254 {
1255 struct mmc_host *mmc = host->mmc;
1256 u8 pwr = 0;
1257
1258 if (!IS_ERR(mmc->supply.vmmc)) {
1259 spin_unlock_irq(&host->lock);
1260 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1261 spin_lock_irq(&host->lock);
1262
1263 if (mode != MMC_POWER_OFF)
1264 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1265 else
1266 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1267
1268 return;
1269 }
1270
1271 if (mode != MMC_POWER_OFF) {
1272 switch (1 << vdd) {
1273 case MMC_VDD_165_195:
1274 pwr = SDHCI_POWER_180;
1275 break;
1276 case MMC_VDD_29_30:
1277 case MMC_VDD_30_31:
1278 pwr = SDHCI_POWER_300;
1279 break;
1280 case MMC_VDD_32_33:
1281 case MMC_VDD_33_34:
1282 pwr = SDHCI_POWER_330;
1283 break;
1284 default:
1285 BUG();
1286 }
1287 }
1288
1289 if (host->pwr == pwr)
1290 return;
1291
1292 host->pwr = pwr;
1293
1294 if (pwr == 0) {
1295 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1296 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1297 sdhci_runtime_pm_bus_off(host);
1298 vdd = 0;
1299 } else {
1300 /*
1301 * Spec says that we should clear the power reg before setting
1302 * a new value. Some controllers don't seem to like this though.
1303 */
1304 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1305 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1306
1307 /*
1308 * At least the Marvell CaFe chip gets confused if we set the
1309 * voltage and set turn on power at the same time, so set the
1310 * voltage first.
1311 */
1312 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1313 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1314
1315 pwr |= SDHCI_POWER_ON;
1316
1317 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1318
1319 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1320 sdhci_runtime_pm_bus_on(host);
1321
1322 /*
1323 * Some controllers need an extra 10ms delay of 10ms before
1324 * they can apply clock after applying power
1325 */
1326 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1327 mdelay(10);
1328 }
1329 }
1330
1331 /*****************************************************************************\
1332 * *
1333 * MMC callbacks *
1334 * *
1335 \*****************************************************************************/
1336
1337 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1338 {
1339 struct sdhci_host *host;
1340 int present;
1341 unsigned long flags;
1342
1343 host = mmc_priv(mmc);
1344
1345 sdhci_runtime_pm_get(host);
1346
1347 /* Firstly check card presence */
1348 present = sdhci_do_get_cd(host);
1349
1350 spin_lock_irqsave(&host->lock, flags);
1351
1352 WARN_ON(host->mrq != NULL);
1353
1354 #ifndef SDHCI_USE_LEDS_CLASS
1355 sdhci_activate_led(host);
1356 #endif
1357
1358 /*
1359 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1360 * requests if Auto-CMD12 is enabled.
1361 */
1362 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1363 if (mrq->stop) {
1364 mrq->data->stop = NULL;
1365 mrq->stop = NULL;
1366 }
1367 }
1368
1369 host->mrq = mrq;
1370
1371 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1372 host->mrq->cmd->error = -ENOMEDIUM;
1373 tasklet_schedule(&host->finish_tasklet);
1374 } else {
1375 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1376 sdhci_send_command(host, mrq->sbc);
1377 else
1378 sdhci_send_command(host, mrq->cmd);
1379 }
1380
1381 mmiowb();
1382 spin_unlock_irqrestore(&host->lock, flags);
1383 }
1384
1385 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1386 {
1387 u8 ctrl;
1388
1389 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1390 if (width == MMC_BUS_WIDTH_8) {
1391 ctrl &= ~SDHCI_CTRL_4BITBUS;
1392 if (host->version >= SDHCI_SPEC_300)
1393 ctrl |= SDHCI_CTRL_8BITBUS;
1394 } else {
1395 if (host->version >= SDHCI_SPEC_300)
1396 ctrl &= ~SDHCI_CTRL_8BITBUS;
1397 if (width == MMC_BUS_WIDTH_4)
1398 ctrl |= SDHCI_CTRL_4BITBUS;
1399 else
1400 ctrl &= ~SDHCI_CTRL_4BITBUS;
1401 }
1402 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1403 }
1404 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1405
1406 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1407 {
1408 u16 ctrl_2;
1409
1410 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1411 /* Select Bus Speed Mode for host */
1412 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1413 if ((timing == MMC_TIMING_MMC_HS200) ||
1414 (timing == MMC_TIMING_UHS_SDR104))
1415 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1416 else if (timing == MMC_TIMING_UHS_SDR12)
1417 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1418 else if (timing == MMC_TIMING_UHS_SDR25)
1419 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1420 else if (timing == MMC_TIMING_UHS_SDR50)
1421 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1422 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1423 (timing == MMC_TIMING_MMC_DDR52))
1424 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1425 else if (timing == MMC_TIMING_MMC_HS400)
1426 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1427 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1428 }
1429 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1430
1431 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1432 {
1433 unsigned long flags;
1434 u8 ctrl;
1435 struct mmc_host *mmc = host->mmc;
1436
1437 spin_lock_irqsave(&host->lock, flags);
1438
1439 if (host->flags & SDHCI_DEVICE_DEAD) {
1440 spin_unlock_irqrestore(&host->lock, flags);
1441 if (!IS_ERR(mmc->supply.vmmc) &&
1442 ios->power_mode == MMC_POWER_OFF)
1443 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1444 return;
1445 }
1446
1447 /*
1448 * Reset the chip on each power off.
1449 * Should clear out any weird states.
1450 */
1451 if (ios->power_mode == MMC_POWER_OFF) {
1452 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1453 sdhci_reinit(host);
1454 }
1455
1456 if (host->version >= SDHCI_SPEC_300 &&
1457 (ios->power_mode == MMC_POWER_UP) &&
1458 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1459 sdhci_enable_preset_value(host, false);
1460
1461 if (!ios->clock || ios->clock != host->clock) {
1462 host->ops->set_clock(host, ios->clock);
1463 host->clock = ios->clock;
1464
1465 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1466 host->clock) {
1467 host->timeout_clk = host->mmc->actual_clock ?
1468 host->mmc->actual_clock / 1000 :
1469 host->clock / 1000;
1470 host->mmc->max_busy_timeout =
1471 host->ops->get_max_timeout_count ?
1472 host->ops->get_max_timeout_count(host) :
1473 1 << 27;
1474 host->mmc->max_busy_timeout /= host->timeout_clk;
1475 }
1476 }
1477
1478 sdhci_set_power(host, ios->power_mode, ios->vdd);
1479
1480 if (host->ops->platform_send_init_74_clocks)
1481 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1482
1483 host->ops->set_bus_width(host, ios->bus_width);
1484
1485 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1486
1487 if ((ios->timing == MMC_TIMING_SD_HS ||
1488 ios->timing == MMC_TIMING_MMC_HS)
1489 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1490 ctrl |= SDHCI_CTRL_HISPD;
1491 else
1492 ctrl &= ~SDHCI_CTRL_HISPD;
1493
1494 if (host->version >= SDHCI_SPEC_300) {
1495 u16 clk, ctrl_2;
1496
1497 /* In case of UHS-I modes, set High Speed Enable */
1498 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1499 (ios->timing == MMC_TIMING_MMC_HS200) ||
1500 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1501 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1502 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1503 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1504 (ios->timing == MMC_TIMING_UHS_SDR25))
1505 ctrl |= SDHCI_CTRL_HISPD;
1506
1507 if (!host->preset_enabled) {
1508 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1509 /*
1510 * We only need to set Driver Strength if the
1511 * preset value enable is not set.
1512 */
1513 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1514 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1515 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1516 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1517 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1518 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1519 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1520 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1521 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1522 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1523 else {
1524 pr_warn("%s: invalid driver type, default to "
1525 "driver type B\n", mmc_hostname(mmc));
1526 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1527 }
1528
1529 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1530 } else {
1531 /*
1532 * According to SDHC Spec v3.00, if the Preset Value
1533 * Enable in the Host Control 2 register is set, we
1534 * need to reset SD Clock Enable before changing High
1535 * Speed Enable to avoid generating clock gliches.
1536 */
1537
1538 /* Reset SD Clock Enable */
1539 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1540 clk &= ~SDHCI_CLOCK_CARD_EN;
1541 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1542
1543 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1544
1545 /* Re-enable SD Clock */
1546 host->ops->set_clock(host, host->clock);
1547 }
1548
1549 /* Reset SD Clock Enable */
1550 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1551 clk &= ~SDHCI_CLOCK_CARD_EN;
1552 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1553
1554 host->ops->set_uhs_signaling(host, ios->timing);
1555 host->timing = ios->timing;
1556
1557 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1558 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1559 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1560 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1561 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1562 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1563 u16 preset;
1564
1565 sdhci_enable_preset_value(host, true);
1566 preset = sdhci_get_preset_value(host);
1567 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1568 >> SDHCI_PRESET_DRV_SHIFT;
1569 }
1570
1571 /* Re-enable SD Clock */
1572 host->ops->set_clock(host, host->clock);
1573 } else
1574 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1575
1576 /*
1577 * Some (ENE) controllers go apeshit on some ios operation,
1578 * signalling timeout and CRC errors even on CMD0. Resetting
1579 * it on each ios seems to solve the problem.
1580 */
1581 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1582 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1583
1584 mmiowb();
1585 spin_unlock_irqrestore(&host->lock, flags);
1586 }
1587
1588 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1589 {
1590 struct sdhci_host *host = mmc_priv(mmc);
1591
1592 sdhci_runtime_pm_get(host);
1593 sdhci_do_set_ios(host, ios);
1594 sdhci_runtime_pm_put(host);
1595 }
1596
1597 static int sdhci_do_get_cd(struct sdhci_host *host)
1598 {
1599 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1600
1601 if (host->flags & SDHCI_DEVICE_DEAD)
1602 return 0;
1603
1604 /* If polling/nonremovable, assume that the card is always present. */
1605 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1606 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1607 return 1;
1608
1609 /* Try slot gpio detect */
1610 if (!IS_ERR_VALUE(gpio_cd))
1611 return !!gpio_cd;
1612
1613 /* Host native card detect */
1614 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1615 }
1616
1617 static int sdhci_get_cd(struct mmc_host *mmc)
1618 {
1619 struct sdhci_host *host = mmc_priv(mmc);
1620 int ret;
1621
1622 sdhci_runtime_pm_get(host);
1623 ret = sdhci_do_get_cd(host);
1624 sdhci_runtime_pm_put(host);
1625 return ret;
1626 }
1627
1628 static int sdhci_check_ro(struct sdhci_host *host)
1629 {
1630 unsigned long flags;
1631 int is_readonly;
1632
1633 spin_lock_irqsave(&host->lock, flags);
1634
1635 if (host->flags & SDHCI_DEVICE_DEAD)
1636 is_readonly = 0;
1637 else if (host->ops->get_ro)
1638 is_readonly = host->ops->get_ro(host);
1639 else
1640 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1641 & SDHCI_WRITE_PROTECT);
1642
1643 spin_unlock_irqrestore(&host->lock, flags);
1644
1645 /* This quirk needs to be replaced by a callback-function later */
1646 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1647 !is_readonly : is_readonly;
1648 }
1649
1650 #define SAMPLE_COUNT 5
1651
1652 static int sdhci_do_get_ro(struct sdhci_host *host)
1653 {
1654 int i, ro_count;
1655
1656 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1657 return sdhci_check_ro(host);
1658
1659 ro_count = 0;
1660 for (i = 0; i < SAMPLE_COUNT; i++) {
1661 if (sdhci_check_ro(host)) {
1662 if (++ro_count > SAMPLE_COUNT / 2)
1663 return 1;
1664 }
1665 msleep(30);
1666 }
1667 return 0;
1668 }
1669
1670 static void sdhci_hw_reset(struct mmc_host *mmc)
1671 {
1672 struct sdhci_host *host = mmc_priv(mmc);
1673
1674 if (host->ops && host->ops->hw_reset)
1675 host->ops->hw_reset(host);
1676 }
1677
1678 static int sdhci_get_ro(struct mmc_host *mmc)
1679 {
1680 struct sdhci_host *host = mmc_priv(mmc);
1681 int ret;
1682
1683 sdhci_runtime_pm_get(host);
1684 ret = sdhci_do_get_ro(host);
1685 sdhci_runtime_pm_put(host);
1686 return ret;
1687 }
1688
1689 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1690 {
1691 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1692 if (enable)
1693 host->ier |= SDHCI_INT_CARD_INT;
1694 else
1695 host->ier &= ~SDHCI_INT_CARD_INT;
1696
1697 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1698 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1699 mmiowb();
1700 }
1701 }
1702
1703 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1704 {
1705 struct sdhci_host *host = mmc_priv(mmc);
1706 unsigned long flags;
1707
1708 sdhci_runtime_pm_get(host);
1709
1710 spin_lock_irqsave(&host->lock, flags);
1711 if (enable)
1712 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1713 else
1714 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1715
1716 sdhci_enable_sdio_irq_nolock(host, enable);
1717 spin_unlock_irqrestore(&host->lock, flags);
1718
1719 sdhci_runtime_pm_put(host);
1720 }
1721
1722 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1723 struct mmc_ios *ios)
1724 {
1725 struct mmc_host *mmc = host->mmc;
1726 u16 ctrl;
1727 int ret;
1728
1729 /*
1730 * Signal Voltage Switching is only applicable for Host Controllers
1731 * v3.00 and above.
1732 */
1733 if (host->version < SDHCI_SPEC_300)
1734 return 0;
1735
1736 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1737
1738 switch (ios->signal_voltage) {
1739 case MMC_SIGNAL_VOLTAGE_330:
1740 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1741 ctrl &= ~SDHCI_CTRL_VDD_180;
1742 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1743
1744 if (!IS_ERR(mmc->supply.vqmmc)) {
1745 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1746 3600000);
1747 if (ret) {
1748 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1749 mmc_hostname(mmc));
1750 return -EIO;
1751 }
1752 }
1753 /* Wait for 5ms */
1754 usleep_range(5000, 5500);
1755
1756 /* 3.3V regulator output should be stable within 5 ms */
1757 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1758 if (!(ctrl & SDHCI_CTRL_VDD_180))
1759 return 0;
1760
1761 pr_warn("%s: 3.3V regulator output did not became stable\n",
1762 mmc_hostname(mmc));
1763
1764 return -EAGAIN;
1765 case MMC_SIGNAL_VOLTAGE_180:
1766 if (!IS_ERR(mmc->supply.vqmmc)) {
1767 ret = regulator_set_voltage(mmc->supply.vqmmc,
1768 1700000, 1950000);
1769 if (ret) {
1770 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1771 mmc_hostname(mmc));
1772 return -EIO;
1773 }
1774 }
1775
1776 /*
1777 * Enable 1.8V Signal Enable in the Host Control2
1778 * register
1779 */
1780 ctrl |= SDHCI_CTRL_VDD_180;
1781 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1782
1783 /* Some controller need to do more when switching */
1784 if (host->ops->voltage_switch)
1785 host->ops->voltage_switch(host);
1786
1787 /* 1.8V regulator output should be stable within 5 ms */
1788 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1789 if (ctrl & SDHCI_CTRL_VDD_180)
1790 return 0;
1791
1792 pr_warn("%s: 1.8V regulator output did not became stable\n",
1793 mmc_hostname(mmc));
1794
1795 return -EAGAIN;
1796 case MMC_SIGNAL_VOLTAGE_120:
1797 if (!IS_ERR(mmc->supply.vqmmc)) {
1798 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1799 1300000);
1800 if (ret) {
1801 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1802 mmc_hostname(mmc));
1803 return -EIO;
1804 }
1805 }
1806 return 0;
1807 default:
1808 /* No signal voltage switch required */
1809 return 0;
1810 }
1811 }
1812
1813 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1814 struct mmc_ios *ios)
1815 {
1816 struct sdhci_host *host = mmc_priv(mmc);
1817 int err;
1818
1819 if (host->version < SDHCI_SPEC_300)
1820 return 0;
1821 sdhci_runtime_pm_get(host);
1822 err = sdhci_do_start_signal_voltage_switch(host, ios);
1823 sdhci_runtime_pm_put(host);
1824 return err;
1825 }
1826
1827 static int sdhci_card_busy(struct mmc_host *mmc)
1828 {
1829 struct sdhci_host *host = mmc_priv(mmc);
1830 u32 present_state;
1831
1832 sdhci_runtime_pm_get(host);
1833 /* Check whether DAT[3:0] is 0000 */
1834 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1835 sdhci_runtime_pm_put(host);
1836
1837 return !(present_state & SDHCI_DATA_LVL_MASK);
1838 }
1839
1840 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1841 {
1842 struct sdhci_host *host = mmc_priv(mmc);
1843 unsigned long flags;
1844
1845 spin_lock_irqsave(&host->lock, flags);
1846 host->flags |= SDHCI_HS400_TUNING;
1847 spin_unlock_irqrestore(&host->lock, flags);
1848
1849 return 0;
1850 }
1851
1852 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1853 {
1854 struct sdhci_host *host = mmc_priv(mmc);
1855 u16 ctrl;
1856 int tuning_loop_counter = MAX_TUNING_LOOP;
1857 int err = 0;
1858 unsigned long flags;
1859 unsigned int tuning_count = 0;
1860 bool hs400_tuning;
1861
1862 sdhci_runtime_pm_get(host);
1863 spin_lock_irqsave(&host->lock, flags);
1864
1865 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1866 host->flags &= ~SDHCI_HS400_TUNING;
1867
1868 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1869 tuning_count = host->tuning_count;
1870
1871 /*
1872 * The Host Controller needs tuning only in case of SDR104 mode
1873 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1874 * Capabilities register.
1875 * If the Host Controller supports the HS200 mode then the
1876 * tuning function has to be executed.
1877 */
1878 switch (host->timing) {
1879 /* HS400 tuning is done in HS200 mode */
1880 case MMC_TIMING_MMC_HS400:
1881 err = -EINVAL;
1882 goto out_unlock;
1883
1884 case MMC_TIMING_MMC_HS200:
1885 /*
1886 * Periodic re-tuning for HS400 is not expected to be needed, so
1887 * disable it here.
1888 */
1889 if (hs400_tuning)
1890 tuning_count = 0;
1891 break;
1892
1893 case MMC_TIMING_UHS_SDR104:
1894 break;
1895
1896 case MMC_TIMING_UHS_SDR50:
1897 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1898 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1899 break;
1900 /* FALLTHROUGH */
1901
1902 default:
1903 goto out_unlock;
1904 }
1905
1906 if (host->ops->platform_execute_tuning) {
1907 spin_unlock_irqrestore(&host->lock, flags);
1908 err = host->ops->platform_execute_tuning(host, opcode);
1909 sdhci_runtime_pm_put(host);
1910 return err;
1911 }
1912
1913 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1914 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1915 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1916 ctrl |= SDHCI_CTRL_TUNED_CLK;
1917 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1918
1919 /*
1920 * As per the Host Controller spec v3.00, tuning command
1921 * generates Buffer Read Ready interrupt, so enable that.
1922 *
1923 * Note: The spec clearly says that when tuning sequence
1924 * is being performed, the controller does not generate
1925 * interrupts other than Buffer Read Ready interrupt. But
1926 * to make sure we don't hit a controller bug, we _only_
1927 * enable Buffer Read Ready interrupt here.
1928 */
1929 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1930 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1931
1932 /*
1933 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1934 * of loops reaches 40 times or a timeout of 150ms occurs.
1935 */
1936 do {
1937 struct mmc_command cmd = {0};
1938 struct mmc_request mrq = {NULL};
1939
1940 cmd.opcode = opcode;
1941 cmd.arg = 0;
1942 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1943 cmd.retries = 0;
1944 cmd.data = NULL;
1945 cmd.error = 0;
1946
1947 if (tuning_loop_counter-- == 0)
1948 break;
1949
1950 mrq.cmd = &cmd;
1951 host->mrq = &mrq;
1952
1953 /*
1954 * In response to CMD19, the card sends 64 bytes of tuning
1955 * block to the Host Controller. So we set the block size
1956 * to 64 here.
1957 */
1958 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1959 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1960 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1961 SDHCI_BLOCK_SIZE);
1962 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1963 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1964 SDHCI_BLOCK_SIZE);
1965 } else {
1966 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1967 SDHCI_BLOCK_SIZE);
1968 }
1969
1970 /*
1971 * The tuning block is sent by the card to the host controller.
1972 * So we set the TRNS_READ bit in the Transfer Mode register.
1973 * This also takes care of setting DMA Enable and Multi Block
1974 * Select in the same register to 0.
1975 */
1976 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1977
1978 sdhci_send_command(host, &cmd);
1979
1980 host->cmd = NULL;
1981 host->mrq = NULL;
1982
1983 spin_unlock_irqrestore(&host->lock, flags);
1984 /* Wait for Buffer Read Ready interrupt */
1985 wait_event_interruptible_timeout(host->buf_ready_int,
1986 (host->tuning_done == 1),
1987 msecs_to_jiffies(50));
1988 spin_lock_irqsave(&host->lock, flags);
1989
1990 if (!host->tuning_done) {
1991 pr_info(DRIVER_NAME ": Timeout waiting for "
1992 "Buffer Read Ready interrupt during tuning "
1993 "procedure, falling back to fixed sampling "
1994 "clock\n");
1995 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1996 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1997 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1998 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1999
2000 err = -EIO;
2001 goto out;
2002 }
2003
2004 host->tuning_done = 0;
2005
2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2007
2008 /* eMMC spec does not require a delay between tuning cycles */
2009 if (opcode == MMC_SEND_TUNING_BLOCK)
2010 mdelay(1);
2011 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2012
2013 /*
2014 * The Host Driver has exhausted the maximum number of loops allowed,
2015 * so use fixed sampling frequency.
2016 */
2017 if (tuning_loop_counter < 0) {
2018 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2019 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2020 }
2021 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2022 pr_info(DRIVER_NAME ": Tuning procedure"
2023 " failed, falling back to fixed sampling"
2024 " clock\n");
2025 err = -EIO;
2026 }
2027
2028 out:
2029 if (tuning_count) {
2030 /*
2031 * In case tuning fails, host controllers which support
2032 * re-tuning can try tuning again at a later time, when the
2033 * re-tuning timer expires. So for these controllers, we
2034 * return 0. Since there might be other controllers who do not
2035 * have this capability, we return error for them.
2036 */
2037 err = 0;
2038 }
2039
2040 host->mmc->retune_period = err ? 0 : tuning_count;
2041
2042 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2043 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2044 out_unlock:
2045 spin_unlock_irqrestore(&host->lock, flags);
2046 sdhci_runtime_pm_put(host);
2047
2048 return err;
2049 }
2050
2051 static int sdhci_select_drive_strength(struct mmc_card *card,
2052 unsigned int max_dtr, int host_drv,
2053 int card_drv, int *drv_type)
2054 {
2055 struct sdhci_host *host = mmc_priv(card->host);
2056
2057 if (!host->ops->select_drive_strength)
2058 return 0;
2059
2060 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2061 card_drv, drv_type);
2062 }
2063
2064 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2065 {
2066 /* Host Controller v3.00 defines preset value registers */
2067 if (host->version < SDHCI_SPEC_300)
2068 return;
2069
2070 /*
2071 * We only enable or disable Preset Value if they are not already
2072 * enabled or disabled respectively. Otherwise, we bail out.
2073 */
2074 if (host->preset_enabled != enable) {
2075 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2076
2077 if (enable)
2078 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2079 else
2080 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2081
2082 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2083
2084 if (enable)
2085 host->flags |= SDHCI_PV_ENABLED;
2086 else
2087 host->flags &= ~SDHCI_PV_ENABLED;
2088
2089 host->preset_enabled = enable;
2090 }
2091 }
2092
2093 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2094 int err)
2095 {
2096 struct sdhci_host *host = mmc_priv(mmc);
2097 struct mmc_data *data = mrq->data;
2098
2099 if (host->flags & SDHCI_REQ_USE_DMA) {
2100 if (data->host_cookie)
2101 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2102 data->flags & MMC_DATA_WRITE ?
2103 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2104 mrq->data->host_cookie = 0;
2105 }
2106 }
2107
2108 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2109 struct mmc_data *data,
2110 struct sdhci_host_next *next)
2111 {
2112 int sg_count;
2113
2114 if (!next && data->host_cookie &&
2115 data->host_cookie != host->next_data.cookie) {
2116 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2117 __func__, data->host_cookie, host->next_data.cookie);
2118 data->host_cookie = 0;
2119 }
2120
2121 /* Check if next job is already prepared */
2122 if (next ||
2123 (!next && data->host_cookie != host->next_data.cookie)) {
2124 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2125 data->sg_len,
2126 data->flags & MMC_DATA_WRITE ?
2127 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2128
2129 } else {
2130 sg_count = host->next_data.sg_count;
2131 host->next_data.sg_count = 0;
2132 }
2133
2134
2135 if (sg_count == 0)
2136 return -EINVAL;
2137
2138 if (next) {
2139 next->sg_count = sg_count;
2140 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2141 } else
2142 host->sg_count = sg_count;
2143
2144 return sg_count;
2145 }
2146
2147 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2148 bool is_first_req)
2149 {
2150 struct sdhci_host *host = mmc_priv(mmc);
2151
2152 if (mrq->data->host_cookie) {
2153 mrq->data->host_cookie = 0;
2154 return;
2155 }
2156
2157 if (host->flags & SDHCI_REQ_USE_DMA)
2158 if (sdhci_pre_dma_transfer(host,
2159 mrq->data,
2160 &host->next_data) < 0)
2161 mrq->data->host_cookie = 0;
2162 }
2163
2164 static void sdhci_card_event(struct mmc_host *mmc)
2165 {
2166 struct sdhci_host *host = mmc_priv(mmc);
2167 unsigned long flags;
2168 int present;
2169
2170 /* First check if client has provided their own card event */
2171 if (host->ops->card_event)
2172 host->ops->card_event(host);
2173
2174 present = sdhci_do_get_cd(host);
2175
2176 spin_lock_irqsave(&host->lock, flags);
2177
2178 /* Check host->mrq first in case we are runtime suspended */
2179 if (host->mrq && !present) {
2180 pr_err("%s: Card removed during transfer!\n",
2181 mmc_hostname(host->mmc));
2182 pr_err("%s: Resetting controller.\n",
2183 mmc_hostname(host->mmc));
2184
2185 sdhci_do_reset(host, SDHCI_RESET_CMD);
2186 sdhci_do_reset(host, SDHCI_RESET_DATA);
2187
2188 host->mrq->cmd->error = -ENOMEDIUM;
2189 tasklet_schedule(&host->finish_tasklet);
2190 }
2191
2192 spin_unlock_irqrestore(&host->lock, flags);
2193 }
2194
2195 static const struct mmc_host_ops sdhci_ops = {
2196 .request = sdhci_request,
2197 .post_req = sdhci_post_req,
2198 .pre_req = sdhci_pre_req,
2199 .set_ios = sdhci_set_ios,
2200 .get_cd = sdhci_get_cd,
2201 .get_ro = sdhci_get_ro,
2202 .hw_reset = sdhci_hw_reset,
2203 .enable_sdio_irq = sdhci_enable_sdio_irq,
2204 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2205 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2206 .execute_tuning = sdhci_execute_tuning,
2207 .select_drive_strength = sdhci_select_drive_strength,
2208 .card_event = sdhci_card_event,
2209 .card_busy = sdhci_card_busy,
2210 };
2211
2212 /*****************************************************************************\
2213 * *
2214 * Tasklets *
2215 * *
2216 \*****************************************************************************/
2217
2218 static void sdhci_tasklet_finish(unsigned long param)
2219 {
2220 struct sdhci_host *host;
2221 unsigned long flags;
2222 struct mmc_request *mrq;
2223
2224 host = (struct sdhci_host*)param;
2225
2226 spin_lock_irqsave(&host->lock, flags);
2227
2228 /*
2229 * If this tasklet gets rescheduled while running, it will
2230 * be run again afterwards but without any active request.
2231 */
2232 if (!host->mrq) {
2233 spin_unlock_irqrestore(&host->lock, flags);
2234 return;
2235 }
2236
2237 del_timer(&host->timer);
2238
2239 mrq = host->mrq;
2240
2241 /*
2242 * The controller needs a reset of internal state machines
2243 * upon error conditions.
2244 */
2245 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2246 ((mrq->cmd && mrq->cmd->error) ||
2247 (mrq->sbc && mrq->sbc->error) ||
2248 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2249 (mrq->data->stop && mrq->data->stop->error))) ||
2250 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2251
2252 /* Some controllers need this kick or reset won't work here */
2253 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2254 /* This is to force an update */
2255 host->ops->set_clock(host, host->clock);
2256
2257 /* Spec says we should do both at the same time, but Ricoh
2258 controllers do not like that. */
2259 sdhci_do_reset(host, SDHCI_RESET_CMD);
2260 sdhci_do_reset(host, SDHCI_RESET_DATA);
2261 }
2262
2263 host->mrq = NULL;
2264 host->cmd = NULL;
2265 host->data = NULL;
2266
2267 #ifndef SDHCI_USE_LEDS_CLASS
2268 sdhci_deactivate_led(host);
2269 #endif
2270
2271 mmiowb();
2272 spin_unlock_irqrestore(&host->lock, flags);
2273
2274 mmc_request_done(host->mmc, mrq);
2275 sdhci_runtime_pm_put(host);
2276 }
2277
2278 static void sdhci_timeout_timer(unsigned long data)
2279 {
2280 struct sdhci_host *host;
2281 unsigned long flags;
2282
2283 host = (struct sdhci_host*)data;
2284
2285 spin_lock_irqsave(&host->lock, flags);
2286
2287 if (host->mrq) {
2288 pr_err("%s: Timeout waiting for hardware "
2289 "interrupt.\n", mmc_hostname(host->mmc));
2290 sdhci_dumpregs(host);
2291
2292 if (host->data) {
2293 host->data->error = -ETIMEDOUT;
2294 sdhci_finish_data(host);
2295 } else {
2296 if (host->cmd)
2297 host->cmd->error = -ETIMEDOUT;
2298 else
2299 host->mrq->cmd->error = -ETIMEDOUT;
2300
2301 tasklet_schedule(&host->finish_tasklet);
2302 }
2303 }
2304
2305 mmiowb();
2306 spin_unlock_irqrestore(&host->lock, flags);
2307 }
2308
2309 /*****************************************************************************\
2310 * *
2311 * Interrupt handling *
2312 * *
2313 \*****************************************************************************/
2314
2315 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2316 {
2317 BUG_ON(intmask == 0);
2318
2319 if (!host->cmd) {
2320 pr_err("%s: Got command interrupt 0x%08x even "
2321 "though no command operation was in progress.\n",
2322 mmc_hostname(host->mmc), (unsigned)intmask);
2323 sdhci_dumpregs(host);
2324 return;
2325 }
2326
2327 if (intmask & SDHCI_INT_TIMEOUT)
2328 host->cmd->error = -ETIMEDOUT;
2329 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2330 SDHCI_INT_INDEX))
2331 host->cmd->error = -EILSEQ;
2332
2333 if (host->cmd->error) {
2334 tasklet_schedule(&host->finish_tasklet);
2335 return;
2336 }
2337
2338 /*
2339 * The host can send and interrupt when the busy state has
2340 * ended, allowing us to wait without wasting CPU cycles.
2341 * Unfortunately this is overloaded on the "data complete"
2342 * interrupt, so we need to take some care when handling
2343 * it.
2344 *
2345 * Note: The 1.0 specification is a bit ambiguous about this
2346 * feature so there might be some problems with older
2347 * controllers.
2348 */
2349 if (host->cmd->flags & MMC_RSP_BUSY) {
2350 if (host->cmd->data)
2351 DBG("Cannot wait for busy signal when also "
2352 "doing a data transfer");
2353 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2354 && !host->busy_handle) {
2355 /* Mark that command complete before busy is ended */
2356 host->busy_handle = 1;
2357 return;
2358 }
2359
2360 /* The controller does not support the end-of-busy IRQ,
2361 * fall through and take the SDHCI_INT_RESPONSE */
2362 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2363 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2364 *mask &= ~SDHCI_INT_DATA_END;
2365 }
2366
2367 if (intmask & SDHCI_INT_RESPONSE)
2368 sdhci_finish_command(host);
2369 }
2370
2371 #ifdef CONFIG_MMC_DEBUG
2372 static void sdhci_adma_show_error(struct sdhci_host *host)
2373 {
2374 const char *name = mmc_hostname(host->mmc);
2375 void *desc = host->adma_table;
2376
2377 sdhci_dumpregs(host);
2378
2379 while (true) {
2380 struct sdhci_adma2_64_desc *dma_desc = desc;
2381
2382 if (host->flags & SDHCI_USE_64_BIT_DMA)
2383 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2384 name, desc, le32_to_cpu(dma_desc->addr_hi),
2385 le32_to_cpu(dma_desc->addr_lo),
2386 le16_to_cpu(dma_desc->len),
2387 le16_to_cpu(dma_desc->cmd));
2388 else
2389 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2390 name, desc, le32_to_cpu(dma_desc->addr_lo),
2391 le16_to_cpu(dma_desc->len),
2392 le16_to_cpu(dma_desc->cmd));
2393
2394 desc += host->desc_sz;
2395
2396 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2397 break;
2398 }
2399 }
2400 #else
2401 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2402 #endif
2403
2404 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2405 {
2406 u32 command;
2407 BUG_ON(intmask == 0);
2408
2409 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2410 if (intmask & SDHCI_INT_DATA_AVAIL) {
2411 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2412 if (command == MMC_SEND_TUNING_BLOCK ||
2413 command == MMC_SEND_TUNING_BLOCK_HS200) {
2414 host->tuning_done = 1;
2415 wake_up(&host->buf_ready_int);
2416 return;
2417 }
2418 }
2419
2420 if (!host->data) {
2421 /*
2422 * The "data complete" interrupt is also used to
2423 * indicate that a busy state has ended. See comment
2424 * above in sdhci_cmd_irq().
2425 */
2426 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2427 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2428 host->cmd->error = -ETIMEDOUT;
2429 tasklet_schedule(&host->finish_tasklet);
2430 return;
2431 }
2432 if (intmask & SDHCI_INT_DATA_END) {
2433 /*
2434 * Some cards handle busy-end interrupt
2435 * before the command completed, so make
2436 * sure we do things in the proper order.
2437 */
2438 if (host->busy_handle)
2439 sdhci_finish_command(host);
2440 else
2441 host->busy_handle = 1;
2442 return;
2443 }
2444 }
2445
2446 pr_err("%s: Got data interrupt 0x%08x even "
2447 "though no data operation was in progress.\n",
2448 mmc_hostname(host->mmc), (unsigned)intmask);
2449 sdhci_dumpregs(host);
2450
2451 return;
2452 }
2453
2454 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2455 host->data->error = -ETIMEDOUT;
2456 else if (intmask & SDHCI_INT_DATA_END_BIT)
2457 host->data->error = -EILSEQ;
2458 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2459 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2460 != MMC_BUS_TEST_R)
2461 host->data->error = -EILSEQ;
2462 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2463 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2464 sdhci_adma_show_error(host);
2465 host->data->error = -EIO;
2466 if (host->ops->adma_workaround)
2467 host->ops->adma_workaround(host, intmask);
2468 }
2469
2470 if (host->data->error)
2471 sdhci_finish_data(host);
2472 else {
2473 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2474 sdhci_transfer_pio(host);
2475
2476 /*
2477 * We currently don't do anything fancy with DMA
2478 * boundaries, but as we can't disable the feature
2479 * we need to at least restart the transfer.
2480 *
2481 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2482 * should return a valid address to continue from, but as
2483 * some controllers are faulty, don't trust them.
2484 */
2485 if (intmask & SDHCI_INT_DMA_END) {
2486 u32 dmastart, dmanow;
2487 dmastart = sg_dma_address(host->data->sg);
2488 dmanow = dmastart + host->data->bytes_xfered;
2489 /*
2490 * Force update to the next DMA block boundary.
2491 */
2492 dmanow = (dmanow &
2493 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2494 SDHCI_DEFAULT_BOUNDARY_SIZE;
2495 host->data->bytes_xfered = dmanow - dmastart;
2496 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2497 " next 0x%08x\n",
2498 mmc_hostname(host->mmc), dmastart,
2499 host->data->bytes_xfered, dmanow);
2500 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2501 }
2502
2503 if (intmask & SDHCI_INT_DATA_END) {
2504 if (host->cmd) {
2505 /*
2506 * Data managed to finish before the
2507 * command completed. Make sure we do
2508 * things in the proper order.
2509 */
2510 host->data_early = 1;
2511 } else {
2512 sdhci_finish_data(host);
2513 }
2514 }
2515 }
2516 }
2517
2518 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2519 {
2520 irqreturn_t result = IRQ_NONE;
2521 struct sdhci_host *host = dev_id;
2522 u32 intmask, mask, unexpected = 0;
2523 int max_loops = 16;
2524
2525 spin_lock(&host->lock);
2526
2527 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2528 spin_unlock(&host->lock);
2529 return IRQ_NONE;
2530 }
2531
2532 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2533 if (!intmask || intmask == 0xffffffff) {
2534 result = IRQ_NONE;
2535 goto out;
2536 }
2537
2538 do {
2539 /* Clear selected interrupts. */
2540 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2541 SDHCI_INT_BUS_POWER);
2542 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2543
2544 DBG("*** %s got interrupt: 0x%08x\n",
2545 mmc_hostname(host->mmc), intmask);
2546
2547 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2548 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2549 SDHCI_CARD_PRESENT;
2550
2551 /*
2552 * There is a observation on i.mx esdhc. INSERT
2553 * bit will be immediately set again when it gets
2554 * cleared, if a card is inserted. We have to mask
2555 * the irq to prevent interrupt storm which will
2556 * freeze the system. And the REMOVE gets the
2557 * same situation.
2558 *
2559 * More testing are needed here to ensure it works
2560 * for other platforms though.
2561 */
2562 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2563 SDHCI_INT_CARD_REMOVE);
2564 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2565 SDHCI_INT_CARD_INSERT;
2566 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2567 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2568
2569 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2570 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2571
2572 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2573 SDHCI_INT_CARD_REMOVE);
2574 result = IRQ_WAKE_THREAD;
2575 }
2576
2577 if (intmask & SDHCI_INT_CMD_MASK)
2578 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2579 &intmask);
2580
2581 if (intmask & SDHCI_INT_DATA_MASK)
2582 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2583
2584 if (intmask & SDHCI_INT_BUS_POWER)
2585 pr_err("%s: Card is consuming too much power!\n",
2586 mmc_hostname(host->mmc));
2587
2588 if (intmask & SDHCI_INT_CARD_INT) {
2589 sdhci_enable_sdio_irq_nolock(host, false);
2590 host->thread_isr |= SDHCI_INT_CARD_INT;
2591 result = IRQ_WAKE_THREAD;
2592 }
2593
2594 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2595 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2596 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2597 SDHCI_INT_CARD_INT);
2598
2599 if (intmask) {
2600 unexpected |= intmask;
2601 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2602 }
2603
2604 if (result == IRQ_NONE)
2605 result = IRQ_HANDLED;
2606
2607 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2608 } while (intmask && --max_loops);
2609 out:
2610 spin_unlock(&host->lock);
2611
2612 if (unexpected) {
2613 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2614 mmc_hostname(host->mmc), unexpected);
2615 sdhci_dumpregs(host);
2616 }
2617
2618 return result;
2619 }
2620
2621 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2622 {
2623 struct sdhci_host *host = dev_id;
2624 unsigned long flags;
2625 u32 isr;
2626
2627 spin_lock_irqsave(&host->lock, flags);
2628 isr = host->thread_isr;
2629 host->thread_isr = 0;
2630 spin_unlock_irqrestore(&host->lock, flags);
2631
2632 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2633 sdhci_card_event(host->mmc);
2634 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2635 }
2636
2637 if (isr & SDHCI_INT_CARD_INT) {
2638 sdio_run_irqs(host->mmc);
2639
2640 spin_lock_irqsave(&host->lock, flags);
2641 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2642 sdhci_enable_sdio_irq_nolock(host, true);
2643 spin_unlock_irqrestore(&host->lock, flags);
2644 }
2645
2646 return isr ? IRQ_HANDLED : IRQ_NONE;
2647 }
2648
2649 /*****************************************************************************\
2650 * *
2651 * Suspend/resume *
2652 * *
2653 \*****************************************************************************/
2654
2655 #ifdef CONFIG_PM
2656 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2657 {
2658 u8 val;
2659 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2660 | SDHCI_WAKE_ON_INT;
2661
2662 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2663 val |= mask ;
2664 /* Avoid fake wake up */
2665 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2666 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2667 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2668 }
2669 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2670
2671 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2672 {
2673 u8 val;
2674 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2675 | SDHCI_WAKE_ON_INT;
2676
2677 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2678 val &= ~mask;
2679 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2680 }
2681
2682 int sdhci_suspend_host(struct sdhci_host *host)
2683 {
2684 sdhci_disable_card_detection(host);
2685
2686 mmc_retune_timer_stop(host->mmc);
2687 mmc_retune_needed(host->mmc);
2688
2689 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2690 host->ier = 0;
2691 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2692 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2693 free_irq(host->irq, host);
2694 } else {
2695 sdhci_enable_irq_wakeups(host);
2696 enable_irq_wake(host->irq);
2697 }
2698 return 0;
2699 }
2700
2701 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2702
2703 int sdhci_resume_host(struct sdhci_host *host)
2704 {
2705 int ret = 0;
2706
2707 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2708 if (host->ops->enable_dma)
2709 host->ops->enable_dma(host);
2710 }
2711
2712 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2713 ret = request_threaded_irq(host->irq, sdhci_irq,
2714 sdhci_thread_irq, IRQF_SHARED,
2715 mmc_hostname(host->mmc), host);
2716 if (ret)
2717 return ret;
2718 } else {
2719 sdhci_disable_irq_wakeups(host);
2720 disable_irq_wake(host->irq);
2721 }
2722
2723 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2724 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2725 /* Card keeps power but host controller does not */
2726 sdhci_init(host, 0);
2727 host->pwr = 0;
2728 host->clock = 0;
2729 sdhci_do_set_ios(host, &host->mmc->ios);
2730 } else {
2731 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2732 mmiowb();
2733 }
2734
2735 sdhci_enable_card_detection(host);
2736
2737 return ret;
2738 }
2739
2740 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2741
2742 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2743 {
2744 return pm_runtime_get_sync(host->mmc->parent);
2745 }
2746
2747 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2748 {
2749 pm_runtime_mark_last_busy(host->mmc->parent);
2750 return pm_runtime_put_autosuspend(host->mmc->parent);
2751 }
2752
2753 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2754 {
2755 if (host->runtime_suspended || host->bus_on)
2756 return;
2757 host->bus_on = true;
2758 pm_runtime_get_noresume(host->mmc->parent);
2759 }
2760
2761 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2762 {
2763 if (host->runtime_suspended || !host->bus_on)
2764 return;
2765 host->bus_on = false;
2766 pm_runtime_put_noidle(host->mmc->parent);
2767 }
2768
2769 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2770 {
2771 unsigned long flags;
2772
2773 mmc_retune_timer_stop(host->mmc);
2774 mmc_retune_needed(host->mmc);
2775
2776 spin_lock_irqsave(&host->lock, flags);
2777 host->ier &= SDHCI_INT_CARD_INT;
2778 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2779 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2780 spin_unlock_irqrestore(&host->lock, flags);
2781
2782 synchronize_hardirq(host->irq);
2783
2784 spin_lock_irqsave(&host->lock, flags);
2785 host->runtime_suspended = true;
2786 spin_unlock_irqrestore(&host->lock, flags);
2787
2788 return 0;
2789 }
2790 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2791
2792 int sdhci_runtime_resume_host(struct sdhci_host *host)
2793 {
2794 unsigned long flags;
2795 int host_flags = host->flags;
2796
2797 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2798 if (host->ops->enable_dma)
2799 host->ops->enable_dma(host);
2800 }
2801
2802 sdhci_init(host, 0);
2803
2804 /* Force clock and power re-program */
2805 host->pwr = 0;
2806 host->clock = 0;
2807 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2808 sdhci_do_set_ios(host, &host->mmc->ios);
2809
2810 if ((host_flags & SDHCI_PV_ENABLED) &&
2811 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2812 spin_lock_irqsave(&host->lock, flags);
2813 sdhci_enable_preset_value(host, true);
2814 spin_unlock_irqrestore(&host->lock, flags);
2815 }
2816
2817 spin_lock_irqsave(&host->lock, flags);
2818
2819 host->runtime_suspended = false;
2820
2821 /* Enable SDIO IRQ */
2822 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2823 sdhci_enable_sdio_irq_nolock(host, true);
2824
2825 /* Enable Card Detection */
2826 sdhci_enable_card_detection(host);
2827
2828 spin_unlock_irqrestore(&host->lock, flags);
2829
2830 return 0;
2831 }
2832 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2833
2834 #endif /* CONFIG_PM */
2835
2836 /*****************************************************************************\
2837 * *
2838 * Device allocation/registration *
2839 * *
2840 \*****************************************************************************/
2841
2842 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2843 size_t priv_size)
2844 {
2845 struct mmc_host *mmc;
2846 struct sdhci_host *host;
2847
2848 WARN_ON(dev == NULL);
2849
2850 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2851 if (!mmc)
2852 return ERR_PTR(-ENOMEM);
2853
2854 host = mmc_priv(mmc);
2855 host->mmc = mmc;
2856
2857 return host;
2858 }
2859
2860 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2861
2862 int sdhci_add_host(struct sdhci_host *host)
2863 {
2864 struct mmc_host *mmc;
2865 u32 caps[2] = {0, 0};
2866 u32 max_current_caps;
2867 unsigned int ocr_avail;
2868 unsigned int override_timeout_clk;
2869 u32 max_clk;
2870 int ret;
2871
2872 WARN_ON(host == NULL);
2873 if (host == NULL)
2874 return -EINVAL;
2875
2876 mmc = host->mmc;
2877
2878 if (debug_quirks)
2879 host->quirks = debug_quirks;
2880 if (debug_quirks2)
2881 host->quirks2 = debug_quirks2;
2882
2883 override_timeout_clk = host->timeout_clk;
2884
2885 sdhci_do_reset(host, SDHCI_RESET_ALL);
2886
2887 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2888 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2889 >> SDHCI_SPEC_VER_SHIFT;
2890 if (host->version > SDHCI_SPEC_300) {
2891 pr_err("%s: Unknown controller version (%d). "
2892 "You may experience problems.\n", mmc_hostname(mmc),
2893 host->version);
2894 }
2895
2896 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2897 sdhci_readl(host, SDHCI_CAPABILITIES);
2898
2899 if (host->version >= SDHCI_SPEC_300)
2900 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2901 host->caps1 :
2902 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2903
2904 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2905 host->flags |= SDHCI_USE_SDMA;
2906 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2907 DBG("Controller doesn't have SDMA capability\n");
2908 else
2909 host->flags |= SDHCI_USE_SDMA;
2910
2911 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2912 (host->flags & SDHCI_USE_SDMA)) {
2913 DBG("Disabling DMA as it is marked broken\n");
2914 host->flags &= ~SDHCI_USE_SDMA;
2915 }
2916
2917 if ((host->version >= SDHCI_SPEC_200) &&
2918 (caps[0] & SDHCI_CAN_DO_ADMA2))
2919 host->flags |= SDHCI_USE_ADMA;
2920
2921 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2922 (host->flags & SDHCI_USE_ADMA)) {
2923 DBG("Disabling ADMA as it is marked broken\n");
2924 host->flags &= ~SDHCI_USE_ADMA;
2925 }
2926
2927 /*
2928 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2929 * and *must* do 64-bit DMA. A driver has the opportunity to change
2930 * that during the first call to ->enable_dma(). Similarly
2931 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2932 * implement.
2933 */
2934 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2935 host->flags |= SDHCI_USE_64_BIT_DMA;
2936
2937 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2938 if (host->ops->enable_dma) {
2939 if (host->ops->enable_dma(host)) {
2940 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2941 mmc_hostname(mmc));
2942 host->flags &=
2943 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2944 }
2945 }
2946 }
2947
2948 /* SDMA does not support 64-bit DMA */
2949 if (host->flags & SDHCI_USE_64_BIT_DMA)
2950 host->flags &= ~SDHCI_USE_SDMA;
2951
2952 if (host->flags & SDHCI_USE_ADMA) {
2953 /*
2954 * The DMA descriptor table size is calculated as the maximum
2955 * number of segments times 2, to allow for an alignment
2956 * descriptor for each segment, plus 1 for a nop end descriptor,
2957 * all multipled by the descriptor size.
2958 */
2959 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2960 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2961 SDHCI_ADMA2_64_DESC_SZ;
2962 host->align_buffer_sz = SDHCI_MAX_SEGS *
2963 SDHCI_ADMA2_64_ALIGN;
2964 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2965 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2966 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2967 } else {
2968 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2969 SDHCI_ADMA2_32_DESC_SZ;
2970 host->align_buffer_sz = SDHCI_MAX_SEGS *
2971 SDHCI_ADMA2_32_ALIGN;
2972 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2973 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2974 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2975 }
2976 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2977 host->adma_table_sz,
2978 &host->adma_addr,
2979 GFP_KERNEL);
2980 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2981 if (!host->adma_table || !host->align_buffer) {
2982 if (host->adma_table)
2983 dma_free_coherent(mmc_dev(mmc),
2984 host->adma_table_sz,
2985 host->adma_table,
2986 host->adma_addr);
2987 kfree(host->align_buffer);
2988 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2989 mmc_hostname(mmc));
2990 host->flags &= ~SDHCI_USE_ADMA;
2991 host->adma_table = NULL;
2992 host->align_buffer = NULL;
2993 } else if (host->adma_addr & host->align_mask) {
2994 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2995 mmc_hostname(mmc));
2996 host->flags &= ~SDHCI_USE_ADMA;
2997 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2998 host->adma_table, host->adma_addr);
2999 kfree(host->align_buffer);
3000 host->adma_table = NULL;
3001 host->align_buffer = NULL;
3002 }
3003 }
3004
3005 /*
3006 * If we use DMA, then it's up to the caller to set the DMA
3007 * mask, but PIO does not need the hw shim so we set a new
3008 * mask here in that case.
3009 */
3010 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3011 host->dma_mask = DMA_BIT_MASK(64);
3012 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3013 }
3014
3015 if (host->version >= SDHCI_SPEC_300)
3016 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3017 >> SDHCI_CLOCK_BASE_SHIFT;
3018 else
3019 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3020 >> SDHCI_CLOCK_BASE_SHIFT;
3021
3022 host->max_clk *= 1000000;
3023 if (host->max_clk == 0 || host->quirks &
3024 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3025 if (!host->ops->get_max_clock) {
3026 pr_err("%s: Hardware doesn't specify base clock "
3027 "frequency.\n", mmc_hostname(mmc));
3028 return -ENODEV;
3029 }
3030 host->max_clk = host->ops->get_max_clock(host);
3031 }
3032
3033 host->next_data.cookie = 1;
3034 /*
3035 * In case of Host Controller v3.00, find out whether clock
3036 * multiplier is supported.
3037 */
3038 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3039 SDHCI_CLOCK_MUL_SHIFT;
3040
3041 /*
3042 * In case the value in Clock Multiplier is 0, then programmable
3043 * clock mode is not supported, otherwise the actual clock
3044 * multiplier is one more than the value of Clock Multiplier
3045 * in the Capabilities Register.
3046 */
3047 if (host->clk_mul)
3048 host->clk_mul += 1;
3049
3050 /*
3051 * Set host parameters.
3052 */
3053 mmc->ops = &sdhci_ops;
3054 max_clk = host->max_clk;
3055
3056 if (host->ops->get_min_clock)
3057 mmc->f_min = host->ops->get_min_clock(host);
3058 else if (host->version >= SDHCI_SPEC_300) {
3059 if (host->clk_mul) {
3060 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3061 max_clk = host->max_clk * host->clk_mul;
3062 } else
3063 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3064 } else
3065 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3066
3067 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3068 mmc->f_max = max_clk;
3069
3070 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3071 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3072 SDHCI_TIMEOUT_CLK_SHIFT;
3073 if (host->timeout_clk == 0) {
3074 if (host->ops->get_timeout_clock) {
3075 host->timeout_clk =
3076 host->ops->get_timeout_clock(host);
3077 } else {
3078 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3079 mmc_hostname(mmc));
3080 return -ENODEV;
3081 }
3082 }
3083
3084 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3085 host->timeout_clk *= 1000;
3086
3087 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3088 host->ops->get_max_timeout_count(host) : 1 << 27;
3089 mmc->max_busy_timeout /= host->timeout_clk;
3090 }
3091
3092 if (override_timeout_clk)
3093 host->timeout_clk = override_timeout_clk;
3094
3095 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3096 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3097
3098 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3099 host->flags |= SDHCI_AUTO_CMD12;
3100
3101 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3102 if ((host->version >= SDHCI_SPEC_300) &&
3103 ((host->flags & SDHCI_USE_ADMA) ||
3104 !(host->flags & SDHCI_USE_SDMA)) &&
3105 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3106 host->flags |= SDHCI_AUTO_CMD23;
3107 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3108 } else {
3109 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3110 }
3111
3112 /*
3113 * A controller may support 8-bit width, but the board itself
3114 * might not have the pins brought out. Boards that support
3115 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3116 * their platform code before calling sdhci_add_host(), and we
3117 * won't assume 8-bit width for hosts without that CAP.
3118 */
3119 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3120 mmc->caps |= MMC_CAP_4_BIT_DATA;
3121
3122 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3123 mmc->caps &= ~MMC_CAP_CMD23;
3124
3125 if (caps[0] & SDHCI_CAN_DO_HISPD)
3126 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3127
3128 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3129 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3130 mmc->caps |= MMC_CAP_NEEDS_POLL;
3131
3132 /* If there are external regulators, get them */
3133 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3134 return -EPROBE_DEFER;
3135
3136 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3137 if (!IS_ERR(mmc->supply.vqmmc)) {
3138 ret = regulator_enable(mmc->supply.vqmmc);
3139 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3140 1950000))
3141 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3142 SDHCI_SUPPORT_SDR50 |
3143 SDHCI_SUPPORT_DDR50);
3144 if (ret) {
3145 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3146 mmc_hostname(mmc), ret);
3147 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3148 }
3149 }
3150
3151 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3152 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3153 SDHCI_SUPPORT_DDR50);
3154
3155 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3156 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3157 SDHCI_SUPPORT_DDR50))
3158 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3159
3160 /* SDR104 supports also implies SDR50 support */
3161 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3162 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3163 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3164 * field can be promoted to support HS200.
3165 */
3166 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3167 mmc->caps2 |= MMC_CAP2_HS200;
3168 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3169 mmc->caps |= MMC_CAP_UHS_SDR50;
3170
3171 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3172 (caps[1] & SDHCI_SUPPORT_HS400))
3173 mmc->caps2 |= MMC_CAP2_HS400;
3174
3175 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3176 (IS_ERR(mmc->supply.vqmmc) ||
3177 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3178 1300000)))
3179 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3180
3181 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3182 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3183 mmc->caps |= MMC_CAP_UHS_DDR50;
3184
3185 /* Does the host need tuning for SDR50? */
3186 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3187 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3188
3189 /* Does the host need tuning for SDR104 / HS200? */
3190 if (mmc->caps2 & MMC_CAP2_HS200)
3191 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3192
3193 /* Driver Type(s) (A, C, D) supported by the host */
3194 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3195 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3196 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3197 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3198 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3199 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3200
3201 /* Initial value for re-tuning timer count */
3202 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3203 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3204
3205 /*
3206 * In case Re-tuning Timer is not disabled, the actual value of
3207 * re-tuning timer will be 2 ^ (n - 1).
3208 */
3209 if (host->tuning_count)
3210 host->tuning_count = 1 << (host->tuning_count - 1);
3211
3212 /* Re-tuning mode supported by the Host Controller */
3213 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3214 SDHCI_RETUNING_MODE_SHIFT;
3215
3216 ocr_avail = 0;
3217
3218 /*
3219 * According to SD Host Controller spec v3.00, if the Host System
3220 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3221 * the value is meaningful only if Voltage Support in the Capabilities
3222 * register is set. The actual current value is 4 times the register
3223 * value.
3224 */
3225 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3226 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3227 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3228 if (curr > 0) {
3229
3230 /* convert to SDHCI_MAX_CURRENT format */
3231 curr = curr/1000; /* convert to mA */
3232 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3233
3234 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3235 max_current_caps =
3236 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3237 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3238 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3239 }
3240 }
3241
3242 if (caps[0] & SDHCI_CAN_VDD_330) {
3243 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3244
3245 mmc->max_current_330 = ((max_current_caps &
3246 SDHCI_MAX_CURRENT_330_MASK) >>
3247 SDHCI_MAX_CURRENT_330_SHIFT) *
3248 SDHCI_MAX_CURRENT_MULTIPLIER;
3249 }
3250 if (caps[0] & SDHCI_CAN_VDD_300) {
3251 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3252
3253 mmc->max_current_300 = ((max_current_caps &
3254 SDHCI_MAX_CURRENT_300_MASK) >>
3255 SDHCI_MAX_CURRENT_300_SHIFT) *
3256 SDHCI_MAX_CURRENT_MULTIPLIER;
3257 }
3258 if (caps[0] & SDHCI_CAN_VDD_180) {
3259 ocr_avail |= MMC_VDD_165_195;
3260
3261 mmc->max_current_180 = ((max_current_caps &
3262 SDHCI_MAX_CURRENT_180_MASK) >>
3263 SDHCI_MAX_CURRENT_180_SHIFT) *
3264 SDHCI_MAX_CURRENT_MULTIPLIER;
3265 }
3266
3267 /* If OCR set by host, use it instead. */
3268 if (host->ocr_mask)
3269 ocr_avail = host->ocr_mask;
3270
3271 /* If OCR set by external regulators, give it highest prio. */
3272 if (mmc->ocr_avail)
3273 ocr_avail = mmc->ocr_avail;
3274
3275 mmc->ocr_avail = ocr_avail;
3276 mmc->ocr_avail_sdio = ocr_avail;
3277 if (host->ocr_avail_sdio)
3278 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3279 mmc->ocr_avail_sd = ocr_avail;
3280 if (host->ocr_avail_sd)
3281 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3282 else /* normal SD controllers don't support 1.8V */
3283 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3284 mmc->ocr_avail_mmc = ocr_avail;
3285 if (host->ocr_avail_mmc)
3286 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3287
3288 if (mmc->ocr_avail == 0) {
3289 pr_err("%s: Hardware doesn't report any "
3290 "support voltages.\n", mmc_hostname(mmc));
3291 return -ENODEV;
3292 }
3293
3294 spin_lock_init(&host->lock);
3295
3296 /*
3297 * Maximum number of segments. Depends on if the hardware
3298 * can do scatter/gather or not.
3299 */
3300 if (host->flags & SDHCI_USE_ADMA)
3301 mmc->max_segs = SDHCI_MAX_SEGS;
3302 else if (host->flags & SDHCI_USE_SDMA)
3303 mmc->max_segs = 1;
3304 else /* PIO */
3305 mmc->max_segs = SDHCI_MAX_SEGS;
3306
3307 /*
3308 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3309 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3310 * is less anyway.
3311 */
3312 mmc->max_req_size = 524288;
3313
3314 /*
3315 * Maximum segment size. Could be one segment with the maximum number
3316 * of bytes. When doing hardware scatter/gather, each entry cannot
3317 * be larger than 64 KiB though.
3318 */
3319 if (host->flags & SDHCI_USE_ADMA) {
3320 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3321 mmc->max_seg_size = 65535;
3322 else
3323 mmc->max_seg_size = 65536;
3324 } else {
3325 mmc->max_seg_size = mmc->max_req_size;
3326 }
3327
3328 /*
3329 * Maximum block size. This varies from controller to controller and
3330 * is specified in the capabilities register.
3331 */
3332 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3333 mmc->max_blk_size = 2;
3334 } else {
3335 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3336 SDHCI_MAX_BLOCK_SHIFT;
3337 if (mmc->max_blk_size >= 3) {
3338 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3339 mmc_hostname(mmc));
3340 mmc->max_blk_size = 0;
3341 }
3342 }
3343
3344 mmc->max_blk_size = 512 << mmc->max_blk_size;
3345
3346 /*
3347 * Maximum block count.
3348 */
3349 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3350
3351 /*
3352 * Init tasklets.
3353 */
3354 tasklet_init(&host->finish_tasklet,
3355 sdhci_tasklet_finish, (unsigned long)host);
3356
3357 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3358
3359 init_waitqueue_head(&host->buf_ready_int);
3360
3361 sdhci_init(host, 0);
3362
3363 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3364 IRQF_SHARED, mmc_hostname(mmc), host);
3365 if (ret) {
3366 pr_err("%s: Failed to request IRQ %d: %d\n",
3367 mmc_hostname(mmc), host->irq, ret);
3368 goto untasklet;
3369 }
3370
3371 #ifdef CONFIG_MMC_DEBUG
3372 sdhci_dumpregs(host);
3373 #endif
3374
3375 #ifdef SDHCI_USE_LEDS_CLASS
3376 snprintf(host->led_name, sizeof(host->led_name),
3377 "%s::", mmc_hostname(mmc));
3378 host->led.name = host->led_name;
3379 host->led.brightness = LED_OFF;
3380 host->led.default_trigger = mmc_hostname(mmc);
3381 host->led.brightness_set = sdhci_led_control;
3382
3383 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3384 if (ret) {
3385 pr_err("%s: Failed to register LED device: %d\n",
3386 mmc_hostname(mmc), ret);
3387 goto reset;
3388 }
3389 #endif
3390
3391 mmiowb();
3392
3393 mmc_add_host(mmc);
3394
3395 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3396 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3397 (host->flags & SDHCI_USE_ADMA) ?
3398 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3399 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3400
3401 sdhci_enable_card_detection(host);
3402
3403 return 0;
3404
3405 #ifdef SDHCI_USE_LEDS_CLASS
3406 reset:
3407 sdhci_do_reset(host, SDHCI_RESET_ALL);
3408 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3409 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3410 free_irq(host->irq, host);
3411 #endif
3412 untasklet:
3413 tasklet_kill(&host->finish_tasklet);
3414
3415 return ret;
3416 }
3417
3418 EXPORT_SYMBOL_GPL(sdhci_add_host);
3419
3420 void sdhci_remove_host(struct sdhci_host *host, int dead)
3421 {
3422 struct mmc_host *mmc = host->mmc;
3423 unsigned long flags;
3424
3425 if (dead) {
3426 spin_lock_irqsave(&host->lock, flags);
3427
3428 host->flags |= SDHCI_DEVICE_DEAD;
3429
3430 if (host->mrq) {
3431 pr_err("%s: Controller removed during "
3432 " transfer!\n", mmc_hostname(mmc));
3433
3434 host->mrq->cmd->error = -ENOMEDIUM;
3435 tasklet_schedule(&host->finish_tasklet);
3436 }
3437
3438 spin_unlock_irqrestore(&host->lock, flags);
3439 }
3440
3441 sdhci_disable_card_detection(host);
3442
3443 mmc_remove_host(mmc);
3444
3445 #ifdef SDHCI_USE_LEDS_CLASS
3446 led_classdev_unregister(&host->led);
3447 #endif
3448
3449 if (!dead)
3450 sdhci_do_reset(host, SDHCI_RESET_ALL);
3451
3452 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3453 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3454 free_irq(host->irq, host);
3455
3456 del_timer_sync(&host->timer);
3457
3458 tasklet_kill(&host->finish_tasklet);
3459
3460 if (!IS_ERR(mmc->supply.vqmmc))
3461 regulator_disable(mmc->supply.vqmmc);
3462
3463 if (host->adma_table)
3464 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3465 host->adma_table, host->adma_addr);
3466 kfree(host->align_buffer);
3467
3468 host->adma_table = NULL;
3469 host->align_buffer = NULL;
3470 }
3471
3472 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3473
3474 void sdhci_free_host(struct sdhci_host *host)
3475 {
3476 mmc_free_host(host->mmc);
3477 }
3478
3479 EXPORT_SYMBOL_GPL(sdhci_free_host);
3480
3481 /*****************************************************************************\
3482 * *
3483 * Driver init/exit *
3484 * *
3485 \*****************************************************************************/
3486
3487 static int __init sdhci_drv_init(void)
3488 {
3489 pr_info(DRIVER_NAME
3490 ": Secure Digital Host Controller Interface driver\n");
3491 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3492
3493 return 0;
3494 }
3495
3496 static void __exit sdhci_drv_exit(void)
3497 {
3498 }
3499
3500 module_init(sdhci_drv_init);
3501 module_exit(sdhci_drv_exit);
3502
3503 module_param(debug_quirks, uint, 0444);
3504 module_param(debug_quirks2, uint, 0444);
3505
3506 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3507 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3508 MODULE_LICENSE("GPL");
3509
3510 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3511 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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