2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 static unsigned int debug_quirks
= 0;
48 static unsigned int debug_quirks2
;
50 static void sdhci_finish_data(struct sdhci_host
*);
52 static void sdhci_finish_command(struct sdhci_host
*);
53 static int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
);
54 static void sdhci_tuning_timer(unsigned long data
);
55 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
);
57 #ifdef CONFIG_PM_RUNTIME
58 static int sdhci_runtime_pm_get(struct sdhci_host
*host
);
59 static int sdhci_runtime_pm_put(struct sdhci_host
*host
);
60 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
);
61 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
);
63 static inline int sdhci_runtime_pm_get(struct sdhci_host
*host
)
67 static inline int sdhci_runtime_pm_put(struct sdhci_host
*host
)
71 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
74 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
79 static void sdhci_dumpregs(struct sdhci_host
*host
)
81 pr_debug(DRIVER_NAME
": =========== REGISTER DUMP (%s)===========\n",
82 mmc_hostname(host
->mmc
));
84 pr_debug(DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
85 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
86 sdhci_readw(host
, SDHCI_HOST_VERSION
));
87 pr_debug(DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
88 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
89 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
90 pr_debug(DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
91 sdhci_readl(host
, SDHCI_ARGUMENT
),
92 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
93 pr_debug(DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
94 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
95 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
96 pr_debug(DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
97 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
98 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
99 pr_debug(DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
100 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
101 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
102 pr_debug(DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
103 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
104 sdhci_readl(host
, SDHCI_INT_STATUS
));
105 pr_debug(DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
106 sdhci_readl(host
, SDHCI_INT_ENABLE
),
107 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
108 pr_debug(DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
109 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
110 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
111 pr_debug(DRIVER_NAME
": Caps: 0x%08x | Caps_1: 0x%08x\n",
112 sdhci_readl(host
, SDHCI_CAPABILITIES
),
113 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
114 pr_debug(DRIVER_NAME
": Cmd: 0x%08x | Max curr: 0x%08x\n",
115 sdhci_readw(host
, SDHCI_COMMAND
),
116 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
117 pr_debug(DRIVER_NAME
": Host ctl2: 0x%08x\n",
118 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
120 if (host
->flags
& SDHCI_USE_ADMA
)
121 pr_debug(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
122 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
123 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
125 pr_debug(DRIVER_NAME
": ===========================================\n");
128 /*****************************************************************************\
130 * Low level functions *
132 \*****************************************************************************/
134 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
138 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) ||
139 (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
))
143 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
146 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
147 SDHCI_INT_CARD_INSERT
;
149 host
->ier
&= ~(SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
);
152 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
153 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
156 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
158 sdhci_set_card_detection(host
, true);
161 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
163 sdhci_set_card_detection(host
, false);
166 void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
168 unsigned long timeout
;
170 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
172 if (mask
& SDHCI_RESET_ALL
) {
174 /* Reset-all turns off SD Bus Power */
175 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
176 sdhci_runtime_pm_bus_off(host
);
179 /* Wait max 100 ms */
182 /* hw clears the bit when it's done */
183 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
185 pr_err("%s: Reset 0x%x never completed.\n",
186 mmc_hostname(host
->mmc
), (int)mask
);
187 sdhci_dumpregs(host
);
194 EXPORT_SYMBOL_GPL(sdhci_reset
);
196 static void sdhci_do_reset(struct sdhci_host
*host
, u8 mask
)
198 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
199 if (!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
204 host
->ops
->reset(host
, mask
);
206 if (mask
& SDHCI_RESET_ALL
) {
207 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
208 if (host
->ops
->enable_dma
)
209 host
->ops
->enable_dma(host
);
212 /* Resetting the controller clears many */
213 host
->preset_enabled
= false;
217 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
);
219 static void sdhci_init(struct sdhci_host
*host
, int soft
)
222 sdhci_do_reset(host
, SDHCI_RESET_CMD
|SDHCI_RESET_DATA
);
224 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
226 host
->ier
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
227 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
|
228 SDHCI_INT_INDEX
| SDHCI_INT_END_BIT
| SDHCI_INT_CRC
|
229 SDHCI_INT_TIMEOUT
| SDHCI_INT_DATA_END
|
232 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
233 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
236 /* force clock reconfiguration */
238 sdhci_set_ios(host
->mmc
, &host
->mmc
->ios
);
242 static void sdhci_reinit(struct sdhci_host
*host
)
246 * Retuning stuffs are affected by different cards inserted and only
247 * applicable to UHS-I cards. So reset these fields to their initial
248 * value when card is removed.
250 if (host
->flags
& SDHCI_USING_RETUNING_TIMER
) {
251 host
->flags
&= ~SDHCI_USING_RETUNING_TIMER
;
253 del_timer_sync(&host
->tuning_timer
);
254 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
255 host
->mmc
->max_blk_count
=
256 (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
258 sdhci_enable_card_detection(host
);
261 static void sdhci_activate_led(struct sdhci_host
*host
)
265 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
266 ctrl
|= SDHCI_CTRL_LED
;
267 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
270 static void sdhci_deactivate_led(struct sdhci_host
*host
)
274 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
275 ctrl
&= ~SDHCI_CTRL_LED
;
276 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
279 #ifdef SDHCI_USE_LEDS_CLASS
280 static void sdhci_led_control(struct led_classdev
*led
,
281 enum led_brightness brightness
)
283 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
286 spin_lock_irqsave(&host
->lock
, flags
);
288 if (host
->runtime_suspended
)
291 if (brightness
== LED_OFF
)
292 sdhci_deactivate_led(host
);
294 sdhci_activate_led(host
);
296 spin_unlock_irqrestore(&host
->lock
, flags
);
300 /*****************************************************************************\
304 \*****************************************************************************/
306 static void sdhci_read_block_pio(struct sdhci_host
*host
)
309 size_t blksize
, len
, chunk
;
310 u32
uninitialized_var(scratch
);
313 DBG("PIO reading\n");
315 blksize
= host
->data
->blksz
;
318 local_irq_save(flags
);
321 if (!sg_miter_next(&host
->sg_miter
))
324 len
= min(host
->sg_miter
.length
, blksize
);
327 host
->sg_miter
.consumed
= len
;
329 buf
= host
->sg_miter
.addr
;
333 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
337 *buf
= scratch
& 0xFF;
346 sg_miter_stop(&host
->sg_miter
);
348 local_irq_restore(flags
);
351 static void sdhci_write_block_pio(struct sdhci_host
*host
)
354 size_t blksize
, len
, chunk
;
358 DBG("PIO writing\n");
360 blksize
= host
->data
->blksz
;
364 local_irq_save(flags
);
367 if (!sg_miter_next(&host
->sg_miter
))
370 len
= min(host
->sg_miter
.length
, blksize
);
373 host
->sg_miter
.consumed
= len
;
375 buf
= host
->sg_miter
.addr
;
378 scratch
|= (u32
)*buf
<< (chunk
* 8);
384 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
385 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
392 sg_miter_stop(&host
->sg_miter
);
394 local_irq_restore(flags
);
397 static void sdhci_transfer_pio(struct sdhci_host
*host
)
403 if (host
->blocks
== 0)
406 if (host
->data
->flags
& MMC_DATA_READ
)
407 mask
= SDHCI_DATA_AVAILABLE
;
409 mask
= SDHCI_SPACE_AVAILABLE
;
412 * Some controllers (JMicron JMB38x) mess up the buffer bits
413 * for transfers < 4 bytes. As long as it is just one block,
414 * we can ignore the bits.
416 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
417 (host
->data
->blocks
== 1))
420 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
421 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
424 if (host
->data
->flags
& MMC_DATA_READ
)
425 sdhci_read_block_pio(host
);
427 sdhci_write_block_pio(host
);
430 if (host
->blocks
== 0)
434 DBG("PIO transfer complete.\n");
437 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
439 local_irq_save(*flags
);
440 return kmap_atomic(sg_page(sg
)) + sg
->offset
;
443 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
445 kunmap_atomic(buffer
);
446 local_irq_restore(*flags
);
449 static void sdhci_adma_write_desc(void *desc
, u32 addr
, int len
, unsigned cmd
)
451 struct sdhci_adma2_32_desc
*dma_desc
= desc
;
453 dma_desc
->cmd
= cpu_to_le16(cmd
);
454 dma_desc
->len
= cpu_to_le16(len
);
455 dma_desc
->addr
= cpu_to_le32(addr
);
458 static void sdhci_adma_mark_end(void *desc
)
460 struct sdhci_adma2_32_desc
*dma_desc
= desc
;
462 dma_desc
->cmd
|= cpu_to_le16(ADMA2_END
);
465 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
466 struct mmc_data
*data
)
473 dma_addr_t align_addr
;
476 struct scatterlist
*sg
;
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
486 if (data
->flags
& MMC_DATA_READ
)
487 direction
= DMA_FROM_DEVICE
;
489 direction
= DMA_TO_DEVICE
;
491 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
492 host
->align_buffer
, host
->align_buffer_sz
, direction
);
493 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
495 BUG_ON(host
->align_addr
& host
->align_mask
);
497 host
->sg_count
= dma_map_sg(mmc_dev(host
->mmc
),
498 data
->sg
, data
->sg_len
, direction
);
499 if (host
->sg_count
== 0)
502 desc
= host
->adma_table
;
503 align
= host
->align_buffer
;
505 align_addr
= host
->align_addr
;
507 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
508 addr
= sg_dma_address(sg
);
509 len
= sg_dma_len(sg
);
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
518 offset
= (host
->align_sz
- (addr
& host
->align_mask
)) &
521 if (data
->flags
& MMC_DATA_WRITE
) {
522 buffer
= sdhci_kmap_atomic(sg
, &flags
);
523 WARN_ON(((long)buffer
& (PAGE_SIZE
- 1)) >
524 (PAGE_SIZE
- offset
));
525 memcpy(align
, buffer
, offset
);
526 sdhci_kunmap_atomic(buffer
, &flags
);
530 sdhci_adma_write_desc(desc
, align_addr
, offset
,
533 BUG_ON(offset
> 65536);
535 align
+= host
->align_sz
;
536 align_addr
+= host
->align_sz
;
538 desc
+= host
->desc_sz
;
547 sdhci_adma_write_desc(desc
, addr
, len
, ADMA2_TRAN_VALID
);
548 desc
+= host
->desc_sz
;
551 * If this triggers then we have a calculation bug
554 WARN_ON((desc
- host
->adma_table
) >= host
->adma_table_sz
);
557 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
559 * Mark the last descriptor as the terminating descriptor
561 if (desc
!= host
->adma_table
) {
562 desc
-= host
->desc_sz
;
563 sdhci_adma_mark_end(desc
);
567 * Add a terminating entry.
570 /* nop, end, valid */
571 sdhci_adma_write_desc(desc
, 0, 0, ADMA2_NOP_END_VALID
);
575 * Resync align buffer as we might have changed it.
577 if (data
->flags
& MMC_DATA_WRITE
) {
578 dma_sync_single_for_device(mmc_dev(host
->mmc
),
579 host
->align_addr
, host
->align_buffer_sz
, direction
);
585 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
586 host
->align_buffer_sz
, direction
);
591 static void sdhci_adma_table_post(struct sdhci_host
*host
,
592 struct mmc_data
*data
)
596 struct scatterlist
*sg
;
603 if (data
->flags
& MMC_DATA_READ
)
604 direction
= DMA_FROM_DEVICE
;
606 direction
= DMA_TO_DEVICE
;
608 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
609 host
->align_buffer_sz
, direction
);
611 /* Do a quick scan of the SG list for any unaligned mappings */
612 has_unaligned
= false;
613 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
)
614 if (sg_dma_address(sg
) & host
->align_mask
) {
615 has_unaligned
= true;
619 if (has_unaligned
&& data
->flags
& MMC_DATA_READ
) {
620 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
621 data
->sg_len
, direction
);
623 align
= host
->align_buffer
;
625 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
626 if (sg_dma_address(sg
) & host
->align_mask
) {
627 size
= host
->align_sz
-
628 (sg_dma_address(sg
) & host
->align_mask
);
630 buffer
= sdhci_kmap_atomic(sg
, &flags
);
631 WARN_ON(((long)buffer
& (PAGE_SIZE
- 1)) >
633 memcpy(buffer
, align
, size
);
634 sdhci_kunmap_atomic(buffer
, &flags
);
636 align
+= host
->align_sz
;
641 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
642 data
->sg_len
, direction
);
645 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
648 struct mmc_data
*data
= cmd
->data
;
649 unsigned target_timeout
, current_timeout
;
652 * If the host controller provides us with an incorrect timeout
653 * value, just skip the check and use 0xE. The hardware may take
654 * longer to time out, but that's much better than having a too-short
657 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
660 /* Unspecified timeout, assume max */
661 if (!data
&& !cmd
->busy_timeout
)
666 target_timeout
= cmd
->busy_timeout
* 1000;
668 target_timeout
= data
->timeout_ns
/ 1000;
670 target_timeout
+= data
->timeout_clks
/ host
->clock
;
674 * Figure out needed cycles.
675 * We do this in steps in order to fit inside a 32 bit int.
676 * The first step is the minimum timeout, which will have a
677 * minimum resolution of 6 bits:
678 * (1) 2^13*1000 > 2^22,
679 * (2) host->timeout_clk < 2^16
684 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
685 while (current_timeout
< target_timeout
) {
687 current_timeout
<<= 1;
693 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
694 mmc_hostname(host
->mmc
), count
, cmd
->opcode
);
701 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
703 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
704 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
706 if (host
->flags
& SDHCI_REQ_USE_DMA
)
707 host
->ier
= (host
->ier
& ~pio_irqs
) | dma_irqs
;
709 host
->ier
= (host
->ier
& ~dma_irqs
) | pio_irqs
;
711 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
712 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
715 static void sdhci_set_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
719 if (host
->ops
->set_timeout
) {
720 host
->ops
->set_timeout(host
, cmd
);
722 count
= sdhci_calc_timeout(host
, cmd
);
723 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
727 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
730 struct mmc_data
*data
= cmd
->data
;
735 if (data
|| (cmd
->flags
& MMC_RSP_BUSY
))
736 sdhci_set_timeout(host
, cmd
);
742 BUG_ON(data
->blksz
* data
->blocks
> 524288);
743 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
744 BUG_ON(data
->blocks
> 65535);
747 host
->data_early
= 0;
748 host
->data
->bytes_xfered
= 0;
750 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))
751 host
->flags
|= SDHCI_REQ_USE_DMA
;
754 * FIXME: This doesn't account for merging when mapping the
757 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
759 struct scatterlist
*sg
;
762 if (host
->flags
& SDHCI_USE_ADMA
) {
763 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
766 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
770 if (unlikely(broken
)) {
771 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
772 if (sg
->length
& 0x3) {
773 DBG("Reverting to PIO because of "
774 "transfer size (%d)\n",
776 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
784 * The assumption here being that alignment is the same after
785 * translation to device address space.
787 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
789 struct scatterlist
*sg
;
792 if (host
->flags
& SDHCI_USE_ADMA
) {
794 * As we use 3 byte chunks to work around
795 * alignment problems, we need to check this
798 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
801 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
805 if (unlikely(broken
)) {
806 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
807 if (sg
->offset
& 0x3) {
808 DBG("Reverting to PIO because of "
810 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
817 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
818 if (host
->flags
& SDHCI_USE_ADMA
) {
819 ret
= sdhci_adma_table_pre(host
, data
);
822 * This only happens when someone fed
823 * us an invalid request.
826 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
828 sdhci_writel(host
, host
->adma_addr
,
834 sg_cnt
= dma_map_sg(mmc_dev(host
->mmc
),
835 data
->sg
, data
->sg_len
,
836 (data
->flags
& MMC_DATA_READ
) ?
841 * This only happens when someone fed
842 * us an invalid request.
845 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
847 WARN_ON(sg_cnt
!= 1);
848 sdhci_writel(host
, sg_dma_address(data
->sg
),
855 * Always adjust the DMA selection as some controllers
856 * (e.g. JMicron) can't do PIO properly when the selection
859 if (host
->version
>= SDHCI_SPEC_200
) {
860 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
861 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
862 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
863 (host
->flags
& SDHCI_USE_ADMA
))
864 ctrl
|= SDHCI_CTRL_ADMA32
;
866 ctrl
|= SDHCI_CTRL_SDMA
;
867 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
870 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
873 flags
= SG_MITER_ATOMIC
;
874 if (host
->data
->flags
& MMC_DATA_READ
)
875 flags
|= SG_MITER_TO_SG
;
877 flags
|= SG_MITER_FROM_SG
;
878 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
879 host
->blocks
= data
->blocks
;
882 sdhci_set_transfer_irqs(host
);
884 /* Set the DMA boundary value and block size */
885 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
886 data
->blksz
), SDHCI_BLOCK_SIZE
);
887 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
890 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
891 struct mmc_command
*cmd
)
894 struct mmc_data
*data
= cmd
->data
;
897 /* clear Auto CMD settings for no data CMDs */
898 mode
= sdhci_readw(host
, SDHCI_TRANSFER_MODE
);
899 sdhci_writew(host
, mode
& ~(SDHCI_TRNS_AUTO_CMD12
|
900 SDHCI_TRNS_AUTO_CMD23
), SDHCI_TRANSFER_MODE
);
904 WARN_ON(!host
->data
);
906 mode
= SDHCI_TRNS_BLK_CNT_EN
;
907 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
908 mode
|= SDHCI_TRNS_MULTI
;
910 * If we are sending CMD23, CMD12 never gets sent
911 * on successful completion (so no Auto-CMD12).
913 if (!host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
))
914 mode
|= SDHCI_TRNS_AUTO_CMD12
;
915 else if (host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
916 mode
|= SDHCI_TRNS_AUTO_CMD23
;
917 sdhci_writel(host
, host
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
921 if (data
->flags
& MMC_DATA_READ
)
922 mode
|= SDHCI_TRNS_READ
;
923 if (host
->flags
& SDHCI_REQ_USE_DMA
)
924 mode
|= SDHCI_TRNS_DMA
;
926 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
929 static void sdhci_finish_data(struct sdhci_host
*host
)
931 struct mmc_data
*data
;
938 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
939 if (host
->flags
& SDHCI_USE_ADMA
)
940 sdhci_adma_table_post(host
, data
);
942 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
943 data
->sg_len
, (data
->flags
& MMC_DATA_READ
) ?
944 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
949 * The specification states that the block count register must
950 * be updated, but it does not specify at what point in the
951 * data flow. That makes the register entirely useless to read
952 * back so we have to assume that nothing made it to the card
953 * in the event of an error.
956 data
->bytes_xfered
= 0;
958 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
961 * Need to send CMD12 if -
962 * a) open-ended multiblock transfer (no CMD23)
963 * b) error in multiblock transfer
970 * The controller needs a reset of internal state machines
971 * upon error conditions.
974 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
975 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
978 sdhci_send_command(host
, data
->stop
);
980 tasklet_schedule(&host
->finish_tasklet
);
983 void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
987 unsigned long timeout
;
994 mask
= SDHCI_CMD_INHIBIT
;
995 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
996 mask
|= SDHCI_DATA_INHIBIT
;
998 /* We shouldn't wait for data inihibit for stop commands, even
999 though they might use busy signaling */
1000 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
1001 mask
&= ~SDHCI_DATA_INHIBIT
;
1003 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
1005 pr_err("%s: Controller never released "
1006 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
1007 sdhci_dumpregs(host
);
1009 tasklet_schedule(&host
->finish_tasklet
);
1017 if (!cmd
->data
&& cmd
->busy_timeout
> 9000)
1018 timeout
+= DIV_ROUND_UP(cmd
->busy_timeout
, 1000) * HZ
+ HZ
;
1021 mod_timer(&host
->timer
, timeout
);
1024 host
->busy_handle
= 0;
1026 sdhci_prepare_data(host
, cmd
);
1028 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
1030 sdhci_set_transfer_mode(host
, cmd
);
1032 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
1033 pr_err("%s: Unsupported response type!\n",
1034 mmc_hostname(host
->mmc
));
1035 cmd
->error
= -EINVAL
;
1036 tasklet_schedule(&host
->finish_tasklet
);
1040 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
1041 flags
= SDHCI_CMD_RESP_NONE
;
1042 else if (cmd
->flags
& MMC_RSP_136
)
1043 flags
= SDHCI_CMD_RESP_LONG
;
1044 else if (cmd
->flags
& MMC_RSP_BUSY
)
1045 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
1047 flags
= SDHCI_CMD_RESP_SHORT
;
1049 if (cmd
->flags
& MMC_RSP_CRC
)
1050 flags
|= SDHCI_CMD_CRC
;
1051 if (cmd
->flags
& MMC_RSP_OPCODE
)
1052 flags
|= SDHCI_CMD_INDEX
;
1054 /* CMD19 is special in that the Data Present Select should be set */
1055 if (cmd
->data
|| cmd
->opcode
== MMC_SEND_TUNING_BLOCK
||
1056 cmd
->opcode
== MMC_SEND_TUNING_BLOCK_HS200
)
1057 flags
|= SDHCI_CMD_DATA
;
1059 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1061 EXPORT_SYMBOL_GPL(sdhci_send_command
);
1063 static void sdhci_finish_command(struct sdhci_host
*host
)
1067 BUG_ON(host
->cmd
== NULL
);
1069 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
1070 if (host
->cmd
->flags
& MMC_RSP_136
) {
1071 /* CRC is stripped so we need to do some shifting. */
1072 for (i
= 0;i
< 4;i
++) {
1073 host
->cmd
->resp
[i
] = sdhci_readl(host
,
1074 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
1076 host
->cmd
->resp
[i
] |=
1078 SDHCI_RESPONSE
+ (3-i
)*4-1);
1081 host
->cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1085 host
->cmd
->error
= 0;
1087 /* Finished CMD23, now send actual command. */
1088 if (host
->cmd
== host
->mrq
->sbc
) {
1090 sdhci_send_command(host
, host
->mrq
->cmd
);
1093 /* Processed actual command. */
1094 if (host
->data
&& host
->data_early
)
1095 sdhci_finish_data(host
);
1097 if (!host
->cmd
->data
)
1098 tasklet_schedule(&host
->finish_tasklet
);
1104 static u16
sdhci_get_preset_value(struct sdhci_host
*host
)
1108 switch (host
->timing
) {
1109 case MMC_TIMING_UHS_SDR12
:
1110 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1112 case MMC_TIMING_UHS_SDR25
:
1113 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR25
);
1115 case MMC_TIMING_UHS_SDR50
:
1116 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR50
);
1118 case MMC_TIMING_UHS_SDR104
:
1119 case MMC_TIMING_MMC_HS200
:
1120 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR104
);
1122 case MMC_TIMING_UHS_DDR50
:
1123 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_DDR50
);
1126 pr_warn("%s: Invalid UHS-I mode selected\n",
1127 mmc_hostname(host
->mmc
));
1128 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1134 void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1136 int div
= 0; /* Initialized for compiler warning */
1137 int real_div
= div
, clk_mul
= 1;
1139 unsigned long timeout
;
1141 host
->mmc
->actual_clock
= 0;
1143 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1148 if (host
->version
>= SDHCI_SPEC_300
) {
1149 if (host
->preset_enabled
) {
1152 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1153 pre_val
= sdhci_get_preset_value(host
);
1154 div
= (pre_val
& SDHCI_PRESET_SDCLK_FREQ_MASK
)
1155 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT
;
1156 if (host
->clk_mul
&&
1157 (pre_val
& SDHCI_PRESET_CLKGEN_SEL_MASK
)) {
1158 clk
= SDHCI_PROG_CLOCK_MODE
;
1160 clk_mul
= host
->clk_mul
;
1162 real_div
= max_t(int, 1, div
<< 1);
1168 * Check if the Host Controller supports Programmable Clock
1171 if (host
->clk_mul
) {
1172 for (div
= 1; div
<= 1024; div
++) {
1173 if ((host
->max_clk
* host
->clk_mul
/ div
)
1178 * Set Programmable Clock Mode in the Clock
1181 clk
= SDHCI_PROG_CLOCK_MODE
;
1183 clk_mul
= host
->clk_mul
;
1186 /* Version 3.00 divisors must be a multiple of 2. */
1187 if (host
->max_clk
<= clock
)
1190 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1192 if ((host
->max_clk
/ div
) <= clock
)
1200 /* Version 2.00 divisors must be a power of 2. */
1201 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1202 if ((host
->max_clk
/ div
) <= clock
)
1211 host
->mmc
->actual_clock
= (host
->max_clk
* clk_mul
) / real_div
;
1212 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1213 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1214 << SDHCI_DIVIDER_HI_SHIFT
;
1215 clk
|= SDHCI_CLOCK_INT_EN
;
1216 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1218 /* Wait max 20 ms */
1220 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1221 & SDHCI_CLOCK_INT_STABLE
)) {
1223 pr_err("%s: Internal clock never "
1224 "stabilised.\n", mmc_hostname(host
->mmc
));
1225 sdhci_dumpregs(host
);
1232 clk
|= SDHCI_CLOCK_CARD_EN
;
1233 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1235 EXPORT_SYMBOL_GPL(sdhci_set_clock
);
1237 static void sdhci_set_power(struct sdhci_host
*host
, unsigned char mode
,
1240 struct mmc_host
*mmc
= host
->mmc
;
1243 if (!IS_ERR(mmc
->supply
.vmmc
)) {
1244 spin_unlock_irq(&host
->lock
);
1245 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, vdd
);
1246 spin_lock_irq(&host
->lock
);
1250 if (mode
!= MMC_POWER_OFF
) {
1252 case MMC_VDD_165_195
:
1253 pwr
= SDHCI_POWER_180
;
1257 pwr
= SDHCI_POWER_300
;
1261 pwr
= SDHCI_POWER_330
;
1268 if (host
->pwr
== pwr
)
1274 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1275 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1276 sdhci_runtime_pm_bus_off(host
);
1280 * Spec says that we should clear the power reg before setting
1281 * a new value. Some controllers don't seem to like this though.
1283 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1284 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1287 * At least the Marvell CaFe chip gets confused if we set the
1288 * voltage and set turn on power at the same time, so set the
1291 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1292 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1294 pwr
|= SDHCI_POWER_ON
;
1296 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1298 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1299 sdhci_runtime_pm_bus_on(host
);
1302 * Some controllers need an extra 10ms delay of 10ms before
1303 * they can apply clock after applying power
1305 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1310 /*****************************************************************************\
1314 \*****************************************************************************/
1316 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1318 struct sdhci_host
*host
;
1320 unsigned long flags
;
1323 host
= mmc_priv(mmc
);
1325 sdhci_runtime_pm_get(host
);
1327 spin_lock_irqsave(&host
->lock
, flags
);
1329 WARN_ON(host
->mrq
!= NULL
);
1331 #ifndef SDHCI_USE_LEDS_CLASS
1332 sdhci_activate_led(host
);
1336 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1337 * requests if Auto-CMD12 is enabled.
1339 if (!mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
)) {
1341 mrq
->data
->stop
= NULL
;
1349 * Firstly check card presence from cd-gpio. The return could
1350 * be one of the following possibilities:
1351 * negative: cd-gpio is not available
1352 * zero: cd-gpio is used, and card is removed
1353 * one: cd-gpio is used, and card is present
1355 present
= mmc_gpio_get_cd(host
->mmc
);
1357 /* If polling, assume that the card is always present. */
1358 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1361 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
1365 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1366 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1367 tasklet_schedule(&host
->finish_tasklet
);
1371 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1373 * Check if the re-tuning timer has already expired and there
1374 * is no on-going data transfer and DAT0 is not busy. If so,
1375 * we need to execute tuning procedure before sending command.
1377 if ((host
->flags
& SDHCI_NEEDS_RETUNING
) &&
1378 !(present_state
& (SDHCI_DOING_WRITE
| SDHCI_DOING_READ
)) &&
1379 (present_state
& SDHCI_DATA_0_LVL_MASK
)) {
1381 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1383 mmc
->card
->type
== MMC_TYPE_MMC
?
1384 MMC_SEND_TUNING_BLOCK_HS200
:
1385 MMC_SEND_TUNING_BLOCK
;
1387 /* Here we need to set the host->mrq to NULL,
1388 * in case the pending finish_tasklet
1389 * finishes it incorrectly.
1393 spin_unlock_irqrestore(&host
->lock
, flags
);
1394 sdhci_execute_tuning(mmc
, tuning_opcode
);
1395 spin_lock_irqsave(&host
->lock
, flags
);
1397 /* Restore original mmc_request structure */
1402 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1403 sdhci_send_command(host
, mrq
->sbc
);
1405 sdhci_send_command(host
, mrq
->cmd
);
1409 spin_unlock_irqrestore(&host
->lock
, flags
);
1412 void sdhci_set_bus_width(struct sdhci_host
*host
, int width
)
1416 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1417 if (width
== MMC_BUS_WIDTH_8
) {
1418 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1419 if (host
->version
>= SDHCI_SPEC_300
)
1420 ctrl
|= SDHCI_CTRL_8BITBUS
;
1422 if (host
->version
>= SDHCI_SPEC_300
)
1423 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1424 if (width
== MMC_BUS_WIDTH_4
)
1425 ctrl
|= SDHCI_CTRL_4BITBUS
;
1427 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1429 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1431 EXPORT_SYMBOL_GPL(sdhci_set_bus_width
);
1433 void sdhci_set_uhs_signaling(struct sdhci_host
*host
, unsigned timing
)
1437 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1438 /* Select Bus Speed Mode for host */
1439 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1440 if ((timing
== MMC_TIMING_MMC_HS200
) ||
1441 (timing
== MMC_TIMING_UHS_SDR104
))
1442 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1443 else if (timing
== MMC_TIMING_UHS_SDR12
)
1444 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1445 else if (timing
== MMC_TIMING_UHS_SDR25
)
1446 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1447 else if (timing
== MMC_TIMING_UHS_SDR50
)
1448 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1449 else if ((timing
== MMC_TIMING_UHS_DDR50
) ||
1450 (timing
== MMC_TIMING_MMC_DDR52
))
1451 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1452 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1454 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling
);
1456 static void sdhci_do_set_ios(struct sdhci_host
*host
, struct mmc_ios
*ios
)
1458 unsigned long flags
;
1460 struct mmc_host
*mmc
= host
->mmc
;
1462 spin_lock_irqsave(&host
->lock
, flags
);
1464 if (host
->flags
& SDHCI_DEVICE_DEAD
) {
1465 spin_unlock_irqrestore(&host
->lock
, flags
);
1466 if (!IS_ERR(mmc
->supply
.vmmc
) &&
1467 ios
->power_mode
== MMC_POWER_OFF
)
1468 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1473 * Reset the chip on each power off.
1474 * Should clear out any weird states.
1476 if (ios
->power_mode
== MMC_POWER_OFF
) {
1477 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1481 if (host
->version
>= SDHCI_SPEC_300
&&
1482 (ios
->power_mode
== MMC_POWER_UP
) &&
1483 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
))
1484 sdhci_enable_preset_value(host
, false);
1486 if (!ios
->clock
|| ios
->clock
!= host
->clock
) {
1487 host
->ops
->set_clock(host
, ios
->clock
);
1488 host
->clock
= ios
->clock
;
1490 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
&&
1492 host
->timeout_clk
= host
->mmc
->actual_clock
?
1493 host
->mmc
->actual_clock
/ 1000 :
1495 host
->mmc
->max_busy_timeout
=
1496 host
->ops
->get_max_timeout_count
?
1497 host
->ops
->get_max_timeout_count(host
) :
1499 host
->mmc
->max_busy_timeout
/= host
->timeout_clk
;
1503 sdhci_set_power(host
, ios
->power_mode
, ios
->vdd
);
1505 if (host
->ops
->platform_send_init_74_clocks
)
1506 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1508 host
->ops
->set_bus_width(host
, ios
->bus_width
);
1510 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1512 if ((ios
->timing
== MMC_TIMING_SD_HS
||
1513 ios
->timing
== MMC_TIMING_MMC_HS
)
1514 && !(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
))
1515 ctrl
|= SDHCI_CTRL_HISPD
;
1517 ctrl
&= ~SDHCI_CTRL_HISPD
;
1519 if (host
->version
>= SDHCI_SPEC_300
) {
1522 /* In case of UHS-I modes, set High Speed Enable */
1523 if ((ios
->timing
== MMC_TIMING_MMC_HS200
) ||
1524 (ios
->timing
== MMC_TIMING_MMC_DDR52
) ||
1525 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1526 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1527 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1528 (ios
->timing
== MMC_TIMING_UHS_SDR25
))
1529 ctrl
|= SDHCI_CTRL_HISPD
;
1531 if (!host
->preset_enabled
) {
1532 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1534 * We only need to set Driver Strength if the
1535 * preset value enable is not set.
1537 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1538 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1539 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1540 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1541 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1542 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1544 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1547 * According to SDHC Spec v3.00, if the Preset Value
1548 * Enable in the Host Control 2 register is set, we
1549 * need to reset SD Clock Enable before changing High
1550 * Speed Enable to avoid generating clock gliches.
1553 /* Reset SD Clock Enable */
1554 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1555 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1556 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1558 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1560 /* Re-enable SD Clock */
1561 host
->ops
->set_clock(host
, host
->clock
);
1564 /* Reset SD Clock Enable */
1565 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1566 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1567 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1569 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1570 host
->timing
= ios
->timing
;
1572 if (!(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
) &&
1573 ((ios
->timing
== MMC_TIMING_UHS_SDR12
) ||
1574 (ios
->timing
== MMC_TIMING_UHS_SDR25
) ||
1575 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1576 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1577 (ios
->timing
== MMC_TIMING_UHS_DDR50
))) {
1580 sdhci_enable_preset_value(host
, true);
1581 preset
= sdhci_get_preset_value(host
);
1582 ios
->drv_type
= (preset
& SDHCI_PRESET_DRV_MASK
)
1583 >> SDHCI_PRESET_DRV_SHIFT
;
1586 /* Re-enable SD Clock */
1587 host
->ops
->set_clock(host
, host
->clock
);
1589 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1592 * Some (ENE) controllers go apeshit on some ios operation,
1593 * signalling timeout and CRC errors even on CMD0. Resetting
1594 * it on each ios seems to solve the problem.
1596 if(host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1597 sdhci_do_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1600 spin_unlock_irqrestore(&host
->lock
, flags
);
1603 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1605 struct sdhci_host
*host
= mmc_priv(mmc
);
1607 sdhci_runtime_pm_get(host
);
1608 sdhci_do_set_ios(host
, ios
);
1609 sdhci_runtime_pm_put(host
);
1612 static int sdhci_do_get_cd(struct sdhci_host
*host
)
1614 int gpio_cd
= mmc_gpio_get_cd(host
->mmc
);
1616 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1619 /* If polling/nonremovable, assume that the card is always present. */
1620 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) ||
1621 (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
))
1624 /* Try slot gpio detect */
1625 if (!IS_ERR_VALUE(gpio_cd
))
1628 /* Host native card detect */
1629 return !!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
);
1632 static int sdhci_get_cd(struct mmc_host
*mmc
)
1634 struct sdhci_host
*host
= mmc_priv(mmc
);
1637 sdhci_runtime_pm_get(host
);
1638 ret
= sdhci_do_get_cd(host
);
1639 sdhci_runtime_pm_put(host
);
1643 static int sdhci_check_ro(struct sdhci_host
*host
)
1645 unsigned long flags
;
1648 spin_lock_irqsave(&host
->lock
, flags
);
1650 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1652 else if (host
->ops
->get_ro
)
1653 is_readonly
= host
->ops
->get_ro(host
);
1655 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1656 & SDHCI_WRITE_PROTECT
);
1658 spin_unlock_irqrestore(&host
->lock
, flags
);
1660 /* This quirk needs to be replaced by a callback-function later */
1661 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1662 !is_readonly
: is_readonly
;
1665 #define SAMPLE_COUNT 5
1667 static int sdhci_do_get_ro(struct sdhci_host
*host
)
1671 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1672 return sdhci_check_ro(host
);
1675 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1676 if (sdhci_check_ro(host
)) {
1677 if (++ro_count
> SAMPLE_COUNT
/ 2)
1685 static void sdhci_hw_reset(struct mmc_host
*mmc
)
1687 struct sdhci_host
*host
= mmc_priv(mmc
);
1689 if (host
->ops
&& host
->ops
->hw_reset
)
1690 host
->ops
->hw_reset(host
);
1693 static int sdhci_get_ro(struct mmc_host
*mmc
)
1695 struct sdhci_host
*host
= mmc_priv(mmc
);
1698 sdhci_runtime_pm_get(host
);
1699 ret
= sdhci_do_get_ro(host
);
1700 sdhci_runtime_pm_put(host
);
1704 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host
*host
, int enable
)
1706 if (!(host
->flags
& SDHCI_DEVICE_DEAD
)) {
1708 host
->ier
|= SDHCI_INT_CARD_INT
;
1710 host
->ier
&= ~SDHCI_INT_CARD_INT
;
1712 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
1713 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
1718 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1720 struct sdhci_host
*host
= mmc_priv(mmc
);
1721 unsigned long flags
;
1723 sdhci_runtime_pm_get(host
);
1725 spin_lock_irqsave(&host
->lock
, flags
);
1727 host
->flags
|= SDHCI_SDIO_IRQ_ENABLED
;
1729 host
->flags
&= ~SDHCI_SDIO_IRQ_ENABLED
;
1731 sdhci_enable_sdio_irq_nolock(host
, enable
);
1732 spin_unlock_irqrestore(&host
->lock
, flags
);
1734 sdhci_runtime_pm_put(host
);
1737 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host
*host
,
1738 struct mmc_ios
*ios
)
1740 struct mmc_host
*mmc
= host
->mmc
;
1745 * Signal Voltage Switching is only applicable for Host Controllers
1748 if (host
->version
< SDHCI_SPEC_300
)
1751 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1753 switch (ios
->signal_voltage
) {
1754 case MMC_SIGNAL_VOLTAGE_330
:
1755 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1756 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1757 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1759 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1760 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 2700000,
1763 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1769 usleep_range(5000, 5500);
1771 /* 3.3V regulator output should be stable within 5 ms */
1772 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1773 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1776 pr_warn("%s: 3.3V regulator output did not became stable\n",
1780 case MMC_SIGNAL_VOLTAGE_180
:
1781 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1782 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
,
1785 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1792 * Enable 1.8V Signal Enable in the Host Control2
1795 ctrl
|= SDHCI_CTRL_VDD_180
;
1796 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1798 /* 1.8V regulator output should be stable within 5 ms */
1799 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1800 if (ctrl
& SDHCI_CTRL_VDD_180
)
1803 pr_warn("%s: 1.8V regulator output did not became stable\n",
1807 case MMC_SIGNAL_VOLTAGE_120
:
1808 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1809 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 1100000,
1812 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1819 /* No signal voltage switch required */
1824 static int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1825 struct mmc_ios
*ios
)
1827 struct sdhci_host
*host
= mmc_priv(mmc
);
1830 if (host
->version
< SDHCI_SPEC_300
)
1832 sdhci_runtime_pm_get(host
);
1833 err
= sdhci_do_start_signal_voltage_switch(host
, ios
);
1834 sdhci_runtime_pm_put(host
);
1838 static int sdhci_card_busy(struct mmc_host
*mmc
)
1840 struct sdhci_host
*host
= mmc_priv(mmc
);
1843 sdhci_runtime_pm_get(host
);
1844 /* Check whether DAT[3:0] is 0000 */
1845 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1846 sdhci_runtime_pm_put(host
);
1848 return !(present_state
& SDHCI_DATA_LVL_MASK
);
1851 static int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1853 struct sdhci_host
*host
= mmc_priv(mmc
);
1855 int tuning_loop_counter
= MAX_TUNING_LOOP
;
1857 unsigned long flags
;
1859 sdhci_runtime_pm_get(host
);
1860 spin_lock_irqsave(&host
->lock
, flags
);
1863 * The Host Controller needs tuning only in case of SDR104 mode
1864 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1865 * Capabilities register.
1866 * If the Host Controller supports the HS200 mode then the
1867 * tuning function has to be executed.
1869 switch (host
->timing
) {
1870 case MMC_TIMING_MMC_HS200
:
1871 case MMC_TIMING_UHS_SDR104
:
1874 case MMC_TIMING_UHS_SDR50
:
1875 if (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
||
1876 host
->flags
& SDHCI_SDR104_NEEDS_TUNING
)
1881 spin_unlock_irqrestore(&host
->lock
, flags
);
1882 sdhci_runtime_pm_put(host
);
1886 if (host
->ops
->platform_execute_tuning
) {
1887 spin_unlock_irqrestore(&host
->lock
, flags
);
1888 err
= host
->ops
->platform_execute_tuning(host
, opcode
);
1889 sdhci_runtime_pm_put(host
);
1893 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1894 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1895 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1898 * As per the Host Controller spec v3.00, tuning command
1899 * generates Buffer Read Ready interrupt, so enable that.
1901 * Note: The spec clearly says that when tuning sequence
1902 * is being performed, the controller does not generate
1903 * interrupts other than Buffer Read Ready interrupt. But
1904 * to make sure we don't hit a controller bug, we _only_
1905 * enable Buffer Read Ready interrupt here.
1907 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_INT_ENABLE
);
1908 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_SIGNAL_ENABLE
);
1911 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1912 * of loops reaches 40 times or a timeout of 150ms occurs.
1915 struct mmc_command cmd
= {0};
1916 struct mmc_request mrq
= {NULL
};
1918 cmd
.opcode
= opcode
;
1920 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
1925 if (tuning_loop_counter
-- == 0)
1932 * In response to CMD19, the card sends 64 bytes of tuning
1933 * block to the Host Controller. So we set the block size
1936 if (cmd
.opcode
== MMC_SEND_TUNING_BLOCK_HS200
) {
1937 if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
1938 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 128),
1940 else if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
1941 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1944 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1949 * The tuning block is sent by the card to the host controller.
1950 * So we set the TRNS_READ bit in the Transfer Mode register.
1951 * This also takes care of setting DMA Enable and Multi Block
1952 * Select in the same register to 0.
1954 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
1956 sdhci_send_command(host
, &cmd
);
1961 spin_unlock_irqrestore(&host
->lock
, flags
);
1962 /* Wait for Buffer Read Ready interrupt */
1963 wait_event_interruptible_timeout(host
->buf_ready_int
,
1964 (host
->tuning_done
== 1),
1965 msecs_to_jiffies(50));
1966 spin_lock_irqsave(&host
->lock
, flags
);
1968 if (!host
->tuning_done
) {
1969 pr_info(DRIVER_NAME
": Timeout waiting for "
1970 "Buffer Read Ready interrupt during tuning "
1971 "procedure, falling back to fixed sampling "
1973 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1974 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1975 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
1976 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1982 host
->tuning_done
= 0;
1984 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1986 /* eMMC spec does not require a delay between tuning cycles */
1987 if (opcode
== MMC_SEND_TUNING_BLOCK
)
1989 } while (ctrl
& SDHCI_CTRL_EXEC_TUNING
);
1992 * The Host Driver has exhausted the maximum number of loops allowed,
1993 * so use fixed sampling frequency.
1995 if (tuning_loop_counter
< 0) {
1996 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
1997 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1999 if (!(ctrl
& SDHCI_CTRL_TUNED_CLK
)) {
2000 pr_info(DRIVER_NAME
": Tuning procedure"
2001 " failed, falling back to fixed sampling"
2008 * If this is the very first time we are here, we start the retuning
2009 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2010 * flag won't be set, we check this condition before actually starting
2013 if (!(host
->flags
& SDHCI_NEEDS_RETUNING
) && host
->tuning_count
&&
2014 (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)) {
2015 host
->flags
|= SDHCI_USING_RETUNING_TIMER
;
2016 mod_timer(&host
->tuning_timer
, jiffies
+
2017 host
->tuning_count
* HZ
);
2018 /* Tuning mode 1 limits the maximum data length to 4MB */
2019 mmc
->max_blk_count
= (4 * 1024 * 1024) / mmc
->max_blk_size
;
2020 } else if (host
->flags
& SDHCI_USING_RETUNING_TIMER
) {
2021 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2022 /* Reload the new initial value for timer */
2023 mod_timer(&host
->tuning_timer
, jiffies
+
2024 host
->tuning_count
* HZ
);
2028 * In case tuning fails, host controllers which support re-tuning can
2029 * try tuning again at a later time, when the re-tuning timer expires.
2030 * So for these controllers, we return 0. Since there might be other
2031 * controllers who do not have this capability, we return error for
2032 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2033 * a retuning timer to do the retuning for the card.
2035 if (err
&& (host
->flags
& SDHCI_USING_RETUNING_TIMER
))
2038 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2039 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2040 spin_unlock_irqrestore(&host
->lock
, flags
);
2041 sdhci_runtime_pm_put(host
);
2047 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
)
2049 /* Host Controller v3.00 defines preset value registers */
2050 if (host
->version
< SDHCI_SPEC_300
)
2054 * We only enable or disable Preset Value if they are not already
2055 * enabled or disabled respectively. Otherwise, we bail out.
2057 if (host
->preset_enabled
!= enable
) {
2058 u16 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2061 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
2063 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
2065 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2068 host
->flags
|= SDHCI_PV_ENABLED
;
2070 host
->flags
&= ~SDHCI_PV_ENABLED
;
2072 host
->preset_enabled
= enable
;
2076 static void sdhci_card_event(struct mmc_host
*mmc
)
2078 struct sdhci_host
*host
= mmc_priv(mmc
);
2079 unsigned long flags
;
2081 /* First check if client has provided their own card event */
2082 if (host
->ops
->card_event
)
2083 host
->ops
->card_event(host
);
2085 spin_lock_irqsave(&host
->lock
, flags
);
2087 /* Check host->mrq first in case we are runtime suspended */
2088 if (host
->mrq
&& !sdhci_do_get_cd(host
)) {
2089 pr_err("%s: Card removed during transfer!\n",
2090 mmc_hostname(host
->mmc
));
2091 pr_err("%s: Resetting controller.\n",
2092 mmc_hostname(host
->mmc
));
2094 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2095 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2097 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
2098 tasklet_schedule(&host
->finish_tasklet
);
2101 spin_unlock_irqrestore(&host
->lock
, flags
);
2104 static const struct mmc_host_ops sdhci_ops
= {
2105 .request
= sdhci_request
,
2106 .set_ios
= sdhci_set_ios
,
2107 .get_cd
= sdhci_get_cd
,
2108 .get_ro
= sdhci_get_ro
,
2109 .hw_reset
= sdhci_hw_reset
,
2110 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
2111 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
2112 .execute_tuning
= sdhci_execute_tuning
,
2113 .card_event
= sdhci_card_event
,
2114 .card_busy
= sdhci_card_busy
,
2117 /*****************************************************************************\
2121 \*****************************************************************************/
2123 static void sdhci_tasklet_finish(unsigned long param
)
2125 struct sdhci_host
*host
;
2126 unsigned long flags
;
2127 struct mmc_request
*mrq
;
2129 host
= (struct sdhci_host
*)param
;
2131 spin_lock_irqsave(&host
->lock
, flags
);
2134 * If this tasklet gets rescheduled while running, it will
2135 * be run again afterwards but without any active request.
2138 spin_unlock_irqrestore(&host
->lock
, flags
);
2142 del_timer(&host
->timer
);
2147 * The controller needs a reset of internal state machines
2148 * upon error conditions.
2150 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
2151 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
2152 (mrq
->sbc
&& mrq
->sbc
->error
) ||
2153 (mrq
->data
&& ((mrq
->data
->error
&& !mrq
->data
->stop
) ||
2154 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
2155 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
2157 /* Some controllers need this kick or reset won't work here */
2158 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
)
2159 /* This is to force an update */
2160 host
->ops
->set_clock(host
, host
->clock
);
2162 /* Spec says we should do both at the same time, but Ricoh
2163 controllers do not like that. */
2164 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2165 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2172 #ifndef SDHCI_USE_LEDS_CLASS
2173 sdhci_deactivate_led(host
);
2177 spin_unlock_irqrestore(&host
->lock
, flags
);
2179 mmc_request_done(host
->mmc
, mrq
);
2180 sdhci_runtime_pm_put(host
);
2183 static void sdhci_timeout_timer(unsigned long data
)
2185 struct sdhci_host
*host
;
2186 unsigned long flags
;
2188 host
= (struct sdhci_host
*)data
;
2190 spin_lock_irqsave(&host
->lock
, flags
);
2193 pr_err("%s: Timeout waiting for hardware "
2194 "interrupt.\n", mmc_hostname(host
->mmc
));
2195 sdhci_dumpregs(host
);
2198 host
->data
->error
= -ETIMEDOUT
;
2199 sdhci_finish_data(host
);
2202 host
->cmd
->error
= -ETIMEDOUT
;
2204 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
2206 tasklet_schedule(&host
->finish_tasklet
);
2211 spin_unlock_irqrestore(&host
->lock
, flags
);
2214 static void sdhci_tuning_timer(unsigned long data
)
2216 struct sdhci_host
*host
;
2217 unsigned long flags
;
2219 host
= (struct sdhci_host
*)data
;
2221 spin_lock_irqsave(&host
->lock
, flags
);
2223 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2225 spin_unlock_irqrestore(&host
->lock
, flags
);
2228 /*****************************************************************************\
2230 * Interrupt handling *
2232 \*****************************************************************************/
2234 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
, u32
*mask
)
2236 BUG_ON(intmask
== 0);
2239 pr_err("%s: Got command interrupt 0x%08x even "
2240 "though no command operation was in progress.\n",
2241 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2242 sdhci_dumpregs(host
);
2246 if (intmask
& SDHCI_INT_TIMEOUT
)
2247 host
->cmd
->error
= -ETIMEDOUT
;
2248 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
2250 host
->cmd
->error
= -EILSEQ
;
2252 if (host
->cmd
->error
) {
2253 tasklet_schedule(&host
->finish_tasklet
);
2258 * The host can send and interrupt when the busy state has
2259 * ended, allowing us to wait without wasting CPU cycles.
2260 * Unfortunately this is overloaded on the "data complete"
2261 * interrupt, so we need to take some care when handling
2264 * Note: The 1.0 specification is a bit ambiguous about this
2265 * feature so there might be some problems with older
2268 if (host
->cmd
->flags
& MMC_RSP_BUSY
) {
2269 if (host
->cmd
->data
)
2270 DBG("Cannot wait for busy signal when also "
2271 "doing a data transfer");
2272 else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
)
2273 && !host
->busy_handle
) {
2274 /* Mark that command complete before busy is ended */
2275 host
->busy_handle
= 1;
2279 /* The controller does not support the end-of-busy IRQ,
2280 * fall through and take the SDHCI_INT_RESPONSE */
2281 } else if ((host
->quirks2
& SDHCI_QUIRK2_STOP_WITH_TC
) &&
2282 host
->cmd
->opcode
== MMC_STOP_TRANSMISSION
&& !host
->data
) {
2283 *mask
&= ~SDHCI_INT_DATA_END
;
2286 if (intmask
& SDHCI_INT_RESPONSE
)
2287 sdhci_finish_command(host
);
2290 #ifdef CONFIG_MMC_DEBUG
2291 static void sdhci_adma_show_error(struct sdhci_host
*host
)
2293 const char *name
= mmc_hostname(host
->mmc
);
2294 void *desc
= host
->adma_table
;
2296 sdhci_dumpregs(host
);
2299 struct sdhci_adma2_32_desc
*dma_desc
= desc
;
2301 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2302 name
, desc
, le32_to_cpu(dma_desc
->addr
),
2303 le16_to_cpu(dma_desc
->len
),
2304 le16_to_cpu(dma_desc
->cmd
));
2306 desc
+= host
->desc_sz
;
2308 if (dma_desc
->cmd
& cpu_to_le16(ADMA2_END
))
2313 static void sdhci_adma_show_error(struct sdhci_host
*host
) { }
2316 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2319 BUG_ON(intmask
== 0);
2321 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2322 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2323 command
= SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
));
2324 if (command
== MMC_SEND_TUNING_BLOCK
||
2325 command
== MMC_SEND_TUNING_BLOCK_HS200
) {
2326 host
->tuning_done
= 1;
2327 wake_up(&host
->buf_ready_int
);
2334 * The "data complete" interrupt is also used to
2335 * indicate that a busy state has ended. See comment
2336 * above in sdhci_cmd_irq().
2338 if (host
->cmd
&& (host
->cmd
->flags
& MMC_RSP_BUSY
)) {
2339 if (intmask
& SDHCI_INT_DATA_TIMEOUT
) {
2340 host
->cmd
->error
= -ETIMEDOUT
;
2341 tasklet_schedule(&host
->finish_tasklet
);
2344 if (intmask
& SDHCI_INT_DATA_END
) {
2346 * Some cards handle busy-end interrupt
2347 * before the command completed, so make
2348 * sure we do things in the proper order.
2350 if (host
->busy_handle
)
2351 sdhci_finish_command(host
);
2353 host
->busy_handle
= 1;
2358 pr_err("%s: Got data interrupt 0x%08x even "
2359 "though no data operation was in progress.\n",
2360 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2361 sdhci_dumpregs(host
);
2366 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2367 host
->data
->error
= -ETIMEDOUT
;
2368 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2369 host
->data
->error
= -EILSEQ
;
2370 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2371 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2373 host
->data
->error
= -EILSEQ
;
2374 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2375 pr_err("%s: ADMA error\n", mmc_hostname(host
->mmc
));
2376 sdhci_adma_show_error(host
);
2377 host
->data
->error
= -EIO
;
2378 if (host
->ops
->adma_workaround
)
2379 host
->ops
->adma_workaround(host
, intmask
);
2382 if (host
->data
->error
)
2383 sdhci_finish_data(host
);
2385 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2386 sdhci_transfer_pio(host
);
2389 * We currently don't do anything fancy with DMA
2390 * boundaries, but as we can't disable the feature
2391 * we need to at least restart the transfer.
2393 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2394 * should return a valid address to continue from, but as
2395 * some controllers are faulty, don't trust them.
2397 if (intmask
& SDHCI_INT_DMA_END
) {
2398 u32 dmastart
, dmanow
;
2399 dmastart
= sg_dma_address(host
->data
->sg
);
2400 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2402 * Force update to the next DMA block boundary.
2405 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2406 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2407 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2408 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2410 mmc_hostname(host
->mmc
), dmastart
,
2411 host
->data
->bytes_xfered
, dmanow
);
2412 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2415 if (intmask
& SDHCI_INT_DATA_END
) {
2418 * Data managed to finish before the
2419 * command completed. Make sure we do
2420 * things in the proper order.
2422 host
->data_early
= 1;
2424 sdhci_finish_data(host
);
2430 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2432 irqreturn_t result
= IRQ_NONE
;
2433 struct sdhci_host
*host
= dev_id
;
2434 u32 intmask
, mask
, unexpected
= 0;
2437 spin_lock(&host
->lock
);
2439 if (host
->runtime_suspended
&& !sdhci_sdio_irq_enabled(host
)) {
2440 spin_unlock(&host
->lock
);
2444 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2445 if (!intmask
|| intmask
== 0xffffffff) {
2451 /* Clear selected interrupts. */
2452 mask
= intmask
& (SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2453 SDHCI_INT_BUS_POWER
);
2454 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
2456 DBG("*** %s got interrupt: 0x%08x\n",
2457 mmc_hostname(host
->mmc
), intmask
);
2459 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2460 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2464 * There is a observation on i.mx esdhc. INSERT
2465 * bit will be immediately set again when it gets
2466 * cleared, if a card is inserted. We have to mask
2467 * the irq to prevent interrupt storm which will
2468 * freeze the system. And the REMOVE gets the
2471 * More testing are needed here to ensure it works
2472 * for other platforms though.
2474 host
->ier
&= ~(SDHCI_INT_CARD_INSERT
|
2475 SDHCI_INT_CARD_REMOVE
);
2476 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
2477 SDHCI_INT_CARD_INSERT
;
2478 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2479 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2481 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2482 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2484 host
->thread_isr
|= intmask
& (SDHCI_INT_CARD_INSERT
|
2485 SDHCI_INT_CARD_REMOVE
);
2486 result
= IRQ_WAKE_THREAD
;
2489 if (intmask
& SDHCI_INT_CMD_MASK
)
2490 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
,
2493 if (intmask
& SDHCI_INT_DATA_MASK
)
2494 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2496 if (intmask
& SDHCI_INT_BUS_POWER
)
2497 pr_err("%s: Card is consuming too much power!\n",
2498 mmc_hostname(host
->mmc
));
2500 if (intmask
& SDHCI_INT_CARD_INT
) {
2501 sdhci_enable_sdio_irq_nolock(host
, false);
2502 host
->thread_isr
|= SDHCI_INT_CARD_INT
;
2503 result
= IRQ_WAKE_THREAD
;
2506 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
|
2507 SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2508 SDHCI_INT_ERROR
| SDHCI_INT_BUS_POWER
|
2509 SDHCI_INT_CARD_INT
);
2512 unexpected
|= intmask
;
2513 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2516 if (result
== IRQ_NONE
)
2517 result
= IRQ_HANDLED
;
2519 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2520 } while (intmask
&& --max_loops
);
2522 spin_unlock(&host
->lock
);
2525 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2526 mmc_hostname(host
->mmc
), unexpected
);
2527 sdhci_dumpregs(host
);
2533 static irqreturn_t
sdhci_thread_irq(int irq
, void *dev_id
)
2535 struct sdhci_host
*host
= dev_id
;
2536 unsigned long flags
;
2539 spin_lock_irqsave(&host
->lock
, flags
);
2540 isr
= host
->thread_isr
;
2541 host
->thread_isr
= 0;
2542 spin_unlock_irqrestore(&host
->lock
, flags
);
2544 if (isr
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2545 sdhci_card_event(host
->mmc
);
2546 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
2549 if (isr
& SDHCI_INT_CARD_INT
) {
2550 sdio_run_irqs(host
->mmc
);
2552 spin_lock_irqsave(&host
->lock
, flags
);
2553 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2554 sdhci_enable_sdio_irq_nolock(host
, true);
2555 spin_unlock_irqrestore(&host
->lock
, flags
);
2558 return isr
? IRQ_HANDLED
: IRQ_NONE
;
2561 /*****************************************************************************\
2565 \*****************************************************************************/
2568 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2571 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2572 | SDHCI_WAKE_ON_INT
;
2574 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2576 /* Avoid fake wake up */
2577 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
2578 val
&= ~(SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
);
2579 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2581 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2583 static void sdhci_disable_irq_wakeups(struct sdhci_host
*host
)
2586 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2587 | SDHCI_WAKE_ON_INT
;
2589 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2591 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2594 int sdhci_suspend_host(struct sdhci_host
*host
)
2596 sdhci_disable_card_detection(host
);
2598 /* Disable tuning since we are suspending */
2599 if (host
->flags
& SDHCI_USING_RETUNING_TIMER
) {
2600 del_timer_sync(&host
->tuning_timer
);
2601 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2604 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2606 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
2607 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
2608 free_irq(host
->irq
, host
);
2610 sdhci_enable_irq_wakeups(host
);
2611 enable_irq_wake(host
->irq
);
2616 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2618 int sdhci_resume_host(struct sdhci_host
*host
)
2622 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2623 if (host
->ops
->enable_dma
)
2624 host
->ops
->enable_dma(host
);
2627 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2628 ret
= request_threaded_irq(host
->irq
, sdhci_irq
,
2629 sdhci_thread_irq
, IRQF_SHARED
,
2630 mmc_hostname(host
->mmc
), host
);
2634 sdhci_disable_irq_wakeups(host
);
2635 disable_irq_wake(host
->irq
);
2638 if ((host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
) &&
2639 (host
->quirks2
& SDHCI_QUIRK2_HOST_OFF_CARD_ON
)) {
2640 /* Card keeps power but host controller does not */
2641 sdhci_init(host
, 0);
2644 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2646 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2650 sdhci_enable_card_detection(host
);
2652 /* Set the re-tuning expiration flag */
2653 if (host
->flags
& SDHCI_USING_RETUNING_TIMER
)
2654 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2659 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2660 #endif /* CONFIG_PM */
2662 #ifdef CONFIG_PM_RUNTIME
2664 static int sdhci_runtime_pm_get(struct sdhci_host
*host
)
2666 return pm_runtime_get_sync(host
->mmc
->parent
);
2669 static int sdhci_runtime_pm_put(struct sdhci_host
*host
)
2671 pm_runtime_mark_last_busy(host
->mmc
->parent
);
2672 return pm_runtime_put_autosuspend(host
->mmc
->parent
);
2675 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
2677 if (host
->runtime_suspended
|| host
->bus_on
)
2679 host
->bus_on
= true;
2680 pm_runtime_get_noresume(host
->mmc
->parent
);
2683 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
2685 if (host
->runtime_suspended
|| !host
->bus_on
)
2687 host
->bus_on
= false;
2688 pm_runtime_put_noidle(host
->mmc
->parent
);
2691 int sdhci_runtime_suspend_host(struct sdhci_host
*host
)
2693 unsigned long flags
;
2695 /* Disable tuning since we are suspending */
2696 if (host
->flags
& SDHCI_USING_RETUNING_TIMER
) {
2697 del_timer_sync(&host
->tuning_timer
);
2698 host
->flags
&= ~SDHCI_NEEDS_RETUNING
;
2701 spin_lock_irqsave(&host
->lock
, flags
);
2702 host
->ier
&= SDHCI_INT_CARD_INT
;
2703 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2704 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2705 spin_unlock_irqrestore(&host
->lock
, flags
);
2707 synchronize_hardirq(host
->irq
);
2709 spin_lock_irqsave(&host
->lock
, flags
);
2710 host
->runtime_suspended
= true;
2711 spin_unlock_irqrestore(&host
->lock
, flags
);
2715 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host
);
2717 int sdhci_runtime_resume_host(struct sdhci_host
*host
)
2719 unsigned long flags
;
2720 int host_flags
= host
->flags
;
2722 if (host_flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2723 if (host
->ops
->enable_dma
)
2724 host
->ops
->enable_dma(host
);
2727 sdhci_init(host
, 0);
2729 /* Force clock and power re-program */
2732 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2734 sdhci_do_start_signal_voltage_switch(host
, &host
->mmc
->ios
);
2735 if ((host_flags
& SDHCI_PV_ENABLED
) &&
2736 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
)) {
2737 spin_lock_irqsave(&host
->lock
, flags
);
2738 sdhci_enable_preset_value(host
, true);
2739 spin_unlock_irqrestore(&host
->lock
, flags
);
2742 /* Set the re-tuning expiration flag */
2743 if (host
->flags
& SDHCI_USING_RETUNING_TIMER
)
2744 host
->flags
|= SDHCI_NEEDS_RETUNING
;
2746 spin_lock_irqsave(&host
->lock
, flags
);
2748 host
->runtime_suspended
= false;
2750 /* Enable SDIO IRQ */
2751 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2752 sdhci_enable_sdio_irq_nolock(host
, true);
2754 /* Enable Card Detection */
2755 sdhci_enable_card_detection(host
);
2757 spin_unlock_irqrestore(&host
->lock
, flags
);
2761 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host
);
2765 /*****************************************************************************\
2767 * Device allocation/registration *
2769 \*****************************************************************************/
2771 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
2774 struct mmc_host
*mmc
;
2775 struct sdhci_host
*host
;
2777 WARN_ON(dev
== NULL
);
2779 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
2781 return ERR_PTR(-ENOMEM
);
2783 host
= mmc_priv(mmc
);
2789 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
2791 int sdhci_add_host(struct sdhci_host
*host
)
2793 struct mmc_host
*mmc
;
2794 u32 caps
[2] = {0, 0};
2795 u32 max_current_caps
;
2796 unsigned int ocr_avail
;
2797 unsigned int override_timeout_clk
;
2800 WARN_ON(host
== NULL
);
2807 host
->quirks
= debug_quirks
;
2809 host
->quirks2
= debug_quirks2
;
2811 override_timeout_clk
= host
->timeout_clk
;
2813 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
2815 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
2816 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
2817 >> SDHCI_SPEC_VER_SHIFT
;
2818 if (host
->version
> SDHCI_SPEC_300
) {
2819 pr_err("%s: Unknown controller version (%d). "
2820 "You may experience problems.\n", mmc_hostname(mmc
),
2824 caps
[0] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ? host
->caps
:
2825 sdhci_readl(host
, SDHCI_CAPABILITIES
);
2827 if (host
->version
>= SDHCI_SPEC_300
)
2828 caps
[1] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ?
2830 sdhci_readl(host
, SDHCI_CAPABILITIES_1
);
2832 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
2833 host
->flags
|= SDHCI_USE_SDMA
;
2834 else if (!(caps
[0] & SDHCI_CAN_DO_SDMA
))
2835 DBG("Controller doesn't have SDMA capability\n");
2837 host
->flags
|= SDHCI_USE_SDMA
;
2839 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
2840 (host
->flags
& SDHCI_USE_SDMA
)) {
2841 DBG("Disabling DMA as it is marked broken\n");
2842 host
->flags
&= ~SDHCI_USE_SDMA
;
2845 if ((host
->version
>= SDHCI_SPEC_200
) &&
2846 (caps
[0] & SDHCI_CAN_DO_ADMA2
))
2847 host
->flags
|= SDHCI_USE_ADMA
;
2849 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
2850 (host
->flags
& SDHCI_USE_ADMA
)) {
2851 DBG("Disabling ADMA as it is marked broken\n");
2852 host
->flags
&= ~SDHCI_USE_ADMA
;
2855 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2856 if (host
->ops
->enable_dma
) {
2857 if (host
->ops
->enable_dma(host
)) {
2858 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2861 ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
2866 if (host
->flags
& SDHCI_USE_ADMA
) {
2868 * The DMA descriptor table size is calculated as the maximum
2869 * number of segments times 2, to allow for an alignment
2870 * descriptor for each segment, plus 1 for a nop end descriptor,
2871 * all multipled by the descriptor size.
2873 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
2874 SDHCI_ADMA2_32_DESC_SZ
;
2875 host
->align_buffer_sz
= SDHCI_MAX_SEGS
*
2876 SDHCI_ADMA2_32_ALIGN
;
2877 host
->desc_sz
= SDHCI_ADMA2_32_DESC_SZ
;
2878 host
->align_sz
= SDHCI_ADMA2_32_ALIGN
;
2879 host
->align_mask
= SDHCI_ADMA2_32_ALIGN
- 1;
2880 host
->adma_table
= dma_alloc_coherent(mmc_dev(mmc
),
2881 host
->adma_table_sz
,
2884 host
->align_buffer
= kmalloc(host
->align_buffer_sz
, GFP_KERNEL
);
2885 if (!host
->adma_table
|| !host
->align_buffer
) {
2886 dma_free_coherent(mmc_dev(mmc
), host
->adma_table_sz
,
2887 host
->adma_table
, host
->adma_addr
);
2888 kfree(host
->align_buffer
);
2889 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2891 host
->flags
&= ~SDHCI_USE_ADMA
;
2892 host
->adma_table
= NULL
;
2893 host
->align_buffer
= NULL
;
2894 } else if (host
->adma_addr
& host
->align_mask
) {
2895 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2897 host
->flags
&= ~SDHCI_USE_ADMA
;
2898 dma_free_coherent(mmc_dev(mmc
), host
->adma_table_sz
,
2899 host
->adma_table
, host
->adma_addr
);
2900 kfree(host
->align_buffer
);
2901 host
->adma_table
= NULL
;
2902 host
->align_buffer
= NULL
;
2907 * If we use DMA, then it's up to the caller to set the DMA
2908 * mask, but PIO does not need the hw shim so we set a new
2909 * mask here in that case.
2911 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
2912 host
->dma_mask
= DMA_BIT_MASK(64);
2913 mmc_dev(mmc
)->dma_mask
= &host
->dma_mask
;
2916 if (host
->version
>= SDHCI_SPEC_300
)
2917 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_V3_BASE_MASK
)
2918 >> SDHCI_CLOCK_BASE_SHIFT
;
2920 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_BASE_MASK
)
2921 >> SDHCI_CLOCK_BASE_SHIFT
;
2923 host
->max_clk
*= 1000000;
2924 if (host
->max_clk
== 0 || host
->quirks
&
2925 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
2926 if (!host
->ops
->get_max_clock
) {
2927 pr_err("%s: Hardware doesn't specify base clock "
2928 "frequency.\n", mmc_hostname(mmc
));
2931 host
->max_clk
= host
->ops
->get_max_clock(host
);
2935 * In case of Host Controller v3.00, find out whether clock
2936 * multiplier is supported.
2938 host
->clk_mul
= (caps
[1] & SDHCI_CLOCK_MUL_MASK
) >>
2939 SDHCI_CLOCK_MUL_SHIFT
;
2942 * In case the value in Clock Multiplier is 0, then programmable
2943 * clock mode is not supported, otherwise the actual clock
2944 * multiplier is one more than the value of Clock Multiplier
2945 * in the Capabilities Register.
2951 * Set host parameters.
2953 mmc
->ops
= &sdhci_ops
;
2954 mmc
->f_max
= host
->max_clk
;
2955 if (host
->ops
->get_min_clock
)
2956 mmc
->f_min
= host
->ops
->get_min_clock(host
);
2957 else if (host
->version
>= SDHCI_SPEC_300
) {
2958 if (host
->clk_mul
) {
2959 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
2960 mmc
->f_max
= host
->max_clk
* host
->clk_mul
;
2962 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
2964 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
2966 if (!(host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
2967 host
->timeout_clk
= (caps
[0] & SDHCI_TIMEOUT_CLK_MASK
) >>
2968 SDHCI_TIMEOUT_CLK_SHIFT
;
2969 if (host
->timeout_clk
== 0) {
2970 if (host
->ops
->get_timeout_clock
) {
2972 host
->ops
->get_timeout_clock(host
);
2974 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2980 if (caps
[0] & SDHCI_TIMEOUT_CLK_UNIT
)
2981 host
->timeout_clk
*= 1000;
2983 mmc
->max_busy_timeout
= host
->ops
->get_max_timeout_count
?
2984 host
->ops
->get_max_timeout_count(host
) : 1 << 27;
2985 mmc
->max_busy_timeout
/= host
->timeout_clk
;
2988 if (override_timeout_clk
)
2989 host
->timeout_clk
= override_timeout_clk
;
2991 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
2992 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
2994 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
2995 host
->flags
|= SDHCI_AUTO_CMD12
;
2997 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2998 if ((host
->version
>= SDHCI_SPEC_300
) &&
2999 ((host
->flags
& SDHCI_USE_ADMA
) ||
3000 !(host
->flags
& SDHCI_USE_SDMA
))) {
3001 host
->flags
|= SDHCI_AUTO_CMD23
;
3002 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc
));
3004 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc
));
3008 * A controller may support 8-bit width, but the board itself
3009 * might not have the pins brought out. Boards that support
3010 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3011 * their platform code before calling sdhci_add_host(), and we
3012 * won't assume 8-bit width for hosts without that CAP.
3014 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
3015 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
3017 if (host
->quirks2
& SDHCI_QUIRK2_HOST_NO_CMD23
)
3018 mmc
->caps
&= ~MMC_CAP_CMD23
;
3020 if (caps
[0] & SDHCI_CAN_DO_HISPD
)
3021 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
3023 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
3024 !(mmc
->caps
& MMC_CAP_NONREMOVABLE
))
3025 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
3027 /* If there are external regulators, get them */
3028 if (mmc_regulator_get_supply(mmc
) == -EPROBE_DEFER
)
3029 return -EPROBE_DEFER
;
3031 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3032 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
3033 ret
= regulator_enable(mmc
->supply
.vqmmc
);
3034 if (!regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1700000,
3036 caps
[1] &= ~(SDHCI_SUPPORT_SDR104
|
3037 SDHCI_SUPPORT_SDR50
|
3038 SDHCI_SUPPORT_DDR50
);
3040 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3041 mmc_hostname(mmc
), ret
);
3042 mmc
->supply
.vqmmc
= NULL
;
3046 if (host
->quirks2
& SDHCI_QUIRK2_NO_1_8_V
)
3047 caps
[1] &= ~(SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3048 SDHCI_SUPPORT_DDR50
);
3050 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3051 if (caps
[1] & (SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3052 SDHCI_SUPPORT_DDR50
))
3053 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
3055 /* SDR104 supports also implies SDR50 support */
3056 if (caps
[1] & SDHCI_SUPPORT_SDR104
) {
3057 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
3058 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3059 * field can be promoted to support HS200.
3061 if (!(host
->quirks2
& SDHCI_QUIRK2_BROKEN_HS200
)) {
3062 mmc
->caps2
|= MMC_CAP2_HS200
;
3063 if (IS_ERR(mmc
->supply
.vqmmc
) ||
3064 !regulator_is_supported_voltage
3065 (mmc
->supply
.vqmmc
, 1100000, 1300000))
3066 mmc
->caps2
&= ~MMC_CAP2_HS200_1_2V_SDR
;
3068 } else if (caps
[1] & SDHCI_SUPPORT_SDR50
)
3069 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
3071 if ((caps
[1] & SDHCI_SUPPORT_DDR50
) &&
3072 !(host
->quirks2
& SDHCI_QUIRK2_BROKEN_DDR50
))
3073 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
3075 /* Does the host need tuning for SDR50? */
3076 if (caps
[1] & SDHCI_USE_SDR50_TUNING
)
3077 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
3079 /* Does the host need tuning for SDR104 / HS200? */
3080 if (mmc
->caps2
& MMC_CAP2_HS200
)
3081 host
->flags
|= SDHCI_SDR104_NEEDS_TUNING
;
3083 /* Driver Type(s) (A, C, D) supported by the host */
3084 if (caps
[1] & SDHCI_DRIVER_TYPE_A
)
3085 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
3086 if (caps
[1] & SDHCI_DRIVER_TYPE_C
)
3087 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
3088 if (caps
[1] & SDHCI_DRIVER_TYPE_D
)
3089 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
3091 /* Initial value for re-tuning timer count */
3092 host
->tuning_count
= (caps
[1] & SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
3093 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
3096 * In case Re-tuning Timer is not disabled, the actual value of
3097 * re-tuning timer will be 2 ^ (n - 1).
3099 if (host
->tuning_count
)
3100 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
3102 /* Re-tuning mode supported by the Host Controller */
3103 host
->tuning_mode
= (caps
[1] & SDHCI_RETUNING_MODE_MASK
) >>
3104 SDHCI_RETUNING_MODE_SHIFT
;
3109 * According to SD Host Controller spec v3.00, if the Host System
3110 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3111 * the value is meaningful only if Voltage Support in the Capabilities
3112 * register is set. The actual current value is 4 times the register
3115 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
3116 if (!max_current_caps
&& !IS_ERR(mmc
->supply
.vmmc
)) {
3117 int curr
= regulator_get_current_limit(mmc
->supply
.vmmc
);
3120 /* convert to SDHCI_MAX_CURRENT format */
3121 curr
= curr
/1000; /* convert to mA */
3122 curr
= curr
/SDHCI_MAX_CURRENT_MULTIPLIER
;
3124 curr
= min_t(u32
, curr
, SDHCI_MAX_CURRENT_LIMIT
);
3126 (curr
<< SDHCI_MAX_CURRENT_330_SHIFT
) |
3127 (curr
<< SDHCI_MAX_CURRENT_300_SHIFT
) |
3128 (curr
<< SDHCI_MAX_CURRENT_180_SHIFT
);
3132 if (caps
[0] & SDHCI_CAN_VDD_330
) {
3133 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
3135 mmc
->max_current_330
= ((max_current_caps
&
3136 SDHCI_MAX_CURRENT_330_MASK
) >>
3137 SDHCI_MAX_CURRENT_330_SHIFT
) *
3138 SDHCI_MAX_CURRENT_MULTIPLIER
;
3140 if (caps
[0] & SDHCI_CAN_VDD_300
) {
3141 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
3143 mmc
->max_current_300
= ((max_current_caps
&
3144 SDHCI_MAX_CURRENT_300_MASK
) >>
3145 SDHCI_MAX_CURRENT_300_SHIFT
) *
3146 SDHCI_MAX_CURRENT_MULTIPLIER
;
3148 if (caps
[0] & SDHCI_CAN_VDD_180
) {
3149 ocr_avail
|= MMC_VDD_165_195
;
3151 mmc
->max_current_180
= ((max_current_caps
&
3152 SDHCI_MAX_CURRENT_180_MASK
) >>
3153 SDHCI_MAX_CURRENT_180_SHIFT
) *
3154 SDHCI_MAX_CURRENT_MULTIPLIER
;
3157 /* If OCR set by external regulators, use it instead */
3159 ocr_avail
= mmc
->ocr_avail
;
3162 ocr_avail
&= host
->ocr_mask
;
3164 mmc
->ocr_avail
= ocr_avail
;
3165 mmc
->ocr_avail_sdio
= ocr_avail
;
3166 if (host
->ocr_avail_sdio
)
3167 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
3168 mmc
->ocr_avail_sd
= ocr_avail
;
3169 if (host
->ocr_avail_sd
)
3170 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
3171 else /* normal SD controllers don't support 1.8V */
3172 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
3173 mmc
->ocr_avail_mmc
= ocr_avail
;
3174 if (host
->ocr_avail_mmc
)
3175 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
3177 if (mmc
->ocr_avail
== 0) {
3178 pr_err("%s: Hardware doesn't report any "
3179 "support voltages.\n", mmc_hostname(mmc
));
3183 spin_lock_init(&host
->lock
);
3186 * Maximum number of segments. Depends on if the hardware
3187 * can do scatter/gather or not.
3189 if (host
->flags
& SDHCI_USE_ADMA
)
3190 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3191 else if (host
->flags
& SDHCI_USE_SDMA
)
3194 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3197 * Maximum number of sectors in one transfer. Limited by DMA boundary
3200 mmc
->max_req_size
= 524288;
3203 * Maximum segment size. Could be one segment with the maximum number
3204 * of bytes. When doing hardware scatter/gather, each entry cannot
3205 * be larger than 64 KiB though.
3207 if (host
->flags
& SDHCI_USE_ADMA
) {
3208 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
3209 mmc
->max_seg_size
= 65535;
3211 mmc
->max_seg_size
= 65536;
3213 mmc
->max_seg_size
= mmc
->max_req_size
;
3217 * Maximum block size. This varies from controller to controller and
3218 * is specified in the capabilities register.
3220 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
3221 mmc
->max_blk_size
= 2;
3223 mmc
->max_blk_size
= (caps
[0] & SDHCI_MAX_BLOCK_MASK
) >>
3224 SDHCI_MAX_BLOCK_SHIFT
;
3225 if (mmc
->max_blk_size
>= 3) {
3226 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3228 mmc
->max_blk_size
= 0;
3232 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
3235 * Maximum block count.
3237 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
3242 tasklet_init(&host
->finish_tasklet
,
3243 sdhci_tasklet_finish
, (unsigned long)host
);
3245 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
3247 if (host
->version
>= SDHCI_SPEC_300
) {
3248 init_waitqueue_head(&host
->buf_ready_int
);
3250 /* Initialize re-tuning timer */
3251 init_timer(&host
->tuning_timer
);
3252 host
->tuning_timer
.data
= (unsigned long)host
;
3253 host
->tuning_timer
.function
= sdhci_tuning_timer
;
3256 sdhci_init(host
, 0);
3258 ret
= request_threaded_irq(host
->irq
, sdhci_irq
, sdhci_thread_irq
,
3259 IRQF_SHARED
, mmc_hostname(mmc
), host
);
3261 pr_err("%s: Failed to request IRQ %d: %d\n",
3262 mmc_hostname(mmc
), host
->irq
, ret
);
3266 #ifdef CONFIG_MMC_DEBUG
3267 sdhci_dumpregs(host
);
3270 #ifdef SDHCI_USE_LEDS_CLASS
3271 snprintf(host
->led_name
, sizeof(host
->led_name
),
3272 "%s::", mmc_hostname(mmc
));
3273 host
->led
.name
= host
->led_name
;
3274 host
->led
.brightness
= LED_OFF
;
3275 host
->led
.default_trigger
= mmc_hostname(mmc
);
3276 host
->led
.brightness_set
= sdhci_led_control
;
3278 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
3280 pr_err("%s: Failed to register LED device: %d\n",
3281 mmc_hostname(mmc
), ret
);
3290 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3291 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
3292 (host
->flags
& SDHCI_USE_ADMA
) ? "ADMA" :
3293 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
3295 sdhci_enable_card_detection(host
);
3299 #ifdef SDHCI_USE_LEDS_CLASS
3301 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3302 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3303 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3304 free_irq(host
->irq
, host
);
3307 tasklet_kill(&host
->finish_tasklet
);
3312 EXPORT_SYMBOL_GPL(sdhci_add_host
);
3314 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
3316 struct mmc_host
*mmc
= host
->mmc
;
3317 unsigned long flags
;
3320 spin_lock_irqsave(&host
->lock
, flags
);
3322 host
->flags
|= SDHCI_DEVICE_DEAD
;
3325 pr_err("%s: Controller removed during "
3326 " transfer!\n", mmc_hostname(mmc
));
3328 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
3329 tasklet_schedule(&host
->finish_tasklet
);
3332 spin_unlock_irqrestore(&host
->lock
, flags
);
3335 sdhci_disable_card_detection(host
);
3337 mmc_remove_host(mmc
);
3339 #ifdef SDHCI_USE_LEDS_CLASS
3340 led_classdev_unregister(&host
->led
);
3344 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3346 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3347 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3348 free_irq(host
->irq
, host
);
3350 del_timer_sync(&host
->timer
);
3352 tasklet_kill(&host
->finish_tasklet
);
3354 if (!IS_ERR(mmc
->supply
.vqmmc
))
3355 regulator_disable(mmc
->supply
.vqmmc
);
3357 if (host
->adma_table
)
3358 dma_free_coherent(mmc_dev(mmc
), host
->adma_table_sz
,
3359 host
->adma_table
, host
->adma_addr
);
3360 kfree(host
->align_buffer
);
3362 host
->adma_table
= NULL
;
3363 host
->align_buffer
= NULL
;
3366 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
3368 void sdhci_free_host(struct sdhci_host
*host
)
3370 mmc_free_host(host
->mmc
);
3373 EXPORT_SYMBOL_GPL(sdhci_free_host
);
3375 /*****************************************************************************\
3377 * Driver init/exit *
3379 \*****************************************************************************/
3381 static int __init
sdhci_drv_init(void)
3384 ": Secure Digital Host Controller Interface driver\n");
3385 pr_info(DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
3390 static void __exit
sdhci_drv_exit(void)
3394 module_init(sdhci_drv_init
);
3395 module_exit(sdhci_drv_exit
);
3397 module_param(debug_quirks
, uint
, 0444);
3398 module_param(debug_quirks2
, uint
, 0444);
3400 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3401 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3402 MODULE_LICENSE("GPL");
3404 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");
3405 MODULE_PARM_DESC(debug_quirks2
, "Force certain other quirks.");