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printk: add and use LOGLEVEL_<level> defines for KERN_<LEVEL> equivalents
[deliverable/linux.git] / drivers / mmc / host / sh_mmcif.c
1 /*
2 * MMCIF eMMC driver.
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 *
12 * TODO
13 * 1. DMA
14 * 2. Power management
15 * 3. Handle MMC errors better
16 *
17 */
18
19 /*
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
22 *
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
30 *
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
34 *
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
43 */
44
45 #include <linux/bitops.h>
46 #include <linux/clk.h>
47 #include <linux/completion.h>
48 #include <linux/delay.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/dmaengine.h>
51 #include <linux/mmc/card.h>
52 #include <linux/mmc/core.h>
53 #include <linux/mmc/host.h>
54 #include <linux/mmc/mmc.h>
55 #include <linux/mmc/sdio.h>
56 #include <linux/mmc/sh_mmcif.h>
57 #include <linux/mmc/slot-gpio.h>
58 #include <linux/mod_devicetable.h>
59 #include <linux/mutex.h>
60 #include <linux/pagemap.h>
61 #include <linux/platform_device.h>
62 #include <linux/pm_qos.h>
63 #include <linux/pm_runtime.h>
64 #include <linux/sh_dma.h>
65 #include <linux/spinlock.h>
66 #include <linux/module.h>
67
68 #define DRIVER_NAME "sh_mmcif"
69 #define DRIVER_VERSION "2010-04-28"
70
71 /* CE_CMD_SET */
72 #define CMD_MASK 0x3f000000
73 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
74 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
75 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
76 #define CMD_SET_RBSY (1 << 21) /* R1b */
77 #define CMD_SET_CCSEN (1 << 20)
78 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
79 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
80 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
81 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
82 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
83 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
84 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
85 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
86 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
87 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
88 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
89 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
90 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
91 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
92 #define CMD_SET_CCSH (1 << 5)
93 #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
94 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
95 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
96 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
97
98 /* CE_CMD_CTRL */
99 #define CMD_CTRL_BREAK (1 << 0)
100
101 /* CE_BLOCK_SET */
102 #define BLOCK_SIZE_MASK 0x0000ffff
103
104 /* CE_INT */
105 #define INT_CCSDE (1 << 29)
106 #define INT_CMD12DRE (1 << 26)
107 #define INT_CMD12RBE (1 << 25)
108 #define INT_CMD12CRE (1 << 24)
109 #define INT_DTRANE (1 << 23)
110 #define INT_BUFRE (1 << 22)
111 #define INT_BUFWEN (1 << 21)
112 #define INT_BUFREN (1 << 20)
113 #define INT_CCSRCV (1 << 19)
114 #define INT_RBSYE (1 << 17)
115 #define INT_CRSPE (1 << 16)
116 #define INT_CMDVIO (1 << 15)
117 #define INT_BUFVIO (1 << 14)
118 #define INT_WDATERR (1 << 11)
119 #define INT_RDATERR (1 << 10)
120 #define INT_RIDXERR (1 << 9)
121 #define INT_RSPERR (1 << 8)
122 #define INT_CCSTO (1 << 5)
123 #define INT_CRCSTO (1 << 4)
124 #define INT_WDATTO (1 << 3)
125 #define INT_RDATTO (1 << 2)
126 #define INT_RBSYTO (1 << 1)
127 #define INT_RSPTO (1 << 0)
128 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
129 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
130 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
131 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
132
133 #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \
134 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
135 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
136
137 #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
138
139 /* CE_INT_MASK */
140 #define MASK_ALL 0x00000000
141 #define MASK_MCCSDE (1 << 29)
142 #define MASK_MCMD12DRE (1 << 26)
143 #define MASK_MCMD12RBE (1 << 25)
144 #define MASK_MCMD12CRE (1 << 24)
145 #define MASK_MDTRANE (1 << 23)
146 #define MASK_MBUFRE (1 << 22)
147 #define MASK_MBUFWEN (1 << 21)
148 #define MASK_MBUFREN (1 << 20)
149 #define MASK_MCCSRCV (1 << 19)
150 #define MASK_MRBSYE (1 << 17)
151 #define MASK_MCRSPE (1 << 16)
152 #define MASK_MCMDVIO (1 << 15)
153 #define MASK_MBUFVIO (1 << 14)
154 #define MASK_MWDATERR (1 << 11)
155 #define MASK_MRDATERR (1 << 10)
156 #define MASK_MRIDXERR (1 << 9)
157 #define MASK_MRSPERR (1 << 8)
158 #define MASK_MCCSTO (1 << 5)
159 #define MASK_MCRCSTO (1 << 4)
160 #define MASK_MWDATTO (1 << 3)
161 #define MASK_MRDATTO (1 << 2)
162 #define MASK_MRBSYTO (1 << 1)
163 #define MASK_MRSPTO (1 << 0)
164
165 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
166 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
167 MASK_MCRCSTO | MASK_MWDATTO | \
168 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
169
170 #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \
171 MASK_MBUFREN | MASK_MBUFWEN | \
172 MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \
173 MASK_MCMD12RBE | MASK_MCMD12CRE)
174
175 /* CE_HOST_STS1 */
176 #define STS1_CMDSEQ (1 << 31)
177
178 /* CE_HOST_STS2 */
179 #define STS2_CRCSTE (1 << 31)
180 #define STS2_CRC16E (1 << 30)
181 #define STS2_AC12CRCE (1 << 29)
182 #define STS2_RSPCRC7E (1 << 28)
183 #define STS2_CRCSTEBE (1 << 27)
184 #define STS2_RDATEBE (1 << 26)
185 #define STS2_AC12REBE (1 << 25)
186 #define STS2_RSPEBE (1 << 24)
187 #define STS2_AC12IDXE (1 << 23)
188 #define STS2_RSPIDXE (1 << 22)
189 #define STS2_CCSTO (1 << 15)
190 #define STS2_RDATTO (1 << 14)
191 #define STS2_DATBSYTO (1 << 13)
192 #define STS2_CRCSTTO (1 << 12)
193 #define STS2_AC12BSYTO (1 << 11)
194 #define STS2_RSPBSYTO (1 << 10)
195 #define STS2_AC12RSPTO (1 << 9)
196 #define STS2_RSPTO (1 << 8)
197 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
198 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
199 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
200 STS2_DATBSYTO | STS2_CRCSTTO | \
201 STS2_AC12BSYTO | STS2_RSPBSYTO | \
202 STS2_AC12RSPTO | STS2_RSPTO)
203
204 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
205 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
206 #define CLKDEV_INIT 400000 /* 400 KHz */
207
208 enum mmcif_state {
209 STATE_IDLE,
210 STATE_REQUEST,
211 STATE_IOS,
212 STATE_TIMEOUT,
213 };
214
215 enum mmcif_wait_for {
216 MMCIF_WAIT_FOR_REQUEST,
217 MMCIF_WAIT_FOR_CMD,
218 MMCIF_WAIT_FOR_MREAD,
219 MMCIF_WAIT_FOR_MWRITE,
220 MMCIF_WAIT_FOR_READ,
221 MMCIF_WAIT_FOR_WRITE,
222 MMCIF_WAIT_FOR_READ_END,
223 MMCIF_WAIT_FOR_WRITE_END,
224 MMCIF_WAIT_FOR_STOP,
225 };
226
227 struct sh_mmcif_host {
228 struct mmc_host *mmc;
229 struct mmc_request *mrq;
230 struct platform_device *pd;
231 struct clk *hclk;
232 unsigned int clk;
233 int bus_width;
234 unsigned char timing;
235 bool sd_error;
236 bool dying;
237 long timeout;
238 void __iomem *addr;
239 u32 *pio_ptr;
240 spinlock_t lock; /* protect sh_mmcif_host::state */
241 enum mmcif_state state;
242 enum mmcif_wait_for wait_for;
243 struct delayed_work timeout_work;
244 size_t blocksize;
245 int sg_idx;
246 int sg_blkidx;
247 bool power;
248 bool card_present;
249 bool ccs_enable; /* Command Completion Signal support */
250 bool clk_ctrl2_enable;
251 struct mutex thread_lock;
252
253 /* DMA support */
254 struct dma_chan *chan_rx;
255 struct dma_chan *chan_tx;
256 struct completion dma_complete;
257 bool dma_active;
258 };
259
260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
261 unsigned int reg, u32 val)
262 {
263 writel(val | readl(host->addr + reg), host->addr + reg);
264 }
265
266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
267 unsigned int reg, u32 val)
268 {
269 writel(~val & readl(host->addr + reg), host->addr + reg);
270 }
271
272 static void mmcif_dma_complete(void *arg)
273 {
274 struct sh_mmcif_host *host = arg;
275 struct mmc_request *mrq = host->mrq;
276
277 dev_dbg(&host->pd->dev, "Command completed\n");
278
279 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
280 dev_name(&host->pd->dev)))
281 return;
282
283 complete(&host->dma_complete);
284 }
285
286 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
287 {
288 struct mmc_data *data = host->mrq->data;
289 struct scatterlist *sg = data->sg;
290 struct dma_async_tx_descriptor *desc = NULL;
291 struct dma_chan *chan = host->chan_rx;
292 dma_cookie_t cookie = -EINVAL;
293 int ret;
294
295 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
296 DMA_FROM_DEVICE);
297 if (ret > 0) {
298 host->dma_active = true;
299 desc = dmaengine_prep_slave_sg(chan, sg, ret,
300 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
301 }
302
303 if (desc) {
304 desc->callback = mmcif_dma_complete;
305 desc->callback_param = host;
306 cookie = dmaengine_submit(desc);
307 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
308 dma_async_issue_pending(chan);
309 }
310 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
311 __func__, data->sg_len, ret, cookie);
312
313 if (!desc) {
314 /* DMA failed, fall back to PIO */
315 if (ret >= 0)
316 ret = -EIO;
317 host->chan_rx = NULL;
318 host->dma_active = false;
319 dma_release_channel(chan);
320 /* Free the Tx channel too */
321 chan = host->chan_tx;
322 if (chan) {
323 host->chan_tx = NULL;
324 dma_release_channel(chan);
325 }
326 dev_warn(&host->pd->dev,
327 "DMA failed: %d, falling back to PIO\n", ret);
328 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
329 }
330
331 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
332 desc, cookie, data->sg_len);
333 }
334
335 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
336 {
337 struct mmc_data *data = host->mrq->data;
338 struct scatterlist *sg = data->sg;
339 struct dma_async_tx_descriptor *desc = NULL;
340 struct dma_chan *chan = host->chan_tx;
341 dma_cookie_t cookie = -EINVAL;
342 int ret;
343
344 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
345 DMA_TO_DEVICE);
346 if (ret > 0) {
347 host->dma_active = true;
348 desc = dmaengine_prep_slave_sg(chan, sg, ret,
349 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
350 }
351
352 if (desc) {
353 desc->callback = mmcif_dma_complete;
354 desc->callback_param = host;
355 cookie = dmaengine_submit(desc);
356 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
357 dma_async_issue_pending(chan);
358 }
359 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
360 __func__, data->sg_len, ret, cookie);
361
362 if (!desc) {
363 /* DMA failed, fall back to PIO */
364 if (ret >= 0)
365 ret = -EIO;
366 host->chan_tx = NULL;
367 host->dma_active = false;
368 dma_release_channel(chan);
369 /* Free the Rx channel too */
370 chan = host->chan_rx;
371 if (chan) {
372 host->chan_rx = NULL;
373 dma_release_channel(chan);
374 }
375 dev_warn(&host->pd->dev,
376 "DMA failed: %d, falling back to PIO\n", ret);
377 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
378 }
379
380 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
381 desc, cookie);
382 }
383
384 static struct dma_chan *
385 sh_mmcif_request_dma_one(struct sh_mmcif_host *host,
386 struct sh_mmcif_plat_data *pdata,
387 enum dma_transfer_direction direction)
388 {
389 struct dma_slave_config cfg = { 0, };
390 struct dma_chan *chan;
391 unsigned int slave_id;
392 struct resource *res;
393 dma_cap_mask_t mask;
394 int ret;
395
396 dma_cap_zero(mask);
397 dma_cap_set(DMA_SLAVE, mask);
398
399 if (pdata)
400 slave_id = direction == DMA_MEM_TO_DEV
401 ? pdata->slave_id_tx : pdata->slave_id_rx;
402 else
403 slave_id = 0;
404
405 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
406 (void *)(unsigned long)slave_id, &host->pd->dev,
407 direction == DMA_MEM_TO_DEV ? "tx" : "rx");
408
409 dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__,
410 direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan);
411
412 if (!chan)
413 return NULL;
414
415 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
416
417 /* In the OF case the driver will get the slave ID from the DT */
418 cfg.slave_id = slave_id;
419 cfg.direction = direction;
420
421 if (direction == DMA_DEV_TO_MEM) {
422 cfg.src_addr = res->start + MMCIF_CE_DATA;
423 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
424 } else {
425 cfg.dst_addr = res->start + MMCIF_CE_DATA;
426 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
427 }
428
429 ret = dmaengine_slave_config(chan, &cfg);
430 if (ret < 0) {
431 dma_release_channel(chan);
432 return NULL;
433 }
434
435 return chan;
436 }
437
438 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
439 struct sh_mmcif_plat_data *pdata)
440 {
441 host->dma_active = false;
442
443 if (pdata) {
444 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
445 return;
446 } else if (!host->pd->dev.of_node) {
447 return;
448 }
449
450 /* We can only either use DMA for both Tx and Rx or not use it at all */
451 host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV);
452 if (!host->chan_tx)
453 return;
454
455 host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM);
456 if (!host->chan_rx) {
457 dma_release_channel(host->chan_tx);
458 host->chan_tx = NULL;
459 }
460 }
461
462 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
463 {
464 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
465 /* Descriptors are freed automatically */
466 if (host->chan_tx) {
467 struct dma_chan *chan = host->chan_tx;
468 host->chan_tx = NULL;
469 dma_release_channel(chan);
470 }
471 if (host->chan_rx) {
472 struct dma_chan *chan = host->chan_rx;
473 host->chan_rx = NULL;
474 dma_release_channel(chan);
475 }
476
477 host->dma_active = false;
478 }
479
480 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
481 {
482 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
483 bool sup_pclk = p ? p->sup_pclk : false;
484
485 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
487
488 if (!clk)
489 return;
490 if (sup_pclk && clk == host->clk)
491 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
492 else
493 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
494 ((fls(DIV_ROUND_UP(host->clk,
495 clk) - 1) - 1) << 16));
496
497 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
498 }
499
500 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
501 {
502 u32 tmp;
503
504 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
505
506 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
507 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
508 if (host->ccs_enable)
509 tmp |= SCCSTO_29;
510 if (host->clk_ctrl2_enable)
511 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
512 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
513 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
514 /* byte swap on */
515 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
516 }
517
518 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
519 {
520 u32 state1, state2;
521 int ret, timeout;
522
523 host->sd_error = false;
524
525 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
526 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
527 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
528 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
529
530 if (state1 & STS1_CMDSEQ) {
531 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
532 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
533 for (timeout = 10000000; timeout; timeout--) {
534 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
535 & STS1_CMDSEQ))
536 break;
537 mdelay(1);
538 }
539 if (!timeout) {
540 dev_err(&host->pd->dev,
541 "Forced end of command sequence timeout err\n");
542 return -EIO;
543 }
544 sh_mmcif_sync_reset(host);
545 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
546 return -EIO;
547 }
548
549 if (state2 & STS2_CRC_ERR) {
550 dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n",
551 host->state, host->wait_for);
552 ret = -EIO;
553 } else if (state2 & STS2_TIMEOUT_ERR) {
554 dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n",
555 host->state, host->wait_for);
556 ret = -ETIMEDOUT;
557 } else {
558 dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n",
559 host->state, host->wait_for);
560 ret = -EIO;
561 }
562 return ret;
563 }
564
565 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
566 {
567 struct mmc_data *data = host->mrq->data;
568
569 host->sg_blkidx += host->blocksize;
570
571 /* data->sg->length must be a multiple of host->blocksize? */
572 BUG_ON(host->sg_blkidx > data->sg->length);
573
574 if (host->sg_blkidx == data->sg->length) {
575 host->sg_blkidx = 0;
576 if (++host->sg_idx < data->sg_len)
577 host->pio_ptr = sg_virt(++data->sg);
578 } else {
579 host->pio_ptr = p;
580 }
581
582 return host->sg_idx != data->sg_len;
583 }
584
585 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
586 struct mmc_request *mrq)
587 {
588 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
589 BLOCK_SIZE_MASK) + 3;
590
591 host->wait_for = MMCIF_WAIT_FOR_READ;
592
593 /* buf read enable */
594 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
595 }
596
597 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
598 {
599 struct mmc_data *data = host->mrq->data;
600 u32 *p = sg_virt(data->sg);
601 int i;
602
603 if (host->sd_error) {
604 data->error = sh_mmcif_error_manage(host);
605 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
606 return false;
607 }
608
609 for (i = 0; i < host->blocksize / 4; i++)
610 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
611
612 /* buffer read end */
613 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
614 host->wait_for = MMCIF_WAIT_FOR_READ_END;
615
616 return true;
617 }
618
619 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
620 struct mmc_request *mrq)
621 {
622 struct mmc_data *data = mrq->data;
623
624 if (!data->sg_len || !data->sg->length)
625 return;
626
627 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
628 BLOCK_SIZE_MASK;
629
630 host->wait_for = MMCIF_WAIT_FOR_MREAD;
631 host->sg_idx = 0;
632 host->sg_blkidx = 0;
633 host->pio_ptr = sg_virt(data->sg);
634
635 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
636 }
637
638 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
639 {
640 struct mmc_data *data = host->mrq->data;
641 u32 *p = host->pio_ptr;
642 int i;
643
644 if (host->sd_error) {
645 data->error = sh_mmcif_error_manage(host);
646 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
647 return false;
648 }
649
650 BUG_ON(!data->sg->length);
651
652 for (i = 0; i < host->blocksize / 4; i++)
653 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
654
655 if (!sh_mmcif_next_block(host, p))
656 return false;
657
658 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
659
660 return true;
661 }
662
663 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
664 struct mmc_request *mrq)
665 {
666 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
667 BLOCK_SIZE_MASK) + 3;
668
669 host->wait_for = MMCIF_WAIT_FOR_WRITE;
670
671 /* buf write enable */
672 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
673 }
674
675 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
676 {
677 struct mmc_data *data = host->mrq->data;
678 u32 *p = sg_virt(data->sg);
679 int i;
680
681 if (host->sd_error) {
682 data->error = sh_mmcif_error_manage(host);
683 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
684 return false;
685 }
686
687 for (i = 0; i < host->blocksize / 4; i++)
688 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
689
690 /* buffer write end */
691 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
692 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
693
694 return true;
695 }
696
697 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
698 struct mmc_request *mrq)
699 {
700 struct mmc_data *data = mrq->data;
701
702 if (!data->sg_len || !data->sg->length)
703 return;
704
705 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
706 BLOCK_SIZE_MASK;
707
708 host->wait_for = MMCIF_WAIT_FOR_MWRITE;
709 host->sg_idx = 0;
710 host->sg_blkidx = 0;
711 host->pio_ptr = sg_virt(data->sg);
712
713 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
714 }
715
716 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
717 {
718 struct mmc_data *data = host->mrq->data;
719 u32 *p = host->pio_ptr;
720 int i;
721
722 if (host->sd_error) {
723 data->error = sh_mmcif_error_manage(host);
724 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error);
725 return false;
726 }
727
728 BUG_ON(!data->sg->length);
729
730 for (i = 0; i < host->blocksize / 4; i++)
731 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
732
733 if (!sh_mmcif_next_block(host, p))
734 return false;
735
736 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
737
738 return true;
739 }
740
741 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
742 struct mmc_command *cmd)
743 {
744 if (cmd->flags & MMC_RSP_136) {
745 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
746 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
747 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
748 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
749 } else
750 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
751 }
752
753 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
754 struct mmc_command *cmd)
755 {
756 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
757 }
758
759 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
760 struct mmc_request *mrq)
761 {
762 struct mmc_data *data = mrq->data;
763 struct mmc_command *cmd = mrq->cmd;
764 u32 opc = cmd->opcode;
765 u32 tmp = 0;
766
767 /* Response Type check */
768 switch (mmc_resp_type(cmd)) {
769 case MMC_RSP_NONE:
770 tmp |= CMD_SET_RTYP_NO;
771 break;
772 case MMC_RSP_R1:
773 case MMC_RSP_R1B:
774 case MMC_RSP_R3:
775 tmp |= CMD_SET_RTYP_6B;
776 break;
777 case MMC_RSP_R2:
778 tmp |= CMD_SET_RTYP_17B;
779 break;
780 default:
781 dev_err(&host->pd->dev, "Unsupported response type.\n");
782 break;
783 }
784 switch (opc) {
785 /* RBSY */
786 case MMC_SLEEP_AWAKE:
787 case MMC_SWITCH:
788 case MMC_STOP_TRANSMISSION:
789 case MMC_SET_WRITE_PROT:
790 case MMC_CLR_WRITE_PROT:
791 case MMC_ERASE:
792 tmp |= CMD_SET_RBSY;
793 break;
794 }
795 /* WDAT / DATW */
796 if (data) {
797 tmp |= CMD_SET_WDAT;
798 switch (host->bus_width) {
799 case MMC_BUS_WIDTH_1:
800 tmp |= CMD_SET_DATW_1;
801 break;
802 case MMC_BUS_WIDTH_4:
803 tmp |= CMD_SET_DATW_4;
804 break;
805 case MMC_BUS_WIDTH_8:
806 tmp |= CMD_SET_DATW_8;
807 break;
808 default:
809 dev_err(&host->pd->dev, "Unsupported bus width.\n");
810 break;
811 }
812 switch (host->timing) {
813 case MMC_TIMING_MMC_DDR52:
814 /*
815 * MMC core will only set this timing, if the host
816 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR
817 * capability. MMCIF implementations with this
818 * capability, e.g. sh73a0, will have to set it
819 * in their platform data.
820 */
821 tmp |= CMD_SET_DARS;
822 break;
823 }
824 }
825 /* DWEN */
826 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
827 tmp |= CMD_SET_DWEN;
828 /* CMLTE/CMD12EN */
829 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
830 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
831 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
832 data->blocks << 16);
833 }
834 /* RIDXC[1:0] check bits */
835 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
836 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
837 tmp |= CMD_SET_RIDXC_BITS;
838 /* RCRC7C[1:0] check bits */
839 if (opc == MMC_SEND_OP_COND)
840 tmp |= CMD_SET_CRC7C_BITS;
841 /* RCRC7C[1:0] internal CRC7 */
842 if (opc == MMC_ALL_SEND_CID ||
843 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
844 tmp |= CMD_SET_CRC7C_INTERNAL;
845
846 return (opc << 24) | tmp;
847 }
848
849 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
850 struct mmc_request *mrq, u32 opc)
851 {
852 switch (opc) {
853 case MMC_READ_MULTIPLE_BLOCK:
854 sh_mmcif_multi_read(host, mrq);
855 return 0;
856 case MMC_WRITE_MULTIPLE_BLOCK:
857 sh_mmcif_multi_write(host, mrq);
858 return 0;
859 case MMC_WRITE_BLOCK:
860 sh_mmcif_single_write(host, mrq);
861 return 0;
862 case MMC_READ_SINGLE_BLOCK:
863 case MMC_SEND_EXT_CSD:
864 sh_mmcif_single_read(host, mrq);
865 return 0;
866 default:
867 dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc);
868 return -EINVAL;
869 }
870 }
871
872 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
873 struct mmc_request *mrq)
874 {
875 struct mmc_command *cmd = mrq->cmd;
876 u32 opc = cmd->opcode;
877 u32 mask;
878
879 switch (opc) {
880 /* response busy check */
881 case MMC_SLEEP_AWAKE:
882 case MMC_SWITCH:
883 case MMC_STOP_TRANSMISSION:
884 case MMC_SET_WRITE_PROT:
885 case MMC_CLR_WRITE_PROT:
886 case MMC_ERASE:
887 mask = MASK_START_CMD | MASK_MRBSYE;
888 break;
889 default:
890 mask = MASK_START_CMD | MASK_MCRSPE;
891 break;
892 }
893
894 if (host->ccs_enable)
895 mask |= MASK_MCCSTO;
896
897 if (mrq->data) {
898 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
899 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
900 mrq->data->blksz);
901 }
902 opc = sh_mmcif_set_cmd(host, mrq);
903
904 if (host->ccs_enable)
905 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
906 else
907 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
908 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
909 /* set arg */
910 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
911 /* set cmd */
912 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
913
914 host->wait_for = MMCIF_WAIT_FOR_CMD;
915 schedule_delayed_work(&host->timeout_work, host->timeout);
916 }
917
918 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
919 struct mmc_request *mrq)
920 {
921 switch (mrq->cmd->opcode) {
922 case MMC_READ_MULTIPLE_BLOCK:
923 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
924 break;
925 case MMC_WRITE_MULTIPLE_BLOCK:
926 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
927 break;
928 default:
929 dev_err(&host->pd->dev, "unsupported stop cmd\n");
930 mrq->stop->error = sh_mmcif_error_manage(host);
931 return;
932 }
933
934 host->wait_for = MMCIF_WAIT_FOR_STOP;
935 }
936
937 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
938 {
939 struct sh_mmcif_host *host = mmc_priv(mmc);
940 unsigned long flags;
941
942 spin_lock_irqsave(&host->lock, flags);
943 if (host->state != STATE_IDLE) {
944 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
945 spin_unlock_irqrestore(&host->lock, flags);
946 mrq->cmd->error = -EAGAIN;
947 mmc_request_done(mmc, mrq);
948 return;
949 }
950
951 host->state = STATE_REQUEST;
952 spin_unlock_irqrestore(&host->lock, flags);
953
954 switch (mrq->cmd->opcode) {
955 /* MMCIF does not support SD/SDIO command */
956 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */
957 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
958 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)
959 break;
960 case MMC_APP_CMD:
961 case SD_IO_RW_DIRECT:
962 host->state = STATE_IDLE;
963 mrq->cmd->error = -ETIMEDOUT;
964 mmc_request_done(mmc, mrq);
965 return;
966 default:
967 break;
968 }
969
970 host->mrq = mrq;
971
972 sh_mmcif_start_cmd(host, mrq);
973 }
974
975 static int sh_mmcif_clk_update(struct sh_mmcif_host *host)
976 {
977 int ret = clk_prepare_enable(host->hclk);
978
979 if (!ret) {
980 host->clk = clk_get_rate(host->hclk);
981 host->mmc->f_max = host->clk / 2;
982 host->mmc->f_min = host->clk / 512;
983 }
984
985 return ret;
986 }
987
988 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios)
989 {
990 struct mmc_host *mmc = host->mmc;
991
992 if (!IS_ERR(mmc->supply.vmmc))
993 /* Errors ignored... */
994 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
995 ios->power_mode ? ios->vdd : 0);
996 }
997
998 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
999 {
1000 struct sh_mmcif_host *host = mmc_priv(mmc);
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&host->lock, flags);
1004 if (host->state != STATE_IDLE) {
1005 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state);
1006 spin_unlock_irqrestore(&host->lock, flags);
1007 return;
1008 }
1009
1010 host->state = STATE_IOS;
1011 spin_unlock_irqrestore(&host->lock, flags);
1012
1013 if (ios->power_mode == MMC_POWER_UP) {
1014 if (!host->card_present) {
1015 /* See if we also get DMA */
1016 sh_mmcif_request_dma(host, host->pd->dev.platform_data);
1017 host->card_present = true;
1018 }
1019 sh_mmcif_set_power(host, ios);
1020 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
1021 /* clock stop */
1022 sh_mmcif_clock_control(host, 0);
1023 if (ios->power_mode == MMC_POWER_OFF) {
1024 if (host->card_present) {
1025 sh_mmcif_release_dma(host);
1026 host->card_present = false;
1027 }
1028 }
1029 if (host->power) {
1030 pm_runtime_put_sync(&host->pd->dev);
1031 clk_disable_unprepare(host->hclk);
1032 host->power = false;
1033 if (ios->power_mode == MMC_POWER_OFF)
1034 sh_mmcif_set_power(host, ios);
1035 }
1036 host->state = STATE_IDLE;
1037 return;
1038 }
1039
1040 if (ios->clock) {
1041 if (!host->power) {
1042 sh_mmcif_clk_update(host);
1043 pm_runtime_get_sync(&host->pd->dev);
1044 host->power = true;
1045 sh_mmcif_sync_reset(host);
1046 }
1047 sh_mmcif_clock_control(host, ios->clock);
1048 }
1049
1050 host->timing = ios->timing;
1051 host->bus_width = ios->bus_width;
1052 host->state = STATE_IDLE;
1053 }
1054
1055 static int sh_mmcif_get_cd(struct mmc_host *mmc)
1056 {
1057 struct sh_mmcif_host *host = mmc_priv(mmc);
1058 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
1059 int ret = mmc_gpio_get_cd(mmc);
1060
1061 if (ret >= 0)
1062 return ret;
1063
1064 if (!p || !p->get_cd)
1065 return -ENOSYS;
1066 else
1067 return p->get_cd(host->pd);
1068 }
1069
1070 static struct mmc_host_ops sh_mmcif_ops = {
1071 .request = sh_mmcif_request,
1072 .set_ios = sh_mmcif_set_ios,
1073 .get_cd = sh_mmcif_get_cd,
1074 };
1075
1076 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1077 {
1078 struct mmc_command *cmd = host->mrq->cmd;
1079 struct mmc_data *data = host->mrq->data;
1080 long time;
1081
1082 if (host->sd_error) {
1083 switch (cmd->opcode) {
1084 case MMC_ALL_SEND_CID:
1085 case MMC_SELECT_CARD:
1086 case MMC_APP_CMD:
1087 cmd->error = -ETIMEDOUT;
1088 break;
1089 default:
1090 cmd->error = sh_mmcif_error_manage(host);
1091 break;
1092 }
1093 dev_dbg(&host->pd->dev, "CMD%d error %d\n",
1094 cmd->opcode, cmd->error);
1095 host->sd_error = false;
1096 return false;
1097 }
1098 if (!(cmd->flags & MMC_RSP_PRESENT)) {
1099 cmd->error = 0;
1100 return false;
1101 }
1102
1103 sh_mmcif_get_response(host, cmd);
1104
1105 if (!data)
1106 return false;
1107
1108 /*
1109 * Completion can be signalled from DMA callback and error, so, have to
1110 * reset here, before setting .dma_active
1111 */
1112 init_completion(&host->dma_complete);
1113
1114 if (data->flags & MMC_DATA_READ) {
1115 if (host->chan_rx)
1116 sh_mmcif_start_dma_rx(host);
1117 } else {
1118 if (host->chan_tx)
1119 sh_mmcif_start_dma_tx(host);
1120 }
1121
1122 if (!host->dma_active) {
1123 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1124 return !data->error;
1125 }
1126
1127 /* Running in the IRQ thread, can sleep */
1128 time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1129 host->timeout);
1130
1131 if (data->flags & MMC_DATA_READ)
1132 dma_unmap_sg(host->chan_rx->device->dev,
1133 data->sg, data->sg_len,
1134 DMA_FROM_DEVICE);
1135 else
1136 dma_unmap_sg(host->chan_tx->device->dev,
1137 data->sg, data->sg_len,
1138 DMA_TO_DEVICE);
1139
1140 if (host->sd_error) {
1141 dev_err(host->mmc->parent,
1142 "Error IRQ while waiting for DMA completion!\n");
1143 /* Woken up by an error IRQ: abort DMA */
1144 data->error = sh_mmcif_error_manage(host);
1145 } else if (!time) {
1146 dev_err(host->mmc->parent, "DMA timeout!\n");
1147 data->error = -ETIMEDOUT;
1148 } else if (time < 0) {
1149 dev_err(host->mmc->parent,
1150 "wait_for_completion_...() error %ld!\n", time);
1151 data->error = time;
1152 }
1153 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1154 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1155 host->dma_active = false;
1156
1157 if (data->error) {
1158 data->bytes_xfered = 0;
1159 /* Abort DMA */
1160 if (data->flags & MMC_DATA_READ)
1161 dmaengine_terminate_all(host->chan_rx);
1162 else
1163 dmaengine_terminate_all(host->chan_tx);
1164 }
1165
1166 return false;
1167 }
1168
1169 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1170 {
1171 struct sh_mmcif_host *host = dev_id;
1172 struct mmc_request *mrq;
1173 bool wait = false;
1174
1175 cancel_delayed_work_sync(&host->timeout_work);
1176
1177 mutex_lock(&host->thread_lock);
1178
1179 mrq = host->mrq;
1180 if (!mrq) {
1181 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
1182 host->state, host->wait_for);
1183 mutex_unlock(&host->thread_lock);
1184 return IRQ_HANDLED;
1185 }
1186
1187 /*
1188 * All handlers return true, if processing continues, and false, if the
1189 * request has to be completed - successfully or not
1190 */
1191 switch (host->wait_for) {
1192 case MMCIF_WAIT_FOR_REQUEST:
1193 /* We're too late, the timeout has already kicked in */
1194 mutex_unlock(&host->thread_lock);
1195 return IRQ_HANDLED;
1196 case MMCIF_WAIT_FOR_CMD:
1197 /* Wait for data? */
1198 wait = sh_mmcif_end_cmd(host);
1199 break;
1200 case MMCIF_WAIT_FOR_MREAD:
1201 /* Wait for more data? */
1202 wait = sh_mmcif_mread_block(host);
1203 break;
1204 case MMCIF_WAIT_FOR_READ:
1205 /* Wait for data end? */
1206 wait = sh_mmcif_read_block(host);
1207 break;
1208 case MMCIF_WAIT_FOR_MWRITE:
1209 /* Wait data to write? */
1210 wait = sh_mmcif_mwrite_block(host);
1211 break;
1212 case MMCIF_WAIT_FOR_WRITE:
1213 /* Wait for data end? */
1214 wait = sh_mmcif_write_block(host);
1215 break;
1216 case MMCIF_WAIT_FOR_STOP:
1217 if (host->sd_error) {
1218 mrq->stop->error = sh_mmcif_error_manage(host);
1219 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error);
1220 break;
1221 }
1222 sh_mmcif_get_cmd12response(host, mrq->stop);
1223 mrq->stop->error = 0;
1224 break;
1225 case MMCIF_WAIT_FOR_READ_END:
1226 case MMCIF_WAIT_FOR_WRITE_END:
1227 if (host->sd_error) {
1228 mrq->data->error = sh_mmcif_error_manage(host);
1229 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error);
1230 }
1231 break;
1232 default:
1233 BUG();
1234 }
1235
1236 if (wait) {
1237 schedule_delayed_work(&host->timeout_work, host->timeout);
1238 /* Wait for more data */
1239 mutex_unlock(&host->thread_lock);
1240 return IRQ_HANDLED;
1241 }
1242
1243 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1244 struct mmc_data *data = mrq->data;
1245 if (!mrq->cmd->error && data && !data->error)
1246 data->bytes_xfered =
1247 data->blocks * data->blksz;
1248
1249 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1250 sh_mmcif_stop_cmd(host, mrq);
1251 if (!mrq->stop->error) {
1252 schedule_delayed_work(&host->timeout_work, host->timeout);
1253 mutex_unlock(&host->thread_lock);
1254 return IRQ_HANDLED;
1255 }
1256 }
1257 }
1258
1259 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1260 host->state = STATE_IDLE;
1261 host->mrq = NULL;
1262 mmc_request_done(host->mmc, mrq);
1263
1264 mutex_unlock(&host->thread_lock);
1265
1266 return IRQ_HANDLED;
1267 }
1268
1269 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1270 {
1271 struct sh_mmcif_host *host = dev_id;
1272 u32 state, mask;
1273
1274 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1275 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1276 if (host->ccs_enable)
1277 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1278 else
1279 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
1280 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1281
1282 if (state & ~MASK_CLEAN)
1283 dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n",
1284 state);
1285
1286 if (state & INT_ERR_STS || state & ~INT_ALL) {
1287 host->sd_error = true;
1288 dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state);
1289 }
1290 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1291 if (!host->mrq)
1292 dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state);
1293 if (!host->dma_active)
1294 return IRQ_WAKE_THREAD;
1295 else if (host->sd_error)
1296 mmcif_dma_complete(host);
1297 } else {
1298 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1299 }
1300
1301 return IRQ_HANDLED;
1302 }
1303
1304 static void mmcif_timeout_work(struct work_struct *work)
1305 {
1306 struct delayed_work *d = container_of(work, struct delayed_work, work);
1307 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1308 struct mmc_request *mrq = host->mrq;
1309 unsigned long flags;
1310
1311 if (host->dying)
1312 /* Don't run after mmc_remove_host() */
1313 return;
1314
1315 dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n",
1316 host->wait_for, mrq->cmd->opcode);
1317
1318 spin_lock_irqsave(&host->lock, flags);
1319 if (host->state == STATE_IDLE) {
1320 spin_unlock_irqrestore(&host->lock, flags);
1321 return;
1322 }
1323
1324 host->state = STATE_TIMEOUT;
1325 spin_unlock_irqrestore(&host->lock, flags);
1326
1327 /*
1328 * Handle races with cancel_delayed_work(), unless
1329 * cancel_delayed_work_sync() is used
1330 */
1331 switch (host->wait_for) {
1332 case MMCIF_WAIT_FOR_CMD:
1333 mrq->cmd->error = sh_mmcif_error_manage(host);
1334 break;
1335 case MMCIF_WAIT_FOR_STOP:
1336 mrq->stop->error = sh_mmcif_error_manage(host);
1337 break;
1338 case MMCIF_WAIT_FOR_MREAD:
1339 case MMCIF_WAIT_FOR_MWRITE:
1340 case MMCIF_WAIT_FOR_READ:
1341 case MMCIF_WAIT_FOR_WRITE:
1342 case MMCIF_WAIT_FOR_READ_END:
1343 case MMCIF_WAIT_FOR_WRITE_END:
1344 mrq->data->error = sh_mmcif_error_manage(host);
1345 break;
1346 default:
1347 BUG();
1348 }
1349
1350 host->state = STATE_IDLE;
1351 host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1352 host->mrq = NULL;
1353 mmc_request_done(host->mmc, mrq);
1354 }
1355
1356 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
1357 {
1358 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data;
1359 struct mmc_host *mmc = host->mmc;
1360
1361 mmc_regulator_get_supply(mmc);
1362
1363 if (!pd)
1364 return;
1365
1366 if (!mmc->ocr_avail)
1367 mmc->ocr_avail = pd->ocr;
1368 else if (pd->ocr)
1369 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1370 }
1371
1372 static int sh_mmcif_probe(struct platform_device *pdev)
1373 {
1374 int ret = 0, irq[2];
1375 struct mmc_host *mmc;
1376 struct sh_mmcif_host *host;
1377 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data;
1378 struct resource *res;
1379 void __iomem *reg;
1380 const char *name;
1381
1382 irq[0] = platform_get_irq(pdev, 0);
1383 irq[1] = platform_get_irq(pdev, 1);
1384 if (irq[0] < 0) {
1385 dev_err(&pdev->dev, "Get irq error\n");
1386 return -ENXIO;
1387 }
1388
1389 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1390 reg = devm_ioremap_resource(&pdev->dev, res);
1391 if (IS_ERR(reg))
1392 return PTR_ERR(reg);
1393
1394 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1395 if (!mmc)
1396 return -ENOMEM;
1397
1398 ret = mmc_of_parse(mmc);
1399 if (ret < 0)
1400 goto err_host;
1401
1402 host = mmc_priv(mmc);
1403 host->mmc = mmc;
1404 host->addr = reg;
1405 host->timeout = msecs_to_jiffies(1000);
1406 host->ccs_enable = !pd || !pd->ccs_unsupported;
1407 host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present;
1408
1409 host->pd = pdev;
1410
1411 spin_lock_init(&host->lock);
1412
1413 mmc->ops = &sh_mmcif_ops;
1414 sh_mmcif_init_ocr(host);
1415
1416 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1417 if (pd && pd->caps)
1418 mmc->caps |= pd->caps;
1419 mmc->max_segs = 32;
1420 mmc->max_blk_size = 512;
1421 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1422 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1423 mmc->max_seg_size = mmc->max_req_size;
1424
1425 platform_set_drvdata(pdev, host);
1426
1427 pm_runtime_enable(&pdev->dev);
1428 host->power = false;
1429
1430 host->hclk = devm_clk_get(&pdev->dev, NULL);
1431 if (IS_ERR(host->hclk)) {
1432 ret = PTR_ERR(host->hclk);
1433 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
1434 goto err_pm;
1435 }
1436 ret = sh_mmcif_clk_update(host);
1437 if (ret < 0)
1438 goto err_pm;
1439
1440 ret = pm_runtime_resume(&pdev->dev);
1441 if (ret < 0)
1442 goto err_clk;
1443
1444 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1445
1446 sh_mmcif_sync_reset(host);
1447 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1448
1449 name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error";
1450 ret = devm_request_threaded_irq(&pdev->dev, irq[0], sh_mmcif_intr,
1451 sh_mmcif_irqt, 0, name, host);
1452 if (ret) {
1453 dev_err(&pdev->dev, "request_irq error (%s)\n", name);
1454 goto err_clk;
1455 }
1456 if (irq[1] >= 0) {
1457 ret = devm_request_threaded_irq(&pdev->dev, irq[1],
1458 sh_mmcif_intr, sh_mmcif_irqt,
1459 0, "sh_mmc:int", host);
1460 if (ret) {
1461 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1462 goto err_clk;
1463 }
1464 }
1465
1466 if (pd && pd->use_cd_gpio) {
1467 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
1468 if (ret < 0)
1469 goto err_clk;
1470 }
1471
1472 mutex_init(&host->thread_lock);
1473
1474 ret = mmc_add_host(mmc);
1475 if (ret < 0)
1476 goto err_clk;
1477
1478 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1479
1480 dev_info(&pdev->dev, "Chip version 0x%04x, clock rate %luMHz\n",
1481 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
1482 clk_get_rate(host->hclk) / 1000000UL);
1483
1484 clk_disable_unprepare(host->hclk);
1485 return ret;
1486
1487 err_clk:
1488 clk_disable_unprepare(host->hclk);
1489 err_pm:
1490 pm_runtime_disable(&pdev->dev);
1491 err_host:
1492 mmc_free_host(mmc);
1493 return ret;
1494 }
1495
1496 static int sh_mmcif_remove(struct platform_device *pdev)
1497 {
1498 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1499
1500 host->dying = true;
1501 clk_prepare_enable(host->hclk);
1502 pm_runtime_get_sync(&pdev->dev);
1503
1504 dev_pm_qos_hide_latency_limit(&pdev->dev);
1505
1506 mmc_remove_host(host->mmc);
1507 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1508
1509 /*
1510 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1511 * mmc_remove_host() call above. But swapping order doesn't help either
1512 * (a query on the linux-mmc mailing list didn't bring any replies).
1513 */
1514 cancel_delayed_work_sync(&host->timeout_work);
1515
1516 clk_disable_unprepare(host->hclk);
1517 mmc_free_host(host->mmc);
1518 pm_runtime_put_sync(&pdev->dev);
1519 pm_runtime_disable(&pdev->dev);
1520
1521 return 0;
1522 }
1523
1524 #ifdef CONFIG_PM_SLEEP
1525 static int sh_mmcif_suspend(struct device *dev)
1526 {
1527 struct sh_mmcif_host *host = dev_get_drvdata(dev);
1528
1529 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1530
1531 return 0;
1532 }
1533
1534 static int sh_mmcif_resume(struct device *dev)
1535 {
1536 return 0;
1537 }
1538 #endif
1539
1540 static const struct of_device_id mmcif_of_match[] = {
1541 { .compatible = "renesas,sh-mmcif" },
1542 { }
1543 };
1544 MODULE_DEVICE_TABLE(of, mmcif_of_match);
1545
1546 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1547 SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)
1548 };
1549
1550 static struct platform_driver sh_mmcif_driver = {
1551 .probe = sh_mmcif_probe,
1552 .remove = sh_mmcif_remove,
1553 .driver = {
1554 .name = DRIVER_NAME,
1555 .pm = &sh_mmcif_dev_pm_ops,
1556 .of_match_table = mmcif_of_match,
1557 },
1558 };
1559
1560 module_platform_driver(sh_mmcif_driver);
1561
1562 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1563 MODULE_LICENSE("GPL");
1564 MODULE_ALIAS("platform:" DRIVER_NAME);
1565 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
Linux kernel - Deliverables
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