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mmc: sunxi: Check the value returned by clk_round_rate
[deliverable/linux.git] / drivers / mmc / host / sunxi-mmc.c
1 /*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <linux/device.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22
23 #include <linux/clk.h>
24 #include <linux/gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/spinlock.h>
27 #include <linux/scatterlist.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/slab.h>
30 #include <linux/reset.h>
31 #include <linux/regulator/consumer.h>
32
33 #include <linux/of_address.h>
34 #include <linux/of_gpio.h>
35 #include <linux/of_platform.h>
36
37 #include <linux/mmc/host.h>
38 #include <linux/mmc/sd.h>
39 #include <linux/mmc/sdio.h>
40 #include <linux/mmc/mmc.h>
41 #include <linux/mmc/core.h>
42 #include <linux/mmc/card.h>
43 #include <linux/mmc/slot-gpio.h>
44
45 /* register offset definitions */
46 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
47 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
48 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
49 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
50 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
51 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
52 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
53 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
54 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
55 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
56 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
57 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
58 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
59 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
60 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
61 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
62 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
63 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
64 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
65 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
66 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
67 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
68 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
69 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
70 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
71 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
72 #define SDXC_REG_CHDA (0x90)
73 #define SDXC_REG_CBDA (0x94)
74
75 #define mmc_readl(host, reg) \
76 readl((host)->reg_base + SDXC_##reg)
77 #define mmc_writel(host, reg, value) \
78 writel((value), (host)->reg_base + SDXC_##reg)
79
80 /* global control register bits */
81 #define SDXC_SOFT_RESET BIT(0)
82 #define SDXC_FIFO_RESET BIT(1)
83 #define SDXC_DMA_RESET BIT(2)
84 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
85 #define SDXC_DMA_ENABLE_BIT BIT(5)
86 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
87 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
88 #define SDXC_DDR_MODE BIT(10)
89 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
90 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
91 #define SDXC_ACCESS_BY_AHB BIT(31)
92 #define SDXC_ACCESS_BY_DMA (0 << 31)
93 #define SDXC_HARDWARE_RESET \
94 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
95
96 /* clock control bits */
97 #define SDXC_CARD_CLOCK_ON BIT(16)
98 #define SDXC_LOW_POWER_ON BIT(17)
99
100 /* bus width */
101 #define SDXC_WIDTH1 0
102 #define SDXC_WIDTH4 1
103 #define SDXC_WIDTH8 2
104
105 /* smc command bits */
106 #define SDXC_RESP_EXPIRE BIT(6)
107 #define SDXC_LONG_RESPONSE BIT(7)
108 #define SDXC_CHECK_RESPONSE_CRC BIT(8)
109 #define SDXC_DATA_EXPIRE BIT(9)
110 #define SDXC_WRITE BIT(10)
111 #define SDXC_SEQUENCE_MODE BIT(11)
112 #define SDXC_SEND_AUTO_STOP BIT(12)
113 #define SDXC_WAIT_PRE_OVER BIT(13)
114 #define SDXC_STOP_ABORT_CMD BIT(14)
115 #define SDXC_SEND_INIT_SEQUENCE BIT(15)
116 #define SDXC_UPCLK_ONLY BIT(21)
117 #define SDXC_READ_CEATA_DEV BIT(22)
118 #define SDXC_CCS_EXPIRE BIT(23)
119 #define SDXC_ENABLE_BIT_BOOT BIT(24)
120 #define SDXC_ALT_BOOT_OPTIONS BIT(25)
121 #define SDXC_BOOT_ACK_EXPIRE BIT(26)
122 #define SDXC_BOOT_ABORT BIT(27)
123 #define SDXC_VOLTAGE_SWITCH BIT(28)
124 #define SDXC_USE_HOLD_REGISTER BIT(29)
125 #define SDXC_START BIT(31)
126
127 /* interrupt bits */
128 #define SDXC_RESP_ERROR BIT(1)
129 #define SDXC_COMMAND_DONE BIT(2)
130 #define SDXC_DATA_OVER BIT(3)
131 #define SDXC_TX_DATA_REQUEST BIT(4)
132 #define SDXC_RX_DATA_REQUEST BIT(5)
133 #define SDXC_RESP_CRC_ERROR BIT(6)
134 #define SDXC_DATA_CRC_ERROR BIT(7)
135 #define SDXC_RESP_TIMEOUT BIT(8)
136 #define SDXC_DATA_TIMEOUT BIT(9)
137 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
138 #define SDXC_FIFO_RUN_ERROR BIT(11)
139 #define SDXC_HARD_WARE_LOCKED BIT(12)
140 #define SDXC_START_BIT_ERROR BIT(13)
141 #define SDXC_AUTO_COMMAND_DONE BIT(14)
142 #define SDXC_END_BIT_ERROR BIT(15)
143 #define SDXC_SDIO_INTERRUPT BIT(16)
144 #define SDXC_CARD_INSERT BIT(30)
145 #define SDXC_CARD_REMOVE BIT(31)
146 #define SDXC_INTERRUPT_ERROR_BIT \
147 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
148 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
149 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
150 #define SDXC_INTERRUPT_DONE_BIT \
151 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
152 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
153
154 /* status */
155 #define SDXC_RXWL_FLAG BIT(0)
156 #define SDXC_TXWL_FLAG BIT(1)
157 #define SDXC_FIFO_EMPTY BIT(2)
158 #define SDXC_FIFO_FULL BIT(3)
159 #define SDXC_CARD_PRESENT BIT(8)
160 #define SDXC_CARD_DATA_BUSY BIT(9)
161 #define SDXC_DATA_FSM_BUSY BIT(10)
162 #define SDXC_DMA_REQUEST BIT(31)
163 #define SDXC_FIFO_SIZE 16
164
165 /* Function select */
166 #define SDXC_CEATA_ON (0xceaa << 16)
167 #define SDXC_SEND_IRQ_RESPONSE BIT(0)
168 #define SDXC_SDIO_READ_WAIT BIT(1)
169 #define SDXC_ABORT_READ_DATA BIT(2)
170 #define SDXC_SEND_CCSD BIT(8)
171 #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
172 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
173
174 /* IDMA controller bus mod bit field */
175 #define SDXC_IDMAC_SOFT_RESET BIT(0)
176 #define SDXC_IDMAC_FIX_BURST BIT(1)
177 #define SDXC_IDMAC_IDMA_ON BIT(7)
178 #define SDXC_IDMAC_REFETCH_DES BIT(31)
179
180 /* IDMA status bit field */
181 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
182 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
183 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
184 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
185 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
186 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
187 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
188 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
189 #define SDXC_IDMAC_IDLE (0 << 13)
190 #define SDXC_IDMAC_SUSPEND (1 << 13)
191 #define SDXC_IDMAC_DESC_READ (2 << 13)
192 #define SDXC_IDMAC_DESC_CHECK (3 << 13)
193 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
194 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
195 #define SDXC_IDMAC_READ (6 << 13)
196 #define SDXC_IDMAC_WRITE (7 << 13)
197 #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
198
199 /*
200 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
201 * Bits 0-12: buf1 size
202 * Bits 13-25: buf2 size
203 * Bits 26-31: not used
204 * Since we only ever set buf1 size, we can simply store it directly.
205 */
206 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
207 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
208 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
209 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
210 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
211 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
212 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
213
214 #define SDXC_CLK_400K 0
215 #define SDXC_CLK_25M 1
216 #define SDXC_CLK_50M 2
217 #define SDXC_CLK_50M_DDR 3
218 #define SDXC_CLK_50M_DDR_8BIT 4
219
220 struct sunxi_mmc_clk_delay {
221 u32 output;
222 u32 sample;
223 };
224
225 struct sunxi_idma_des {
226 u32 config;
227 u32 buf_size;
228 u32 buf_addr_ptr1;
229 u32 buf_addr_ptr2;
230 };
231
232 struct sunxi_mmc_cfg {
233 u32 idma_des_size_bits;
234 const struct sunxi_mmc_clk_delay *clk_delays;
235 };
236
237 struct sunxi_mmc_host {
238 struct mmc_host *mmc;
239 struct reset_control *reset;
240 const struct sunxi_mmc_cfg *cfg;
241
242 /* IO mapping base */
243 void __iomem *reg_base;
244
245 /* clock management */
246 struct clk *clk_ahb;
247 struct clk *clk_mmc;
248 struct clk *clk_sample;
249 struct clk *clk_output;
250
251 /* irq */
252 spinlock_t lock;
253 int irq;
254 u32 int_sum;
255 u32 sdio_imask;
256
257 /* dma */
258 dma_addr_t sg_dma;
259 void *sg_cpu;
260 bool wait_dma;
261
262 struct mmc_request *mrq;
263 struct mmc_request *manual_stop_mrq;
264 int ferror;
265
266 /* vqmmc */
267 bool vqmmc_enabled;
268 };
269
270 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
271 {
272 unsigned long expire = jiffies + msecs_to_jiffies(250);
273 u32 rval;
274
275 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
276 do {
277 rval = mmc_readl(host, REG_GCTRL);
278 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
279
280 if (rval & SDXC_HARDWARE_RESET) {
281 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
282 return -EIO;
283 }
284
285 return 0;
286 }
287
288 static int sunxi_mmc_init_host(struct mmc_host *mmc)
289 {
290 u32 rval;
291 struct sunxi_mmc_host *host = mmc_priv(mmc);
292
293 if (sunxi_mmc_reset_host(host))
294 return -EIO;
295
296 /*
297 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
298 *
299 * TODO: sun9i has a larger FIFO and supports higher trigger values
300 */
301 mmc_writel(host, REG_FTRGL, 0x20070008);
302 /* Maximum timeout value */
303 mmc_writel(host, REG_TMOUT, 0xffffffff);
304 /* Unmask SDIO interrupt if needed */
305 mmc_writel(host, REG_IMASK, host->sdio_imask);
306 /* Clear all pending interrupts */
307 mmc_writel(host, REG_RINTR, 0xffffffff);
308 /* Debug register? undocumented */
309 mmc_writel(host, REG_DBGC, 0xdeb);
310 /* Enable CEATA support */
311 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
312 /* Set DMA descriptor list base address */
313 mmc_writel(host, REG_DLBA, host->sg_dma);
314
315 rval = mmc_readl(host, REG_GCTRL);
316 rval |= SDXC_INTERRUPT_ENABLE_BIT;
317 /* Undocumented, but found in Allwinner code */
318 rval &= ~SDXC_ACCESS_DONE_DIRECT;
319 mmc_writel(host, REG_GCTRL, rval);
320
321 return 0;
322 }
323
324 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
325 struct mmc_data *data)
326 {
327 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
328 dma_addr_t next_desc = host->sg_dma;
329 int i, max_len = (1 << host->cfg->idma_des_size_bits);
330
331 for (i = 0; i < data->sg_len; i++) {
332 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
333 SDXC_IDMAC_DES0_DIC;
334
335 if (data->sg[i].length == max_len)
336 pdes[i].buf_size = 0; /* 0 == max_len */
337 else
338 pdes[i].buf_size = data->sg[i].length;
339
340 next_desc += sizeof(struct sunxi_idma_des);
341 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
342 pdes[i].buf_addr_ptr2 = (u32)next_desc;
343 }
344
345 pdes[0].config |= SDXC_IDMAC_DES0_FD;
346 pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER;
347 pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC;
348 pdes[i - 1].buf_addr_ptr2 = 0;
349
350 /*
351 * Avoid the io-store starting the idmac hitting io-mem before the
352 * descriptors hit the main-mem.
353 */
354 wmb();
355 }
356
357 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
358 {
359 if (data->flags & MMC_DATA_WRITE)
360 return DMA_TO_DEVICE;
361 else
362 return DMA_FROM_DEVICE;
363 }
364
365 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
366 struct mmc_data *data)
367 {
368 u32 i, dma_len;
369 struct scatterlist *sg;
370
371 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
372 sunxi_mmc_get_dma_dir(data));
373 if (dma_len == 0) {
374 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
375 return -ENOMEM;
376 }
377
378 for_each_sg(data->sg, sg, data->sg_len, i) {
379 if (sg->offset & 3 || sg->length & 3) {
380 dev_err(mmc_dev(host->mmc),
381 "unaligned scatterlist: os %x length %d\n",
382 sg->offset, sg->length);
383 return -EINVAL;
384 }
385 }
386
387 return 0;
388 }
389
390 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
391 struct mmc_data *data)
392 {
393 u32 rval;
394
395 sunxi_mmc_init_idma_des(host, data);
396
397 rval = mmc_readl(host, REG_GCTRL);
398 rval |= SDXC_DMA_ENABLE_BIT;
399 mmc_writel(host, REG_GCTRL, rval);
400 rval |= SDXC_DMA_RESET;
401 mmc_writel(host, REG_GCTRL, rval);
402
403 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
404
405 if (!(data->flags & MMC_DATA_WRITE))
406 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
407
408 mmc_writel(host, REG_DMAC,
409 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
410 }
411
412 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
413 struct mmc_request *req)
414 {
415 u32 arg, cmd_val, ri;
416 unsigned long expire = jiffies + msecs_to_jiffies(1000);
417
418 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
419 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
420
421 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
422 cmd_val |= SD_IO_RW_DIRECT;
423 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
424 ((req->cmd->arg >> 28) & 0x7);
425 } else {
426 cmd_val |= MMC_STOP_TRANSMISSION;
427 arg = 0;
428 }
429
430 mmc_writel(host, REG_CARG, arg);
431 mmc_writel(host, REG_CMDR, cmd_val);
432
433 do {
434 ri = mmc_readl(host, REG_RINTR);
435 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
436 time_before(jiffies, expire));
437
438 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
439 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
440 if (req->stop)
441 req->stop->resp[0] = -ETIMEDOUT;
442 } else {
443 if (req->stop)
444 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
445 }
446
447 mmc_writel(host, REG_RINTR, 0xffff);
448 }
449
450 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
451 {
452 struct mmc_command *cmd = host->mrq->cmd;
453 struct mmc_data *data = host->mrq->data;
454
455 /* For some cmds timeout is normal with sd/mmc cards */
456 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
457 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
458 cmd->opcode == SD_IO_RW_DIRECT))
459 return;
460
461 dev_err(mmc_dev(host->mmc),
462 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
463 host->mmc->index, cmd->opcode,
464 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
465 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
466 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
467 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
468 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
469 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
470 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
471 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
472 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
473 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
474 );
475 }
476
477 /* Called in interrupt context! */
478 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
479 {
480 struct mmc_request *mrq = host->mrq;
481 struct mmc_data *data = mrq->data;
482 u32 rval;
483
484 mmc_writel(host, REG_IMASK, host->sdio_imask);
485 mmc_writel(host, REG_IDIE, 0);
486
487 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
488 sunxi_mmc_dump_errinfo(host);
489 mrq->cmd->error = -ETIMEDOUT;
490
491 if (data) {
492 data->error = -ETIMEDOUT;
493 host->manual_stop_mrq = mrq;
494 }
495
496 if (mrq->stop)
497 mrq->stop->error = -ETIMEDOUT;
498 } else {
499 if (mrq->cmd->flags & MMC_RSP_136) {
500 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
501 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
502 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
503 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
504 } else {
505 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
506 }
507
508 if (data)
509 data->bytes_xfered = data->blocks * data->blksz;
510 }
511
512 if (data) {
513 mmc_writel(host, REG_IDST, 0x337);
514 mmc_writel(host, REG_DMAC, 0);
515 rval = mmc_readl(host, REG_GCTRL);
516 rval |= SDXC_DMA_RESET;
517 mmc_writel(host, REG_GCTRL, rval);
518 rval &= ~SDXC_DMA_ENABLE_BIT;
519 mmc_writel(host, REG_GCTRL, rval);
520 rval |= SDXC_FIFO_RESET;
521 mmc_writel(host, REG_GCTRL, rval);
522 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
523 sunxi_mmc_get_dma_dir(data));
524 }
525
526 mmc_writel(host, REG_RINTR, 0xffff);
527
528 host->mrq = NULL;
529 host->int_sum = 0;
530 host->wait_dma = false;
531
532 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
533 }
534
535 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
536 {
537 struct sunxi_mmc_host *host = dev_id;
538 struct mmc_request *mrq;
539 u32 msk_int, idma_int;
540 bool finalize = false;
541 bool sdio_int = false;
542 irqreturn_t ret = IRQ_HANDLED;
543
544 spin_lock(&host->lock);
545
546 idma_int = mmc_readl(host, REG_IDST);
547 msk_int = mmc_readl(host, REG_MISTA);
548
549 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
550 host->mrq, msk_int, idma_int);
551
552 mrq = host->mrq;
553 if (mrq) {
554 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
555 host->wait_dma = false;
556
557 host->int_sum |= msk_int;
558
559 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
560 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
561 !(host->int_sum & SDXC_COMMAND_DONE))
562 mmc_writel(host, REG_IMASK,
563 host->sdio_imask | SDXC_COMMAND_DONE);
564 /* Don't wait for dma on error */
565 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
566 finalize = true;
567 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
568 !host->wait_dma)
569 finalize = true;
570 }
571
572 if (msk_int & SDXC_SDIO_INTERRUPT)
573 sdio_int = true;
574
575 mmc_writel(host, REG_RINTR, msk_int);
576 mmc_writel(host, REG_IDST, idma_int);
577
578 if (finalize)
579 ret = sunxi_mmc_finalize_request(host);
580
581 spin_unlock(&host->lock);
582
583 if (finalize && ret == IRQ_HANDLED)
584 mmc_request_done(host->mmc, mrq);
585
586 if (sdio_int)
587 mmc_signal_sdio_irq(host->mmc);
588
589 return ret;
590 }
591
592 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
593 {
594 struct sunxi_mmc_host *host = dev_id;
595 struct mmc_request *mrq;
596 unsigned long iflags;
597
598 spin_lock_irqsave(&host->lock, iflags);
599 mrq = host->manual_stop_mrq;
600 spin_unlock_irqrestore(&host->lock, iflags);
601
602 if (!mrq) {
603 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
604 return IRQ_HANDLED;
605 }
606
607 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
608
609 /*
610 * We will never have more than one outstanding request,
611 * and we do not complete the request until after
612 * we've cleared host->manual_stop_mrq so we do not need to
613 * spin lock this function.
614 * Additionally we have wait states within this function
615 * so having it in a lock is a very bad idea.
616 */
617 sunxi_mmc_send_manual_stop(host, mrq);
618
619 spin_lock_irqsave(&host->lock, iflags);
620 host->manual_stop_mrq = NULL;
621 spin_unlock_irqrestore(&host->lock, iflags);
622
623 mmc_request_done(host->mmc, mrq);
624
625 return IRQ_HANDLED;
626 }
627
628 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
629 {
630 unsigned long expire = jiffies + msecs_to_jiffies(750);
631 u32 rval;
632
633 rval = mmc_readl(host, REG_CLKCR);
634 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
635
636 if (oclk_en)
637 rval |= SDXC_CARD_CLOCK_ON;
638
639 mmc_writel(host, REG_CLKCR, rval);
640
641 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
642 mmc_writel(host, REG_CMDR, rval);
643
644 do {
645 rval = mmc_readl(host, REG_CMDR);
646 } while (time_before(jiffies, expire) && (rval & SDXC_START));
647
648 /* clear irq status bits set by the command */
649 mmc_writel(host, REG_RINTR,
650 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
651
652 if (rval & SDXC_START) {
653 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
654 return -EIO;
655 }
656
657 return 0;
658 }
659
660 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
661 struct mmc_ios *ios, u32 rate)
662 {
663 int index;
664
665 if (!host->cfg->clk_delays)
666 return 0;
667
668 /* determine delays */
669 if (rate <= 400000) {
670 index = SDXC_CLK_400K;
671 } else if (rate <= 25000000) {
672 index = SDXC_CLK_25M;
673 } else if (rate <= 52000000) {
674 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
675 ios->timing != MMC_TIMING_MMC_DDR52) {
676 index = SDXC_CLK_50M;
677 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
678 index = SDXC_CLK_50M_DDR_8BIT;
679 } else {
680 index = SDXC_CLK_50M_DDR;
681 }
682 } else {
683 return -EINVAL;
684 }
685
686 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
687 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
688
689 return 0;
690 }
691
692 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
693 struct mmc_ios *ios)
694 {
695 long rate;
696 u32 rval, clock = ios->clock;
697 int ret;
698
699 /* 8 bit DDR requires a higher module clock */
700 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
701 ios->bus_width == MMC_BUS_WIDTH_8)
702 clock <<= 1;
703
704 rate = clk_round_rate(host->clk_mmc, clock);
705 if (rate < 0) {
706 dev_err(mmc_dev(host->mmc), "error rounding clk to %d: %ld\n",
707 clock, rate);
708 return rate;
709 }
710 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %ld\n",
711 clock, rate);
712
713 /* setting clock rate */
714 ret = clk_set_rate(host->clk_mmc, rate);
715 if (ret) {
716 dev_err(mmc_dev(host->mmc), "error setting clk to %ld: %d\n",
717 rate, ret);
718 return ret;
719 }
720
721 ret = sunxi_mmc_oclk_onoff(host, 0);
722 if (ret)
723 return ret;
724
725 /* clear internal divider */
726 rval = mmc_readl(host, REG_CLKCR);
727 rval &= ~0xff;
728 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
729 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
730 ios->bus_width == MMC_BUS_WIDTH_8) {
731 rval |= 1;
732 rate >>= 1;
733 }
734 mmc_writel(host, REG_CLKCR, rval);
735
736 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
737 if (ret)
738 return ret;
739
740 return sunxi_mmc_oclk_onoff(host, 1);
741 }
742
743 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
744 {
745 struct sunxi_mmc_host *host = mmc_priv(mmc);
746 u32 rval;
747
748 /* Set the power state */
749 switch (ios->power_mode) {
750 case MMC_POWER_ON:
751 break;
752
753 case MMC_POWER_UP:
754 host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
755 ios->vdd);
756 if (host->ferror)
757 return;
758
759 if (!IS_ERR(mmc->supply.vqmmc)) {
760 host->ferror = regulator_enable(mmc->supply.vqmmc);
761 if (host->ferror) {
762 dev_err(mmc_dev(mmc),
763 "failed to enable vqmmc\n");
764 return;
765 }
766 host->vqmmc_enabled = true;
767 }
768
769 host->ferror = sunxi_mmc_init_host(mmc);
770 if (host->ferror)
771 return;
772
773 dev_dbg(mmc_dev(mmc), "power on!\n");
774 break;
775
776 case MMC_POWER_OFF:
777 dev_dbg(mmc_dev(mmc), "power off!\n");
778 sunxi_mmc_reset_host(host);
779 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
780 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
781 regulator_disable(mmc->supply.vqmmc);
782 host->vqmmc_enabled = false;
783 break;
784 }
785
786 /* set bus width */
787 switch (ios->bus_width) {
788 case MMC_BUS_WIDTH_1:
789 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
790 break;
791 case MMC_BUS_WIDTH_4:
792 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
793 break;
794 case MMC_BUS_WIDTH_8:
795 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
796 break;
797 }
798
799 /* set ddr mode */
800 rval = mmc_readl(host, REG_GCTRL);
801 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
802 ios->timing == MMC_TIMING_MMC_DDR52)
803 rval |= SDXC_DDR_MODE;
804 else
805 rval &= ~SDXC_DDR_MODE;
806 mmc_writel(host, REG_GCTRL, rval);
807
808 /* set up clock */
809 if (ios->clock && ios->power_mode) {
810 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
811 /* Android code had a usleep_range(50000, 55000); here */
812 }
813 }
814
815 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
816 {
817 /* vqmmc regulator is available */
818 if (!IS_ERR(mmc->supply.vqmmc))
819 return mmc_regulator_set_vqmmc(mmc, ios);
820
821 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
822 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
823 return 0;
824
825 return -EINVAL;
826 }
827
828 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
829 {
830 struct sunxi_mmc_host *host = mmc_priv(mmc);
831 unsigned long flags;
832 u32 imask;
833
834 spin_lock_irqsave(&host->lock, flags);
835
836 imask = mmc_readl(host, REG_IMASK);
837 if (enable) {
838 host->sdio_imask = SDXC_SDIO_INTERRUPT;
839 imask |= SDXC_SDIO_INTERRUPT;
840 } else {
841 host->sdio_imask = 0;
842 imask &= ~SDXC_SDIO_INTERRUPT;
843 }
844 mmc_writel(host, REG_IMASK, imask);
845 spin_unlock_irqrestore(&host->lock, flags);
846 }
847
848 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
849 {
850 struct sunxi_mmc_host *host = mmc_priv(mmc);
851 mmc_writel(host, REG_HWRST, 0);
852 udelay(10);
853 mmc_writel(host, REG_HWRST, 1);
854 udelay(300);
855 }
856
857 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
858 {
859 struct sunxi_mmc_host *host = mmc_priv(mmc);
860 struct mmc_command *cmd = mrq->cmd;
861 struct mmc_data *data = mrq->data;
862 unsigned long iflags;
863 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
864 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
865 bool wait_dma = host->wait_dma;
866 int ret;
867
868 /* Check for set_ios errors (should never happen) */
869 if (host->ferror) {
870 mrq->cmd->error = host->ferror;
871 mmc_request_done(mmc, mrq);
872 return;
873 }
874
875 if (data) {
876 ret = sunxi_mmc_map_dma(host, data);
877 if (ret < 0) {
878 dev_err(mmc_dev(mmc), "map DMA failed\n");
879 cmd->error = ret;
880 data->error = ret;
881 mmc_request_done(mmc, mrq);
882 return;
883 }
884 }
885
886 if (cmd->opcode == MMC_GO_IDLE_STATE) {
887 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
888 imask |= SDXC_COMMAND_DONE;
889 }
890
891 if (cmd->flags & MMC_RSP_PRESENT) {
892 cmd_val |= SDXC_RESP_EXPIRE;
893 if (cmd->flags & MMC_RSP_136)
894 cmd_val |= SDXC_LONG_RESPONSE;
895 if (cmd->flags & MMC_RSP_CRC)
896 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
897
898 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
899 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
900
901 if (cmd->data->stop) {
902 imask |= SDXC_AUTO_COMMAND_DONE;
903 cmd_val |= SDXC_SEND_AUTO_STOP;
904 } else {
905 imask |= SDXC_DATA_OVER;
906 }
907
908 if (cmd->data->flags & MMC_DATA_WRITE)
909 cmd_val |= SDXC_WRITE;
910 else
911 wait_dma = true;
912 } else {
913 imask |= SDXC_COMMAND_DONE;
914 }
915 } else {
916 imask |= SDXC_COMMAND_DONE;
917 }
918
919 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
920 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
921 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
922
923 spin_lock_irqsave(&host->lock, iflags);
924
925 if (host->mrq || host->manual_stop_mrq) {
926 spin_unlock_irqrestore(&host->lock, iflags);
927
928 if (data)
929 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
930 sunxi_mmc_get_dma_dir(data));
931
932 dev_err(mmc_dev(mmc), "request already pending\n");
933 mrq->cmd->error = -EBUSY;
934 mmc_request_done(mmc, mrq);
935 return;
936 }
937
938 if (data) {
939 mmc_writel(host, REG_BLKSZ, data->blksz);
940 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
941 sunxi_mmc_start_dma(host, data);
942 }
943
944 host->mrq = mrq;
945 host->wait_dma = wait_dma;
946 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
947 mmc_writel(host, REG_CARG, cmd->arg);
948 mmc_writel(host, REG_CMDR, cmd_val);
949
950 spin_unlock_irqrestore(&host->lock, iflags);
951 }
952
953 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
954 {
955 struct sunxi_mmc_host *host = mmc_priv(mmc);
956
957 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
958 }
959
960 static struct mmc_host_ops sunxi_mmc_ops = {
961 .request = sunxi_mmc_request,
962 .set_ios = sunxi_mmc_set_ios,
963 .get_ro = mmc_gpio_get_ro,
964 .get_cd = mmc_gpio_get_cd,
965 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
966 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
967 .hw_reset = sunxi_mmc_hw_reset,
968 .card_busy = sunxi_mmc_card_busy,
969 };
970
971 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
972 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
973 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
974 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
975 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
976 /* Value from A83T "new timing mode". Works but might not be right. */
977 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
978 };
979
980 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
981 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
982 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
983 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
984 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
985 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
986 };
987
988 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
989 .idma_des_size_bits = 13,
990 .clk_delays = NULL,
991 };
992
993 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
994 .idma_des_size_bits = 16,
995 .clk_delays = NULL,
996 };
997
998 static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
999 .idma_des_size_bits = 16,
1000 .clk_delays = sunxi_mmc_clk_delays,
1001 };
1002
1003 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1004 .idma_des_size_bits = 16,
1005 .clk_delays = sun9i_mmc_clk_delays,
1006 };
1007
1008 static const struct of_device_id sunxi_mmc_of_match[] = {
1009 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1010 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
1011 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
1012 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
1013 { /* sentinel */ }
1014 };
1015 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1016
1017 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1018 struct platform_device *pdev)
1019 {
1020 int ret;
1021
1022 host->cfg = of_device_get_match_data(&pdev->dev);
1023 if (!host->cfg)
1024 return -EINVAL;
1025
1026 ret = mmc_regulator_get_supply(host->mmc);
1027 if (ret) {
1028 if (ret != -EPROBE_DEFER)
1029 dev_err(&pdev->dev, "Could not get vmmc supply\n");
1030 return ret;
1031 }
1032
1033 host->reg_base = devm_ioremap_resource(&pdev->dev,
1034 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1035 if (IS_ERR(host->reg_base))
1036 return PTR_ERR(host->reg_base);
1037
1038 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1039 if (IS_ERR(host->clk_ahb)) {
1040 dev_err(&pdev->dev, "Could not get ahb clock\n");
1041 return PTR_ERR(host->clk_ahb);
1042 }
1043
1044 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1045 if (IS_ERR(host->clk_mmc)) {
1046 dev_err(&pdev->dev, "Could not get mmc clock\n");
1047 return PTR_ERR(host->clk_mmc);
1048 }
1049
1050 if (host->cfg->clk_delays) {
1051 host->clk_output = devm_clk_get(&pdev->dev, "output");
1052 if (IS_ERR(host->clk_output)) {
1053 dev_err(&pdev->dev, "Could not get output clock\n");
1054 return PTR_ERR(host->clk_output);
1055 }
1056
1057 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1058 if (IS_ERR(host->clk_sample)) {
1059 dev_err(&pdev->dev, "Could not get sample clock\n");
1060 return PTR_ERR(host->clk_sample);
1061 }
1062 }
1063
1064 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1065 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1066 return PTR_ERR(host->reset);
1067
1068 ret = clk_prepare_enable(host->clk_ahb);
1069 if (ret) {
1070 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1071 return ret;
1072 }
1073
1074 ret = clk_prepare_enable(host->clk_mmc);
1075 if (ret) {
1076 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1077 goto error_disable_clk_ahb;
1078 }
1079
1080 ret = clk_prepare_enable(host->clk_output);
1081 if (ret) {
1082 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1083 goto error_disable_clk_mmc;
1084 }
1085
1086 ret = clk_prepare_enable(host->clk_sample);
1087 if (ret) {
1088 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1089 goto error_disable_clk_output;
1090 }
1091
1092 if (!IS_ERR(host->reset)) {
1093 ret = reset_control_deassert(host->reset);
1094 if (ret) {
1095 dev_err(&pdev->dev, "reset err %d\n", ret);
1096 goto error_disable_clk_sample;
1097 }
1098 }
1099
1100 /*
1101 * Sometimes the controller asserts the irq on boot for some reason,
1102 * make sure the controller is in a sane state before enabling irqs.
1103 */
1104 ret = sunxi_mmc_reset_host(host);
1105 if (ret)
1106 goto error_assert_reset;
1107
1108 host->irq = platform_get_irq(pdev, 0);
1109 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1110 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1111
1112 error_assert_reset:
1113 if (!IS_ERR(host->reset))
1114 reset_control_assert(host->reset);
1115 error_disable_clk_sample:
1116 clk_disable_unprepare(host->clk_sample);
1117 error_disable_clk_output:
1118 clk_disable_unprepare(host->clk_output);
1119 error_disable_clk_mmc:
1120 clk_disable_unprepare(host->clk_mmc);
1121 error_disable_clk_ahb:
1122 clk_disable_unprepare(host->clk_ahb);
1123 return ret;
1124 }
1125
1126 static int sunxi_mmc_probe(struct platform_device *pdev)
1127 {
1128 struct sunxi_mmc_host *host;
1129 struct mmc_host *mmc;
1130 int ret;
1131
1132 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1133 if (!mmc) {
1134 dev_err(&pdev->dev, "mmc alloc host failed\n");
1135 return -ENOMEM;
1136 }
1137
1138 host = mmc_priv(mmc);
1139 host->mmc = mmc;
1140 spin_lock_init(&host->lock);
1141
1142 ret = sunxi_mmc_resource_request(host, pdev);
1143 if (ret)
1144 goto error_free_host;
1145
1146 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1147 &host->sg_dma, GFP_KERNEL);
1148 if (!host->sg_cpu) {
1149 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1150 ret = -ENOMEM;
1151 goto error_free_host;
1152 }
1153
1154 mmc->ops = &sunxi_mmc_ops;
1155 mmc->max_blk_count = 8192;
1156 mmc->max_blk_size = 4096;
1157 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1158 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
1159 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1160 /* 400kHz ~ 52MHz */
1161 mmc->f_min = 400000;
1162 mmc->f_max = 52000000;
1163 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1164 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1165
1166 if (host->cfg->clk_delays)
1167 mmc->caps |= MMC_CAP_1_8V_DDR;
1168
1169 ret = mmc_of_parse(mmc);
1170 if (ret)
1171 goto error_free_dma;
1172
1173 ret = mmc_add_host(mmc);
1174 if (ret)
1175 goto error_free_dma;
1176
1177 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1178 platform_set_drvdata(pdev, mmc);
1179 return 0;
1180
1181 error_free_dma:
1182 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1183 error_free_host:
1184 mmc_free_host(mmc);
1185 return ret;
1186 }
1187
1188 static int sunxi_mmc_remove(struct platform_device *pdev)
1189 {
1190 struct mmc_host *mmc = platform_get_drvdata(pdev);
1191 struct sunxi_mmc_host *host = mmc_priv(mmc);
1192
1193 mmc_remove_host(mmc);
1194 disable_irq(host->irq);
1195 sunxi_mmc_reset_host(host);
1196
1197 if (!IS_ERR(host->reset))
1198 reset_control_assert(host->reset);
1199
1200 clk_disable_unprepare(host->clk_sample);
1201 clk_disable_unprepare(host->clk_output);
1202 clk_disable_unprepare(host->clk_mmc);
1203 clk_disable_unprepare(host->clk_ahb);
1204
1205 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1206 mmc_free_host(mmc);
1207
1208 return 0;
1209 }
1210
1211 static struct platform_driver sunxi_mmc_driver = {
1212 .driver = {
1213 .name = "sunxi-mmc",
1214 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1215 },
1216 .probe = sunxi_mmc_probe,
1217 .remove = sunxi_mmc_remove,
1218 };
1219 module_platform_driver(sunxi_mmc_driver);
1220
1221 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1222 MODULE_LICENSE("GPL v2");
1223 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1224 MODULE_ALIAS("platform:sunxi-mmc");
Linux kernel - Deliverables
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