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[deliverable/linux.git] / drivers / mtd / devices / m25p80.c
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37
38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
47 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
48 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
49 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
50
51 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
52 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
53 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
54 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
55 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
56
57 /* Used for SST flashes only. */
58 #define OPCODE_BP 0x02 /* Byte program */
59 #define OPCODE_WRDI 0x04 /* Write disable */
60 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
61
62 /* Used for Macronix and Winbond flashes. */
63 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
64 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
65
66 /* Used for Spansion flashes only. */
67 #define OPCODE_BRWR 0x17 /* Bank register write */
68
69 /* Status Register bits. */
70 #define SR_WIP 1 /* Write in progress */
71 #define SR_WEL 2 /* Write enable latch */
72 /* meaning of other SR_* bits may differ between vendors */
73 #define SR_BP0 4 /* Block protect 0 */
74 #define SR_BP1 8 /* Block protect 1 */
75 #define SR_BP2 0x10 /* Block protect 2 */
76 #define SR_SRWD 0x80 /* SR write protect */
77
78 /* Define max times to check status register before we give up. */
79 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
80 #define MAX_CMD_SIZE 5
81
82 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
83
84 /****************************************************************************/
85
86 struct m25p {
87 struct spi_device *spi;
88 struct mutex lock;
89 struct mtd_info mtd;
90 u16 page_size;
91 u16 addr_width;
92 u8 erase_opcode;
93 u8 read_opcode;
94 u8 program_opcode;
95 u8 *command;
96 bool fast_read;
97 };
98
99 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
100 {
101 return container_of(mtd, struct m25p, mtd);
102 }
103
104 /****************************************************************************/
105
106 /*
107 * Internal helper functions
108 */
109
110 /*
111 * Read the status register, returning its value in the location
112 * Return the status register value.
113 * Returns negative if error occurred.
114 */
115 static int read_sr(struct m25p *flash)
116 {
117 ssize_t retval;
118 u8 code = OPCODE_RDSR;
119 u8 val;
120
121 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
122
123 if (retval < 0) {
124 dev_err(&flash->spi->dev, "error %d reading SR\n",
125 (int) retval);
126 return retval;
127 }
128
129 return val;
130 }
131
132 /*
133 * Write status register 1 byte
134 * Returns negative if error occurred.
135 */
136 static int write_sr(struct m25p *flash, u8 val)
137 {
138 flash->command[0] = OPCODE_WRSR;
139 flash->command[1] = val;
140
141 return spi_write(flash->spi, flash->command, 2);
142 }
143
144 /*
145 * Set write enable latch with Write Enable command.
146 * Returns negative if error occurred.
147 */
148 static inline int write_enable(struct m25p *flash)
149 {
150 u8 code = OPCODE_WREN;
151
152 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
153 }
154
155 /*
156 * Send write disble instruction to the chip.
157 */
158 static inline int write_disable(struct m25p *flash)
159 {
160 u8 code = OPCODE_WRDI;
161
162 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
163 }
164
165 /*
166 * Enable/disable 4-byte addressing mode.
167 */
168 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
169 {
170 switch (JEDEC_MFR(jedec_id)) {
171 case CFI_MFR_MACRONIX:
172 case CFI_MFR_ST: /* Micron, actually */
173 case 0xEF /* winbond */:
174 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
175 return spi_write(flash->spi, flash->command, 1);
176 default:
177 /* Spansion style */
178 flash->command[0] = OPCODE_BRWR;
179 flash->command[1] = enable << 7;
180 return spi_write(flash->spi, flash->command, 2);
181 }
182 }
183
184 /*
185 * Service routine to read status register until ready, or timeout occurs.
186 * Returns non-zero if error.
187 */
188 static int wait_till_ready(struct m25p *flash)
189 {
190 unsigned long deadline;
191 int sr;
192
193 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
194
195 do {
196 if ((sr = read_sr(flash)) < 0)
197 break;
198 else if (!(sr & SR_WIP))
199 return 0;
200
201 cond_resched();
202
203 } while (!time_after_eq(jiffies, deadline));
204
205 return 1;
206 }
207
208 /*
209 * Erase the whole flash memory
210 *
211 * Returns 0 if successful, non-zero otherwise.
212 */
213 static int erase_chip(struct m25p *flash)
214 {
215 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
216 (long long)(flash->mtd.size >> 10));
217
218 /* Wait until finished previous write command. */
219 if (wait_till_ready(flash))
220 return 1;
221
222 /* Send write enable, then erase commands. */
223 write_enable(flash);
224
225 /* Set up command buffer. */
226 flash->command[0] = OPCODE_CHIP_ERASE;
227
228 spi_write(flash->spi, flash->command, 1);
229
230 return 0;
231 }
232
233 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
234 {
235 /* opcode is in cmd[0] */
236 cmd[1] = addr >> (flash->addr_width * 8 - 8);
237 cmd[2] = addr >> (flash->addr_width * 8 - 16);
238 cmd[3] = addr >> (flash->addr_width * 8 - 24);
239 cmd[4] = addr >> (flash->addr_width * 8 - 32);
240 }
241
242 static int m25p_cmdsz(struct m25p *flash)
243 {
244 return 1 + flash->addr_width;
245 }
246
247 /*
248 * Erase one sector of flash memory at offset ``offset'' which is any
249 * address within the sector which should be erased.
250 *
251 * Returns 0 if successful, non-zero otherwise.
252 */
253 static int erase_sector(struct m25p *flash, u32 offset)
254 {
255 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
256 __func__, flash->mtd.erasesize / 1024, offset);
257
258 /* Wait until finished previous write command. */
259 if (wait_till_ready(flash))
260 return 1;
261
262 /* Send write enable, then erase commands. */
263 write_enable(flash);
264
265 /* Set up command buffer. */
266 flash->command[0] = flash->erase_opcode;
267 m25p_addr2cmd(flash, offset, flash->command);
268
269 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
270
271 return 0;
272 }
273
274 /****************************************************************************/
275
276 /*
277 * MTD implementation
278 */
279
280 /*
281 * Erase an address range on the flash chip. The address range may extend
282 * one or more erase sectors. Return an error is there is a problem erasing.
283 */
284 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
285 {
286 struct m25p *flash = mtd_to_m25p(mtd);
287 u32 addr,len;
288 uint32_t rem;
289
290 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
291 __func__, (long long)instr->addr,
292 (long long)instr->len);
293
294 div_u64_rem(instr->len, mtd->erasesize, &rem);
295 if (rem)
296 return -EINVAL;
297
298 addr = instr->addr;
299 len = instr->len;
300
301 mutex_lock(&flash->lock);
302
303 /* whole-chip erase? */
304 if (len == flash->mtd.size) {
305 if (erase_chip(flash)) {
306 instr->state = MTD_ERASE_FAILED;
307 mutex_unlock(&flash->lock);
308 return -EIO;
309 }
310
311 /* REVISIT in some cases we could speed up erasing large regions
312 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
313 * to use "small sector erase", but that's not always optimal.
314 */
315
316 /* "sector"-at-a-time erase */
317 } else {
318 while (len) {
319 if (erase_sector(flash, addr)) {
320 instr->state = MTD_ERASE_FAILED;
321 mutex_unlock(&flash->lock);
322 return -EIO;
323 }
324
325 addr += mtd->erasesize;
326 len -= mtd->erasesize;
327 }
328 }
329
330 mutex_unlock(&flash->lock);
331
332 instr->state = MTD_ERASE_DONE;
333 mtd_erase_callback(instr);
334
335 return 0;
336 }
337
338 /*
339 * Read an address range from the flash chip. The address range
340 * may be any size provided it is within the physical boundaries.
341 */
342 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
343 size_t *retlen, u_char *buf)
344 {
345 struct m25p *flash = mtd_to_m25p(mtd);
346 struct spi_transfer t[2];
347 struct spi_message m;
348 uint8_t opcode;
349
350 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
351 __func__, (u32)from, len);
352
353 spi_message_init(&m);
354 memset(t, 0, (sizeof t));
355
356 /* NOTE:
357 * OPCODE_FAST_READ (if available) is faster.
358 * Should add 1 byte DUMMY_BYTE.
359 */
360 t[0].tx_buf = flash->command;
361 t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
362 spi_message_add_tail(&t[0], &m);
363
364 t[1].rx_buf = buf;
365 t[1].len = len;
366 spi_message_add_tail(&t[1], &m);
367
368 mutex_lock(&flash->lock);
369
370 /* Wait till previous write/erase is done. */
371 if (wait_till_ready(flash)) {
372 /* REVISIT status return?? */
373 mutex_unlock(&flash->lock);
374 return 1;
375 }
376
377 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
378 * clocks; and at this writing, every chip this driver handles
379 * supports that opcode.
380 */
381
382 /* Set up the write data buffer. */
383 opcode = flash->read_opcode;
384 flash->command[0] = opcode;
385 m25p_addr2cmd(flash, from, flash->command);
386
387 spi_sync(flash->spi, &m);
388
389 *retlen = m.actual_length - m25p_cmdsz(flash) -
390 (flash->fast_read ? 1 : 0);
391
392 mutex_unlock(&flash->lock);
393
394 return 0;
395 }
396
397 /*
398 * Write an address range to the flash chip. Data must be written in
399 * FLASH_PAGESIZE chunks. The address range may be any size provided
400 * it is within the physical boundaries.
401 */
402 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
403 size_t *retlen, const u_char *buf)
404 {
405 struct m25p *flash = mtd_to_m25p(mtd);
406 u32 page_offset, page_size;
407 struct spi_transfer t[2];
408 struct spi_message m;
409
410 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
411 __func__, (u32)to, len);
412
413 spi_message_init(&m);
414 memset(t, 0, (sizeof t));
415
416 t[0].tx_buf = flash->command;
417 t[0].len = m25p_cmdsz(flash);
418 spi_message_add_tail(&t[0], &m);
419
420 t[1].tx_buf = buf;
421 spi_message_add_tail(&t[1], &m);
422
423 mutex_lock(&flash->lock);
424
425 /* Wait until finished previous write command. */
426 if (wait_till_ready(flash)) {
427 mutex_unlock(&flash->lock);
428 return 1;
429 }
430
431 write_enable(flash);
432
433 /* Set up the opcode in the write buffer. */
434 flash->command[0] = flash->program_opcode;
435 m25p_addr2cmd(flash, to, flash->command);
436
437 page_offset = to & (flash->page_size - 1);
438
439 /* do all the bytes fit onto one page? */
440 if (page_offset + len <= flash->page_size) {
441 t[1].len = len;
442
443 spi_sync(flash->spi, &m);
444
445 *retlen = m.actual_length - m25p_cmdsz(flash);
446 } else {
447 u32 i;
448
449 /* the size of data remaining on the first page */
450 page_size = flash->page_size - page_offset;
451
452 t[1].len = page_size;
453 spi_sync(flash->spi, &m);
454
455 *retlen = m.actual_length - m25p_cmdsz(flash);
456
457 /* write everything in flash->page_size chunks */
458 for (i = page_size; i < len; i += page_size) {
459 page_size = len - i;
460 if (page_size > flash->page_size)
461 page_size = flash->page_size;
462
463 /* write the next page to flash */
464 m25p_addr2cmd(flash, to + i, flash->command);
465
466 t[1].tx_buf = buf + i;
467 t[1].len = page_size;
468
469 wait_till_ready(flash);
470
471 write_enable(flash);
472
473 spi_sync(flash->spi, &m);
474
475 *retlen += m.actual_length - m25p_cmdsz(flash);
476 }
477 }
478
479 mutex_unlock(&flash->lock);
480
481 return 0;
482 }
483
484 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
485 size_t *retlen, const u_char *buf)
486 {
487 struct m25p *flash = mtd_to_m25p(mtd);
488 struct spi_transfer t[2];
489 struct spi_message m;
490 size_t actual;
491 int cmd_sz, ret;
492
493 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
494 __func__, (u32)to, len);
495
496 spi_message_init(&m);
497 memset(t, 0, (sizeof t));
498
499 t[0].tx_buf = flash->command;
500 t[0].len = m25p_cmdsz(flash);
501 spi_message_add_tail(&t[0], &m);
502
503 t[1].tx_buf = buf;
504 spi_message_add_tail(&t[1], &m);
505
506 mutex_lock(&flash->lock);
507
508 /* Wait until finished previous write command. */
509 ret = wait_till_ready(flash);
510 if (ret)
511 goto time_out;
512
513 write_enable(flash);
514
515 actual = to % 2;
516 /* Start write from odd address. */
517 if (actual) {
518 flash->command[0] = OPCODE_BP;
519 m25p_addr2cmd(flash, to, flash->command);
520
521 /* write one byte. */
522 t[1].len = 1;
523 spi_sync(flash->spi, &m);
524 ret = wait_till_ready(flash);
525 if (ret)
526 goto time_out;
527 *retlen += m.actual_length - m25p_cmdsz(flash);
528 }
529 to += actual;
530
531 flash->command[0] = OPCODE_AAI_WP;
532 m25p_addr2cmd(flash, to, flash->command);
533
534 /* Write out most of the data here. */
535 cmd_sz = m25p_cmdsz(flash);
536 for (; actual < len - 1; actual += 2) {
537 t[0].len = cmd_sz;
538 /* write two bytes. */
539 t[1].len = 2;
540 t[1].tx_buf = buf + actual;
541
542 spi_sync(flash->spi, &m);
543 ret = wait_till_ready(flash);
544 if (ret)
545 goto time_out;
546 *retlen += m.actual_length - cmd_sz;
547 cmd_sz = 1;
548 to += 2;
549 }
550 write_disable(flash);
551 ret = wait_till_ready(flash);
552 if (ret)
553 goto time_out;
554
555 /* Write out trailing byte if it exists. */
556 if (actual != len) {
557 write_enable(flash);
558 flash->command[0] = OPCODE_BP;
559 m25p_addr2cmd(flash, to, flash->command);
560 t[0].len = m25p_cmdsz(flash);
561 t[1].len = 1;
562 t[1].tx_buf = buf + actual;
563
564 spi_sync(flash->spi, &m);
565 ret = wait_till_ready(flash);
566 if (ret)
567 goto time_out;
568 *retlen += m.actual_length - m25p_cmdsz(flash);
569 write_disable(flash);
570 }
571
572 time_out:
573 mutex_unlock(&flash->lock);
574 return ret;
575 }
576
577 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
578 {
579 struct m25p *flash = mtd_to_m25p(mtd);
580 uint32_t offset = ofs;
581 uint8_t status_old, status_new;
582 int res = 0;
583
584 mutex_lock(&flash->lock);
585 /* Wait until finished previous command */
586 if (wait_till_ready(flash)) {
587 res = 1;
588 goto err;
589 }
590
591 status_old = read_sr(flash);
592
593 if (offset < flash->mtd.size-(flash->mtd.size/2))
594 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
595 else if (offset < flash->mtd.size-(flash->mtd.size/4))
596 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
597 else if (offset < flash->mtd.size-(flash->mtd.size/8))
598 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
599 else if (offset < flash->mtd.size-(flash->mtd.size/16))
600 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
601 else if (offset < flash->mtd.size-(flash->mtd.size/32))
602 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
603 else if (offset < flash->mtd.size-(flash->mtd.size/64))
604 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
605 else
606 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
607
608 /* Only modify protection if it will not unlock other areas */
609 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
610 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
611 write_enable(flash);
612 if (write_sr(flash, status_new) < 0) {
613 res = 1;
614 goto err;
615 }
616 }
617
618 err: mutex_unlock(&flash->lock);
619 return res;
620 }
621
622 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
623 {
624 struct m25p *flash = mtd_to_m25p(mtd);
625 uint32_t offset = ofs;
626 uint8_t status_old, status_new;
627 int res = 0;
628
629 mutex_lock(&flash->lock);
630 /* Wait until finished previous command */
631 if (wait_till_ready(flash)) {
632 res = 1;
633 goto err;
634 }
635
636 status_old = read_sr(flash);
637
638 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
639 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
640 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
641 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
642 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
643 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
644 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
645 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
646 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
647 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
648 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
649 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
650 else
651 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
652
653 /* Only modify protection if it will not lock other areas */
654 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
655 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
656 write_enable(flash);
657 if (write_sr(flash, status_new) < 0) {
658 res = 1;
659 goto err;
660 }
661 }
662
663 err: mutex_unlock(&flash->lock);
664 return res;
665 }
666
667 /****************************************************************************/
668
669 /*
670 * SPI device driver setup and teardown
671 */
672
673 struct flash_info {
674 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
675 * a high byte of zero plus three data bytes: the manufacturer id,
676 * then a two byte device id.
677 */
678 u32 jedec_id;
679 u16 ext_id;
680
681 /* The size listed here is what works with OPCODE_SE, which isn't
682 * necessarily called a "sector" by the vendor.
683 */
684 unsigned sector_size;
685 u16 n_sectors;
686
687 u16 page_size;
688 u16 addr_width;
689
690 u16 flags;
691 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
692 #define M25P_NO_ERASE 0x02 /* No erase command needed */
693 #define SST_WRITE 0x04 /* use SST byte programming */
694 };
695
696 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
697 ((kernel_ulong_t)&(struct flash_info) { \
698 .jedec_id = (_jedec_id), \
699 .ext_id = (_ext_id), \
700 .sector_size = (_sector_size), \
701 .n_sectors = (_n_sectors), \
702 .page_size = 256, \
703 .flags = (_flags), \
704 })
705
706 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
707 ((kernel_ulong_t)&(struct flash_info) { \
708 .sector_size = (_sector_size), \
709 .n_sectors = (_n_sectors), \
710 .page_size = (_page_size), \
711 .addr_width = (_addr_width), \
712 .flags = M25P_NO_ERASE, \
713 })
714
715 /* NOTE: double check command sets and memory organization when you add
716 * more flash chips. This current list focusses on newer chips, which
717 * have been converging on command sets which including JEDEC ID.
718 */
719 static const struct spi_device_id m25p_ids[] = {
720 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
721 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
722 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
723
724 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
725 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
726 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
727
728 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
729 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
730 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
731 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
732
733 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
734
735 /* EON -- en25xxx */
736 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
737 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
738 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
739 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
740 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
741 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
742
743 /* Everspin */
744 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2) },
745
746 /* GigaDevice */
747 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
748 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
749
750 /* Intel/Numonyx -- xxxs33b */
751 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
752 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
753 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
754
755 /* Macronix */
756 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
757 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
758 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
759 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
760 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
761 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
762 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
763 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
764 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
765 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
766 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
767
768 /* Micron */
769 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
770 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
771 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
772 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
773
774 /* Spansion -- single (large) sector size only, at least
775 * for the chips listed here (without boot sectors).
776 */
777 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
778 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
779 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
780 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
781 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
782 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
783 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
784 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
785 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
786 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
787 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
788 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
789 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
790 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
791 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
792 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
793 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
794
795 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
796 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
797 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
798 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
799 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
800 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
801 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
802 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
803 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
804 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
805
806 /* ST Microelectronics -- newer production may have feature updates */
807 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
808 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
809 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
810 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
811 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
812 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
813 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
814 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
815 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
816 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
817
818 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
819 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
820 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
821 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
822 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
823 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
824 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
825 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
826 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
827
828 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
829 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
830 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
831
832 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
833 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
834 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
835
836 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
837 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
838 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
839 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
840
841 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
842 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
843 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
844 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
845 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
846 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
847 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
848 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
849 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
850 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
851 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
852 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
853 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
854 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
855 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
856 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
857
858 /* Catalyst / On Semiconductor -- non-JEDEC */
859 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
860 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
861 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
862 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
863 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
864 { },
865 };
866 MODULE_DEVICE_TABLE(spi, m25p_ids);
867
868 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
869 {
870 int tmp;
871 u8 code = OPCODE_RDID;
872 u8 id[5];
873 u32 jedec;
874 u16 ext_jedec;
875 struct flash_info *info;
876
877 /* JEDEC also defines an optional "extended device information"
878 * string for after vendor-specific data, after the three bytes
879 * we use here. Supporting some chips might require using it.
880 */
881 tmp = spi_write_then_read(spi, &code, 1, id, 5);
882 if (tmp < 0) {
883 pr_debug("%s: error %d reading JEDEC ID\n",
884 dev_name(&spi->dev), tmp);
885 return ERR_PTR(tmp);
886 }
887 jedec = id[0];
888 jedec = jedec << 8;
889 jedec |= id[1];
890 jedec = jedec << 8;
891 jedec |= id[2];
892
893 ext_jedec = id[3] << 8 | id[4];
894
895 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
896 info = (void *)m25p_ids[tmp].driver_data;
897 if (info->jedec_id == jedec) {
898 if (info->ext_id != 0 && info->ext_id != ext_jedec)
899 continue;
900 return &m25p_ids[tmp];
901 }
902 }
903 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
904 return ERR_PTR(-ENODEV);
905 }
906
907
908 /*
909 * board specific setup should have ensured the SPI clock used here
910 * matches what the READ command supports, at least until this driver
911 * understands FAST_READ (for clocks over 25 MHz).
912 */
913 static int m25p_probe(struct spi_device *spi)
914 {
915 const struct spi_device_id *id = spi_get_device_id(spi);
916 struct flash_platform_data *data;
917 struct m25p *flash;
918 struct flash_info *info;
919 unsigned i;
920 struct mtd_part_parser_data ppdata;
921 struct device_node __maybe_unused *np = spi->dev.of_node;
922
923 #ifdef CONFIG_MTD_OF_PARTS
924 if (!of_device_is_available(np))
925 return -ENODEV;
926 #endif
927
928 /* Platform data helps sort out which chip type we have, as
929 * well as how this board partitions it. If we don't have
930 * a chip ID, try the JEDEC id commands; they'll work for most
931 * newer chips, even if we don't recognize the particular chip.
932 */
933 data = dev_get_platdata(&spi->dev);
934 if (data && data->type) {
935 const struct spi_device_id *plat_id;
936
937 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
938 plat_id = &m25p_ids[i];
939 if (strcmp(data->type, plat_id->name))
940 continue;
941 break;
942 }
943
944 if (i < ARRAY_SIZE(m25p_ids) - 1)
945 id = plat_id;
946 else
947 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
948 }
949
950 info = (void *)id->driver_data;
951
952 if (info->jedec_id) {
953 const struct spi_device_id *jid;
954
955 jid = jedec_probe(spi);
956 if (IS_ERR(jid)) {
957 return PTR_ERR(jid);
958 } else if (jid != id) {
959 /*
960 * JEDEC knows better, so overwrite platform ID. We
961 * can't trust partitions any longer, but we'll let
962 * mtd apply them anyway, since some partitions may be
963 * marked read-only, and we don't want to lose that
964 * information, even if it's not 100% accurate.
965 */
966 dev_warn(&spi->dev, "found %s, expected %s\n",
967 jid->name, id->name);
968 id = jid;
969 info = (void *)jid->driver_data;
970 }
971 }
972
973 flash = kzalloc(sizeof *flash, GFP_KERNEL);
974 if (!flash)
975 return -ENOMEM;
976 flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0),
977 GFP_KERNEL);
978 if (!flash->command) {
979 kfree(flash);
980 return -ENOMEM;
981 }
982
983 flash->spi = spi;
984 mutex_init(&flash->lock);
985 spi_set_drvdata(spi, flash);
986
987 /*
988 * Atmel, SST and Intel/Numonyx serial flash tend to power
989 * up with the software protection bits set
990 */
991
992 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
993 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
994 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
995 write_enable(flash);
996 write_sr(flash, 0);
997 }
998
999 if (data && data->name)
1000 flash->mtd.name = data->name;
1001 else
1002 flash->mtd.name = dev_name(&spi->dev);
1003
1004 flash->mtd.type = MTD_NORFLASH;
1005 flash->mtd.writesize = 1;
1006 flash->mtd.flags = MTD_CAP_NORFLASH;
1007 flash->mtd.size = info->sector_size * info->n_sectors;
1008 flash->mtd._erase = m25p80_erase;
1009 flash->mtd._read = m25p80_read;
1010
1011 /* flash protection support for STmicro chips */
1012 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1013 flash->mtd._lock = m25p80_lock;
1014 flash->mtd._unlock = m25p80_unlock;
1015 }
1016
1017 /* sst flash chips use AAI word program */
1018 if (info->flags & SST_WRITE)
1019 flash->mtd._write = sst_write;
1020 else
1021 flash->mtd._write = m25p80_write;
1022
1023 /* prefer "small sector" erase if possible */
1024 if (info->flags & SECT_4K) {
1025 flash->erase_opcode = OPCODE_BE_4K;
1026 flash->mtd.erasesize = 4096;
1027 } else {
1028 flash->erase_opcode = OPCODE_SE;
1029 flash->mtd.erasesize = info->sector_size;
1030 }
1031
1032 if (info->flags & M25P_NO_ERASE)
1033 flash->mtd.flags |= MTD_NO_ERASE;
1034
1035 ppdata.of_node = spi->dev.of_node;
1036 flash->mtd.dev.parent = &spi->dev;
1037 flash->page_size = info->page_size;
1038 flash->mtd.writebufsize = flash->page_size;
1039
1040 flash->fast_read = false;
1041 if (np && of_property_read_bool(np, "m25p,fast-read"))
1042 flash->fast_read = true;
1043
1044 #ifdef CONFIG_M25PXX_USE_FAST_READ
1045 flash->fast_read = true;
1046 #endif
1047
1048 /* Default commands */
1049 if (flash->fast_read)
1050 flash->read_opcode = OPCODE_FAST_READ;
1051 else
1052 flash->read_opcode = OPCODE_NORM_READ;
1053
1054 flash->program_opcode = OPCODE_PP;
1055
1056 if (info->addr_width)
1057 flash->addr_width = info->addr_width;
1058 else if (flash->mtd.size > 0x1000000) {
1059 /* enable 4-byte addressing if the device exceeds 16MiB */
1060 flash->addr_width = 4;
1061 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1062 /* Dedicated 4-byte command set */
1063 flash->read_opcode = flash->fast_read ?
1064 OPCODE_FAST_READ_4B :
1065 OPCODE_NORM_READ_4B;
1066 flash->program_opcode = OPCODE_PP_4B;
1067 /* No small sector erase for 4-byte command set */
1068 flash->erase_opcode = OPCODE_SE_4B;
1069 flash->mtd.erasesize = info->sector_size;
1070 } else
1071 set_4byte(flash, info->jedec_id, 1);
1072 } else {
1073 flash->addr_width = 3;
1074 }
1075
1076 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1077 (long long)flash->mtd.size >> 10);
1078
1079 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1080 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1081 flash->mtd.name,
1082 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1083 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1084 flash->mtd.numeraseregions);
1085
1086 if (flash->mtd.numeraseregions)
1087 for (i = 0; i < flash->mtd.numeraseregions; i++)
1088 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1089 ".erasesize = 0x%.8x (%uKiB), "
1090 ".numblocks = %d }\n",
1091 i, (long long)flash->mtd.eraseregions[i].offset,
1092 flash->mtd.eraseregions[i].erasesize,
1093 flash->mtd.eraseregions[i].erasesize / 1024,
1094 flash->mtd.eraseregions[i].numblocks);
1095
1096
1097 /* partitions should match sector boundaries; and it may be good to
1098 * use readonly partitions for writeprotected sectors (BP2..BP0).
1099 */
1100 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1101 data ? data->parts : NULL,
1102 data ? data->nr_parts : 0);
1103 }
1104
1105
1106 static int m25p_remove(struct spi_device *spi)
1107 {
1108 struct m25p *flash = spi_get_drvdata(spi);
1109 int status;
1110
1111 /* Clean up MTD stuff. */
1112 status = mtd_device_unregister(&flash->mtd);
1113 if (status == 0) {
1114 kfree(flash->command);
1115 kfree(flash);
1116 }
1117 return 0;
1118 }
1119
1120
1121 static struct spi_driver m25p80_driver = {
1122 .driver = {
1123 .name = "m25p80",
1124 .owner = THIS_MODULE,
1125 },
1126 .id_table = m25p_ids,
1127 .probe = m25p_probe,
1128 .remove = m25p_remove,
1129
1130 /* REVISIT: many of these chips have deep power-down modes, which
1131 * should clearly be entered on suspend() to minimize power use.
1132 * And also when they're otherwise idle...
1133 */
1134 };
1135
1136 module_spi_driver(m25p80_driver);
1137
1138 MODULE_LICENSE("GPL");
1139 MODULE_AUTHOR("Mike Lavender");
1140 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
Linux kernel - Deliverables
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