2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
4 * Author: Mike Lavender, mike@steroidmicros.com
6 * Copyright (c) 2005, Intec Automation Inc.
8 * Some parts are based on lart.c by Abraham Van Der Merwe
10 * Cleaned up and generalized based on mtd_dataflash.c
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/partitions.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/flash.h>
37 #define OPCODE_WREN 0x06 /* Write enable */
38 #define OPCODE_RDSR 0x05 /* Read status register */
39 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
40 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
41 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
42 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
43 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
44 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
45 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
46 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
47 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
49 /* Used for SST flashes only. */
50 #define OPCODE_BP 0x02 /* Byte program */
51 #define OPCODE_WRDI 0x04 /* Write disable */
52 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
54 /* Status Register bits. */
55 #define SR_WIP 1 /* Write in progress */
56 #define SR_WEL 2 /* Write enable latch */
57 /* meaning of other SR_* bits may differ between vendors */
58 #define SR_BP0 4 /* Block protect 0 */
59 #define SR_BP1 8 /* Block protect 1 */
60 #define SR_BP2 0x10 /* Block protect 2 */
61 #define SR_SRWD 0x80 /* SR write protect */
63 /* Define max times to check status register before we give up. */
64 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
65 #define MAX_CMD_SIZE 4
67 #ifdef CONFIG_M25PXX_USE_FAST_READ
68 #define OPCODE_READ OPCODE_FAST_READ
69 #define FAST_READ_DUMMY_BYTE 1
71 #define OPCODE_READ OPCODE_NORM_READ
72 #define FAST_READ_DUMMY_BYTE 0
75 /****************************************************************************/
78 struct spi_device
*spi
;
81 unsigned partitioned
:1;
88 static inline struct m25p
*mtd_to_m25p(struct mtd_info
*mtd
)
90 return container_of(mtd
, struct m25p
, mtd
);
93 /****************************************************************************/
96 * Internal helper functions
100 * Read the status register, returning its value in the location
101 * Return the status register value.
102 * Returns negative if error occurred.
104 static int read_sr(struct m25p
*flash
)
107 u8 code
= OPCODE_RDSR
;
110 retval
= spi_write_then_read(flash
->spi
, &code
, 1, &val
, 1);
113 dev_err(&flash
->spi
->dev
, "error %d reading SR\n",
122 * Write status register 1 byte
123 * Returns negative if error occurred.
125 static int write_sr(struct m25p
*flash
, u8 val
)
127 flash
->command
[0] = OPCODE_WRSR
;
128 flash
->command
[1] = val
;
130 return spi_write(flash
->spi
, flash
->command
, 2);
134 * Set write enable latch with Write Enable command.
135 * Returns negative if error occurred.
137 static inline int write_enable(struct m25p
*flash
)
139 u8 code
= OPCODE_WREN
;
141 return spi_write_then_read(flash
->spi
, &code
, 1, NULL
, 0);
145 * Send write disble instruction to the chip.
147 static inline int write_disable(struct m25p
*flash
)
149 u8 code
= OPCODE_WRDI
;
151 return spi_write_then_read(flash
->spi
, &code
, 1, NULL
, 0);
155 * Service routine to read status register until ready, or timeout occurs.
156 * Returns non-zero if error.
158 static int wait_till_ready(struct m25p
*flash
)
160 unsigned long deadline
;
163 deadline
= jiffies
+ MAX_READY_WAIT_JIFFIES
;
166 if ((sr
= read_sr(flash
)) < 0)
168 else if (!(sr
& SR_WIP
))
173 } while (!time_after_eq(jiffies
, deadline
));
179 * Erase the whole flash memory
181 * Returns 0 if successful, non-zero otherwise.
183 static int erase_chip(struct m25p
*flash
)
185 DEBUG(MTD_DEBUG_LEVEL3
, "%s: %s %lldKiB\n",
186 dev_name(&flash
->spi
->dev
), __func__
,
187 (long long)(flash
->mtd
.size
>> 10));
189 /* Wait until finished previous write command. */
190 if (wait_till_ready(flash
))
193 /* Send write enable, then erase commands. */
196 /* Set up command buffer. */
197 flash
->command
[0] = OPCODE_CHIP_ERASE
;
199 spi_write(flash
->spi
, flash
->command
, 1);
204 static void m25p_addr2cmd(struct m25p
*flash
, unsigned int addr
, u8
*cmd
)
206 /* opcode is in cmd[0] */
207 cmd
[1] = addr
>> (flash
->addr_width
* 8 - 8);
208 cmd
[2] = addr
>> (flash
->addr_width
* 8 - 16);
209 cmd
[3] = addr
>> (flash
->addr_width
* 8 - 24);
212 static int m25p_cmdsz(struct m25p
*flash
)
214 return 1 + flash
->addr_width
;
218 * Erase one sector of flash memory at offset ``offset'' which is any
219 * address within the sector which should be erased.
221 * Returns 0 if successful, non-zero otherwise.
223 static int erase_sector(struct m25p
*flash
, u32 offset
)
225 DEBUG(MTD_DEBUG_LEVEL3
, "%s: %s %dKiB at 0x%08x\n",
226 dev_name(&flash
->spi
->dev
), __func__
,
227 flash
->mtd
.erasesize
/ 1024, offset
);
229 /* Wait until finished previous write command. */
230 if (wait_till_ready(flash
))
233 /* Send write enable, then erase commands. */
236 /* Set up command buffer. */
237 flash
->command
[0] = flash
->erase_opcode
;
238 m25p_addr2cmd(flash
, offset
, flash
->command
);
240 spi_write(flash
->spi
, flash
->command
, m25p_cmdsz(flash
));
245 /****************************************************************************/
252 * Erase an address range on the flash chip. The address range may extend
253 * one or more erase sectors. Return an error is there is a problem erasing.
255 static int m25p80_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
257 struct m25p
*flash
= mtd_to_m25p(mtd
);
261 DEBUG(MTD_DEBUG_LEVEL2
, "%s: %s %s 0x%llx, len %lld\n",
262 dev_name(&flash
->spi
->dev
), __func__
, "at",
263 (long long)instr
->addr
, (long long)instr
->len
);
266 if (instr
->addr
+ instr
->len
> flash
->mtd
.size
)
268 div_u64_rem(instr
->len
, mtd
->erasesize
, &rem
);
275 mutex_lock(&flash
->lock
);
277 /* whole-chip erase? */
278 if (len
== flash
->mtd
.size
) {
279 if (erase_chip(flash
)) {
280 instr
->state
= MTD_ERASE_FAILED
;
281 mutex_unlock(&flash
->lock
);
285 /* REVISIT in some cases we could speed up erasing large regions
286 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
287 * to use "small sector erase", but that's not always optimal.
290 /* "sector"-at-a-time erase */
293 if (erase_sector(flash
, addr
)) {
294 instr
->state
= MTD_ERASE_FAILED
;
295 mutex_unlock(&flash
->lock
);
299 addr
+= mtd
->erasesize
;
300 len
-= mtd
->erasesize
;
304 mutex_unlock(&flash
->lock
);
306 instr
->state
= MTD_ERASE_DONE
;
307 mtd_erase_callback(instr
);
313 * Read an address range from the flash chip. The address range
314 * may be any size provided it is within the physical boundaries.
316 static int m25p80_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
317 size_t *retlen
, u_char
*buf
)
319 struct m25p
*flash
= mtd_to_m25p(mtd
);
320 struct spi_transfer t
[2];
321 struct spi_message m
;
323 DEBUG(MTD_DEBUG_LEVEL2
, "%s: %s %s 0x%08x, len %zd\n",
324 dev_name(&flash
->spi
->dev
), __func__
, "from",
331 if (from
+ len
> flash
->mtd
.size
)
334 spi_message_init(&m
);
335 memset(t
, 0, (sizeof t
));
338 * OPCODE_FAST_READ (if available) is faster.
339 * Should add 1 byte DUMMY_BYTE.
341 t
[0].tx_buf
= flash
->command
;
342 t
[0].len
= m25p_cmdsz(flash
) + FAST_READ_DUMMY_BYTE
;
343 spi_message_add_tail(&t
[0], &m
);
347 spi_message_add_tail(&t
[1], &m
);
349 /* Byte count starts at zero. */
352 mutex_lock(&flash
->lock
);
354 /* Wait till previous write/erase is done. */
355 if (wait_till_ready(flash
)) {
356 /* REVISIT status return?? */
357 mutex_unlock(&flash
->lock
);
361 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
362 * clocks; and at this writing, every chip this driver handles
363 * supports that opcode.
366 /* Set up the write data buffer. */
367 flash
->command
[0] = OPCODE_READ
;
368 m25p_addr2cmd(flash
, from
, flash
->command
);
370 spi_sync(flash
->spi
, &m
);
372 *retlen
= m
.actual_length
- m25p_cmdsz(flash
) - FAST_READ_DUMMY_BYTE
;
374 mutex_unlock(&flash
->lock
);
380 * Write an address range to the flash chip. Data must be written in
381 * FLASH_PAGESIZE chunks. The address range may be any size provided
382 * it is within the physical boundaries.
384 static int m25p80_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
385 size_t *retlen
, const u_char
*buf
)
387 struct m25p
*flash
= mtd_to_m25p(mtd
);
388 u32 page_offset
, page_size
;
389 struct spi_transfer t
[2];
390 struct spi_message m
;
392 DEBUG(MTD_DEBUG_LEVEL2
, "%s: %s %s 0x%08x, len %zd\n",
393 dev_name(&flash
->spi
->dev
), __func__
, "to",
402 if (to
+ len
> flash
->mtd
.size
)
405 spi_message_init(&m
);
406 memset(t
, 0, (sizeof t
));
408 t
[0].tx_buf
= flash
->command
;
409 t
[0].len
= m25p_cmdsz(flash
);
410 spi_message_add_tail(&t
[0], &m
);
413 spi_message_add_tail(&t
[1], &m
);
415 mutex_lock(&flash
->lock
);
417 /* Wait until finished previous write command. */
418 if (wait_till_ready(flash
)) {
419 mutex_unlock(&flash
->lock
);
425 /* Set up the opcode in the write buffer. */
426 flash
->command
[0] = OPCODE_PP
;
427 m25p_addr2cmd(flash
, to
, flash
->command
);
429 page_offset
= to
& (flash
->page_size
- 1);
431 /* do all the bytes fit onto one page? */
432 if (page_offset
+ len
<= flash
->page_size
) {
435 spi_sync(flash
->spi
, &m
);
437 *retlen
= m
.actual_length
- m25p_cmdsz(flash
);
441 /* the size of data remaining on the first page */
442 page_size
= flash
->page_size
- page_offset
;
444 t
[1].len
= page_size
;
445 spi_sync(flash
->spi
, &m
);
447 *retlen
= m
.actual_length
- m25p_cmdsz(flash
);
449 /* write everything in flash->page_size chunks */
450 for (i
= page_size
; i
< len
; i
+= page_size
) {
452 if (page_size
> flash
->page_size
)
453 page_size
= flash
->page_size
;
455 /* write the next page to flash */
456 m25p_addr2cmd(flash
, to
+ i
, flash
->command
);
458 t
[1].tx_buf
= buf
+ i
;
459 t
[1].len
= page_size
;
461 wait_till_ready(flash
);
465 spi_sync(flash
->spi
, &m
);
467 *retlen
+= m
.actual_length
- m25p_cmdsz(flash
);
471 mutex_unlock(&flash
->lock
);
476 static int sst_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
477 size_t *retlen
, const u_char
*buf
)
479 struct m25p
*flash
= mtd_to_m25p(mtd
);
480 struct spi_transfer t
[2];
481 struct spi_message m
;
491 if (to
+ len
> flash
->mtd
.size
)
494 spi_message_init(&m
);
495 memset(t
, 0, (sizeof t
));
497 t
[0].tx_buf
= flash
->command
;
498 t
[0].len
= m25p_cmdsz(flash
);
499 spi_message_add_tail(&t
[0], &m
);
502 spi_message_add_tail(&t
[1], &m
);
504 mutex_lock(&flash
->lock
);
506 /* Wait until finished previous write command. */
507 ret
= wait_till_ready(flash
);
514 /* Start write from odd address. */
516 flash
->command
[0] = OPCODE_BP
;
517 m25p_addr2cmd(flash
, to
, flash
->command
);
519 /* write one byte. */
521 spi_sync(flash
->spi
, &m
);
522 ret
= wait_till_ready(flash
);
525 *retlen
+= m
.actual_length
- m25p_cmdsz(flash
);
529 flash
->command
[0] = OPCODE_AAI_WP
;
530 m25p_addr2cmd(flash
, to
, flash
->command
);
532 /* Write out most of the data here. */
533 cmd_sz
= m25p_cmdsz(flash
);
534 for (; actual
< len
- 1; actual
+= 2) {
536 /* write two bytes. */
538 t
[1].tx_buf
= buf
+ actual
;
540 spi_sync(flash
->spi
, &m
);
541 ret
= wait_till_ready(flash
);
544 *retlen
+= m
.actual_length
- cmd_sz
;
548 write_disable(flash
);
549 ret
= wait_till_ready(flash
);
553 /* Write out trailing byte if it exists. */
556 flash
->command
[0] = OPCODE_BP
;
557 m25p_addr2cmd(flash
, to
, flash
->command
);
558 t
[0].len
= m25p_cmdsz(flash
);
560 t
[1].tx_buf
= buf
+ actual
;
562 spi_sync(flash
->spi
, &m
);
563 ret
= wait_till_ready(flash
);
566 *retlen
+= m
.actual_length
- m25p_cmdsz(flash
);
567 write_disable(flash
);
571 mutex_unlock(&flash
->lock
);
575 /****************************************************************************/
578 * SPI device driver setup and teardown
582 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
583 * a high byte of zero plus three data bytes: the manufacturer id,
584 * then a two byte device id.
589 /* The size listed here is what works with OPCODE_SE, which isn't
590 * necessarily called a "sector" by the vendor.
592 unsigned sector_size
;
599 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
600 #define M25P_NO_ERASE 0x02 /* No erase command needed */
603 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
604 ((kernel_ulong_t)&(struct flash_info) { \
605 .jedec_id = (_jedec_id), \
606 .ext_id = (_ext_id), \
607 .sector_size = (_sector_size), \
608 .n_sectors = (_n_sectors), \
614 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
615 ((kernel_ulong_t)&(struct flash_info) { \
616 .sector_size = (_sector_size), \
617 .n_sectors = (_n_sectors), \
618 .page_size = (_page_size), \
619 .addr_width = (_addr_width), \
620 .flags = M25P_NO_ERASE, \
623 /* NOTE: double check command sets and memory organization when you add
624 * more flash chips. This current list focusses on newer chips, which
625 * have been converging on command sets which including JEDEC ID.
627 static const struct spi_device_id m25p_ids
[] = {
628 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
629 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K
) },
630 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K
) },
632 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K
) },
633 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K
) },
635 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K
) },
636 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K
) },
637 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K
) },
638 { "at26df321", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K
) },
641 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
642 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
644 /* Intel/Numonyx -- xxxs33b */
645 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
646 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
647 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
650 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K
) },
651 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
652 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
653 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
654 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
655 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
657 /* Spansion -- single (large) sector size only, at least
658 * for the chips listed here (without boot sectors).
660 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
661 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
662 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
663 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
664 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K
) },
665 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
666 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
667 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
668 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
669 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
670 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K
) },
671 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
673 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
674 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K
) },
675 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K
) },
676 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K
) },
677 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K
) },
678 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K
) },
679 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K
) },
680 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K
) },
681 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K
) },
683 /* ST Microelectronics -- newer production may have feature updates */
684 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
685 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
686 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
687 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
688 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
689 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
690 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
691 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
692 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
694 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
695 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
696 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
697 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
698 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
699 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
700 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
701 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
702 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
704 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
705 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
706 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
708 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
709 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K
) },
711 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
712 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K
) },
713 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K
) },
714 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K
) },
715 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K
) },
716 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K
) },
717 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K
) },
718 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K
) },
719 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K
) },
720 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
) },
722 /* Catalyst / On Semiconductor -- non-JEDEC */
723 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
724 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
725 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
726 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
727 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
730 MODULE_DEVICE_TABLE(spi
, m25p_ids
);
732 static const struct spi_device_id
*__devinit
jedec_probe(struct spi_device
*spi
)
735 u8 code
= OPCODE_RDID
;
739 struct flash_info
*info
;
741 /* JEDEC also defines an optional "extended device information"
742 * string for after vendor-specific data, after the three bytes
743 * we use here. Supporting some chips might require using it.
745 tmp
= spi_write_then_read(spi
, &code
, 1, id
, 5);
747 DEBUG(MTD_DEBUG_LEVEL0
, "%s: error %d reading JEDEC ID\n",
748 dev_name(&spi
->dev
), tmp
);
757 ext_jedec
= id
[3] << 8 | id
[4];
759 for (tmp
= 0; tmp
< ARRAY_SIZE(m25p_ids
) - 1; tmp
++) {
760 info
= (void *)m25p_ids
[tmp
].driver_data
;
761 if (info
->jedec_id
== jedec
) {
762 if (info
->ext_id
!= 0 && info
->ext_id
!= ext_jedec
)
764 return &m25p_ids
[tmp
];
767 return ERR_PTR(-ENODEV
);
772 * board specific setup should have ensured the SPI clock used here
773 * matches what the READ command supports, at least until this driver
774 * understands FAST_READ (for clocks over 25 MHz).
776 static int __devinit
m25p_probe(struct spi_device
*spi
)
778 const struct spi_device_id
*id
= spi_get_device_id(spi
);
779 struct flash_platform_data
*data
;
781 struct flash_info
*info
;
784 /* Platform data helps sort out which chip type we have, as
785 * well as how this board partitions it. If we don't have
786 * a chip ID, try the JEDEC id commands; they'll work for most
787 * newer chips, even if we don't recognize the particular chip.
789 data
= spi
->dev
.platform_data
;
790 if (data
&& data
->type
) {
791 const struct spi_device_id
*plat_id
;
793 for (i
= 0; i
< ARRAY_SIZE(m25p_ids
) - 1; i
++) {
794 plat_id
= &m25p_ids
[i
];
795 if (strcmp(data
->type
, plat_id
->name
))
800 if (i
< ARRAY_SIZE(m25p_ids
) - 1)
803 dev_warn(&spi
->dev
, "unrecognized id %s\n", data
->type
);
806 info
= (void *)id
->driver_data
;
808 if (info
->jedec_id
) {
809 const struct spi_device_id
*jid
;
811 jid
= jedec_probe(spi
);
814 } else if (jid
!= id
) {
816 * JEDEC knows better, so overwrite platform ID. We
817 * can't trust partitions any longer, but we'll let
818 * mtd apply them anyway, since some partitions may be
819 * marked read-only, and we don't want to lose that
820 * information, even if it's not 100% accurate.
822 dev_warn(&spi
->dev
, "found %s, expected %s\n",
823 jid
->name
, id
->name
);
825 info
= (void *)jid
->driver_data
;
829 flash
= kzalloc(sizeof *flash
, GFP_KERNEL
);
832 flash
->command
= kmalloc(MAX_CMD_SIZE
+ FAST_READ_DUMMY_BYTE
, GFP_KERNEL
);
833 if (!flash
->command
) {
839 mutex_init(&flash
->lock
);
840 dev_set_drvdata(&spi
->dev
, flash
);
843 * Atmel, SST and Intel/Numonyx serial flash tend to power
844 * up with the software protection bits set
847 if (info
->jedec_id
>> 16 == 0x1f ||
848 info
->jedec_id
>> 16 == 0x89 ||
849 info
->jedec_id
>> 16 == 0xbf) {
854 if (data
&& data
->name
)
855 flash
->mtd
.name
= data
->name
;
857 flash
->mtd
.name
= dev_name(&spi
->dev
);
859 flash
->mtd
.type
= MTD_NORFLASH
;
860 flash
->mtd
.writesize
= 1;
861 flash
->mtd
.flags
= MTD_CAP_NORFLASH
;
862 flash
->mtd
.size
= info
->sector_size
* info
->n_sectors
;
863 flash
->mtd
.erase
= m25p80_erase
;
864 flash
->mtd
.read
= m25p80_read
;
866 /* sst flash chips use AAI word program */
867 if (info
->jedec_id
>> 16 == 0xbf)
868 flash
->mtd
.write
= sst_write
;
870 flash
->mtd
.write
= m25p80_write
;
872 /* prefer "small sector" erase if possible */
873 if (info
->flags
& SECT_4K
) {
874 flash
->erase_opcode
= OPCODE_BE_4K
;
875 flash
->mtd
.erasesize
= 4096;
877 flash
->erase_opcode
= OPCODE_SE
;
878 flash
->mtd
.erasesize
= info
->sector_size
;
881 if (info
->flags
& M25P_NO_ERASE
)
882 flash
->mtd
.flags
|= MTD_NO_ERASE
;
884 flash
->mtd
.dev
.parent
= &spi
->dev
;
885 flash
->page_size
= info
->page_size
;
886 flash
->addr_width
= info
->addr_width
;
888 dev_info(&spi
->dev
, "%s (%lld Kbytes)\n", id
->name
,
889 (long long)flash
->mtd
.size
>> 10);
891 DEBUG(MTD_DEBUG_LEVEL2
,
892 "mtd .name = %s, .size = 0x%llx (%lldMiB) "
893 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
895 (long long)flash
->mtd
.size
, (long long)(flash
->mtd
.size
>> 20),
896 flash
->mtd
.erasesize
, flash
->mtd
.erasesize
/ 1024,
897 flash
->mtd
.numeraseregions
);
899 if (flash
->mtd
.numeraseregions
)
900 for (i
= 0; i
< flash
->mtd
.numeraseregions
; i
++)
901 DEBUG(MTD_DEBUG_LEVEL2
,
902 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
903 ".erasesize = 0x%.8x (%uKiB), "
904 ".numblocks = %d }\n",
905 i
, (long long)flash
->mtd
.eraseregions
[i
].offset
,
906 flash
->mtd
.eraseregions
[i
].erasesize
,
907 flash
->mtd
.eraseregions
[i
].erasesize
/ 1024,
908 flash
->mtd
.eraseregions
[i
].numblocks
);
911 /* partitions should match sector boundaries; and it may be good to
912 * use readonly partitions for writeprotected sectors (BP2..BP0).
914 if (mtd_has_partitions()) {
915 struct mtd_partition
*parts
= NULL
;
918 if (mtd_has_cmdlinepart()) {
919 static const char *part_probes
[]
920 = { "cmdlinepart", NULL
, };
922 nr_parts
= parse_mtd_partitions(&flash
->mtd
,
923 part_probes
, &parts
, 0);
926 if (nr_parts
<= 0 && data
&& data
->parts
) {
928 nr_parts
= data
->nr_parts
;
931 #ifdef CONFIG_MTD_OF_PARTS
932 if (nr_parts
<= 0 && spi
->dev
.of_node
) {
933 nr_parts
= of_mtd_parse_partitions(&spi
->dev
,
934 spi
->dev
.of_node
, &parts
);
939 for (i
= 0; i
< nr_parts
; i
++) {
940 DEBUG(MTD_DEBUG_LEVEL2
, "partitions[%d] = "
941 "{.name = %s, .offset = 0x%llx, "
942 ".size = 0x%llx (%lldKiB) }\n",
944 (long long)parts
[i
].offset
,
945 (long long)parts
[i
].size
,
946 (long long)(parts
[i
].size
>> 10));
948 flash
->partitioned
= 1;
949 return add_mtd_partitions(&flash
->mtd
, parts
, nr_parts
);
951 } else if (data
&& data
->nr_parts
)
952 dev_warn(&spi
->dev
, "ignoring %d default partitions on %s\n",
953 data
->nr_parts
, data
->name
);
955 return add_mtd_device(&flash
->mtd
) == 1 ? -ENODEV
: 0;
959 static int __devexit
m25p_remove(struct spi_device
*spi
)
961 struct m25p
*flash
= dev_get_drvdata(&spi
->dev
);
964 /* Clean up MTD stuff. */
965 if (mtd_has_partitions() && flash
->partitioned
)
966 status
= del_mtd_partitions(&flash
->mtd
);
968 status
= del_mtd_device(&flash
->mtd
);
970 kfree(flash
->command
);
977 static struct spi_driver m25p80_driver
= {
980 .bus
= &spi_bus_type
,
981 .owner
= THIS_MODULE
,
983 .id_table
= m25p_ids
,
985 .remove
= __devexit_p(m25p_remove
),
987 /* REVISIT: many of these chips have deep power-down modes, which
988 * should clearly be entered on suspend() to minimize power use.
989 * And also when they're otherwise idle...
994 static int __init
m25p80_init(void)
996 return spi_register_driver(&m25p80_driver
);
1000 static void __exit
m25p80_exit(void)
1002 spi_unregister_driver(&m25p80_driver
);
1006 module_init(m25p80_init
);
1007 module_exit(m25p80_exit
);
1009 MODULE_LICENSE("GPL");
1010 MODULE_AUTHOR("Mike Lavender");
1011 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
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