drivers/mtd/maps/dilnetpc.c

   1 /* dilnetpc.c -- MTD map driver for SSV DIL/Net PC Boards "DNP" and "ADNP"
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License as published by
   5  * the Free Software Foundation; either version 2 of the License, or
   6  * (at your option) any later version.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  16  *
  17  * $Id: dilnetpc.c,v 1.20 2005/11/07 11:14:26 gleixner Exp $
  18  *
  19  * The DIL/Net PC is a tiny embedded PC board made by SSV Embedded Systems
  20  * featuring the AMD Elan SC410 processor. There are two variants of this
  21  * board: DNP/1486 and ADNP/1486. The DNP version has 2 megs of flash
  22  * ROM (Intel 28F016S3) and 8 megs of DRAM, the ADNP version has 4 megs
  23  * flash and 16 megs of RAM.
  24  * For details, see http://www.ssv-embedded.de/ssv/pc104/p169.htm
  25  * and http://www.ssv-embedded.de/ssv/pc104/p170.htm
  26  */
  27
  28 #include <linux/config.h>
  29 #include <linux/module.h>
  30 #include <linux/types.h>
  31 #include <linux/kernel.h>
  32 #include <linux/init.h>
  33 #include <linux/string.h>
  34
  35 #include <linux/mtd/mtd.h>
  36 #include <linux/mtd/map.h>
  37 #include <linux/mtd/partitions.h>
  38 #include <linux/mtd/concat.h>
  39
  40 #include <asm/io.h>
  41
  42 /*
  43 ** The DIL/NetPC keeps its BIOS in two distinct flash blocks.
  44 ** Destroying any of these blocks transforms the DNPC into
  45 ** a paperweight (albeit not a very useful one, considering
  46 ** it only weighs a few grams).
  47 **
  48 ** Therefore, the BIOS blocks must never be erased or written to
  49 ** except by people who know exactly what they are doing (e.g.
  50 ** to install a BIOS update). These partitions are marked read-only
  51 ** by default, but can be made read/write by undefining
  52 ** DNPC_BIOS_BLOCKS_WRITEPROTECTED:
  53 */
  54 #define DNPC_BIOS_BLOCKS_WRITEPROTECTED
  55
  56 /*
  57 ** The ID string (in ROM) is checked to determine whether we
  58 ** are running on a DNP/1486 or ADNP/1486
  59 */
  60 #define BIOSID_BASE     0x000fe100
  61
  62 #define ID_DNPC "DNP1486"
  63 #define ID_ADNP "ADNP1486"
  64
  65 /*
  66 ** Address where the flash should appear in CPU space
  67 */
  68 #define FLASH_BASE      0x2000000
  69
  70 /*
  71 ** Chip Setup and Control (CSC) indexed register space
  72 */
  73 #define CSC_INDEX       0x22
  74 #define CSC_DATA        0x23
  75
  76 #define CSC_MMSWAR      0x30    /* MMS window C-F attributes register */
  77 #define CSC_MMSWDSR     0x31    /* MMS window C-F device select register */
  78
  79 #define CSC_RBWR        0xa7    /* GPIO Read-Back/Write Register B */
  80
  81 #define CSC_CR          0xd0    /* internal I/O device disable/Echo */
  82                                 /* Z-bus/configuration register */
  83
  84 #define CSC_PCCMDCR     0xf1    /* PC card mode and DMA control register */
  85
  86
  87 /*
  88 ** PC Card indexed register space:
  89 */
  90
  91 #define PCC_INDEX       0x3e0
  92 #define PCC_DATA        0x3e1
  93
  94 #define PCC_AWER_B              0x46    /* Socket B Address Window enable register */
  95 #define PCC_MWSAR_1_Lo  0x58    /* memory window 1 start address low register */
  96 #define PCC_MWSAR_1_Hi  0x59    /* memory window 1 start address high register */
  97 #define PCC_MWEAR_1_Lo  0x5A    /* memory window 1 stop address low register */
  98 #define PCC_MWEAR_1_Hi  0x5B    /* memory window 1 stop address high register */
  99 #define PCC_MWAOR_1_Lo  0x5C    /* memory window 1 address offset low register */
 100 #define PCC_MWAOR_1_Hi  0x5D    /* memory window 1 address offset high register */
 101
 102
 103 /*
 104 ** Access to SC4x0's Chip Setup and Control (CSC)
 105 ** and PC Card (PCC) indexed registers:
 106 */
 107 static inline void setcsc(int reg, unsigned char data)
 108 {
 109         outb(reg, CSC_INDEX);
 110         outb(data, CSC_DATA);
 111 }
 112
 113 static inline unsigned char getcsc(int reg)
 114 {
 115         outb(reg, CSC_INDEX);
 116         return(inb(CSC_DATA));
 117 }
 118
 119 static inline void setpcc(int reg, unsigned char data)
 120 {
 121         outb(reg, PCC_INDEX);
 122         outb(data, PCC_DATA);
 123 }
 124
 125 static inline unsigned char getpcc(int reg)
 126 {
 127         outb(reg, PCC_INDEX);
 128         return(inb(PCC_DATA));
 129 }
 130
 131
 132 /*
 133 ************************************************************
 134 ** Enable access to DIL/NetPC's flash by mapping it into
 135 ** the SC4x0's MMS Window C.
 136 ************************************************************
 137 */
 138 static void dnpc_map_flash(unsigned long flash_base, unsigned long flash_size)
 139 {
 140         unsigned long flash_end = flash_base + flash_size - 1;
 141
 142         /*
 143         ** enable setup of MMS windows C-F:
 144         */
 145         /* - enable PC Card indexed register space */
 146         setcsc(CSC_CR, getcsc(CSC_CR) | 0x2);
 147         /* - set PC Card controller to operate in standard mode */
 148         setcsc(CSC_PCCMDCR, getcsc(CSC_PCCMDCR) & ~1);
 149
 150         /*
 151         ** Program base address and end address of window
 152         ** where the flash ROM should appear in CPU address space
 153         */
 154         setpcc(PCC_MWSAR_1_Lo, (flash_base >> 12) & 0xff);
 155         setpcc(PCC_MWSAR_1_Hi, (flash_base >> 20) & 0x3f);
 156         setpcc(PCC_MWEAR_1_Lo, (flash_end >> 12) & 0xff);
 157         setpcc(PCC_MWEAR_1_Hi, (flash_end >> 20) & 0x3f);
 158
 159         /* program offset of first flash location to appear in this window (0) */
 160         setpcc(PCC_MWAOR_1_Lo, ((0 - flash_base) >> 12) & 0xff);
 161         setpcc(PCC_MWAOR_1_Hi, ((0 - flash_base)>> 20) & 0x3f);
 162
 163         /* set attributes for MMS window C: non-cacheable, write-enabled */
 164         setcsc(CSC_MMSWAR, getcsc(CSC_MMSWAR) & ~0x11);
 165
 166         /* select physical device ROMCS0 (i.e. flash) for MMS Window C */
 167         setcsc(CSC_MMSWDSR, getcsc(CSC_MMSWDSR) & ~0x03);
 168
 169         /* enable memory window 1 */
 170         setpcc(PCC_AWER_B, getpcc(PCC_AWER_B) | 0x02);
 171
 172         /* now disable PC Card indexed register space again */
 173         setcsc(CSC_CR, getcsc(CSC_CR) & ~0x2);
 174 }
 175
 176
 177 /*
 178 ************************************************************
 179 ** Disable access to DIL/NetPC's flash by mapping it into
 180 ** the SC4x0's MMS Window C.
 181 ************************************************************
 182 */
 183 static void dnpc_unmap_flash(void)
 184 {
 185         /* - enable PC Card indexed register space */
 186         setcsc(CSC_CR, getcsc(CSC_CR) | 0x2);
 187
 188         /* disable memory window 1 */
 189         setpcc(PCC_AWER_B, getpcc(PCC_AWER_B) & ~0x02);
 190
 191         /* now disable PC Card indexed register space again */
 192         setcsc(CSC_CR, getcsc(CSC_CR) & ~0x2);
 193 }
 194
 195
 196
 197 /*
 198 ************************************************************
 199 ** Enable/Disable VPP to write to flash
 200 ************************************************************
 201 */
 202
 203 static DEFINE_SPINLOCK(dnpc_spin);
 204 static int        vpp_counter = 0;
 205 /*
 206 ** This is what has to be done for the DNP board ..
 207 */
 208 static void dnp_set_vpp(struct map_info *not_used, int on)
 209 {
 210         spin_lock_irq(&dnpc_spin);
 211
 212         if (on)
 213         {
 214                 if(++vpp_counter == 1)
 215                         setcsc(CSC_RBWR, getcsc(CSC_RBWR) & ~0x4);
 216         }
 217         else
 218         {
 219                 if(--vpp_counter == 0)
 220                         setcsc(CSC_RBWR, getcsc(CSC_RBWR) | 0x4);
 221                 else if(vpp_counter < 0)
 222                         BUG();
 223         }
 224         spin_unlock_irq(&dnpc_spin);
 225 }
 226
 227 /*
 228 ** .. and this the ADNP version:
 229 */
 230 static void adnp_set_vpp(struct map_info *not_used, int on)
 231 {
 232         spin_lock_irq(&dnpc_spin);
 233
 234         if (on)
 235         {
 236                 if(++vpp_counter == 1)
 237                         setcsc(CSC_RBWR, getcsc(CSC_RBWR) & ~0x8);
 238         }
 239         else
 240         {
 241                 if(--vpp_counter == 0)
 242                         setcsc(CSC_RBWR, getcsc(CSC_RBWR) | 0x8);
 243                 else if(vpp_counter < 0)
 244                         BUG();
 245         }
 246         spin_unlock_irq(&dnpc_spin);
 247 }
 248
 249
 250
 251 #define DNP_WINDOW_SIZE         0x00200000      /*  DNP flash size is 2MiB  */
 252 #define ADNP_WINDOW_SIZE        0x00400000      /* ADNP flash size is 4MiB */
 253 #define WINDOW_ADDR             FLASH_BASE
 254
 255 static struct map_info dnpc_map = {
 256         .name = "ADNP Flash Bank",
 257         .size = ADNP_WINDOW_SIZE,
 258         .bankwidth = 1,
 259         .set_vpp = adnp_set_vpp,
 260         .phys = WINDOW_ADDR
 261 };
 262
 263 /*
 264 ** The layout of the flash is somewhat "strange":
 265 **
 266 ** 1.  960 KiB (15 blocks) : Space for ROM Bootloader and user data
 267 ** 2.   64 KiB (1 block)   : System BIOS
 268 ** 3.  960 KiB (15 blocks) : User Data (DNP model) or
 269 ** 3. 3008 KiB (47 blocks) : User Data (ADNP model)
 270 ** 4.   64 KiB (1 block)   : System BIOS Entry
 271 */
 272
 273 static struct mtd_partition partition_info[]=
 274 {
 275         {
 276                 .name =         "ADNP boot",
 277                 .offset =       0,
 278                 .size =         0xf0000,
 279         },
 280         {
 281                 .name =         "ADNP system BIOS",
 282                 .offset =       MTDPART_OFS_NXTBLK,
 283                 .size =         0x10000,
 284 #ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
 285                 .mask_flags =   MTD_WRITEABLE,
 286 #endif
 287         },
 288         {
 289                 .name =         "ADNP file system",
 290                 .offset =       MTDPART_OFS_NXTBLK,
 291                 .size =         0x2f0000,
 292         },
 293         {
 294                 .name =         "ADNP system BIOS entry",
 295                 .offset =       MTDPART_OFS_NXTBLK,
 296                 .size =         MTDPART_SIZ_FULL,
 297 #ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
 298                 .mask_flags =   MTD_WRITEABLE,
 299 #endif
 300         },
 301 };
 302
 303 #define NUM_PARTITIONS (sizeof(partition_info)/sizeof(partition_info[0]))
 304
 305 static struct mtd_info *mymtd;
 306 static struct mtd_info *lowlvl_parts[NUM_PARTITIONS];
 307 static struct mtd_info *merged_mtd;
 308
 309 /*
 310 ** "Highlevel" partition info:
 311 **
 312 ** Using the MTD concat layer, we can re-arrange partitions to our
 313 ** liking: we construct a virtual MTD device by concatenating the
 314 ** partitions, specifying the sequence such that the boot block
 315 ** is immediately followed by the filesystem block (i.e. the stupid
 316 ** system BIOS block is mapped to a different place). When re-partitioning
 317 ** this concatenated MTD device, we can set the boot block size to
 318 ** an arbitrary (though erase block aligned) value i.e. not one that
 319 ** is dictated by the flash's physical layout. We can thus set the
 320 ** boot block to be e.g. 64 KB (which is fully sufficient if we want
 321 ** to boot an etherboot image) or to -say- 1.5 MB if we want to boot
 322 ** a large kernel image. In all cases, the remainder of the flash
 323 ** is available as file system space.
 324 */
 325
 326 static struct mtd_partition higlvl_partition_info[]=
 327 {
 328         {
 329                 .name =         "ADNP boot block",
 330                 .offset =       0,
 331                 .size =         CONFIG_MTD_DILNETPC_BOOTSIZE,
 332         },
 333         {
 334                 .name =         "ADNP file system space",
 335                 .offset =       MTDPART_OFS_NXTBLK,
 336                 .size =         ADNP_WINDOW_SIZE-CONFIG_MTD_DILNETPC_BOOTSIZE-0x20000,
 337         },
 338         {
 339                 .name =         "ADNP system BIOS + BIOS Entry",
 340                 .offset =       MTDPART_OFS_NXTBLK,
 341                 .size =         MTDPART_SIZ_FULL,
 342 #ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
 343                 .mask_flags =   MTD_WRITEABLE,
 344 #endif
 345         },
 346 };
 347
 348 #define NUM_HIGHLVL_PARTITIONS (sizeof(higlvl_partition_info)/sizeof(partition_info[0]))
 349
 350
 351 static int dnp_adnp_probe(void)
 352 {
 353         char *biosid, rc = -1;
 354
 355         biosid = (char*)ioremap(BIOSID_BASE, 16);
 356         if(biosid)
 357         {
 358                 if(!strcmp(biosid, ID_DNPC))
 359                         rc = 1;         /* this is a DNPC  */
 360                 else if(!strcmp(biosid, ID_ADNP))
 361                         rc = 0;         /* this is a ADNPC */
 362         }
 363         iounmap((void *)biosid);
 364         return(rc);
 365 }
 366
 367
 368 static int __init init_dnpc(void)
 369 {
 370         int is_dnp;
 371
 372         /*
 373         ** determine hardware (DNP/ADNP/invalid)
 374         */
 375         if((is_dnp = dnp_adnp_probe()) < 0)
 376                 return -ENXIO;
 377
 378         /*
 379         ** Things are set up for ADNP by default
 380         ** -> modify all that needs to be different for DNP
 381         */
 382         if(is_dnp)
 383         {       /*
 384                 ** Adjust window size, select correct set_vpp function.
 385                 ** The partitioning scheme is identical on both DNP
 386                 ** and ADNP except for the size of the third partition.
 387                 */
 388                 int i;
 389                 dnpc_map.size          = DNP_WINDOW_SIZE;
 390                 dnpc_map.set_vpp       = dnp_set_vpp;
 391                 partition_info[2].size = 0xf0000;
 392
 393                 /*
 394                 ** increment all string pointers so the leading 'A' gets skipped,
 395                 ** thus turning all occurrences of "ADNP ..." into "DNP ..."
 396                 */
 397                 ++dnpc_map.name;
 398                 for(i = 0; i < NUM_PARTITIONS; i++)
 399                         ++partition_info[i].name;
 400                 higlvl_partition_info[1].size = DNP_WINDOW_SIZE -
 401                         CONFIG_MTD_DILNETPC_BOOTSIZE - 0x20000;
 402                 for(i = 0; i < NUM_HIGHLVL_PARTITIONS; i++)
 403                         ++higlvl_partition_info[i].name;
 404         }
 405
 406         printk(KERN_NOTICE "DIL/Net %s flash: 0x%lx at 0x%lx\n",
 407                 is_dnp ? "DNPC" : "ADNP", dnpc_map.size, dnpc_map.phys);
 408
 409         dnpc_map.virt = ioremap_nocache(dnpc_map.phys, dnpc_map.size);
 410
 411         dnpc_map_flash(dnpc_map.phys, dnpc_map.size);
 412
 413         if (!dnpc_map.virt) {
 414                 printk("Failed to ioremap_nocache\n");
 415                 return -EIO;
 416         }
 417         simple_map_init(&dnpc_map);
 418
 419         printk("FLASH virtual address: 0x%p\n", dnpc_map.virt);
 420
 421         mymtd = do_map_probe("jedec_probe", &dnpc_map);
 422
 423         if (!mymtd)
 424                 mymtd = do_map_probe("cfi_probe", &dnpc_map);
 425
 426         /*
 427         ** If flash probes fail, try to make flashes accessible
 428         ** at least as ROM. Ajust erasesize in this case since
 429         ** the default one (128M) will break our partitioning
 430         */
 431         if (!mymtd)
 432                 if((mymtd = do_map_probe("map_rom", &dnpc_map)))
 433                         mymtd->erasesize = 0x10000;
 434
 435         if (!mymtd) {
 436                 iounmap(dnpc_map.virt);
 437                 return -ENXIO;
 438         }
 439
 440         mymtd->owner = THIS_MODULE;
 441
 442         /*
 443         ** Supply pointers to lowlvl_parts[] array to add_mtd_partitions()
 444         ** -> add_mtd_partitions() will _not_ register MTD devices for
 445         ** the partitions, but will instead store pointers to the MTD
 446         ** objects it creates into our lowlvl_parts[] array.
 447         ** NOTE: we arrange the pointers such that the sequence of the
 448         **       partitions gets re-arranged: partition #2 follows
 449         **       partition #0.
 450         */
 451         partition_info[0].mtdp = &lowlvl_parts[0];
 452         partition_info[1].mtdp = &lowlvl_parts[2];
 453         partition_info[2].mtdp = &lowlvl_parts[1];
 454         partition_info[3].mtdp = &lowlvl_parts[3];
 455
 456         add_mtd_partitions(mymtd, partition_info, NUM_PARTITIONS);
 457
 458         /*
 459         ** now create a virtual MTD device by concatenating the for partitions
 460         ** (in the sequence given by the lowlvl_parts[] array.
 461         */
 462         merged_mtd = mtd_concat_create(lowlvl_parts, NUM_PARTITIONS, "(A)DNP Flash Concatenated");
 463         if(merged_mtd)
 464         {       /*
 465                 ** now partition the new device the way we want it. This time,
 466                 ** we do not supply mtd pointers in higlvl_partition_info, so
 467                 ** add_mtd_partitions() will register the devices.
 468                 */
 469                 add_mtd_partitions(merged_mtd, higlvl_partition_info, NUM_HIGHLVL_PARTITIONS);
 470         }
 471
 472         return 0;
 473 }
 474
 475 static void __exit cleanup_dnpc(void)
 476 {
 477         if(merged_mtd) {
 478                 del_mtd_partitions(merged_mtd);
 479                 mtd_concat_destroy(merged_mtd);
 480         }
 481
 482         if (mymtd) {
 483                 del_mtd_partitions(mymtd);
 484                 map_destroy(mymtd);
 485         }
 486         if (dnpc_map.virt) {
 487                 iounmap(dnpc_map.virt);
 488                 dnpc_unmap_flash();
 489                 dnpc_map.virt = NULL;
 490         }
 491 }
 492
 493 module_init(init_dnpc);
 494 module_exit(cleanup_dnpc);
 495
 496 MODULE_LICENSE("GPL");
 497 MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
 498 MODULE_DESCRIPTION("MTD map driver for SSV DIL/NetPC DNP & ADNP");