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22e9137412b4060ae6316d4c1883e11e381baa08
[deliverable/linux.git] / drivers / mtd / nand / atmel_nand.c
1 /*
2 * Copyright © 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
20 *
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30 #include <linux/dma-mapping.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/platform_device.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/of_mtd.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/partitions.h>
42
43 #include <linux/delay.h>
44 #include <linux/dmaengine.h>
45 #include <linux/gpio.h>
46 #include <linux/interrupt.h>
47 #include <linux/io.h>
48 #include <linux/platform_data/atmel.h>
49
50 static int use_dma = 1;
51 module_param(use_dma, int, 0);
52
53 static int on_flash_bbt = 0;
54 module_param(on_flash_bbt, int, 0);
55
56 /* Register access macros */
57 #define ecc_readl(add, reg) \
58 __raw_readl(add + ATMEL_ECC_##reg)
59 #define ecc_writel(add, reg, value) \
60 __raw_writel((value), add + ATMEL_ECC_##reg)
61
62 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
63 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
64
65 /* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
69 */
70 static struct nand_ecclayout atmel_oobinfo_large = {
71 .eccbytes = 4,
72 .eccpos = {60, 61, 62, 63},
73 .oobfree = {
74 {2, 58}
75 },
76 };
77
78 /* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
82 */
83 static struct nand_ecclayout atmel_oobinfo_small = {
84 .eccbytes = 4,
85 .eccpos = {0, 1, 2, 3},
86 .oobfree = {
87 {6, 10}
88 },
89 };
90
91 struct atmel_nfc {
92 void __iomem *base_cmd_regs;
93 void __iomem *hsmc_regs;
94 void __iomem *sram_bank0;
95 dma_addr_t sram_bank0_phys;
96 bool use_nfc_sram;
97 bool write_by_sram;
98
99 bool is_initialized;
100 struct completion comp_nfc;
101
102 /* Point to the sram bank which include readed data via NFC */
103 void __iomem *data_in_sram;
104 bool will_write_sram;
105 };
106 static struct atmel_nfc nand_nfc;
107
108 struct atmel_nand_host {
109 struct nand_chip nand_chip;
110 struct mtd_info mtd;
111 void __iomem *io_base;
112 dma_addr_t io_phys;
113 struct atmel_nand_data board;
114 struct device *dev;
115 void __iomem *ecc;
116
117 struct completion comp;
118 struct dma_chan *dma_chan;
119
120 struct atmel_nfc *nfc;
121
122 bool has_pmecc;
123 u8 pmecc_corr_cap;
124 u16 pmecc_sector_size;
125 u32 pmecc_lookup_table_offset;
126 u32 pmecc_lookup_table_offset_512;
127 u32 pmecc_lookup_table_offset_1024;
128
129 int pmecc_bytes_per_sector;
130 int pmecc_sector_number;
131 int pmecc_degree; /* Degree of remainders */
132 int pmecc_cw_len; /* Length of codeword */
133
134 void __iomem *pmerrloc_base;
135 void __iomem *pmecc_rom_base;
136
137 /* lookup table for alpha_to and index_of */
138 void __iomem *pmecc_alpha_to;
139 void __iomem *pmecc_index_of;
140
141 /* data for pmecc computation */
142 int16_t *pmecc_partial_syn;
143 int16_t *pmecc_si;
144 int16_t *pmecc_smu; /* Sigma table */
145 int16_t *pmecc_lmu; /* polynomal order */
146 int *pmecc_mu;
147 int *pmecc_dmu;
148 int *pmecc_delta;
149 };
150
151 static struct nand_ecclayout atmel_pmecc_oobinfo;
152
153 /*
154 * Enable NAND.
155 */
156 static void atmel_nand_enable(struct atmel_nand_host *host)
157 {
158 if (gpio_is_valid(host->board.enable_pin))
159 gpio_set_value(host->board.enable_pin, 0);
160 }
161
162 /*
163 * Disable NAND.
164 */
165 static void atmel_nand_disable(struct atmel_nand_host *host)
166 {
167 if (gpio_is_valid(host->board.enable_pin))
168 gpio_set_value(host->board.enable_pin, 1);
169 }
170
171 /*
172 * Hardware specific access to control-lines
173 */
174 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
175 {
176 struct nand_chip *nand_chip = mtd->priv;
177 struct atmel_nand_host *host = nand_chip->priv;
178
179 if (ctrl & NAND_CTRL_CHANGE) {
180 if (ctrl & NAND_NCE)
181 atmel_nand_enable(host);
182 else
183 atmel_nand_disable(host);
184 }
185 if (cmd == NAND_CMD_NONE)
186 return;
187
188 if (ctrl & NAND_CLE)
189 writeb(cmd, host->io_base + (1 << host->board.cle));
190 else
191 writeb(cmd, host->io_base + (1 << host->board.ale));
192 }
193
194 /*
195 * Read the Device Ready pin.
196 */
197 static int atmel_nand_device_ready(struct mtd_info *mtd)
198 {
199 struct nand_chip *nand_chip = mtd->priv;
200 struct atmel_nand_host *host = nand_chip->priv;
201
202 return gpio_get_value(host->board.rdy_pin) ^
203 !!host->board.rdy_pin_active_low;
204 }
205
206 /* Set up for hardware ready pin and enable pin. */
207 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
208 {
209 struct nand_chip *chip = mtd->priv;
210 struct atmel_nand_host *host = chip->priv;
211 int res = 0;
212
213 if (gpio_is_valid(host->board.rdy_pin)) {
214 res = devm_gpio_request(host->dev,
215 host->board.rdy_pin, "nand_rdy");
216 if (res < 0) {
217 dev_err(host->dev,
218 "can't request rdy gpio %d\n",
219 host->board.rdy_pin);
220 return res;
221 }
222
223 res = gpio_direction_input(host->board.rdy_pin);
224 if (res < 0) {
225 dev_err(host->dev,
226 "can't request input direction rdy gpio %d\n",
227 host->board.rdy_pin);
228 return res;
229 }
230
231 chip->dev_ready = atmel_nand_device_ready;
232 }
233
234 if (gpio_is_valid(host->board.enable_pin)) {
235 res = devm_gpio_request(host->dev,
236 host->board.enable_pin, "nand_enable");
237 if (res < 0) {
238 dev_err(host->dev,
239 "can't request enable gpio %d\n",
240 host->board.enable_pin);
241 return res;
242 }
243
244 res = gpio_direction_output(host->board.enable_pin, 1);
245 if (res < 0) {
246 dev_err(host->dev,
247 "can't request output direction enable gpio %d\n",
248 host->board.enable_pin);
249 return res;
250 }
251 }
252
253 return res;
254 }
255
256 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
257 {
258 int i;
259 u32 *t = trg;
260 const __iomem u32 *s = src;
261
262 for (i = 0; i < (size >> 2); i++)
263 *t++ = readl_relaxed(s++);
264 }
265
266 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
267 {
268 int i;
269 u32 __iomem *t = trg;
270 const u32 *s = src;
271
272 for (i = 0; i < (size >> 2); i++)
273 writel_relaxed(*s++, t++);
274 }
275
276 /*
277 * Minimal-overhead PIO for data access.
278 */
279 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
280 {
281 struct nand_chip *nand_chip = mtd->priv;
282 struct atmel_nand_host *host = nand_chip->priv;
283
284 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
285 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
286 host->nfc->data_in_sram += len;
287 } else {
288 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
289 }
290 }
291
292 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
293 {
294 struct nand_chip *nand_chip = mtd->priv;
295 struct atmel_nand_host *host = nand_chip->priv;
296
297 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
298 memcpy32_fromio(buf, host->nfc->data_in_sram, len);
299 host->nfc->data_in_sram += len;
300 } else {
301 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
302 }
303 }
304
305 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
306 {
307 struct nand_chip *nand_chip = mtd->priv;
308
309 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
310 }
311
312 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
313 {
314 struct nand_chip *nand_chip = mtd->priv;
315
316 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
317 }
318
319 static void dma_complete_func(void *completion)
320 {
321 complete(completion);
322 }
323
324 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
325 {
326 /* NFC only has two banks. Must be 0 or 1 */
327 if (bank > 1)
328 return -EINVAL;
329
330 if (bank) {
331 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
332 if (host->mtd.writesize > 2048)
333 return -EINVAL;
334 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
335 } else {
336 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
337 }
338
339 return 0;
340 }
341
342 static uint nfc_get_sram_off(struct atmel_nand_host *host)
343 {
344 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
345 return NFC_SRAM_BANK1_OFFSET;
346 else
347 return 0;
348 }
349
350 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
351 {
352 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
353 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
354 else
355 return host->nfc->sram_bank0_phys;
356 }
357
358 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
359 int is_read)
360 {
361 struct dma_device *dma_dev;
362 enum dma_ctrl_flags flags;
363 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
364 struct dma_async_tx_descriptor *tx = NULL;
365 dma_cookie_t cookie;
366 struct nand_chip *chip = mtd->priv;
367 struct atmel_nand_host *host = chip->priv;
368 void *p = buf;
369 int err = -EIO;
370 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
371 struct atmel_nfc *nfc = host->nfc;
372
373 if (buf >= high_memory)
374 goto err_buf;
375
376 dma_dev = host->dma_chan->device;
377
378 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
379
380 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
381 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
382 dev_err(host->dev, "Failed to dma_map_single\n");
383 goto err_buf;
384 }
385
386 if (is_read) {
387 if (nfc && nfc->data_in_sram)
388 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
389 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
390 else
391 dma_src_addr = host->io_phys;
392
393 dma_dst_addr = phys_addr;
394 } else {
395 dma_src_addr = phys_addr;
396
397 if (nfc && nfc->write_by_sram)
398 dma_dst_addr = nfc_sram_phys(host);
399 else
400 dma_dst_addr = host->io_phys;
401 }
402
403 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
404 dma_src_addr, len, flags);
405 if (!tx) {
406 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
407 goto err_dma;
408 }
409
410 init_completion(&host->comp);
411 tx->callback = dma_complete_func;
412 tx->callback_param = &host->comp;
413
414 cookie = tx->tx_submit(tx);
415 if (dma_submit_error(cookie)) {
416 dev_err(host->dev, "Failed to do DMA tx_submit\n");
417 goto err_dma;
418 }
419
420 dma_async_issue_pending(host->dma_chan);
421 wait_for_completion(&host->comp);
422
423 if (is_read && nfc && nfc->data_in_sram)
424 /* After read data from SRAM, need to increase the position */
425 nfc->data_in_sram += len;
426
427 err = 0;
428
429 err_dma:
430 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
431 err_buf:
432 if (err != 0)
433 dev_dbg(host->dev, "Fall back to CPU I/O\n");
434 return err;
435 }
436
437 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
438 {
439 struct nand_chip *chip = mtd->priv;
440 struct atmel_nand_host *host = chip->priv;
441
442 if (use_dma && len > mtd->oobsize)
443 /* only use DMA for bigger than oob size: better performances */
444 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
445 return;
446
447 if (host->board.bus_width_16)
448 atmel_read_buf16(mtd, buf, len);
449 else
450 atmel_read_buf8(mtd, buf, len);
451 }
452
453 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
454 {
455 struct nand_chip *chip = mtd->priv;
456 struct atmel_nand_host *host = chip->priv;
457
458 if (use_dma && len > mtd->oobsize)
459 /* only use DMA for bigger than oob size: better performances */
460 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
461 return;
462
463 if (host->board.bus_width_16)
464 atmel_write_buf16(mtd, buf, len);
465 else
466 atmel_write_buf8(mtd, buf, len);
467 }
468
469 /*
470 * Return number of ecc bytes per sector according to sector size and
471 * correction capability
472 *
473 * Following table shows what at91 PMECC supported:
474 * Correction Capability Sector_512_bytes Sector_1024_bytes
475 * ===================== ================ =================
476 * 2-bits 4-bytes 4-bytes
477 * 4-bits 7-bytes 7-bytes
478 * 8-bits 13-bytes 14-bytes
479 * 12-bits 20-bytes 21-bytes
480 * 24-bits 39-bytes 42-bytes
481 */
482 static int pmecc_get_ecc_bytes(int cap, int sector_size)
483 {
484 int m = 12 + sector_size / 512;
485 return (m * cap + 7) / 8;
486 }
487
488 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
489 int oobsize, int ecc_len)
490 {
491 int i;
492
493 layout->eccbytes = ecc_len;
494
495 /* ECC will occupy the last ecc_len bytes continuously */
496 for (i = 0; i < ecc_len; i++)
497 layout->eccpos[i] = oobsize - ecc_len + i;
498
499 layout->oobfree[0].offset = 2;
500 layout->oobfree[0].length =
501 oobsize - ecc_len - layout->oobfree[0].offset;
502 }
503
504 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
505 {
506 int table_size;
507
508 table_size = host->pmecc_sector_size == 512 ?
509 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
510
511 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
512 table_size * sizeof(int16_t);
513 }
514
515 static int pmecc_data_alloc(struct atmel_nand_host *host)
516 {
517 const int cap = host->pmecc_corr_cap;
518 int size;
519
520 size = (2 * cap + 1) * sizeof(int16_t);
521 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
522 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
523 host->pmecc_lmu = devm_kzalloc(host->dev,
524 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
525 host->pmecc_smu = devm_kzalloc(host->dev,
526 (cap + 2) * size, GFP_KERNEL);
527
528 size = (cap + 1) * sizeof(int);
529 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
530 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
531 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
532
533 if (!host->pmecc_partial_syn ||
534 !host->pmecc_si ||
535 !host->pmecc_lmu ||
536 !host->pmecc_smu ||
537 !host->pmecc_mu ||
538 !host->pmecc_dmu ||
539 !host->pmecc_delta)
540 return -ENOMEM;
541
542 return 0;
543 }
544
545 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
546 {
547 struct nand_chip *nand_chip = mtd->priv;
548 struct atmel_nand_host *host = nand_chip->priv;
549 int i;
550 uint32_t value;
551
552 /* Fill odd syndromes */
553 for (i = 0; i < host->pmecc_corr_cap; i++) {
554 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
555 if (i & 1)
556 value >>= 16;
557 value &= 0xffff;
558 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
559 }
560 }
561
562 static void pmecc_substitute(struct mtd_info *mtd)
563 {
564 struct nand_chip *nand_chip = mtd->priv;
565 struct atmel_nand_host *host = nand_chip->priv;
566 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
567 int16_t __iomem *index_of = host->pmecc_index_of;
568 int16_t *partial_syn = host->pmecc_partial_syn;
569 const int cap = host->pmecc_corr_cap;
570 int16_t *si;
571 int i, j;
572
573 /* si[] is a table that holds the current syndrome value,
574 * an element of that table belongs to the field
575 */
576 si = host->pmecc_si;
577
578 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
579
580 /* Computation 2t syndromes based on S(x) */
581 /* Odd syndromes */
582 for (i = 1; i < 2 * cap; i += 2) {
583 for (j = 0; j < host->pmecc_degree; j++) {
584 if (partial_syn[i] & ((unsigned short)0x1 << j))
585 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
586 }
587 }
588 /* Even syndrome = (Odd syndrome) ** 2 */
589 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
590 if (si[j] == 0) {
591 si[i] = 0;
592 } else {
593 int16_t tmp;
594
595 tmp = readw_relaxed(index_of + si[j]);
596 tmp = (tmp * 2) % host->pmecc_cw_len;
597 si[i] = readw_relaxed(alpha_to + tmp);
598 }
599 }
600
601 return;
602 }
603
604 static void pmecc_get_sigma(struct mtd_info *mtd)
605 {
606 struct nand_chip *nand_chip = mtd->priv;
607 struct atmel_nand_host *host = nand_chip->priv;
608
609 int16_t *lmu = host->pmecc_lmu;
610 int16_t *si = host->pmecc_si;
611 int *mu = host->pmecc_mu;
612 int *dmu = host->pmecc_dmu; /* Discrepancy */
613 int *delta = host->pmecc_delta; /* Delta order */
614 int cw_len = host->pmecc_cw_len;
615 const int16_t cap = host->pmecc_corr_cap;
616 const int num = 2 * cap + 1;
617 int16_t __iomem *index_of = host->pmecc_index_of;
618 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
619 int i, j, k;
620 uint32_t dmu_0_count, tmp;
621 int16_t *smu = host->pmecc_smu;
622
623 /* index of largest delta */
624 int ro;
625 int largest;
626 int diff;
627
628 dmu_0_count = 0;
629
630 /* First Row */
631
632 /* Mu */
633 mu[0] = -1;
634
635 memset(smu, 0, sizeof(int16_t) * num);
636 smu[0] = 1;
637
638 /* discrepancy set to 1 */
639 dmu[0] = 1;
640 /* polynom order set to 0 */
641 lmu[0] = 0;
642 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
643
644 /* Second Row */
645
646 /* Mu */
647 mu[1] = 0;
648 /* Sigma(x) set to 1 */
649 memset(&smu[num], 0, sizeof(int16_t) * num);
650 smu[num] = 1;
651
652 /* discrepancy set to S1 */
653 dmu[1] = si[1];
654
655 /* polynom order set to 0 */
656 lmu[1] = 0;
657
658 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
659
660 /* Init the Sigma(x) last row */
661 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
662
663 for (i = 1; i <= cap; i++) {
664 mu[i + 1] = i << 1;
665 /* Begin Computing Sigma (Mu+1) and L(mu) */
666 /* check if discrepancy is set to 0 */
667 if (dmu[i] == 0) {
668 dmu_0_count++;
669
670 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
671 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
672 tmp += 2;
673 else
674 tmp += 1;
675
676 if (dmu_0_count == tmp) {
677 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
678 smu[(cap + 1) * num + j] =
679 smu[i * num + j];
680
681 lmu[cap + 1] = lmu[i];
682 return;
683 }
684
685 /* copy polynom */
686 for (j = 0; j <= lmu[i] >> 1; j++)
687 smu[(i + 1) * num + j] = smu[i * num + j];
688
689 /* copy previous polynom order to the next */
690 lmu[i + 1] = lmu[i];
691 } else {
692 ro = 0;
693 largest = -1;
694 /* find largest delta with dmu != 0 */
695 for (j = 0; j < i; j++) {
696 if ((dmu[j]) && (delta[j] > largest)) {
697 largest = delta[j];
698 ro = j;
699 }
700 }
701
702 /* compute difference */
703 diff = (mu[i] - mu[ro]);
704
705 /* Compute degree of the new smu polynomial */
706 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
707 lmu[i + 1] = lmu[i];
708 else
709 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
710
711 /* Init smu[i+1] with 0 */
712 for (k = 0; k < num; k++)
713 smu[(i + 1) * num + k] = 0;
714
715 /* Compute smu[i+1] */
716 for (k = 0; k <= lmu[ro] >> 1; k++) {
717 int16_t a, b, c;
718
719 if (!(smu[ro * num + k] && dmu[i]))
720 continue;
721 a = readw_relaxed(index_of + dmu[i]);
722 b = readw_relaxed(index_of + dmu[ro]);
723 c = readw_relaxed(index_of + smu[ro * num + k]);
724 tmp = a + (cw_len - b) + c;
725 a = readw_relaxed(alpha_to + tmp % cw_len);
726 smu[(i + 1) * num + (k + diff)] = a;
727 }
728
729 for (k = 0; k <= lmu[i] >> 1; k++)
730 smu[(i + 1) * num + k] ^= smu[i * num + k];
731 }
732
733 /* End Computing Sigma (Mu+1) and L(mu) */
734 /* In either case compute delta */
735 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
736
737 /* Do not compute discrepancy for the last iteration */
738 if (i >= cap)
739 continue;
740
741 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
742 tmp = 2 * (i - 1);
743 if (k == 0) {
744 dmu[i + 1] = si[tmp + 3];
745 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
746 int16_t a, b, c;
747 a = readw_relaxed(index_of +
748 smu[(i + 1) * num + k]);
749 b = si[2 * (i - 1) + 3 - k];
750 c = readw_relaxed(index_of + b);
751 tmp = a + c;
752 tmp %= cw_len;
753 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
754 dmu[i + 1];
755 }
756 }
757 }
758
759 return;
760 }
761
762 static int pmecc_err_location(struct mtd_info *mtd)
763 {
764 struct nand_chip *nand_chip = mtd->priv;
765 struct atmel_nand_host *host = nand_chip->priv;
766 unsigned long end_time;
767 const int cap = host->pmecc_corr_cap;
768 const int num = 2 * cap + 1;
769 int sector_size = host->pmecc_sector_size;
770 int err_nbr = 0; /* number of error */
771 int roots_nbr; /* number of roots */
772 int i;
773 uint32_t val;
774 int16_t *smu = host->pmecc_smu;
775
776 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
777
778 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
779 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
780 smu[(cap + 1) * num + i]);
781 err_nbr++;
782 }
783
784 val = (err_nbr - 1) << 16;
785 if (sector_size == 1024)
786 val |= 1;
787
788 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
789 pmerrloc_writel(host->pmerrloc_base, ELEN,
790 sector_size * 8 + host->pmecc_degree * cap);
791
792 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
793 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
794 & PMERRLOC_CALC_DONE)) {
795 if (unlikely(time_after(jiffies, end_time))) {
796 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
797 return -1;
798 }
799 cpu_relax();
800 }
801
802 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
803 & PMERRLOC_ERR_NUM_MASK) >> 8;
804 /* Number of roots == degree of smu hence <= cap */
805 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
806 return err_nbr - 1;
807
808 /* Number of roots does not match the degree of smu
809 * unable to correct error */
810 return -1;
811 }
812
813 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
814 int sector_num, int extra_bytes, int err_nbr)
815 {
816 struct nand_chip *nand_chip = mtd->priv;
817 struct atmel_nand_host *host = nand_chip->priv;
818 int i = 0;
819 int byte_pos, bit_pos, sector_size, pos;
820 uint32_t tmp;
821 uint8_t err_byte;
822
823 sector_size = host->pmecc_sector_size;
824
825 while (err_nbr) {
826 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
827 byte_pos = tmp / 8;
828 bit_pos = tmp % 8;
829
830 if (byte_pos >= (sector_size + extra_bytes))
831 BUG(); /* should never happen */
832
833 if (byte_pos < sector_size) {
834 err_byte = *(buf + byte_pos);
835 *(buf + byte_pos) ^= (1 << bit_pos);
836
837 pos = sector_num * host->pmecc_sector_size + byte_pos;
838 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
839 pos, bit_pos, err_byte, *(buf + byte_pos));
840 } else {
841 /* Bit flip in OOB area */
842 tmp = sector_num * host->pmecc_bytes_per_sector
843 + (byte_pos - sector_size);
844 err_byte = ecc[tmp];
845 ecc[tmp] ^= (1 << bit_pos);
846
847 pos = tmp + nand_chip->ecc.layout->eccpos[0];
848 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
849 pos, bit_pos, err_byte, ecc[tmp]);
850 }
851
852 i++;
853 err_nbr--;
854 }
855
856 return;
857 }
858
859 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
860 u8 *ecc)
861 {
862 struct nand_chip *nand_chip = mtd->priv;
863 struct atmel_nand_host *host = nand_chip->priv;
864 int i, err_nbr;
865 uint8_t *buf_pos;
866 int total_err = 0;
867
868 for (i = 0; i < nand_chip->ecc.total; i++)
869 if (ecc[i] != 0xff)
870 goto normal_check;
871 /* Erased page, return OK */
872 return 0;
873
874 normal_check:
875 for (i = 0; i < host->pmecc_sector_number; i++) {
876 err_nbr = 0;
877 if (pmecc_stat & 0x1) {
878 buf_pos = buf + i * host->pmecc_sector_size;
879
880 pmecc_gen_syndrome(mtd, i);
881 pmecc_substitute(mtd);
882 pmecc_get_sigma(mtd);
883
884 err_nbr = pmecc_err_location(mtd);
885 if (err_nbr == -1) {
886 dev_err(host->dev, "PMECC: Too many errors\n");
887 mtd->ecc_stats.failed++;
888 return -EIO;
889 } else {
890 pmecc_correct_data(mtd, buf_pos, ecc, i,
891 host->pmecc_bytes_per_sector, err_nbr);
892 mtd->ecc_stats.corrected += err_nbr;
893 total_err += err_nbr;
894 }
895 }
896 pmecc_stat >>= 1;
897 }
898
899 return total_err;
900 }
901
902 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
903 {
904 u32 val;
905
906 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
907 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
908 return;
909 }
910
911 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
912 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
913 val = pmecc_readl_relaxed(host->ecc, CFG);
914
915 if (ecc_op == NAND_ECC_READ)
916 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
917 | PMECC_CFG_AUTO_ENABLE);
918 else
919 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
920 & ~PMECC_CFG_AUTO_ENABLE);
921
922 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
923 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
924 }
925
926 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
927 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
928 {
929 struct atmel_nand_host *host = chip->priv;
930 int eccsize = chip->ecc.size * chip->ecc.steps;
931 uint8_t *oob = chip->oob_poi;
932 uint32_t *eccpos = chip->ecc.layout->eccpos;
933 uint32_t stat;
934 unsigned long end_time;
935 int bitflips = 0;
936
937 if (!host->nfc || !host->nfc->use_nfc_sram)
938 pmecc_enable(host, NAND_ECC_READ);
939
940 chip->read_buf(mtd, buf, eccsize);
941 chip->read_buf(mtd, oob, mtd->oobsize);
942
943 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
944 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
945 if (unlikely(time_after(jiffies, end_time))) {
946 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
947 return -EIO;
948 }
949 cpu_relax();
950 }
951
952 stat = pmecc_readl_relaxed(host->ecc, ISR);
953 if (stat != 0) {
954 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
955 if (bitflips < 0)
956 /* uncorrectable errors */
957 return 0;
958 }
959
960 return bitflips;
961 }
962
963 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
964 struct nand_chip *chip, const uint8_t *buf, int oob_required)
965 {
966 struct atmel_nand_host *host = chip->priv;
967 uint32_t *eccpos = chip->ecc.layout->eccpos;
968 int i, j;
969 unsigned long end_time;
970
971 if (!host->nfc || !host->nfc->write_by_sram) {
972 pmecc_enable(host, NAND_ECC_WRITE);
973 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
974 }
975
976 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
977 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
978 if (unlikely(time_after(jiffies, end_time))) {
979 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
980 return -EIO;
981 }
982 cpu_relax();
983 }
984
985 for (i = 0; i < host->pmecc_sector_number; i++) {
986 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
987 int pos;
988
989 pos = i * host->pmecc_bytes_per_sector + j;
990 chip->oob_poi[eccpos[pos]] =
991 pmecc_readb_ecc_relaxed(host->ecc, i, j);
992 }
993 }
994 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
995
996 return 0;
997 }
998
999 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1000 {
1001 struct nand_chip *nand_chip = mtd->priv;
1002 struct atmel_nand_host *host = nand_chip->priv;
1003 uint32_t val = 0;
1004 struct nand_ecclayout *ecc_layout;
1005
1006 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1007 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1008
1009 switch (host->pmecc_corr_cap) {
1010 case 2:
1011 val = PMECC_CFG_BCH_ERR2;
1012 break;
1013 case 4:
1014 val = PMECC_CFG_BCH_ERR4;
1015 break;
1016 case 8:
1017 val = PMECC_CFG_BCH_ERR8;
1018 break;
1019 case 12:
1020 val = PMECC_CFG_BCH_ERR12;
1021 break;
1022 case 24:
1023 val = PMECC_CFG_BCH_ERR24;
1024 break;
1025 }
1026
1027 if (host->pmecc_sector_size == 512)
1028 val |= PMECC_CFG_SECTOR512;
1029 else if (host->pmecc_sector_size == 1024)
1030 val |= PMECC_CFG_SECTOR1024;
1031
1032 switch (host->pmecc_sector_number) {
1033 case 1:
1034 val |= PMECC_CFG_PAGE_1SECTOR;
1035 break;
1036 case 2:
1037 val |= PMECC_CFG_PAGE_2SECTORS;
1038 break;
1039 case 4:
1040 val |= PMECC_CFG_PAGE_4SECTORS;
1041 break;
1042 case 8:
1043 val |= PMECC_CFG_PAGE_8SECTORS;
1044 break;
1045 }
1046
1047 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1048 | PMECC_CFG_AUTO_DISABLE);
1049 pmecc_writel(host->ecc, CFG, val);
1050
1051 ecc_layout = nand_chip->ecc.layout;
1052 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1053 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1054 pmecc_writel(host->ecc, EADDR,
1055 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1056 /* See datasheet about PMECC Clock Control Register */
1057 pmecc_writel(host->ecc, CLK, 2);
1058 pmecc_writel(host->ecc, IDR, 0xff);
1059 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1060 }
1061
1062 /*
1063 * Get minimum ecc requirements from NAND.
1064 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1065 * will set them according to minimum ecc requirement. Otherwise, use the
1066 * value in DTS file.
1067 * return 0 if success. otherwise return error code.
1068 */
1069 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1070 int *cap, int *sector_size)
1071 {
1072 /* Get minimum ECC requirements */
1073 if (host->nand_chip.ecc_strength_ds) {
1074 *cap = host->nand_chip.ecc_strength_ds;
1075 *sector_size = host->nand_chip.ecc_step_ds;
1076 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1077 *cap, *sector_size);
1078 } else {
1079 *cap = 2;
1080 *sector_size = 512;
1081 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1082 }
1083
1084 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1085 if (host->pmecc_corr_cap == 0) {
1086 /* use the most fitable ecc bits (the near bigger one ) */
1087 if (*cap <= 2)
1088 host->pmecc_corr_cap = 2;
1089 else if (*cap <= 4)
1090 host->pmecc_corr_cap = 4;
1091 else if (*cap <= 8)
1092 host->pmecc_corr_cap = 8;
1093 else if (*cap <= 12)
1094 host->pmecc_corr_cap = 12;
1095 else if (*cap <= 24)
1096 host->pmecc_corr_cap = 24;
1097 else
1098 return -EINVAL;
1099 }
1100 if (host->pmecc_sector_size == 0) {
1101 /* use the most fitable sector size (the near smaller one ) */
1102 if (*sector_size >= 1024)
1103 host->pmecc_sector_size = 1024;
1104 else if (*sector_size >= 512)
1105 host->pmecc_sector_size = 512;
1106 else
1107 return -EINVAL;
1108 }
1109 return 0;
1110 }
1111
1112 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1113 struct atmel_nand_host *host)
1114 {
1115 struct mtd_info *mtd = &host->mtd;
1116 struct nand_chip *nand_chip = &host->nand_chip;
1117 struct resource *regs, *regs_pmerr, *regs_rom;
1118 int cap, sector_size, err_no;
1119
1120 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1121 if (err_no) {
1122 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1123 return err_no;
1124 }
1125
1126 if (cap > host->pmecc_corr_cap ||
1127 sector_size != host->pmecc_sector_size)
1128 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1129
1130 cap = host->pmecc_corr_cap;
1131 sector_size = host->pmecc_sector_size;
1132 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1133 host->pmecc_lookup_table_offset_512 :
1134 host->pmecc_lookup_table_offset_1024;
1135
1136 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1137 cap, sector_size);
1138
1139 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1140 if (!regs) {
1141 dev_warn(host->dev,
1142 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1143 nand_chip->ecc.mode = NAND_ECC_SOFT;
1144 return 0;
1145 }
1146
1147 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1148 if (IS_ERR(host->ecc)) {
1149 dev_err(host->dev, "ioremap failed\n");
1150 err_no = PTR_ERR(host->ecc);
1151 goto err;
1152 }
1153
1154 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1155 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1156 if (IS_ERR(host->pmerrloc_base)) {
1157 dev_err(host->dev,
1158 "Can not get I/O resource for PMECC ERRLOC controller!\n");
1159 err_no = PTR_ERR(host->pmerrloc_base);
1160 goto err;
1161 }
1162
1163 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1164 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom);
1165 if (IS_ERR(host->pmecc_rom_base)) {
1166 dev_err(host->dev, "Can not get I/O resource for ROM!\n");
1167 err_no = PTR_ERR(host->pmecc_rom_base);
1168 goto err;
1169 }
1170
1171 nand_chip->ecc.size = sector_size;
1172
1173 /* set ECC page size and oob layout */
1174 switch (mtd->writesize) {
1175 case 2048:
1176 host->pmecc_degree = (sector_size == 512) ?
1177 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1178 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1179 host->pmecc_sector_number = mtd->writesize / sector_size;
1180 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
1181 cap, sector_size);
1182 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1183 host->pmecc_index_of = host->pmecc_rom_base +
1184 host->pmecc_lookup_table_offset;
1185
1186 nand_chip->ecc.steps = host->pmecc_sector_number;
1187 nand_chip->ecc.strength = cap;
1188 nand_chip->ecc.bytes = host->pmecc_bytes_per_sector;
1189 nand_chip->ecc.total = host->pmecc_bytes_per_sector *
1190 host->pmecc_sector_number;
1191 if (nand_chip->ecc.total > mtd->oobsize - 2) {
1192 dev_err(host->dev, "No room for ECC bytes\n");
1193 err_no = -EINVAL;
1194 goto err;
1195 }
1196 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1197 mtd->oobsize,
1198 nand_chip->ecc.total);
1199
1200 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1201 break;
1202 case 512:
1203 case 1024:
1204 case 4096:
1205 /* TODO */
1206 dev_warn(host->dev,
1207 "Unsupported page size for PMECC, use Software ECC\n");
1208 default:
1209 /* page size not handled by HW ECC */
1210 /* switching back to soft ECC */
1211 nand_chip->ecc.mode = NAND_ECC_SOFT;
1212 return 0;
1213 }
1214
1215 /* Allocate data for PMECC computation */
1216 err_no = pmecc_data_alloc(host);
1217 if (err_no) {
1218 dev_err(host->dev,
1219 "Cannot allocate memory for PMECC computation!\n");
1220 goto err;
1221 }
1222
1223 nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1224 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1225 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1226
1227 atmel_pmecc_core_init(mtd);
1228
1229 return 0;
1230
1231 err:
1232 return err_no;
1233 }
1234
1235 /*
1236 * Calculate HW ECC
1237 *
1238 * function called after a write
1239 *
1240 * mtd: MTD block structure
1241 * dat: raw data (unused)
1242 * ecc_code: buffer for ECC
1243 */
1244 static int atmel_nand_calculate(struct mtd_info *mtd,
1245 const u_char *dat, unsigned char *ecc_code)
1246 {
1247 struct nand_chip *nand_chip = mtd->priv;
1248 struct atmel_nand_host *host = nand_chip->priv;
1249 unsigned int ecc_value;
1250
1251 /* get the first 2 ECC bytes */
1252 ecc_value = ecc_readl(host->ecc, PR);
1253
1254 ecc_code[0] = ecc_value & 0xFF;
1255 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1256
1257 /* get the last 2 ECC bytes */
1258 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1259
1260 ecc_code[2] = ecc_value & 0xFF;
1261 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1262
1263 return 0;
1264 }
1265
1266 /*
1267 * HW ECC read page function
1268 *
1269 * mtd: mtd info structure
1270 * chip: nand chip info structure
1271 * buf: buffer to store read data
1272 * oob_required: caller expects OOB data read to chip->oob_poi
1273 */
1274 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1275 uint8_t *buf, int oob_required, int page)
1276 {
1277 int eccsize = chip->ecc.size;
1278 int eccbytes = chip->ecc.bytes;
1279 uint32_t *eccpos = chip->ecc.layout->eccpos;
1280 uint8_t *p = buf;
1281 uint8_t *oob = chip->oob_poi;
1282 uint8_t *ecc_pos;
1283 int stat;
1284 unsigned int max_bitflips = 0;
1285
1286 /*
1287 * Errata: ALE is incorrectly wired up to the ECC controller
1288 * on the AP7000, so it will include the address cycles in the
1289 * ECC calculation.
1290 *
1291 * Workaround: Reset the parity registers before reading the
1292 * actual data.
1293 */
1294 struct atmel_nand_host *host = chip->priv;
1295 if (host->board.need_reset_workaround)
1296 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1297
1298 /* read the page */
1299 chip->read_buf(mtd, p, eccsize);
1300
1301 /* move to ECC position if needed */
1302 if (eccpos[0] != 0) {
1303 /* This only works on large pages
1304 * because the ECC controller waits for
1305 * NAND_CMD_RNDOUTSTART after the
1306 * NAND_CMD_RNDOUT.
1307 * anyway, for small pages, the eccpos[0] == 0
1308 */
1309 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1310 mtd->writesize + eccpos[0], -1);
1311 }
1312
1313 /* the ECC controller needs to read the ECC just after the data */
1314 ecc_pos = oob + eccpos[0];
1315 chip->read_buf(mtd, ecc_pos, eccbytes);
1316
1317 /* check if there's an error */
1318 stat = chip->ecc.correct(mtd, p, oob, NULL);
1319
1320 if (stat < 0) {
1321 mtd->ecc_stats.failed++;
1322 } else {
1323 mtd->ecc_stats.corrected += stat;
1324 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1325 }
1326
1327 /* get back to oob start (end of page) */
1328 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1329
1330 /* read the oob */
1331 chip->read_buf(mtd, oob, mtd->oobsize);
1332
1333 return max_bitflips;
1334 }
1335
1336 /*
1337 * HW ECC Correction
1338 *
1339 * function called after a read
1340 *
1341 * mtd: MTD block structure
1342 * dat: raw data read from the chip
1343 * read_ecc: ECC from the chip (unused)
1344 * isnull: unused
1345 *
1346 * Detect and correct a 1 bit error for a page
1347 */
1348 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1349 u_char *read_ecc, u_char *isnull)
1350 {
1351 struct nand_chip *nand_chip = mtd->priv;
1352 struct atmel_nand_host *host = nand_chip->priv;
1353 unsigned int ecc_status;
1354 unsigned int ecc_word, ecc_bit;
1355
1356 /* get the status from the Status Register */
1357 ecc_status = ecc_readl(host->ecc, SR);
1358
1359 /* if there's no error */
1360 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1361 return 0;
1362
1363 /* get error bit offset (4 bits) */
1364 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1365 /* get word address (12 bits) */
1366 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1367 ecc_word >>= 4;
1368
1369 /* if there are multiple errors */
1370 if (ecc_status & ATMEL_ECC_MULERR) {
1371 /* check if it is a freshly erased block
1372 * (filled with 0xff) */
1373 if ((ecc_bit == ATMEL_ECC_BITADDR)
1374 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1375 /* the block has just been erased, return OK */
1376 return 0;
1377 }
1378 /* it doesn't seems to be a freshly
1379 * erased block.
1380 * We can't correct so many errors */
1381 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1382 " Unable to correct.\n");
1383 return -EIO;
1384 }
1385
1386 /* if there's a single bit error : we can correct it */
1387 if (ecc_status & ATMEL_ECC_ECCERR) {
1388 /* there's nothing much to do here.
1389 * the bit error is on the ECC itself.
1390 */
1391 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1392 " Nothing to correct\n");
1393 return 0;
1394 }
1395
1396 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1397 " (word offset in the page :"
1398 " 0x%x bit offset : 0x%x)\n",
1399 ecc_word, ecc_bit);
1400 /* correct the error */
1401 if (nand_chip->options & NAND_BUSWIDTH_16) {
1402 /* 16 bits words */
1403 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1404 } else {
1405 /* 8 bits words */
1406 dat[ecc_word] ^= (1 << ecc_bit);
1407 }
1408 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1409 return 1;
1410 }
1411
1412 /*
1413 * Enable HW ECC : unused on most chips
1414 */
1415 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1416 {
1417 struct nand_chip *nand_chip = mtd->priv;
1418 struct atmel_nand_host *host = nand_chip->priv;
1419
1420 if (host->board.need_reset_workaround)
1421 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1422 }
1423
1424 static int atmel_of_init_port(struct atmel_nand_host *host,
1425 struct device_node *np)
1426 {
1427 u32 val;
1428 u32 offset[2];
1429 int ecc_mode;
1430 struct atmel_nand_data *board = &host->board;
1431 enum of_gpio_flags flags = 0;
1432
1433 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1434 if (val >= 32) {
1435 dev_err(host->dev, "invalid addr-offset %u\n", val);
1436 return -EINVAL;
1437 }
1438 board->ale = val;
1439 }
1440
1441 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1442 if (val >= 32) {
1443 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1444 return -EINVAL;
1445 }
1446 board->cle = val;
1447 }
1448
1449 ecc_mode = of_get_nand_ecc_mode(np);
1450
1451 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1452
1453 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1454
1455 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1456
1457 if (of_get_nand_bus_width(np) == 16)
1458 board->bus_width_16 = 1;
1459
1460 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1461 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1462
1463 board->enable_pin = of_get_gpio(np, 1);
1464 board->det_pin = of_get_gpio(np, 2);
1465
1466 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1467
1468 /* load the nfc driver if there is */
1469 of_platform_populate(np, NULL, NULL, host->dev);
1470
1471 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1472 return 0; /* Not using PMECC */
1473
1474 /* use PMECC, get correction capability, sector size and lookup
1475 * table offset.
1476 * If correction bits and sector size are not specified, then find
1477 * them from NAND ONFI parameters.
1478 */
1479 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1480 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1481 (val != 24)) {
1482 dev_err(host->dev,
1483 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1484 val);
1485 return -EINVAL;
1486 }
1487 host->pmecc_corr_cap = (u8)val;
1488 }
1489
1490 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1491 if ((val != 512) && (val != 1024)) {
1492 dev_err(host->dev,
1493 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1494 val);
1495 return -EINVAL;
1496 }
1497 host->pmecc_sector_size = (u16)val;
1498 }
1499
1500 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1501 offset, 2) != 0) {
1502 dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
1503 return -EINVAL;
1504 }
1505 if (!offset[0] && !offset[1]) {
1506 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1507 return -EINVAL;
1508 }
1509 host->pmecc_lookup_table_offset_512 = offset[0];
1510 host->pmecc_lookup_table_offset_1024 = offset[1];
1511
1512 return 0;
1513 }
1514
1515 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1516 struct atmel_nand_host *host)
1517 {
1518 struct mtd_info *mtd = &host->mtd;
1519 struct nand_chip *nand_chip = &host->nand_chip;
1520 struct resource *regs;
1521
1522 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1523 if (!regs) {
1524 dev_err(host->dev,
1525 "Can't get I/O resource regs, use software ECC\n");
1526 nand_chip->ecc.mode = NAND_ECC_SOFT;
1527 return 0;
1528 }
1529
1530 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1531 if (IS_ERR(host->ecc)) {
1532 dev_err(host->dev, "ioremap failed\n");
1533 return PTR_ERR(host->ecc);
1534 }
1535
1536 /* ECC is calculated for the whole page (1 step) */
1537 nand_chip->ecc.size = mtd->writesize;
1538
1539 /* set ECC page size and oob layout */
1540 switch (mtd->writesize) {
1541 case 512:
1542 nand_chip->ecc.layout = &atmel_oobinfo_small;
1543 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1544 break;
1545 case 1024:
1546 nand_chip->ecc.layout = &atmel_oobinfo_large;
1547 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1548 break;
1549 case 2048:
1550 nand_chip->ecc.layout = &atmel_oobinfo_large;
1551 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1552 break;
1553 case 4096:
1554 nand_chip->ecc.layout = &atmel_oobinfo_large;
1555 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1556 break;
1557 default:
1558 /* page size not handled by HW ECC */
1559 /* switching back to soft ECC */
1560 nand_chip->ecc.mode = NAND_ECC_SOFT;
1561 return 0;
1562 }
1563
1564 /* set up for HW ECC */
1565 nand_chip->ecc.calculate = atmel_nand_calculate;
1566 nand_chip->ecc.correct = atmel_nand_correct;
1567 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1568 nand_chip->ecc.read_page = atmel_nand_read_page;
1569 nand_chip->ecc.bytes = 4;
1570 nand_chip->ecc.strength = 1;
1571
1572 return 0;
1573 }
1574
1575 static inline u32 nfc_read_status(struct atmel_nand_host *host)
1576 {
1577 u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1578 u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1579
1580 if (unlikely(nfc_status & err_flags)) {
1581 if (nfc_status & NFC_SR_DTOE)
1582 dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1583 else if (nfc_status & NFC_SR_UNDEF)
1584 dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1585 else if (nfc_status & NFC_SR_AWB)
1586 dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1587 else if (nfc_status & NFC_SR_ASE)
1588 dev_err(host->dev, "NFC: Access memory Size Error\n");
1589 }
1590
1591 return nfc_status;
1592 }
1593
1594 /* SMC interrupt service routine */
1595 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1596 {
1597 struct atmel_nand_host *host = dev_id;
1598 u32 status, mask, pending;
1599 irqreturn_t ret = IRQ_HANDLED;
1600
1601 status = nfc_read_status(host);
1602 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1603 pending = status & mask;
1604
1605 if (pending & NFC_SR_XFR_DONE) {
1606 complete(&host->nfc->comp_nfc);
1607 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1608 } else if (pending & NFC_SR_RB_EDGE) {
1609 complete(&host->nfc->comp_nfc);
1610 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1611 } else if (pending & NFC_SR_CMD_DONE) {
1612 complete(&host->nfc->comp_nfc);
1613 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1614 } else {
1615 ret = IRQ_NONE;
1616 }
1617
1618 return ret;
1619 }
1620
1621 /* NFC(Nand Flash Controller) related functions */
1622 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1623 {
1624 unsigned long timeout;
1625 init_completion(&host->nfc->comp_nfc);
1626
1627 /* Enable interrupt that need to wait for */
1628 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1629
1630 timeout = wait_for_completion_timeout(&host->nfc->comp_nfc,
1631 msecs_to_jiffies(NFC_TIME_OUT_MS));
1632 if (timeout)
1633 return 0;
1634
1635 /* Time out to wait for the interrupt */
1636 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1637 return -ETIMEDOUT;
1638 }
1639
1640 static int nfc_send_command(struct atmel_nand_host *host,
1641 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1642 {
1643 unsigned long timeout;
1644 dev_dbg(host->dev,
1645 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1646 cmd, addr, cycle0);
1647
1648 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1649 while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs)
1650 & NFCADDR_CMD_NFCBUSY) {
1651 if (time_after(jiffies, timeout)) {
1652 dev_err(host->dev,
1653 "Time out to wait CMD_NFCBUSY ready!\n");
1654 return -ETIMEDOUT;
1655 }
1656 }
1657 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1658 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1659 return nfc_wait_interrupt(host, NFC_SR_CMD_DONE);
1660 }
1661
1662 static int nfc_device_ready(struct mtd_info *mtd)
1663 {
1664 struct nand_chip *nand_chip = mtd->priv;
1665 struct atmel_nand_host *host = nand_chip->priv;
1666 if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE))
1667 return 1;
1668 return 0;
1669 }
1670
1671 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1672 {
1673 struct nand_chip *nand_chip = mtd->priv;
1674 struct atmel_nand_host *host = nand_chip->priv;
1675
1676 if (chip == -1)
1677 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1678 else
1679 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1680 }
1681
1682 static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1683 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1684 {
1685 struct nand_chip *chip = mtd->priv;
1686
1687 int acycle = 0;
1688 unsigned char addr_bytes[8];
1689 int index = 0, bit_shift;
1690
1691 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1692
1693 *cycle0 = 0;
1694 *addr1234 = 0;
1695
1696 if (column != -1) {
1697 if (chip->options & NAND_BUSWIDTH_16 &&
1698 !nand_opcode_8bits(command))
1699 column >>= 1;
1700 addr_bytes[acycle++] = column & 0xff;
1701 if (mtd->writesize > 512)
1702 addr_bytes[acycle++] = (column >> 8) & 0xff;
1703 }
1704
1705 if (page_addr != -1) {
1706 addr_bytes[acycle++] = page_addr & 0xff;
1707 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1708 if (chip->chipsize > (128 << 20))
1709 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1710 }
1711
1712 if (acycle > 4)
1713 *cycle0 = addr_bytes[index++];
1714
1715 for (bit_shift = 0; index < acycle; bit_shift += 8)
1716 *addr1234 += addr_bytes[index++] << bit_shift;
1717
1718 /* return acycle in cmd register */
1719 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1720 }
1721
1722 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1723 int column, int page_addr)
1724 {
1725 struct nand_chip *chip = mtd->priv;
1726 struct atmel_nand_host *host = chip->priv;
1727 unsigned long timeout;
1728 unsigned int nfc_addr_cmd = 0;
1729
1730 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1731
1732 /* Set default settings: no cmd2, no addr cycle. read from nand */
1733 unsigned int cmd2 = 0;
1734 unsigned int vcmd2 = 0;
1735 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1736 int csid = NFCADDR_CMD_CSID_3;
1737 int dataen = NFCADDR_CMD_DATADIS;
1738 int nfcwr = NFCADDR_CMD_NFCRD;
1739 unsigned int addr1234 = 0;
1740 unsigned int cycle0 = 0;
1741 bool do_addr = true;
1742 host->nfc->data_in_sram = NULL;
1743
1744 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1745 __func__, command, column, page_addr);
1746
1747 switch (command) {
1748 case NAND_CMD_RESET:
1749 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1750 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1751 udelay(chip->chip_delay);
1752
1753 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1754 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1755 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1756 if (time_after(jiffies, timeout)) {
1757 dev_err(host->dev,
1758 "Time out to wait status ready!\n");
1759 break;
1760 }
1761 }
1762 return;
1763 case NAND_CMD_STATUS:
1764 do_addr = false;
1765 break;
1766 case NAND_CMD_PARAM:
1767 case NAND_CMD_READID:
1768 do_addr = false;
1769 acycle = NFCADDR_CMD_ACYCLE_1;
1770 if (column != -1)
1771 addr1234 = column;
1772 break;
1773 case NAND_CMD_RNDOUT:
1774 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1775 vcmd2 = NFCADDR_CMD_VCMD2;
1776 break;
1777 case NAND_CMD_READ0:
1778 case NAND_CMD_READOOB:
1779 if (command == NAND_CMD_READOOB) {
1780 column += mtd->writesize;
1781 command = NAND_CMD_READ0; /* only READ0 is valid */
1782 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1783 }
1784 if (host->nfc->use_nfc_sram) {
1785 /* Enable Data transfer to sram */
1786 dataen = NFCADDR_CMD_DATAEN;
1787
1788 /* Need enable PMECC now, since NFC will transfer
1789 * data in bus after sending nfc read command.
1790 */
1791 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1792 pmecc_enable(host, NAND_ECC_READ);
1793 }
1794
1795 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1796 vcmd2 = NFCADDR_CMD_VCMD2;
1797 break;
1798 /* For prgramming command, the cmd need set to write enable */
1799 case NAND_CMD_PAGEPROG:
1800 case NAND_CMD_SEQIN:
1801 case NAND_CMD_RNDIN:
1802 nfcwr = NFCADDR_CMD_NFCWR;
1803 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1804 dataen = NFCADDR_CMD_DATAEN;
1805 break;
1806 default:
1807 break;
1808 }
1809
1810 if (do_addr)
1811 acycle = nfc_make_addr(mtd, command, column, page_addr,
1812 &addr1234, &cycle0);
1813
1814 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1815 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1816
1817 if (dataen == NFCADDR_CMD_DATAEN)
1818 if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE))
1819 dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n");
1820
1821 /*
1822 * Program and erase have their own busy handlers status, sequential
1823 * in, and deplete1 need no delay.
1824 */
1825 switch (command) {
1826 case NAND_CMD_CACHEDPROG:
1827 case NAND_CMD_PAGEPROG:
1828 case NAND_CMD_ERASE1:
1829 case NAND_CMD_ERASE2:
1830 case NAND_CMD_RNDIN:
1831 case NAND_CMD_STATUS:
1832 case NAND_CMD_RNDOUT:
1833 case NAND_CMD_SEQIN:
1834 case NAND_CMD_READID:
1835 return;
1836
1837 case NAND_CMD_READ0:
1838 if (dataen == NFCADDR_CMD_DATAEN) {
1839 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1840 nfc_get_sram_off(host);
1841 return;
1842 }
1843 /* fall through */
1844 default:
1845 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1846 }
1847 }
1848
1849 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1850 uint32_t offset, int data_len, const uint8_t *buf,
1851 int oob_required, int page, int cached, int raw)
1852 {
1853 int cfg, len;
1854 int status = 0;
1855 struct atmel_nand_host *host = chip->priv;
1856 void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1857
1858 /* Subpage write is not supported */
1859 if (offset || (data_len < mtd->writesize))
1860 return -EINVAL;
1861
1862 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1863 len = mtd->writesize;
1864
1865 if (unlikely(raw)) {
1866 len += mtd->oobsize;
1867 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1868 } else
1869 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1870
1871 /* Copy page data to sram that will write to nand via NFC */
1872 if (use_dma) {
1873 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1874 /* Fall back to use cpu copy */
1875 memcpy32_toio(sram, buf, len);
1876 } else {
1877 memcpy32_toio(sram, buf, len);
1878 }
1879
1880 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1881 /*
1882 * When use NFC sram, need set up PMECC before send
1883 * NAND_CMD_SEQIN command. Since when the nand command
1884 * is sent, nfc will do transfer from sram and nand.
1885 */
1886 pmecc_enable(host, NAND_ECC_WRITE);
1887
1888 host->nfc->will_write_sram = true;
1889 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1890 host->nfc->will_write_sram = false;
1891
1892 if (likely(!raw))
1893 /* Need to write ecc into oob */
1894 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
1895
1896 if (status < 0)
1897 return status;
1898
1899 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1900 status = chip->waitfunc(mtd, chip);
1901
1902 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1903 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
1904
1905 if (status & NAND_STATUS_FAIL)
1906 return -EIO;
1907
1908 return 0;
1909 }
1910
1911 static int nfc_sram_init(struct mtd_info *mtd)
1912 {
1913 struct nand_chip *chip = mtd->priv;
1914 struct atmel_nand_host *host = chip->priv;
1915 int res = 0;
1916
1917 /* Initialize the NFC CFG register */
1918 unsigned int cfg_nfc = 0;
1919
1920 /* set page size and oob layout */
1921 switch (mtd->writesize) {
1922 case 512:
1923 cfg_nfc = NFC_CFG_PAGESIZE_512;
1924 break;
1925 case 1024:
1926 cfg_nfc = NFC_CFG_PAGESIZE_1024;
1927 break;
1928 case 2048:
1929 cfg_nfc = NFC_CFG_PAGESIZE_2048;
1930 break;
1931 case 4096:
1932 cfg_nfc = NFC_CFG_PAGESIZE_4096;
1933 break;
1934 case 8192:
1935 cfg_nfc = NFC_CFG_PAGESIZE_8192;
1936 break;
1937 default:
1938 dev_err(host->dev, "Unsupported page size for NFC.\n");
1939 res = -ENXIO;
1940 return res;
1941 }
1942
1943 /* oob bytes size = (NFCSPARESIZE + 1) * 4
1944 * Max support spare size is 512 bytes. */
1945 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1946 & NFC_CFG_NFC_SPARESIZE);
1947 /* default set a max timeout */
1948 cfg_nfc |= NFC_CFG_RSPARE |
1949 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
1950
1951 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
1952
1953 host->nfc->will_write_sram = false;
1954 nfc_set_sram_bank(host, 0);
1955
1956 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
1957 if (host->nfc->write_by_sram) {
1958 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
1959 chip->ecc.mode == NAND_ECC_NONE)
1960 chip->write_page = nfc_sram_write_page;
1961 else
1962 host->nfc->write_by_sram = false;
1963 }
1964
1965 dev_info(host->dev, "Using NFC Sram read %s\n",
1966 host->nfc->write_by_sram ? "and write" : "");
1967 return 0;
1968 }
1969
1970 static struct platform_driver atmel_nand_nfc_driver;
1971 /*
1972 * Probe for the NAND device.
1973 */
1974 static int atmel_nand_probe(struct platform_device *pdev)
1975 {
1976 struct atmel_nand_host *host;
1977 struct mtd_info *mtd;
1978 struct nand_chip *nand_chip;
1979 struct resource *mem;
1980 struct mtd_part_parser_data ppdata = {};
1981 int res, irq;
1982
1983 /* Allocate memory for the device structure (and zero it) */
1984 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
1985 if (!host)
1986 return -ENOMEM;
1987
1988 res = platform_driver_register(&atmel_nand_nfc_driver);
1989 if (res)
1990 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
1991
1992 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1993 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
1994 if (IS_ERR(host->io_base)) {
1995 dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n");
1996 res = PTR_ERR(host->io_base);
1997 goto err_nand_ioremap;
1998 }
1999 host->io_phys = (dma_addr_t)mem->start;
2000
2001 mtd = &host->mtd;
2002 nand_chip = &host->nand_chip;
2003 host->dev = &pdev->dev;
2004 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2005 /* Only when CONFIG_OF is enabled of_node can be parsed */
2006 res = atmel_of_init_port(host, pdev->dev.of_node);
2007 if (res)
2008 goto err_nand_ioremap;
2009 } else {
2010 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2011 sizeof(struct atmel_nand_data));
2012 }
2013
2014 nand_chip->priv = host; /* link the private data structures */
2015 mtd->priv = nand_chip;
2016 mtd->owner = THIS_MODULE;
2017
2018 /* Set address of NAND IO lines */
2019 nand_chip->IO_ADDR_R = host->io_base;
2020 nand_chip->IO_ADDR_W = host->io_base;
2021
2022 if (nand_nfc.is_initialized) {
2023 /* NFC driver is probed and initialized */
2024 host->nfc = &nand_nfc;
2025
2026 nand_chip->select_chip = nfc_select_chip;
2027 nand_chip->dev_ready = nfc_device_ready;
2028 nand_chip->cmdfunc = nfc_nand_command;
2029
2030 /* Initialize the interrupt for NFC */
2031 irq = platform_get_irq(pdev, 0);
2032 if (irq < 0) {
2033 dev_err(host->dev, "Cannot get HSMC irq!\n");
2034 res = irq;
2035 goto err_nand_ioremap;
2036 }
2037
2038 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2039 0, "hsmc", host);
2040 if (res) {
2041 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2042 irq);
2043 goto err_nand_ioremap;
2044 }
2045 } else {
2046 res = atmel_nand_set_enable_ready_pins(mtd);
2047 if (res)
2048 goto err_nand_ioremap;
2049
2050 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2051 }
2052
2053 nand_chip->ecc.mode = host->board.ecc_mode;
2054 nand_chip->chip_delay = 20; /* 20us command delay time */
2055
2056 if (host->board.bus_width_16) /* 16-bit bus width */
2057 nand_chip->options |= NAND_BUSWIDTH_16;
2058
2059 nand_chip->read_buf = atmel_read_buf;
2060 nand_chip->write_buf = atmel_write_buf;
2061
2062 platform_set_drvdata(pdev, host);
2063 atmel_nand_enable(host);
2064
2065 if (gpio_is_valid(host->board.det_pin)) {
2066 res = devm_gpio_request(&pdev->dev,
2067 host->board.det_pin, "nand_det");
2068 if (res < 0) {
2069 dev_err(&pdev->dev,
2070 "can't request det gpio %d\n",
2071 host->board.det_pin);
2072 goto err_no_card;
2073 }
2074
2075 res = gpio_direction_input(host->board.det_pin);
2076 if (res < 0) {
2077 dev_err(&pdev->dev,
2078 "can't request input direction det gpio %d\n",
2079 host->board.det_pin);
2080 goto err_no_card;
2081 }
2082
2083 if (gpio_get_value(host->board.det_pin)) {
2084 dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2085 res = -ENXIO;
2086 goto err_no_card;
2087 }
2088 }
2089
2090 if (host->board.on_flash_bbt || on_flash_bbt) {
2091 dev_info(&pdev->dev, "Use On Flash BBT\n");
2092 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2093 }
2094
2095 if (!host->board.has_dma)
2096 use_dma = 0;
2097
2098 if (use_dma) {
2099 dma_cap_mask_t mask;
2100
2101 dma_cap_zero(mask);
2102 dma_cap_set(DMA_MEMCPY, mask);
2103 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2104 if (!host->dma_chan) {
2105 dev_err(host->dev, "Failed to request DMA channel\n");
2106 use_dma = 0;
2107 }
2108 }
2109 if (use_dma)
2110 dev_info(host->dev, "Using %s for DMA transfers.\n",
2111 dma_chan_name(host->dma_chan));
2112 else
2113 dev_info(host->dev, "No DMA support for NAND access.\n");
2114
2115 /* first scan to find the device and get the page size */
2116 if (nand_scan_ident(mtd, 1, NULL)) {
2117 res = -ENXIO;
2118 goto err_scan_ident;
2119 }
2120
2121 if (nand_chip->ecc.mode == NAND_ECC_HW) {
2122 if (host->has_pmecc)
2123 res = atmel_pmecc_nand_init_params(pdev, host);
2124 else
2125 res = atmel_hw_nand_init_params(pdev, host);
2126
2127 if (res != 0)
2128 goto err_hw_ecc;
2129 }
2130
2131 /* initialize the nfc configuration register */
2132 if (host->nfc && host->nfc->use_nfc_sram) {
2133 res = nfc_sram_init(mtd);
2134 if (res) {
2135 host->nfc->use_nfc_sram = false;
2136 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2137 }
2138 }
2139
2140 /* second phase scan */
2141 if (nand_scan_tail(mtd)) {
2142 res = -ENXIO;
2143 goto err_scan_tail;
2144 }
2145
2146 mtd->name = "atmel_nand";
2147 ppdata.of_node = pdev->dev.of_node;
2148 res = mtd_device_parse_register(mtd, NULL, &ppdata,
2149 host->board.parts, host->board.num_parts);
2150 if (!res)
2151 return res;
2152
2153 err_scan_tail:
2154 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2155 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2156 err_hw_ecc:
2157 err_scan_ident:
2158 err_no_card:
2159 atmel_nand_disable(host);
2160 if (host->dma_chan)
2161 dma_release_channel(host->dma_chan);
2162 err_nand_ioremap:
2163 return res;
2164 }
2165
2166 /*
2167 * Remove a NAND device.
2168 */
2169 static int atmel_nand_remove(struct platform_device *pdev)
2170 {
2171 struct atmel_nand_host *host = platform_get_drvdata(pdev);
2172 struct mtd_info *mtd = &host->mtd;
2173
2174 nand_release(mtd);
2175
2176 atmel_nand_disable(host);
2177
2178 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2179 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2180 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2181 PMERRLOC_DISABLE);
2182 }
2183
2184 if (host->dma_chan)
2185 dma_release_channel(host->dma_chan);
2186
2187 platform_driver_unregister(&atmel_nand_nfc_driver);
2188
2189 return 0;
2190 }
2191
2192 static const struct of_device_id atmel_nand_dt_ids[] = {
2193 { .compatible = "atmel,at91rm9200-nand" },
2194 { /* sentinel */ }
2195 };
2196
2197 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2198
2199 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2200 {
2201 struct atmel_nfc *nfc = &nand_nfc;
2202 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2203
2204 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2205 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2206 if (IS_ERR(nfc->base_cmd_regs))
2207 return PTR_ERR(nfc->base_cmd_regs);
2208
2209 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2210 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2211 if (IS_ERR(nfc->hsmc_regs))
2212 return PTR_ERR(nfc->hsmc_regs);
2213
2214 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2215 if (nfc_sram) {
2216 nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram);
2217 if (IS_ERR(nfc->sram_bank0)) {
2218 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2219 PTR_ERR(nfc->sram_bank0));
2220 } else {
2221 nfc->use_nfc_sram = true;
2222 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2223
2224 if (pdev->dev.of_node)
2225 nfc->write_by_sram = of_property_read_bool(
2226 pdev->dev.of_node,
2227 "atmel,write-by-sram");
2228 }
2229 }
2230
2231 nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2232 nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */
2233
2234 nfc->is_initialized = true;
2235 dev_info(&pdev->dev, "NFC is probed.\n");
2236 return 0;
2237 }
2238
2239 static const struct of_device_id atmel_nand_nfc_match[] = {
2240 { .compatible = "atmel,sama5d3-nfc" },
2241 { /* sentinel */ }
2242 };
2243 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2244
2245 static struct platform_driver atmel_nand_nfc_driver = {
2246 .driver = {
2247 .name = "atmel_nand_nfc",
2248 .owner = THIS_MODULE,
2249 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2250 },
2251 .probe = atmel_nand_nfc_probe,
2252 };
2253
2254 static struct platform_driver atmel_nand_driver = {
2255 .probe = atmel_nand_probe,
2256 .remove = atmel_nand_remove,
2257 .driver = {
2258 .name = "atmel_nand",
2259 .owner = THIS_MODULE,
2260 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2261 },
2262 };
2263
2264 module_platform_driver(atmel_nand_driver);
2265
2266 MODULE_LICENSE("GPL");
2267 MODULE_AUTHOR("Rick Bronson");
2268 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2269 MODULE_ALIAS("platform:atmel_nand");
Linux kernel - Deliverables
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