2 * Copyright © 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #include <linux/dma-mapping.h>
31 #include <linux/slab.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/of_mtd.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/partitions.h>
43 #include <linux/delay.h>
44 #include <linux/dmaengine.h>
45 #include <linux/gpio.h>
46 #include <linux/interrupt.h>
48 #include <linux/platform_data/atmel.h>
50 static int use_dma
= 1;
51 module_param(use_dma
, int, 0);
53 static int on_flash_bbt
= 0;
54 module_param(on_flash_bbt
, int, 0);
56 /* Register access macros */
57 #define ecc_readl(add, reg) \
58 __raw_readl(add + ATMEL_ECC_##reg)
59 #define ecc_writel(add, reg, value) \
60 __raw_writel((value), add + ATMEL_ECC_##reg)
62 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
63 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
65 /* oob layout for large page size
66 * bad block info is on bytes 0 and 1
67 * the bytes have to be consecutives to avoid
68 * several NAND_CMD_RNDOUT during read
70 static struct nand_ecclayout atmel_oobinfo_large
= {
72 .eccpos
= {60, 61, 62, 63},
78 /* oob layout for small page size
79 * bad block info is on bytes 4 and 5
80 * the bytes have to be consecutives to avoid
81 * several NAND_CMD_RNDOUT during read
83 static struct nand_ecclayout atmel_oobinfo_small
= {
85 .eccpos
= {0, 1, 2, 3},
92 void __iomem
*base_cmd_regs
;
93 void __iomem
*hsmc_regs
;
94 void __iomem
*sram_bank0
;
95 dma_addr_t sram_bank0_phys
;
100 struct completion comp_ready
;
101 struct completion comp_cmd_done
;
102 struct completion comp_xfer_done
;
104 /* Point to the sram bank which include readed data via NFC */
105 void __iomem
*data_in_sram
;
106 bool will_write_sram
;
108 static struct atmel_nfc nand_nfc
;
110 struct atmel_nand_host
{
111 struct nand_chip nand_chip
;
113 void __iomem
*io_base
;
115 struct atmel_nand_data board
;
119 struct completion comp
;
120 struct dma_chan
*dma_chan
;
122 struct atmel_nfc
*nfc
;
126 u16 pmecc_sector_size
;
127 u32 pmecc_lookup_table_offset
;
128 u32 pmecc_lookup_table_offset_512
;
129 u32 pmecc_lookup_table_offset_1024
;
131 int pmecc_bytes_per_sector
;
132 int pmecc_sector_number
;
133 int pmecc_degree
; /* Degree of remainders */
134 int pmecc_cw_len
; /* Length of codeword */
136 void __iomem
*pmerrloc_base
;
137 void __iomem
*pmecc_rom_base
;
139 /* lookup table for alpha_to and index_of */
140 void __iomem
*pmecc_alpha_to
;
141 void __iomem
*pmecc_index_of
;
143 /* data for pmecc computation */
144 int16_t *pmecc_partial_syn
;
146 int16_t *pmecc_smu
; /* Sigma table */
147 int16_t *pmecc_lmu
; /* polynomal order */
153 static struct nand_ecclayout atmel_pmecc_oobinfo
;
158 static void atmel_nand_enable(struct atmel_nand_host
*host
)
160 if (gpio_is_valid(host
->board
.enable_pin
))
161 gpio_set_value(host
->board
.enable_pin
, 0);
167 static void atmel_nand_disable(struct atmel_nand_host
*host
)
169 if (gpio_is_valid(host
->board
.enable_pin
))
170 gpio_set_value(host
->board
.enable_pin
, 1);
174 * Hardware specific access to control-lines
176 static void atmel_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
178 struct nand_chip
*nand_chip
= mtd
->priv
;
179 struct atmel_nand_host
*host
= nand_chip
->priv
;
181 if (ctrl
& NAND_CTRL_CHANGE
) {
183 atmel_nand_enable(host
);
185 atmel_nand_disable(host
);
187 if (cmd
== NAND_CMD_NONE
)
191 writeb(cmd
, host
->io_base
+ (1 << host
->board
.cle
));
193 writeb(cmd
, host
->io_base
+ (1 << host
->board
.ale
));
197 * Read the Device Ready pin.
199 static int atmel_nand_device_ready(struct mtd_info
*mtd
)
201 struct nand_chip
*nand_chip
= mtd
->priv
;
202 struct atmel_nand_host
*host
= nand_chip
->priv
;
204 return gpio_get_value(host
->board
.rdy_pin
) ^
205 !!host
->board
.rdy_pin_active_low
;
208 /* Set up for hardware ready pin and enable pin. */
209 static int atmel_nand_set_enable_ready_pins(struct mtd_info
*mtd
)
211 struct nand_chip
*chip
= mtd
->priv
;
212 struct atmel_nand_host
*host
= chip
->priv
;
215 if (gpio_is_valid(host
->board
.rdy_pin
)) {
216 res
= devm_gpio_request(host
->dev
,
217 host
->board
.rdy_pin
, "nand_rdy");
220 "can't request rdy gpio %d\n",
221 host
->board
.rdy_pin
);
225 res
= gpio_direction_input(host
->board
.rdy_pin
);
228 "can't request input direction rdy gpio %d\n",
229 host
->board
.rdy_pin
);
233 chip
->dev_ready
= atmel_nand_device_ready
;
236 if (gpio_is_valid(host
->board
.enable_pin
)) {
237 res
= devm_gpio_request(host
->dev
,
238 host
->board
.enable_pin
, "nand_enable");
241 "can't request enable gpio %d\n",
242 host
->board
.enable_pin
);
246 res
= gpio_direction_output(host
->board
.enable_pin
, 1);
249 "can't request output direction enable gpio %d\n",
250 host
->board
.enable_pin
);
258 static void memcpy32_fromio(void *trg
, const void __iomem
*src
, size_t size
)
262 const __iomem u32
*s
= src
;
264 for (i
= 0; i
< (size
>> 2); i
++)
265 *t
++ = readl_relaxed(s
++);
268 static void memcpy32_toio(void __iomem
*trg
, const void *src
, int size
)
271 u32 __iomem
*t
= trg
;
274 for (i
= 0; i
< (size
>> 2); i
++)
275 writel_relaxed(*s
++, t
++);
279 * Minimal-overhead PIO for data access.
281 static void atmel_read_buf8(struct mtd_info
*mtd
, u8
*buf
, int len
)
283 struct nand_chip
*nand_chip
= mtd
->priv
;
284 struct atmel_nand_host
*host
= nand_chip
->priv
;
286 if (host
->nfc
&& host
->nfc
->use_nfc_sram
&& host
->nfc
->data_in_sram
) {
287 memcpy32_fromio(buf
, host
->nfc
->data_in_sram
, len
);
288 host
->nfc
->data_in_sram
+= len
;
290 __raw_readsb(nand_chip
->IO_ADDR_R
, buf
, len
);
294 static void atmel_read_buf16(struct mtd_info
*mtd
, u8
*buf
, int len
)
296 struct nand_chip
*nand_chip
= mtd
->priv
;
297 struct atmel_nand_host
*host
= nand_chip
->priv
;
299 if (host
->nfc
&& host
->nfc
->use_nfc_sram
&& host
->nfc
->data_in_sram
) {
300 memcpy32_fromio(buf
, host
->nfc
->data_in_sram
, len
);
301 host
->nfc
->data_in_sram
+= len
;
303 __raw_readsw(nand_chip
->IO_ADDR_R
, buf
, len
/ 2);
307 static void atmel_write_buf8(struct mtd_info
*mtd
, const u8
*buf
, int len
)
309 struct nand_chip
*nand_chip
= mtd
->priv
;
311 __raw_writesb(nand_chip
->IO_ADDR_W
, buf
, len
);
314 static void atmel_write_buf16(struct mtd_info
*mtd
, const u8
*buf
, int len
)
316 struct nand_chip
*nand_chip
= mtd
->priv
;
318 __raw_writesw(nand_chip
->IO_ADDR_W
, buf
, len
/ 2);
321 static void dma_complete_func(void *completion
)
323 complete(completion
);
326 static int nfc_set_sram_bank(struct atmel_nand_host
*host
, unsigned int bank
)
328 /* NFC only has two banks. Must be 0 or 1 */
333 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
334 if (host
->mtd
.writesize
> 2048)
336 nfc_writel(host
->nfc
->hsmc_regs
, BANK
, ATMEL_HSMC_NFC_BANK1
);
338 nfc_writel(host
->nfc
->hsmc_regs
, BANK
, ATMEL_HSMC_NFC_BANK0
);
344 static uint
nfc_get_sram_off(struct atmel_nand_host
*host
)
346 if (nfc_readl(host
->nfc
->hsmc_regs
, BANK
) & ATMEL_HSMC_NFC_BANK1
)
347 return NFC_SRAM_BANK1_OFFSET
;
352 static dma_addr_t
nfc_sram_phys(struct atmel_nand_host
*host
)
354 if (nfc_readl(host
->nfc
->hsmc_regs
, BANK
) & ATMEL_HSMC_NFC_BANK1
)
355 return host
->nfc
->sram_bank0_phys
+ NFC_SRAM_BANK1_OFFSET
;
357 return host
->nfc
->sram_bank0_phys
;
360 static int atmel_nand_dma_op(struct mtd_info
*mtd
, void *buf
, int len
,
363 struct dma_device
*dma_dev
;
364 enum dma_ctrl_flags flags
;
365 dma_addr_t dma_src_addr
, dma_dst_addr
, phys_addr
;
366 struct dma_async_tx_descriptor
*tx
= NULL
;
368 struct nand_chip
*chip
= mtd
->priv
;
369 struct atmel_nand_host
*host
= chip
->priv
;
372 enum dma_data_direction dir
= is_read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
373 struct atmel_nfc
*nfc
= host
->nfc
;
375 if (buf
>= high_memory
)
378 dma_dev
= host
->dma_chan
->device
;
380 flags
= DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
;
382 phys_addr
= dma_map_single(dma_dev
->dev
, p
, len
, dir
);
383 if (dma_mapping_error(dma_dev
->dev
, phys_addr
)) {
384 dev_err(host
->dev
, "Failed to dma_map_single\n");
389 if (nfc
&& nfc
->data_in_sram
)
390 dma_src_addr
= nfc_sram_phys(host
) + (nfc
->data_in_sram
391 - (nfc
->sram_bank0
+ nfc_get_sram_off(host
)));
393 dma_src_addr
= host
->io_phys
;
395 dma_dst_addr
= phys_addr
;
397 dma_src_addr
= phys_addr
;
399 if (nfc
&& nfc
->write_by_sram
)
400 dma_dst_addr
= nfc_sram_phys(host
);
402 dma_dst_addr
= host
->io_phys
;
405 tx
= dma_dev
->device_prep_dma_memcpy(host
->dma_chan
, dma_dst_addr
,
406 dma_src_addr
, len
, flags
);
408 dev_err(host
->dev
, "Failed to prepare DMA memcpy\n");
412 init_completion(&host
->comp
);
413 tx
->callback
= dma_complete_func
;
414 tx
->callback_param
= &host
->comp
;
416 cookie
= tx
->tx_submit(tx
);
417 if (dma_submit_error(cookie
)) {
418 dev_err(host
->dev
, "Failed to do DMA tx_submit\n");
422 dma_async_issue_pending(host
->dma_chan
);
423 wait_for_completion(&host
->comp
);
425 if (is_read
&& nfc
&& nfc
->data_in_sram
)
426 /* After read data from SRAM, need to increase the position */
427 nfc
->data_in_sram
+= len
;
432 dma_unmap_single(dma_dev
->dev
, phys_addr
, len
, dir
);
435 dev_dbg(host
->dev
, "Fall back to CPU I/O\n");
439 static void atmel_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
441 struct nand_chip
*chip
= mtd
->priv
;
442 struct atmel_nand_host
*host
= chip
->priv
;
444 if (use_dma
&& len
> mtd
->oobsize
)
445 /* only use DMA for bigger than oob size: better performances */
446 if (atmel_nand_dma_op(mtd
, buf
, len
, 1) == 0)
449 if (host
->board
.bus_width_16
)
450 atmel_read_buf16(mtd
, buf
, len
);
452 atmel_read_buf8(mtd
, buf
, len
);
455 static void atmel_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
457 struct nand_chip
*chip
= mtd
->priv
;
458 struct atmel_nand_host
*host
= chip
->priv
;
460 if (use_dma
&& len
> mtd
->oobsize
)
461 /* only use DMA for bigger than oob size: better performances */
462 if (atmel_nand_dma_op(mtd
, (void *)buf
, len
, 0) == 0)
465 if (host
->board
.bus_width_16
)
466 atmel_write_buf16(mtd
, buf
, len
);
468 atmel_write_buf8(mtd
, buf
, len
);
472 * Return number of ecc bytes per sector according to sector size and
473 * correction capability
475 * Following table shows what at91 PMECC supported:
476 * Correction Capability Sector_512_bytes Sector_1024_bytes
477 * ===================== ================ =================
478 * 2-bits 4-bytes 4-bytes
479 * 4-bits 7-bytes 7-bytes
480 * 8-bits 13-bytes 14-bytes
481 * 12-bits 20-bytes 21-bytes
482 * 24-bits 39-bytes 42-bytes
484 static int pmecc_get_ecc_bytes(int cap
, int sector_size
)
486 int m
= 12 + sector_size
/ 512;
487 return (m
* cap
+ 7) / 8;
490 static void pmecc_config_ecc_layout(struct nand_ecclayout
*layout
,
491 int oobsize
, int ecc_len
)
495 layout
->eccbytes
= ecc_len
;
497 /* ECC will occupy the last ecc_len bytes continuously */
498 for (i
= 0; i
< ecc_len
; i
++)
499 layout
->eccpos
[i
] = oobsize
- ecc_len
+ i
;
501 layout
->oobfree
[0].offset
= 2;
502 layout
->oobfree
[0].length
=
503 oobsize
- ecc_len
- layout
->oobfree
[0].offset
;
506 static void __iomem
*pmecc_get_alpha_to(struct atmel_nand_host
*host
)
510 table_size
= host
->pmecc_sector_size
== 512 ?
511 PMECC_LOOKUP_TABLE_SIZE_512
: PMECC_LOOKUP_TABLE_SIZE_1024
;
513 return host
->pmecc_rom_base
+ host
->pmecc_lookup_table_offset
+
514 table_size
* sizeof(int16_t);
517 static int pmecc_data_alloc(struct atmel_nand_host
*host
)
519 const int cap
= host
->pmecc_corr_cap
;
522 size
= (2 * cap
+ 1) * sizeof(int16_t);
523 host
->pmecc_partial_syn
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
524 host
->pmecc_si
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
525 host
->pmecc_lmu
= devm_kzalloc(host
->dev
,
526 (cap
+ 1) * sizeof(int16_t), GFP_KERNEL
);
527 host
->pmecc_smu
= devm_kzalloc(host
->dev
,
528 (cap
+ 2) * size
, GFP_KERNEL
);
530 size
= (cap
+ 1) * sizeof(int);
531 host
->pmecc_mu
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
532 host
->pmecc_dmu
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
533 host
->pmecc_delta
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
535 if (!host
->pmecc_partial_syn
||
547 static void pmecc_gen_syndrome(struct mtd_info
*mtd
, int sector
)
549 struct nand_chip
*nand_chip
= mtd
->priv
;
550 struct atmel_nand_host
*host
= nand_chip
->priv
;
554 /* Fill odd syndromes */
555 for (i
= 0; i
< host
->pmecc_corr_cap
; i
++) {
556 value
= pmecc_readl_rem_relaxed(host
->ecc
, sector
, i
/ 2);
560 host
->pmecc_partial_syn
[(2 * i
) + 1] = (int16_t)value
;
564 static void pmecc_substitute(struct mtd_info
*mtd
)
566 struct nand_chip
*nand_chip
= mtd
->priv
;
567 struct atmel_nand_host
*host
= nand_chip
->priv
;
568 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
569 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
570 int16_t *partial_syn
= host
->pmecc_partial_syn
;
571 const int cap
= host
->pmecc_corr_cap
;
575 /* si[] is a table that holds the current syndrome value,
576 * an element of that table belongs to the field
580 memset(&si
[1], 0, sizeof(int16_t) * (2 * cap
- 1));
582 /* Computation 2t syndromes based on S(x) */
584 for (i
= 1; i
< 2 * cap
; i
+= 2) {
585 for (j
= 0; j
< host
->pmecc_degree
; j
++) {
586 if (partial_syn
[i
] & ((unsigned short)0x1 << j
))
587 si
[i
] = readw_relaxed(alpha_to
+ i
* j
) ^ si
[i
];
590 /* Even syndrome = (Odd syndrome) ** 2 */
591 for (i
= 2, j
= 1; j
<= cap
; i
= ++j
<< 1) {
597 tmp
= readw_relaxed(index_of
+ si
[j
]);
598 tmp
= (tmp
* 2) % host
->pmecc_cw_len
;
599 si
[i
] = readw_relaxed(alpha_to
+ tmp
);
606 static void pmecc_get_sigma(struct mtd_info
*mtd
)
608 struct nand_chip
*nand_chip
= mtd
->priv
;
609 struct atmel_nand_host
*host
= nand_chip
->priv
;
611 int16_t *lmu
= host
->pmecc_lmu
;
612 int16_t *si
= host
->pmecc_si
;
613 int *mu
= host
->pmecc_mu
;
614 int *dmu
= host
->pmecc_dmu
; /* Discrepancy */
615 int *delta
= host
->pmecc_delta
; /* Delta order */
616 int cw_len
= host
->pmecc_cw_len
;
617 const int16_t cap
= host
->pmecc_corr_cap
;
618 const int num
= 2 * cap
+ 1;
619 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
620 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
622 uint32_t dmu_0_count
, tmp
;
623 int16_t *smu
= host
->pmecc_smu
;
625 /* index of largest delta */
637 memset(smu
, 0, sizeof(int16_t) * num
);
640 /* discrepancy set to 1 */
642 /* polynom order set to 0 */
644 delta
[0] = (mu
[0] * 2 - lmu
[0]) >> 1;
650 /* Sigma(x) set to 1 */
651 memset(&smu
[num
], 0, sizeof(int16_t) * num
);
654 /* discrepancy set to S1 */
657 /* polynom order set to 0 */
660 delta
[1] = (mu
[1] * 2 - lmu
[1]) >> 1;
662 /* Init the Sigma(x) last row */
663 memset(&smu
[(cap
+ 1) * num
], 0, sizeof(int16_t) * num
);
665 for (i
= 1; i
<= cap
; i
++) {
667 /* Begin Computing Sigma (Mu+1) and L(mu) */
668 /* check if discrepancy is set to 0 */
672 tmp
= ((cap
- (lmu
[i
] >> 1) - 1) / 2);
673 if ((cap
- (lmu
[i
] >> 1) - 1) & 0x1)
678 if (dmu_0_count
== tmp
) {
679 for (j
= 0; j
<= (lmu
[i
] >> 1) + 1; j
++)
680 smu
[(cap
+ 1) * num
+ j
] =
683 lmu
[cap
+ 1] = lmu
[i
];
688 for (j
= 0; j
<= lmu
[i
] >> 1; j
++)
689 smu
[(i
+ 1) * num
+ j
] = smu
[i
* num
+ j
];
691 /* copy previous polynom order to the next */
696 /* find largest delta with dmu != 0 */
697 for (j
= 0; j
< i
; j
++) {
698 if ((dmu
[j
]) && (delta
[j
] > largest
)) {
704 /* compute difference */
705 diff
= (mu
[i
] - mu
[ro
]);
707 /* Compute degree of the new smu polynomial */
708 if ((lmu
[i
] >> 1) > ((lmu
[ro
] >> 1) + diff
))
711 lmu
[i
+ 1] = ((lmu
[ro
] >> 1) + diff
) * 2;
713 /* Init smu[i+1] with 0 */
714 for (k
= 0; k
< num
; k
++)
715 smu
[(i
+ 1) * num
+ k
] = 0;
717 /* Compute smu[i+1] */
718 for (k
= 0; k
<= lmu
[ro
] >> 1; k
++) {
721 if (!(smu
[ro
* num
+ k
] && dmu
[i
]))
723 a
= readw_relaxed(index_of
+ dmu
[i
]);
724 b
= readw_relaxed(index_of
+ dmu
[ro
]);
725 c
= readw_relaxed(index_of
+ smu
[ro
* num
+ k
]);
726 tmp
= a
+ (cw_len
- b
) + c
;
727 a
= readw_relaxed(alpha_to
+ tmp
% cw_len
);
728 smu
[(i
+ 1) * num
+ (k
+ diff
)] = a
;
731 for (k
= 0; k
<= lmu
[i
] >> 1; k
++)
732 smu
[(i
+ 1) * num
+ k
] ^= smu
[i
* num
+ k
];
735 /* End Computing Sigma (Mu+1) and L(mu) */
736 /* In either case compute delta */
737 delta
[i
+ 1] = (mu
[i
+ 1] * 2 - lmu
[i
+ 1]) >> 1;
739 /* Do not compute discrepancy for the last iteration */
743 for (k
= 0; k
<= (lmu
[i
+ 1] >> 1); k
++) {
746 dmu
[i
+ 1] = si
[tmp
+ 3];
747 } else if (smu
[(i
+ 1) * num
+ k
] && si
[tmp
+ 3 - k
]) {
749 a
= readw_relaxed(index_of
+
750 smu
[(i
+ 1) * num
+ k
]);
751 b
= si
[2 * (i
- 1) + 3 - k
];
752 c
= readw_relaxed(index_of
+ b
);
755 dmu
[i
+ 1] = readw_relaxed(alpha_to
+ tmp
) ^
764 static int pmecc_err_location(struct mtd_info
*mtd
)
766 struct nand_chip
*nand_chip
= mtd
->priv
;
767 struct atmel_nand_host
*host
= nand_chip
->priv
;
768 unsigned long end_time
;
769 const int cap
= host
->pmecc_corr_cap
;
770 const int num
= 2 * cap
+ 1;
771 int sector_size
= host
->pmecc_sector_size
;
772 int err_nbr
= 0; /* number of error */
773 int roots_nbr
; /* number of roots */
776 int16_t *smu
= host
->pmecc_smu
;
778 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
, PMERRLOC_DISABLE
);
780 for (i
= 0; i
<= host
->pmecc_lmu
[cap
+ 1] >> 1; i
++) {
781 pmerrloc_writel_sigma_relaxed(host
->pmerrloc_base
, i
,
782 smu
[(cap
+ 1) * num
+ i
]);
786 val
= (err_nbr
- 1) << 16;
787 if (sector_size
== 1024)
790 pmerrloc_writel(host
->pmerrloc_base
, ELCFG
, val
);
791 pmerrloc_writel(host
->pmerrloc_base
, ELEN
,
792 sector_size
* 8 + host
->pmecc_degree
* cap
);
794 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
795 while (!(pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
796 & PMERRLOC_CALC_DONE
)) {
797 if (unlikely(time_after(jiffies
, end_time
))) {
798 dev_err(host
->dev
, "PMECC: Timeout to calculate error location.\n");
804 roots_nbr
= (pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
805 & PMERRLOC_ERR_NUM_MASK
) >> 8;
806 /* Number of roots == degree of smu hence <= cap */
807 if (roots_nbr
== host
->pmecc_lmu
[cap
+ 1] >> 1)
810 /* Number of roots does not match the degree of smu
811 * unable to correct error */
815 static void pmecc_correct_data(struct mtd_info
*mtd
, uint8_t *buf
, uint8_t *ecc
,
816 int sector_num
, int extra_bytes
, int err_nbr
)
818 struct nand_chip
*nand_chip
= mtd
->priv
;
819 struct atmel_nand_host
*host
= nand_chip
->priv
;
821 int byte_pos
, bit_pos
, sector_size
, pos
;
825 sector_size
= host
->pmecc_sector_size
;
828 tmp
= pmerrloc_readl_el_relaxed(host
->pmerrloc_base
, i
) - 1;
832 if (byte_pos
>= (sector_size
+ extra_bytes
))
833 BUG(); /* should never happen */
835 if (byte_pos
< sector_size
) {
836 err_byte
= *(buf
+ byte_pos
);
837 *(buf
+ byte_pos
) ^= (1 << bit_pos
);
839 pos
= sector_num
* host
->pmecc_sector_size
+ byte_pos
;
840 dev_info(host
->dev
, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
841 pos
, bit_pos
, err_byte
, *(buf
+ byte_pos
));
843 /* Bit flip in OOB area */
844 tmp
= sector_num
* host
->pmecc_bytes_per_sector
845 + (byte_pos
- sector_size
);
847 ecc
[tmp
] ^= (1 << bit_pos
);
849 pos
= tmp
+ nand_chip
->ecc
.layout
->eccpos
[0];
850 dev_info(host
->dev
, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
851 pos
, bit_pos
, err_byte
, ecc
[tmp
]);
861 static int pmecc_correction(struct mtd_info
*mtd
, u32 pmecc_stat
, uint8_t *buf
,
864 struct nand_chip
*nand_chip
= mtd
->priv
;
865 struct atmel_nand_host
*host
= nand_chip
->priv
;
870 for (i
= 0; i
< nand_chip
->ecc
.total
; i
++)
873 /* Erased page, return OK */
877 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
879 if (pmecc_stat
& 0x1) {
880 buf_pos
= buf
+ i
* host
->pmecc_sector_size
;
882 pmecc_gen_syndrome(mtd
, i
);
883 pmecc_substitute(mtd
);
884 pmecc_get_sigma(mtd
);
886 err_nbr
= pmecc_err_location(mtd
);
888 dev_err(host
->dev
, "PMECC: Too many errors\n");
889 mtd
->ecc_stats
.failed
++;
892 pmecc_correct_data(mtd
, buf_pos
, ecc
, i
,
893 host
->pmecc_bytes_per_sector
, err_nbr
);
894 mtd
->ecc_stats
.corrected
+= err_nbr
;
895 total_err
+= err_nbr
;
904 static void pmecc_enable(struct atmel_nand_host
*host
, int ecc_op
)
908 if (ecc_op
!= NAND_ECC_READ
&& ecc_op
!= NAND_ECC_WRITE
) {
909 dev_err(host
->dev
, "atmel_nand: wrong pmecc operation type!");
913 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
914 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
915 val
= pmecc_readl_relaxed(host
->ecc
, CFG
);
917 if (ecc_op
== NAND_ECC_READ
)
918 pmecc_writel(host
->ecc
, CFG
, (val
& ~PMECC_CFG_WRITE_OP
)
919 | PMECC_CFG_AUTO_ENABLE
);
921 pmecc_writel(host
->ecc
, CFG
, (val
| PMECC_CFG_WRITE_OP
)
922 & ~PMECC_CFG_AUTO_ENABLE
);
924 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
925 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DATA
);
928 static int atmel_nand_pmecc_read_page(struct mtd_info
*mtd
,
929 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
931 struct atmel_nand_host
*host
= chip
->priv
;
932 int eccsize
= chip
->ecc
.size
* chip
->ecc
.steps
;
933 uint8_t *oob
= chip
->oob_poi
;
934 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
936 unsigned long end_time
;
939 if (!host
->nfc
|| !host
->nfc
->use_nfc_sram
)
940 pmecc_enable(host
, NAND_ECC_READ
);
942 chip
->read_buf(mtd
, buf
, eccsize
);
943 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
945 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
946 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
947 if (unlikely(time_after(jiffies
, end_time
))) {
948 dev_err(host
->dev
, "PMECC: Timeout to get error status.\n");
954 stat
= pmecc_readl_relaxed(host
->ecc
, ISR
);
956 bitflips
= pmecc_correction(mtd
, stat
, buf
, &oob
[eccpos
[0]]);
958 /* uncorrectable errors */
965 static int atmel_nand_pmecc_write_page(struct mtd_info
*mtd
,
966 struct nand_chip
*chip
, const uint8_t *buf
, int oob_required
)
968 struct atmel_nand_host
*host
= chip
->priv
;
969 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
971 unsigned long end_time
;
973 if (!host
->nfc
|| !host
->nfc
->write_by_sram
) {
974 pmecc_enable(host
, NAND_ECC_WRITE
);
975 chip
->write_buf(mtd
, (u8
*)buf
, mtd
->writesize
);
978 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
979 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
980 if (unlikely(time_after(jiffies
, end_time
))) {
981 dev_err(host
->dev
, "PMECC: Timeout to get ECC value.\n");
987 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
988 for (j
= 0; j
< host
->pmecc_bytes_per_sector
; j
++) {
991 pos
= i
* host
->pmecc_bytes_per_sector
+ j
;
992 chip
->oob_poi
[eccpos
[pos
]] =
993 pmecc_readb_ecc_relaxed(host
->ecc
, i
, j
);
996 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1001 static void atmel_pmecc_core_init(struct mtd_info
*mtd
)
1003 struct nand_chip
*nand_chip
= mtd
->priv
;
1004 struct atmel_nand_host
*host
= nand_chip
->priv
;
1006 struct nand_ecclayout
*ecc_layout
;
1008 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
1009 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
1011 switch (host
->pmecc_corr_cap
) {
1013 val
= PMECC_CFG_BCH_ERR2
;
1016 val
= PMECC_CFG_BCH_ERR4
;
1019 val
= PMECC_CFG_BCH_ERR8
;
1022 val
= PMECC_CFG_BCH_ERR12
;
1025 val
= PMECC_CFG_BCH_ERR24
;
1029 if (host
->pmecc_sector_size
== 512)
1030 val
|= PMECC_CFG_SECTOR512
;
1031 else if (host
->pmecc_sector_size
== 1024)
1032 val
|= PMECC_CFG_SECTOR1024
;
1034 switch (host
->pmecc_sector_number
) {
1036 val
|= PMECC_CFG_PAGE_1SECTOR
;
1039 val
|= PMECC_CFG_PAGE_2SECTORS
;
1042 val
|= PMECC_CFG_PAGE_4SECTORS
;
1045 val
|= PMECC_CFG_PAGE_8SECTORS
;
1049 val
|= (PMECC_CFG_READ_OP
| PMECC_CFG_SPARE_DISABLE
1050 | PMECC_CFG_AUTO_DISABLE
);
1051 pmecc_writel(host
->ecc
, CFG
, val
);
1053 ecc_layout
= nand_chip
->ecc
.layout
;
1054 pmecc_writel(host
->ecc
, SAREA
, mtd
->oobsize
- 1);
1055 pmecc_writel(host
->ecc
, SADDR
, ecc_layout
->eccpos
[0]);
1056 pmecc_writel(host
->ecc
, EADDR
,
1057 ecc_layout
->eccpos
[ecc_layout
->eccbytes
- 1]);
1058 /* See datasheet about PMECC Clock Control Register */
1059 pmecc_writel(host
->ecc
, CLK
, 2);
1060 pmecc_writel(host
->ecc
, IDR
, 0xff);
1061 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
1065 * Get minimum ecc requirements from NAND.
1066 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1067 * will set them according to minimum ecc requirement. Otherwise, use the
1068 * value in DTS file.
1069 * return 0 if success. otherwise return error code.
1071 static int pmecc_choose_ecc(struct atmel_nand_host
*host
,
1072 int *cap
, int *sector_size
)
1074 /* Get minimum ECC requirements */
1075 if (host
->nand_chip
.ecc_strength_ds
) {
1076 *cap
= host
->nand_chip
.ecc_strength_ds
;
1077 *sector_size
= host
->nand_chip
.ecc_step_ds
;
1078 dev_info(host
->dev
, "minimum ECC: %d bits in %d bytes\n",
1079 *cap
, *sector_size
);
1083 dev_info(host
->dev
, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1086 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1087 if (host
->pmecc_corr_cap
== 0) {
1088 /* use the most fitable ecc bits (the near bigger one ) */
1090 host
->pmecc_corr_cap
= 2;
1092 host
->pmecc_corr_cap
= 4;
1094 host
->pmecc_corr_cap
= 8;
1095 else if (*cap
<= 12)
1096 host
->pmecc_corr_cap
= 12;
1097 else if (*cap
<= 24)
1098 host
->pmecc_corr_cap
= 24;
1102 if (host
->pmecc_sector_size
== 0) {
1103 /* use the most fitable sector size (the near smaller one ) */
1104 if (*sector_size
>= 1024)
1105 host
->pmecc_sector_size
= 1024;
1106 else if (*sector_size
>= 512)
1107 host
->pmecc_sector_size
= 512;
1114 static int atmel_pmecc_nand_init_params(struct platform_device
*pdev
,
1115 struct atmel_nand_host
*host
)
1117 struct mtd_info
*mtd
= &host
->mtd
;
1118 struct nand_chip
*nand_chip
= &host
->nand_chip
;
1119 struct resource
*regs
, *regs_pmerr
, *regs_rom
;
1120 int cap
, sector_size
, err_no
;
1122 err_no
= pmecc_choose_ecc(host
, &cap
, §or_size
);
1124 dev_err(host
->dev
, "The NAND flash's ECC requirement are not support!");
1128 if (cap
> host
->pmecc_corr_cap
||
1129 sector_size
!= host
->pmecc_sector_size
)
1130 dev_info(host
->dev
, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1132 cap
= host
->pmecc_corr_cap
;
1133 sector_size
= host
->pmecc_sector_size
;
1134 host
->pmecc_lookup_table_offset
= (sector_size
== 512) ?
1135 host
->pmecc_lookup_table_offset_512
:
1136 host
->pmecc_lookup_table_offset_1024
;
1138 dev_info(host
->dev
, "Initialize PMECC params, cap: %d, sector: %d\n",
1141 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1144 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1145 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1149 host
->ecc
= devm_ioremap_resource(&pdev
->dev
, regs
);
1150 if (IS_ERR(host
->ecc
)) {
1151 err_no
= PTR_ERR(host
->ecc
);
1155 regs_pmerr
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
1156 host
->pmerrloc_base
= devm_ioremap_resource(&pdev
->dev
, regs_pmerr
);
1157 if (IS_ERR(host
->pmerrloc_base
)) {
1158 err_no
= PTR_ERR(host
->pmerrloc_base
);
1162 regs_rom
= platform_get_resource(pdev
, IORESOURCE_MEM
, 3);
1163 host
->pmecc_rom_base
= devm_ioremap_resource(&pdev
->dev
, regs_rom
);
1164 if (IS_ERR(host
->pmecc_rom_base
)) {
1165 err_no
= PTR_ERR(host
->pmecc_rom_base
);
1169 nand_chip
->ecc
.size
= sector_size
;
1171 /* set ECC page size and oob layout */
1172 switch (mtd
->writesize
) {
1178 if (sector_size
> mtd
->writesize
) {
1179 dev_err(host
->dev
, "pmecc sector size is bigger than the page size!\n");
1184 host
->pmecc_degree
= (sector_size
== 512) ?
1185 PMECC_GF_DIMENSION_13
: PMECC_GF_DIMENSION_14
;
1186 host
->pmecc_cw_len
= (1 << host
->pmecc_degree
) - 1;
1187 host
->pmecc_sector_number
= mtd
->writesize
/ sector_size
;
1188 host
->pmecc_bytes_per_sector
= pmecc_get_ecc_bytes(
1190 host
->pmecc_alpha_to
= pmecc_get_alpha_to(host
);
1191 host
->pmecc_index_of
= host
->pmecc_rom_base
+
1192 host
->pmecc_lookup_table_offset
;
1194 nand_chip
->ecc
.steps
= host
->pmecc_sector_number
;
1195 nand_chip
->ecc
.strength
= cap
;
1196 nand_chip
->ecc
.bytes
= host
->pmecc_bytes_per_sector
;
1197 nand_chip
->ecc
.total
= host
->pmecc_bytes_per_sector
*
1198 host
->pmecc_sector_number
;
1199 if (nand_chip
->ecc
.total
> mtd
->oobsize
- 2) {
1200 dev_err(host
->dev
, "No room for ECC bytes\n");
1204 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo
,
1206 nand_chip
->ecc
.total
);
1208 nand_chip
->ecc
.layout
= &atmel_pmecc_oobinfo
;
1212 "Unsupported page size for PMECC, use Software ECC\n");
1213 /* page size not handled by HW ECC */
1214 /* switching back to soft ECC */
1215 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1219 /* Allocate data for PMECC computation */
1220 err_no
= pmecc_data_alloc(host
);
1223 "Cannot allocate memory for PMECC computation!\n");
1227 nand_chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
1228 nand_chip
->ecc
.read_page
= atmel_nand_pmecc_read_page
;
1229 nand_chip
->ecc
.write_page
= atmel_nand_pmecc_write_page
;
1231 atmel_pmecc_core_init(mtd
);
1242 * function called after a write
1244 * mtd: MTD block structure
1245 * dat: raw data (unused)
1246 * ecc_code: buffer for ECC
1248 static int atmel_nand_calculate(struct mtd_info
*mtd
,
1249 const u_char
*dat
, unsigned char *ecc_code
)
1251 struct nand_chip
*nand_chip
= mtd
->priv
;
1252 struct atmel_nand_host
*host
= nand_chip
->priv
;
1253 unsigned int ecc_value
;
1255 /* get the first 2 ECC bytes */
1256 ecc_value
= ecc_readl(host
->ecc
, PR
);
1258 ecc_code
[0] = ecc_value
& 0xFF;
1259 ecc_code
[1] = (ecc_value
>> 8) & 0xFF;
1261 /* get the last 2 ECC bytes */
1262 ecc_value
= ecc_readl(host
->ecc
, NPR
) & ATMEL_ECC_NPARITY
;
1264 ecc_code
[2] = ecc_value
& 0xFF;
1265 ecc_code
[3] = (ecc_value
>> 8) & 0xFF;
1271 * HW ECC read page function
1273 * mtd: mtd info structure
1274 * chip: nand chip info structure
1275 * buf: buffer to store read data
1276 * oob_required: caller expects OOB data read to chip->oob_poi
1278 static int atmel_nand_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1279 uint8_t *buf
, int oob_required
, int page
)
1281 int eccsize
= chip
->ecc
.size
;
1282 int eccbytes
= chip
->ecc
.bytes
;
1283 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1285 uint8_t *oob
= chip
->oob_poi
;
1288 unsigned int max_bitflips
= 0;
1291 * Errata: ALE is incorrectly wired up to the ECC controller
1292 * on the AP7000, so it will include the address cycles in the
1295 * Workaround: Reset the parity registers before reading the
1298 struct atmel_nand_host
*host
= chip
->priv
;
1299 if (host
->board
.need_reset_workaround
)
1300 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1303 chip
->read_buf(mtd
, p
, eccsize
);
1305 /* move to ECC position if needed */
1306 if (eccpos
[0] != 0) {
1307 /* This only works on large pages
1308 * because the ECC controller waits for
1309 * NAND_CMD_RNDOUTSTART after the
1311 * anyway, for small pages, the eccpos[0] == 0
1313 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1314 mtd
->writesize
+ eccpos
[0], -1);
1317 /* the ECC controller needs to read the ECC just after the data */
1318 ecc_pos
= oob
+ eccpos
[0];
1319 chip
->read_buf(mtd
, ecc_pos
, eccbytes
);
1321 /* check if there's an error */
1322 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1325 mtd
->ecc_stats
.failed
++;
1327 mtd
->ecc_stats
.corrected
+= stat
;
1328 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1331 /* get back to oob start (end of page) */
1332 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1335 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
1337 return max_bitflips
;
1343 * function called after a read
1345 * mtd: MTD block structure
1346 * dat: raw data read from the chip
1347 * read_ecc: ECC from the chip (unused)
1350 * Detect and correct a 1 bit error for a page
1352 static int atmel_nand_correct(struct mtd_info
*mtd
, u_char
*dat
,
1353 u_char
*read_ecc
, u_char
*isnull
)
1355 struct nand_chip
*nand_chip
= mtd
->priv
;
1356 struct atmel_nand_host
*host
= nand_chip
->priv
;
1357 unsigned int ecc_status
;
1358 unsigned int ecc_word
, ecc_bit
;
1360 /* get the status from the Status Register */
1361 ecc_status
= ecc_readl(host
->ecc
, SR
);
1363 /* if there's no error */
1364 if (likely(!(ecc_status
& ATMEL_ECC_RECERR
)))
1367 /* get error bit offset (4 bits) */
1368 ecc_bit
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_BITADDR
;
1369 /* get word address (12 bits) */
1370 ecc_word
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_WORDADDR
;
1373 /* if there are multiple errors */
1374 if (ecc_status
& ATMEL_ECC_MULERR
) {
1375 /* check if it is a freshly erased block
1376 * (filled with 0xff) */
1377 if ((ecc_bit
== ATMEL_ECC_BITADDR
)
1378 && (ecc_word
== (ATMEL_ECC_WORDADDR
>> 4))) {
1379 /* the block has just been erased, return OK */
1382 /* it doesn't seems to be a freshly
1384 * We can't correct so many errors */
1385 dev_dbg(host
->dev
, "atmel_nand : multiple errors detected."
1386 " Unable to correct.\n");
1390 /* if there's a single bit error : we can correct it */
1391 if (ecc_status
& ATMEL_ECC_ECCERR
) {
1392 /* there's nothing much to do here.
1393 * the bit error is on the ECC itself.
1395 dev_dbg(host
->dev
, "atmel_nand : one bit error on ECC code."
1396 " Nothing to correct\n");
1400 dev_dbg(host
->dev
, "atmel_nand : one bit error on data."
1401 " (word offset in the page :"
1402 " 0x%x bit offset : 0x%x)\n",
1404 /* correct the error */
1405 if (nand_chip
->options
& NAND_BUSWIDTH_16
) {
1407 ((unsigned short *) dat
)[ecc_word
] ^= (1 << ecc_bit
);
1410 dat
[ecc_word
] ^= (1 << ecc_bit
);
1412 dev_dbg(host
->dev
, "atmel_nand : error corrected\n");
1417 * Enable HW ECC : unused on most chips
1419 static void atmel_nand_hwctl(struct mtd_info
*mtd
, int mode
)
1421 struct nand_chip
*nand_chip
= mtd
->priv
;
1422 struct atmel_nand_host
*host
= nand_chip
->priv
;
1424 if (host
->board
.need_reset_workaround
)
1425 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1428 static int atmel_of_init_port(struct atmel_nand_host
*host
,
1429 struct device_node
*np
)
1434 struct atmel_nand_data
*board
= &host
->board
;
1435 enum of_gpio_flags flags
= 0;
1437 if (of_property_read_u32(np
, "atmel,nand-addr-offset", &val
) == 0) {
1439 dev_err(host
->dev
, "invalid addr-offset %u\n", val
);
1445 if (of_property_read_u32(np
, "atmel,nand-cmd-offset", &val
) == 0) {
1447 dev_err(host
->dev
, "invalid cmd-offset %u\n", val
);
1453 ecc_mode
= of_get_nand_ecc_mode(np
);
1455 board
->ecc_mode
= ecc_mode
< 0 ? NAND_ECC_SOFT
: ecc_mode
;
1457 board
->on_flash_bbt
= of_get_nand_on_flash_bbt(np
);
1459 board
->has_dma
= of_property_read_bool(np
, "atmel,nand-has-dma");
1461 if (of_get_nand_bus_width(np
) == 16)
1462 board
->bus_width_16
= 1;
1464 board
->rdy_pin
= of_get_gpio_flags(np
, 0, &flags
);
1465 board
->rdy_pin_active_low
= (flags
== OF_GPIO_ACTIVE_LOW
);
1467 board
->enable_pin
= of_get_gpio(np
, 1);
1468 board
->det_pin
= of_get_gpio(np
, 2);
1470 host
->has_pmecc
= of_property_read_bool(np
, "atmel,has-pmecc");
1472 /* load the nfc driver if there is */
1473 of_platform_populate(np
, NULL
, NULL
, host
->dev
);
1475 if (!(board
->ecc_mode
== NAND_ECC_HW
) || !host
->has_pmecc
)
1476 return 0; /* Not using PMECC */
1478 /* use PMECC, get correction capability, sector size and lookup
1480 * If correction bits and sector size are not specified, then find
1481 * them from NAND ONFI parameters.
1483 if (of_property_read_u32(np
, "atmel,pmecc-cap", &val
) == 0) {
1484 if ((val
!= 2) && (val
!= 4) && (val
!= 8) && (val
!= 12) &&
1487 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1491 host
->pmecc_corr_cap
= (u8
)val
;
1494 if (of_property_read_u32(np
, "atmel,pmecc-sector-size", &val
) == 0) {
1495 if ((val
!= 512) && (val
!= 1024)) {
1497 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1501 host
->pmecc_sector_size
= (u16
)val
;
1504 if (of_property_read_u32_array(np
, "atmel,pmecc-lookup-table-offset",
1506 dev_err(host
->dev
, "Cannot get PMECC lookup table offset\n");
1509 if (!offset
[0] && !offset
[1]) {
1510 dev_err(host
->dev
, "Invalid PMECC lookup table offset\n");
1513 host
->pmecc_lookup_table_offset_512
= offset
[0];
1514 host
->pmecc_lookup_table_offset_1024
= offset
[1];
1519 static int atmel_hw_nand_init_params(struct platform_device
*pdev
,
1520 struct atmel_nand_host
*host
)
1522 struct mtd_info
*mtd
= &host
->mtd
;
1523 struct nand_chip
*nand_chip
= &host
->nand_chip
;
1524 struct resource
*regs
;
1526 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1529 "Can't get I/O resource regs, use software ECC\n");
1530 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1534 host
->ecc
= devm_ioremap_resource(&pdev
->dev
, regs
);
1535 if (IS_ERR(host
->ecc
))
1536 return PTR_ERR(host
->ecc
);
1538 /* ECC is calculated for the whole page (1 step) */
1539 nand_chip
->ecc
.size
= mtd
->writesize
;
1541 /* set ECC page size and oob layout */
1542 switch (mtd
->writesize
) {
1544 nand_chip
->ecc
.layout
= &atmel_oobinfo_small
;
1545 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_528
);
1548 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1549 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_1056
);
1552 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1553 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_2112
);
1556 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1557 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_4224
);
1560 /* page size not handled by HW ECC */
1561 /* switching back to soft ECC */
1562 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1566 /* set up for HW ECC */
1567 nand_chip
->ecc
.calculate
= atmel_nand_calculate
;
1568 nand_chip
->ecc
.correct
= atmel_nand_correct
;
1569 nand_chip
->ecc
.hwctl
= atmel_nand_hwctl
;
1570 nand_chip
->ecc
.read_page
= atmel_nand_read_page
;
1571 nand_chip
->ecc
.bytes
= 4;
1572 nand_chip
->ecc
.strength
= 1;
1577 static inline u32
nfc_read_status(struct atmel_nand_host
*host
)
1579 u32 err_flags
= NFC_SR_DTOE
| NFC_SR_UNDEF
| NFC_SR_AWB
| NFC_SR_ASE
;
1580 u32 nfc_status
= nfc_readl(host
->nfc
->hsmc_regs
, SR
);
1582 if (unlikely(nfc_status
& err_flags
)) {
1583 if (nfc_status
& NFC_SR_DTOE
)
1584 dev_err(host
->dev
, "NFC: Waiting Nand R/B Timeout Error\n");
1585 else if (nfc_status
& NFC_SR_UNDEF
)
1586 dev_err(host
->dev
, "NFC: Access Undefined Area Error\n");
1587 else if (nfc_status
& NFC_SR_AWB
)
1588 dev_err(host
->dev
, "NFC: Access memory While NFC is busy\n");
1589 else if (nfc_status
& NFC_SR_ASE
)
1590 dev_err(host
->dev
, "NFC: Access memory Size Error\n");
1596 /* SMC interrupt service routine */
1597 static irqreturn_t
hsmc_interrupt(int irq
, void *dev_id
)
1599 struct atmel_nand_host
*host
= dev_id
;
1600 u32 status
, mask
, pending
;
1601 irqreturn_t ret
= IRQ_NONE
;
1603 status
= nfc_read_status(host
);
1604 mask
= nfc_readl(host
->nfc
->hsmc_regs
, IMR
);
1605 pending
= status
& mask
;
1607 if (pending
& NFC_SR_XFR_DONE
) {
1608 complete(&host
->nfc
->comp_xfer_done
);
1609 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, NFC_SR_XFR_DONE
);
1612 if (pending
& NFC_SR_RB_EDGE
) {
1613 complete(&host
->nfc
->comp_ready
);
1614 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, NFC_SR_RB_EDGE
);
1617 if (pending
& NFC_SR_CMD_DONE
) {
1618 complete(&host
->nfc
->comp_cmd_done
);
1619 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, NFC_SR_CMD_DONE
);
1626 /* NFC(Nand Flash Controller) related functions */
1627 static void nfc_prepare_interrupt(struct atmel_nand_host
*host
, u32 flag
)
1629 if (flag
& NFC_SR_XFR_DONE
)
1630 init_completion(&host
->nfc
->comp_xfer_done
);
1632 if (flag
& NFC_SR_RB_EDGE
)
1633 init_completion(&host
->nfc
->comp_ready
);
1635 if (flag
& NFC_SR_CMD_DONE
)
1636 init_completion(&host
->nfc
->comp_cmd_done
);
1638 /* Enable interrupt that need to wait for */
1639 nfc_writel(host
->nfc
->hsmc_regs
, IER
, flag
);
1642 static int nfc_wait_interrupt(struct atmel_nand_host
*host
, u32 flag
)
1645 struct completion
*comp
[3]; /* Support 3 interrupt completion */
1647 if (flag
& NFC_SR_XFR_DONE
)
1648 comp
[index
++] = &host
->nfc
->comp_xfer_done
;
1650 if (flag
& NFC_SR_RB_EDGE
)
1651 comp
[index
++] = &host
->nfc
->comp_ready
;
1653 if (flag
& NFC_SR_CMD_DONE
)
1654 comp
[index
++] = &host
->nfc
->comp_cmd_done
;
1657 dev_err(host
->dev
, "Unkown interrupt flag: 0x%08x\n", flag
);
1661 for (i
= 0; i
< index
; i
++) {
1662 if (wait_for_completion_timeout(comp
[i
],
1663 msecs_to_jiffies(NFC_TIME_OUT_MS
)))
1664 continue; /* wait for next completion */
1672 dev_err(host
->dev
, "Time out to wait for interrupt: 0x%08x\n", flag
);
1673 /* Disable the interrupt as it is not handled by interrupt handler */
1674 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, flag
);
1678 static int nfc_send_command(struct atmel_nand_host
*host
,
1679 unsigned int cmd
, unsigned int addr
, unsigned char cycle0
)
1681 unsigned long timeout
;
1682 u32 flag
= NFC_SR_CMD_DONE
;
1683 flag
|= cmd
& NFCADDR_CMD_DATAEN
? NFC_SR_XFR_DONE
: 0;
1686 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1689 timeout
= jiffies
+ msecs_to_jiffies(NFC_TIME_OUT_MS
);
1690 while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY
, host
->nfc
->base_cmd_regs
)
1691 & NFCADDR_CMD_NFCBUSY
) {
1692 if (time_after(jiffies
, timeout
)) {
1694 "Time out to wait CMD_NFCBUSY ready!\n");
1699 nfc_prepare_interrupt(host
, flag
);
1700 nfc_writel(host
->nfc
->hsmc_regs
, CYCLE0
, cycle0
);
1701 nfc_cmd_addr1234_writel(cmd
, addr
, host
->nfc
->base_cmd_regs
);
1702 return nfc_wait_interrupt(host
, flag
);
1705 static int nfc_device_ready(struct mtd_info
*mtd
)
1708 struct nand_chip
*nand_chip
= mtd
->priv
;
1709 struct atmel_nand_host
*host
= nand_chip
->priv
;
1711 status
= nfc_read_status(host
);
1712 mask
= nfc_readl(host
->nfc
->hsmc_regs
, IMR
);
1714 /* The mask should be 0. If not we may lost interrupts */
1715 if (unlikely(mask
& status
))
1716 dev_err(host
->dev
, "Lost the interrupt flags: 0x%08x\n",
1719 return status
& NFC_SR_RB_EDGE
;
1722 static void nfc_select_chip(struct mtd_info
*mtd
, int chip
)
1724 struct nand_chip
*nand_chip
= mtd
->priv
;
1725 struct atmel_nand_host
*host
= nand_chip
->priv
;
1728 nfc_writel(host
->nfc
->hsmc_regs
, CTRL
, NFC_CTRL_DISABLE
);
1730 nfc_writel(host
->nfc
->hsmc_regs
, CTRL
, NFC_CTRL_ENABLE
);
1733 static int nfc_make_addr(struct mtd_info
*mtd
, int command
, int column
,
1734 int page_addr
, unsigned int *addr1234
, unsigned int *cycle0
)
1736 struct nand_chip
*chip
= mtd
->priv
;
1739 unsigned char addr_bytes
[8];
1740 int index
= 0, bit_shift
;
1742 BUG_ON(addr1234
== NULL
|| cycle0
== NULL
);
1748 if (chip
->options
& NAND_BUSWIDTH_16
&&
1749 !nand_opcode_8bits(command
))
1751 addr_bytes
[acycle
++] = column
& 0xff;
1752 if (mtd
->writesize
> 512)
1753 addr_bytes
[acycle
++] = (column
>> 8) & 0xff;
1756 if (page_addr
!= -1) {
1757 addr_bytes
[acycle
++] = page_addr
& 0xff;
1758 addr_bytes
[acycle
++] = (page_addr
>> 8) & 0xff;
1759 if (chip
->chipsize
> (128 << 20))
1760 addr_bytes
[acycle
++] = (page_addr
>> 16) & 0xff;
1764 *cycle0
= addr_bytes
[index
++];
1766 for (bit_shift
= 0; index
< acycle
; bit_shift
+= 8)
1767 *addr1234
+= addr_bytes
[index
++] << bit_shift
;
1769 /* return acycle in cmd register */
1770 return acycle
<< NFCADDR_CMD_ACYCLE_BIT_POS
;
1773 static void nfc_nand_command(struct mtd_info
*mtd
, unsigned int command
,
1774 int column
, int page_addr
)
1776 struct nand_chip
*chip
= mtd
->priv
;
1777 struct atmel_nand_host
*host
= chip
->priv
;
1778 unsigned long timeout
;
1779 unsigned int nfc_addr_cmd
= 0;
1781 unsigned int cmd1
= command
<< NFCADDR_CMD_CMD1_BIT_POS
;
1783 /* Set default settings: no cmd2, no addr cycle. read from nand */
1784 unsigned int cmd2
= 0;
1785 unsigned int vcmd2
= 0;
1786 int acycle
= NFCADDR_CMD_ACYCLE_NONE
;
1787 int csid
= NFCADDR_CMD_CSID_3
;
1788 int dataen
= NFCADDR_CMD_DATADIS
;
1789 int nfcwr
= NFCADDR_CMD_NFCRD
;
1790 unsigned int addr1234
= 0;
1791 unsigned int cycle0
= 0;
1792 bool do_addr
= true;
1793 host
->nfc
->data_in_sram
= NULL
;
1795 dev_dbg(host
->dev
, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1796 __func__
, command
, column
, page_addr
);
1799 case NAND_CMD_RESET
:
1800 nfc_addr_cmd
= cmd1
| acycle
| csid
| dataen
| nfcwr
;
1801 nfc_send_command(host
, nfc_addr_cmd
, addr1234
, cycle0
);
1802 udelay(chip
->chip_delay
);
1804 nfc_nand_command(mtd
, NAND_CMD_STATUS
, -1, -1);
1805 timeout
= jiffies
+ msecs_to_jiffies(NFC_TIME_OUT_MS
);
1806 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
)) {
1807 if (time_after(jiffies
, timeout
)) {
1809 "Time out to wait status ready!\n");
1814 case NAND_CMD_STATUS
:
1817 case NAND_CMD_PARAM
:
1818 case NAND_CMD_READID
:
1820 acycle
= NFCADDR_CMD_ACYCLE_1
;
1824 case NAND_CMD_RNDOUT
:
1825 cmd2
= NAND_CMD_RNDOUTSTART
<< NFCADDR_CMD_CMD2_BIT_POS
;
1826 vcmd2
= NFCADDR_CMD_VCMD2
;
1828 case NAND_CMD_READ0
:
1829 case NAND_CMD_READOOB
:
1830 if (command
== NAND_CMD_READOOB
) {
1831 column
+= mtd
->writesize
;
1832 command
= NAND_CMD_READ0
; /* only READ0 is valid */
1833 cmd1
= command
<< NFCADDR_CMD_CMD1_BIT_POS
;
1835 if (host
->nfc
->use_nfc_sram
) {
1836 /* Enable Data transfer to sram */
1837 dataen
= NFCADDR_CMD_DATAEN
;
1839 /* Need enable PMECC now, since NFC will transfer
1840 * data in bus after sending nfc read command.
1842 if (chip
->ecc
.mode
== NAND_ECC_HW
&& host
->has_pmecc
)
1843 pmecc_enable(host
, NAND_ECC_READ
);
1846 cmd2
= NAND_CMD_READSTART
<< NFCADDR_CMD_CMD2_BIT_POS
;
1847 vcmd2
= NFCADDR_CMD_VCMD2
;
1849 /* For prgramming command, the cmd need set to write enable */
1850 case NAND_CMD_PAGEPROG
:
1851 case NAND_CMD_SEQIN
:
1852 case NAND_CMD_RNDIN
:
1853 nfcwr
= NFCADDR_CMD_NFCWR
;
1854 if (host
->nfc
->will_write_sram
&& command
== NAND_CMD_SEQIN
)
1855 dataen
= NFCADDR_CMD_DATAEN
;
1862 acycle
= nfc_make_addr(mtd
, command
, column
, page_addr
,
1863 &addr1234
, &cycle0
);
1865 nfc_addr_cmd
= cmd1
| cmd2
| vcmd2
| acycle
| csid
| dataen
| nfcwr
;
1866 nfc_send_command(host
, nfc_addr_cmd
, addr1234
, cycle0
);
1869 * Program and erase have their own busy handlers status, sequential
1870 * in, and deplete1 need no delay.
1873 case NAND_CMD_CACHEDPROG
:
1874 case NAND_CMD_PAGEPROG
:
1875 case NAND_CMD_ERASE1
:
1876 case NAND_CMD_ERASE2
:
1877 case NAND_CMD_RNDIN
:
1878 case NAND_CMD_STATUS
:
1879 case NAND_CMD_RNDOUT
:
1880 case NAND_CMD_SEQIN
:
1881 case NAND_CMD_READID
:
1884 case NAND_CMD_READ0
:
1885 if (dataen
== NFCADDR_CMD_DATAEN
) {
1886 host
->nfc
->data_in_sram
= host
->nfc
->sram_bank0
+
1887 nfc_get_sram_off(host
);
1892 nfc_prepare_interrupt(host
, NFC_SR_RB_EDGE
);
1893 nfc_wait_interrupt(host
, NFC_SR_RB_EDGE
);
1897 static int nfc_sram_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1898 uint32_t offset
, int data_len
, const uint8_t *buf
,
1899 int oob_required
, int page
, int cached
, int raw
)
1903 struct atmel_nand_host
*host
= chip
->priv
;
1904 void __iomem
*sram
= host
->nfc
->sram_bank0
+ nfc_get_sram_off(host
);
1906 /* Subpage write is not supported */
1907 if (offset
|| (data_len
< mtd
->writesize
))
1910 len
= mtd
->writesize
;
1911 /* Copy page data to sram that will write to nand via NFC */
1913 if (atmel_nand_dma_op(mtd
, (void *)buf
, len
, 0) != 0)
1914 /* Fall back to use cpu copy */
1915 memcpy32_toio(sram
, buf
, len
);
1917 memcpy32_toio(sram
, buf
, len
);
1920 cfg
= nfc_readl(host
->nfc
->hsmc_regs
, CFG
);
1921 if (unlikely(raw
) && oob_required
) {
1922 memcpy32_toio(sram
+ len
, chip
->oob_poi
, mtd
->oobsize
);
1923 len
+= mtd
->oobsize
;
1924 nfc_writel(host
->nfc
->hsmc_regs
, CFG
, cfg
| NFC_CFG_WSPARE
);
1926 nfc_writel(host
->nfc
->hsmc_regs
, CFG
, cfg
& ~NFC_CFG_WSPARE
);
1929 if (chip
->ecc
.mode
== NAND_ECC_HW
&& host
->has_pmecc
)
1931 * When use NFC sram, need set up PMECC before send
1932 * NAND_CMD_SEQIN command. Since when the nand command
1933 * is sent, nfc will do transfer from sram and nand.
1935 pmecc_enable(host
, NAND_ECC_WRITE
);
1937 host
->nfc
->will_write_sram
= true;
1938 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
1939 host
->nfc
->will_write_sram
= false;
1942 /* Need to write ecc into oob */
1943 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
);
1948 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1949 status
= chip
->waitfunc(mtd
, chip
);
1951 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
1952 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
, page
);
1954 if (status
& NAND_STATUS_FAIL
)
1960 static int nfc_sram_init(struct mtd_info
*mtd
)
1962 struct nand_chip
*chip
= mtd
->priv
;
1963 struct atmel_nand_host
*host
= chip
->priv
;
1966 /* Initialize the NFC CFG register */
1967 unsigned int cfg_nfc
= 0;
1969 /* set page size and oob layout */
1970 switch (mtd
->writesize
) {
1972 cfg_nfc
= NFC_CFG_PAGESIZE_512
;
1975 cfg_nfc
= NFC_CFG_PAGESIZE_1024
;
1978 cfg_nfc
= NFC_CFG_PAGESIZE_2048
;
1981 cfg_nfc
= NFC_CFG_PAGESIZE_4096
;
1984 cfg_nfc
= NFC_CFG_PAGESIZE_8192
;
1987 dev_err(host
->dev
, "Unsupported page size for NFC.\n");
1992 /* oob bytes size = (NFCSPARESIZE + 1) * 4
1993 * Max support spare size is 512 bytes. */
1994 cfg_nfc
|= (((mtd
->oobsize
/ 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
1995 & NFC_CFG_NFC_SPARESIZE
);
1996 /* default set a max timeout */
1997 cfg_nfc
|= NFC_CFG_RSPARE
|
1998 NFC_CFG_NFC_DTOCYC
| NFC_CFG_NFC_DTOMUL
;
2000 nfc_writel(host
->nfc
->hsmc_regs
, CFG
, cfg_nfc
);
2002 host
->nfc
->will_write_sram
= false;
2003 nfc_set_sram_bank(host
, 0);
2005 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2006 if (host
->nfc
->write_by_sram
) {
2007 if ((chip
->ecc
.mode
== NAND_ECC_HW
&& host
->has_pmecc
) ||
2008 chip
->ecc
.mode
== NAND_ECC_NONE
)
2009 chip
->write_page
= nfc_sram_write_page
;
2011 host
->nfc
->write_by_sram
= false;
2014 dev_info(host
->dev
, "Using NFC Sram read %s\n",
2015 host
->nfc
->write_by_sram
? "and write" : "");
2019 static struct platform_driver atmel_nand_nfc_driver
;
2021 * Probe for the NAND device.
2023 static int atmel_nand_probe(struct platform_device
*pdev
)
2025 struct atmel_nand_host
*host
;
2026 struct mtd_info
*mtd
;
2027 struct nand_chip
*nand_chip
;
2028 struct resource
*mem
;
2029 struct mtd_part_parser_data ppdata
= {};
2032 /* Allocate memory for the device structure (and zero it) */
2033 host
= devm_kzalloc(&pdev
->dev
, sizeof(*host
), GFP_KERNEL
);
2037 res
= platform_driver_register(&atmel_nand_nfc_driver
);
2039 dev_err(&pdev
->dev
, "atmel_nand: can't register NFC driver\n");
2041 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2042 host
->io_base
= devm_ioremap_resource(&pdev
->dev
, mem
);
2043 if (IS_ERR(host
->io_base
)) {
2044 res
= PTR_ERR(host
->io_base
);
2045 goto err_nand_ioremap
;
2047 host
->io_phys
= (dma_addr_t
)mem
->start
;
2050 nand_chip
= &host
->nand_chip
;
2051 host
->dev
= &pdev
->dev
;
2052 if (IS_ENABLED(CONFIG_OF
) && pdev
->dev
.of_node
) {
2053 /* Only when CONFIG_OF is enabled of_node can be parsed */
2054 res
= atmel_of_init_port(host
, pdev
->dev
.of_node
);
2056 goto err_nand_ioremap
;
2058 memcpy(&host
->board
, dev_get_platdata(&pdev
->dev
),
2059 sizeof(struct atmel_nand_data
));
2062 nand_chip
->priv
= host
; /* link the private data structures */
2063 mtd
->priv
= nand_chip
;
2064 mtd
->owner
= THIS_MODULE
;
2066 /* Set address of NAND IO lines */
2067 nand_chip
->IO_ADDR_R
= host
->io_base
;
2068 nand_chip
->IO_ADDR_W
= host
->io_base
;
2070 if (nand_nfc
.is_initialized
) {
2071 /* NFC driver is probed and initialized */
2072 host
->nfc
= &nand_nfc
;
2074 nand_chip
->select_chip
= nfc_select_chip
;
2075 nand_chip
->dev_ready
= nfc_device_ready
;
2076 nand_chip
->cmdfunc
= nfc_nand_command
;
2078 /* Initialize the interrupt for NFC */
2079 irq
= platform_get_irq(pdev
, 0);
2081 dev_err(host
->dev
, "Cannot get HSMC irq!\n");
2083 goto err_nand_ioremap
;
2086 res
= devm_request_irq(&pdev
->dev
, irq
, hsmc_interrupt
,
2089 dev_err(&pdev
->dev
, "Unable to request HSMC irq %d\n",
2091 goto err_nand_ioremap
;
2094 res
= atmel_nand_set_enable_ready_pins(mtd
);
2096 goto err_nand_ioremap
;
2098 nand_chip
->cmd_ctrl
= atmel_nand_cmd_ctrl
;
2101 nand_chip
->ecc
.mode
= host
->board
.ecc_mode
;
2102 nand_chip
->chip_delay
= 40; /* 40us command delay time */
2104 if (host
->board
.bus_width_16
) /* 16-bit bus width */
2105 nand_chip
->options
|= NAND_BUSWIDTH_16
;
2107 nand_chip
->read_buf
= atmel_read_buf
;
2108 nand_chip
->write_buf
= atmel_write_buf
;
2110 platform_set_drvdata(pdev
, host
);
2111 atmel_nand_enable(host
);
2113 if (gpio_is_valid(host
->board
.det_pin
)) {
2114 res
= devm_gpio_request(&pdev
->dev
,
2115 host
->board
.det_pin
, "nand_det");
2118 "can't request det gpio %d\n",
2119 host
->board
.det_pin
);
2123 res
= gpio_direction_input(host
->board
.det_pin
);
2126 "can't request input direction det gpio %d\n",
2127 host
->board
.det_pin
);
2131 if (gpio_get_value(host
->board
.det_pin
)) {
2132 dev_info(&pdev
->dev
, "No SmartMedia card inserted.\n");
2138 if (host
->board
.on_flash_bbt
|| on_flash_bbt
) {
2139 dev_info(&pdev
->dev
, "Use On Flash BBT\n");
2140 nand_chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
2143 if (!host
->board
.has_dma
)
2147 dma_cap_mask_t mask
;
2150 dma_cap_set(DMA_MEMCPY
, mask
);
2151 host
->dma_chan
= dma_request_channel(mask
, NULL
, NULL
);
2152 if (!host
->dma_chan
) {
2153 dev_err(host
->dev
, "Failed to request DMA channel\n");
2158 dev_info(host
->dev
, "Using %s for DMA transfers.\n",
2159 dma_chan_name(host
->dma_chan
));
2161 dev_info(host
->dev
, "No DMA support for NAND access.\n");
2163 /* first scan to find the device and get the page size */
2164 if (nand_scan_ident(mtd
, 1, NULL
)) {
2166 goto err_scan_ident
;
2169 if (nand_chip
->ecc
.mode
== NAND_ECC_HW
) {
2170 if (host
->has_pmecc
)
2171 res
= atmel_pmecc_nand_init_params(pdev
, host
);
2173 res
= atmel_hw_nand_init_params(pdev
, host
);
2179 /* initialize the nfc configuration register */
2180 if (host
->nfc
&& host
->nfc
->use_nfc_sram
) {
2181 res
= nfc_sram_init(mtd
);
2183 host
->nfc
->use_nfc_sram
= false;
2184 dev_err(host
->dev
, "Disable use nfc sram for data transfer.\n");
2188 /* second phase scan */
2189 if (nand_scan_tail(mtd
)) {
2194 mtd
->name
= "atmel_nand";
2195 ppdata
.of_node
= pdev
->dev
.of_node
;
2196 res
= mtd_device_parse_register(mtd
, NULL
, &ppdata
,
2197 host
->board
.parts
, host
->board
.num_parts
);
2202 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
)
2203 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
2207 atmel_nand_disable(host
);
2209 dma_release_channel(host
->dma_chan
);
2215 * Remove a NAND device.
2217 static int atmel_nand_remove(struct platform_device
*pdev
)
2219 struct atmel_nand_host
*host
= platform_get_drvdata(pdev
);
2220 struct mtd_info
*mtd
= &host
->mtd
;
2224 atmel_nand_disable(host
);
2226 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
) {
2227 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
2228 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
,
2233 dma_release_channel(host
->dma_chan
);
2235 platform_driver_unregister(&atmel_nand_nfc_driver
);
2240 static const struct of_device_id atmel_nand_dt_ids
[] = {
2241 { .compatible
= "atmel,at91rm9200-nand" },
2245 MODULE_DEVICE_TABLE(of
, atmel_nand_dt_ids
);
2247 static int atmel_nand_nfc_probe(struct platform_device
*pdev
)
2249 struct atmel_nfc
*nfc
= &nand_nfc
;
2250 struct resource
*nfc_cmd_regs
, *nfc_hsmc_regs
, *nfc_sram
;
2252 nfc_cmd_regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2253 nfc
->base_cmd_regs
= devm_ioremap_resource(&pdev
->dev
, nfc_cmd_regs
);
2254 if (IS_ERR(nfc
->base_cmd_regs
))
2255 return PTR_ERR(nfc
->base_cmd_regs
);
2257 nfc_hsmc_regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2258 nfc
->hsmc_regs
= devm_ioremap_resource(&pdev
->dev
, nfc_hsmc_regs
);
2259 if (IS_ERR(nfc
->hsmc_regs
))
2260 return PTR_ERR(nfc
->hsmc_regs
);
2262 nfc_sram
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
2264 nfc
->sram_bank0
= devm_ioremap_resource(&pdev
->dev
, nfc_sram
);
2265 if (IS_ERR(nfc
->sram_bank0
)) {
2266 dev_warn(&pdev
->dev
, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2267 PTR_ERR(nfc
->sram_bank0
));
2269 nfc
->use_nfc_sram
= true;
2270 nfc
->sram_bank0_phys
= (dma_addr_t
)nfc_sram
->start
;
2272 if (pdev
->dev
.of_node
)
2273 nfc
->write_by_sram
= of_property_read_bool(
2275 "atmel,write-by-sram");
2279 nfc_writel(nfc
->hsmc_regs
, IDR
, 0xffffffff);
2280 nfc_readl(nfc
->hsmc_regs
, SR
); /* clear the NFC_SR */
2282 nfc
->is_initialized
= true;
2283 dev_info(&pdev
->dev
, "NFC is probed.\n");
2287 static const struct of_device_id atmel_nand_nfc_match
[] = {
2288 { .compatible
= "atmel,sama5d3-nfc" },
2291 MODULE_DEVICE_TABLE(of
, atmel_nand_nfc_match
);
2293 static struct platform_driver atmel_nand_nfc_driver
= {
2295 .name
= "atmel_nand_nfc",
2296 .owner
= THIS_MODULE
,
2297 .of_match_table
= of_match_ptr(atmel_nand_nfc_match
),
2299 .probe
= atmel_nand_nfc_probe
,
2302 static struct platform_driver atmel_nand_driver
= {
2303 .probe
= atmel_nand_probe
,
2304 .remove
= atmel_nand_remove
,
2306 .name
= "atmel_nand",
2307 .owner
= THIS_MODULE
,
2308 .of_match_table
= of_match_ptr(atmel_nand_dt_ids
),
2312 module_platform_driver(atmel_nand_driver
);
2314 MODULE_LICENSE("GPL");
2315 MODULE_AUTHOR("Rick Bronson");
2316 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2317 MODULE_ALIAS("platform:atmel_nand");