2 * Copyright © 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #include <linux/clk.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/slab.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/of_mtd.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/partitions.h>
44 #include <linux/delay.h>
45 #include <linux/dmaengine.h>
46 #include <linux/gpio.h>
47 #include <linux/interrupt.h>
49 #include <linux/platform_data/atmel.h>
51 static int use_dma
= 1;
52 module_param(use_dma
, int, 0);
54 static int on_flash_bbt
= 0;
55 module_param(on_flash_bbt
, int, 0);
57 /* Register access macros */
58 #define ecc_readl(add, reg) \
59 __raw_readl(add + ATMEL_ECC_##reg)
60 #define ecc_writel(add, reg, value) \
61 __raw_writel((value), add + ATMEL_ECC_##reg)
63 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
64 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
66 struct atmel_nand_caps
{
67 bool pmecc_correct_erase_page
;
70 /* oob layout for large page size
71 * bad block info is on bytes 0 and 1
72 * the bytes have to be consecutives to avoid
73 * several NAND_CMD_RNDOUT during read
75 static struct nand_ecclayout atmel_oobinfo_large
= {
77 .eccpos
= {60, 61, 62, 63},
83 /* oob layout for small page size
84 * bad block info is on bytes 4 and 5
85 * the bytes have to be consecutives to avoid
86 * several NAND_CMD_RNDOUT during read
88 static struct nand_ecclayout atmel_oobinfo_small
= {
90 .eccpos
= {0, 1, 2, 3},
97 void __iomem
*base_cmd_regs
;
98 void __iomem
*hsmc_regs
;
100 dma_addr_t sram_bank0_phys
;
107 struct completion comp_ready
;
108 struct completion comp_cmd_done
;
109 struct completion comp_xfer_done
;
111 /* Point to the sram bank which include readed data via NFC */
113 bool will_write_sram
;
115 static struct atmel_nfc nand_nfc
;
117 struct atmel_nand_host
{
118 struct nand_chip nand_chip
;
119 void __iomem
*io_base
;
121 struct atmel_nand_data board
;
125 struct completion comp
;
126 struct dma_chan
*dma_chan
;
128 struct atmel_nfc
*nfc
;
130 const struct atmel_nand_caps
*caps
;
133 u16 pmecc_sector_size
;
134 bool has_no_lookup_table
;
135 u32 pmecc_lookup_table_offset
;
136 u32 pmecc_lookup_table_offset_512
;
137 u32 pmecc_lookup_table_offset_1024
;
139 int pmecc_degree
; /* Degree of remainders */
140 int pmecc_cw_len
; /* Length of codeword */
142 void __iomem
*pmerrloc_base
;
143 void __iomem
*pmecc_rom_base
;
145 /* lookup table for alpha_to and index_of */
146 void __iomem
*pmecc_alpha_to
;
147 void __iomem
*pmecc_index_of
;
149 /* data for pmecc computation */
150 int16_t *pmecc_partial_syn
;
152 int16_t *pmecc_smu
; /* Sigma table */
153 int16_t *pmecc_lmu
; /* polynomal order */
159 static struct nand_ecclayout atmel_pmecc_oobinfo
;
164 static void atmel_nand_enable(struct atmel_nand_host
*host
)
166 if (gpio_is_valid(host
->board
.enable_pin
))
167 gpio_set_value(host
->board
.enable_pin
, 0);
173 static void atmel_nand_disable(struct atmel_nand_host
*host
)
175 if (gpio_is_valid(host
->board
.enable_pin
))
176 gpio_set_value(host
->board
.enable_pin
, 1);
180 * Hardware specific access to control-lines
182 static void atmel_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
184 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
185 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
187 if (ctrl
& NAND_CTRL_CHANGE
) {
189 atmel_nand_enable(host
);
191 atmel_nand_disable(host
);
193 if (cmd
== NAND_CMD_NONE
)
197 writeb(cmd
, host
->io_base
+ (1 << host
->board
.cle
));
199 writeb(cmd
, host
->io_base
+ (1 << host
->board
.ale
));
203 * Read the Device Ready pin.
205 static int atmel_nand_device_ready(struct mtd_info
*mtd
)
207 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
208 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
210 return gpio_get_value(host
->board
.rdy_pin
) ^
211 !!host
->board
.rdy_pin_active_low
;
214 /* Set up for hardware ready pin and enable pin. */
215 static int atmel_nand_set_enable_ready_pins(struct mtd_info
*mtd
)
217 struct nand_chip
*chip
= mtd_to_nand(mtd
);
218 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
221 if (gpio_is_valid(host
->board
.rdy_pin
)) {
222 res
= devm_gpio_request(host
->dev
,
223 host
->board
.rdy_pin
, "nand_rdy");
226 "can't request rdy gpio %d\n",
227 host
->board
.rdy_pin
);
231 res
= gpio_direction_input(host
->board
.rdy_pin
);
234 "can't request input direction rdy gpio %d\n",
235 host
->board
.rdy_pin
);
239 chip
->dev_ready
= atmel_nand_device_ready
;
242 if (gpio_is_valid(host
->board
.enable_pin
)) {
243 res
= devm_gpio_request(host
->dev
,
244 host
->board
.enable_pin
, "nand_enable");
247 "can't request enable gpio %d\n",
248 host
->board
.enable_pin
);
252 res
= gpio_direction_output(host
->board
.enable_pin
, 1);
255 "can't request output direction enable gpio %d\n",
256 host
->board
.enable_pin
);
265 * Minimal-overhead PIO for data access.
267 static void atmel_read_buf8(struct mtd_info
*mtd
, u8
*buf
, int len
)
269 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
270 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
272 if (host
->nfc
&& host
->nfc
->use_nfc_sram
&& host
->nfc
->data_in_sram
) {
273 memcpy(buf
, host
->nfc
->data_in_sram
, len
);
274 host
->nfc
->data_in_sram
+= len
;
276 __raw_readsb(nand_chip
->IO_ADDR_R
, buf
, len
);
280 static void atmel_read_buf16(struct mtd_info
*mtd
, u8
*buf
, int len
)
282 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
283 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
285 if (host
->nfc
&& host
->nfc
->use_nfc_sram
&& host
->nfc
->data_in_sram
) {
286 memcpy(buf
, host
->nfc
->data_in_sram
, len
);
287 host
->nfc
->data_in_sram
+= len
;
289 __raw_readsw(nand_chip
->IO_ADDR_R
, buf
, len
/ 2);
293 static void atmel_write_buf8(struct mtd_info
*mtd
, const u8
*buf
, int len
)
295 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
297 __raw_writesb(nand_chip
->IO_ADDR_W
, buf
, len
);
300 static void atmel_write_buf16(struct mtd_info
*mtd
, const u8
*buf
, int len
)
302 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
304 __raw_writesw(nand_chip
->IO_ADDR_W
, buf
, len
/ 2);
307 static void dma_complete_func(void *completion
)
309 complete(completion
);
312 static int nfc_set_sram_bank(struct atmel_nand_host
*host
, unsigned int bank
)
314 /* NFC only has two banks. Must be 0 or 1 */
319 struct mtd_info
*mtd
= nand_to_mtd(&host
->nand_chip
);
321 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
322 if (mtd
->writesize
> 2048)
324 nfc_writel(host
->nfc
->hsmc_regs
, BANK
, ATMEL_HSMC_NFC_BANK1
);
326 nfc_writel(host
->nfc
->hsmc_regs
, BANK
, ATMEL_HSMC_NFC_BANK0
);
332 static uint
nfc_get_sram_off(struct atmel_nand_host
*host
)
334 if (nfc_readl(host
->nfc
->hsmc_regs
, BANK
) & ATMEL_HSMC_NFC_BANK1
)
335 return NFC_SRAM_BANK1_OFFSET
;
340 static dma_addr_t
nfc_sram_phys(struct atmel_nand_host
*host
)
342 if (nfc_readl(host
->nfc
->hsmc_regs
, BANK
) & ATMEL_HSMC_NFC_BANK1
)
343 return host
->nfc
->sram_bank0_phys
+ NFC_SRAM_BANK1_OFFSET
;
345 return host
->nfc
->sram_bank0_phys
;
348 static int atmel_nand_dma_op(struct mtd_info
*mtd
, void *buf
, int len
,
351 struct dma_device
*dma_dev
;
352 enum dma_ctrl_flags flags
;
353 dma_addr_t dma_src_addr
, dma_dst_addr
, phys_addr
;
354 struct dma_async_tx_descriptor
*tx
= NULL
;
356 struct nand_chip
*chip
= mtd_to_nand(mtd
);
357 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
360 enum dma_data_direction dir
= is_read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
361 struct atmel_nfc
*nfc
= host
->nfc
;
363 if (buf
>= high_memory
)
366 dma_dev
= host
->dma_chan
->device
;
368 flags
= DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
;
370 phys_addr
= dma_map_single(dma_dev
->dev
, p
, len
, dir
);
371 if (dma_mapping_error(dma_dev
->dev
, phys_addr
)) {
372 dev_err(host
->dev
, "Failed to dma_map_single\n");
377 if (nfc
&& nfc
->data_in_sram
)
378 dma_src_addr
= nfc_sram_phys(host
) + (nfc
->data_in_sram
379 - (nfc
->sram_bank0
+ nfc_get_sram_off(host
)));
381 dma_src_addr
= host
->io_phys
;
383 dma_dst_addr
= phys_addr
;
385 dma_src_addr
= phys_addr
;
387 if (nfc
&& nfc
->write_by_sram
)
388 dma_dst_addr
= nfc_sram_phys(host
);
390 dma_dst_addr
= host
->io_phys
;
393 tx
= dma_dev
->device_prep_dma_memcpy(host
->dma_chan
, dma_dst_addr
,
394 dma_src_addr
, len
, flags
);
396 dev_err(host
->dev
, "Failed to prepare DMA memcpy\n");
400 init_completion(&host
->comp
);
401 tx
->callback
= dma_complete_func
;
402 tx
->callback_param
= &host
->comp
;
404 cookie
= tx
->tx_submit(tx
);
405 if (dma_submit_error(cookie
)) {
406 dev_err(host
->dev
, "Failed to do DMA tx_submit\n");
410 dma_async_issue_pending(host
->dma_chan
);
411 wait_for_completion(&host
->comp
);
413 if (is_read
&& nfc
&& nfc
->data_in_sram
)
414 /* After read data from SRAM, need to increase the position */
415 nfc
->data_in_sram
+= len
;
420 dma_unmap_single(dma_dev
->dev
, phys_addr
, len
, dir
);
423 dev_dbg(host
->dev
, "Fall back to CPU I/O\n");
427 static void atmel_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
429 struct nand_chip
*chip
= mtd_to_nand(mtd
);
430 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
432 if (use_dma
&& len
> mtd
->oobsize
)
433 /* only use DMA for bigger than oob size: better performances */
434 if (atmel_nand_dma_op(mtd
, buf
, len
, 1) == 0)
437 if (host
->board
.bus_width_16
)
438 atmel_read_buf16(mtd
, buf
, len
);
440 atmel_read_buf8(mtd
, buf
, len
);
443 static void atmel_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
445 struct nand_chip
*chip
= mtd_to_nand(mtd
);
446 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
448 if (use_dma
&& len
> mtd
->oobsize
)
449 /* only use DMA for bigger than oob size: better performances */
450 if (atmel_nand_dma_op(mtd
, (void *)buf
, len
, 0) == 0)
453 if (host
->board
.bus_width_16
)
454 atmel_write_buf16(mtd
, buf
, len
);
456 atmel_write_buf8(mtd
, buf
, len
);
460 * Return number of ecc bytes per sector according to sector size and
461 * correction capability
463 * Following table shows what at91 PMECC supported:
464 * Correction Capability Sector_512_bytes Sector_1024_bytes
465 * ===================== ================ =================
466 * 2-bits 4-bytes 4-bytes
467 * 4-bits 7-bytes 7-bytes
468 * 8-bits 13-bytes 14-bytes
469 * 12-bits 20-bytes 21-bytes
470 * 24-bits 39-bytes 42-bytes
472 static int pmecc_get_ecc_bytes(int cap
, int sector_size
)
474 int m
= 12 + sector_size
/ 512;
475 return (m
* cap
+ 7) / 8;
478 static void pmecc_config_ecc_layout(struct nand_ecclayout
*layout
,
479 int oobsize
, int ecc_len
)
483 layout
->eccbytes
= ecc_len
;
485 /* ECC will occupy the last ecc_len bytes continuously */
486 for (i
= 0; i
< ecc_len
; i
++)
487 layout
->eccpos
[i
] = oobsize
- ecc_len
+ i
;
489 layout
->oobfree
[0].offset
= PMECC_OOB_RESERVED_BYTES
;
490 layout
->oobfree
[0].length
=
491 oobsize
- ecc_len
- layout
->oobfree
[0].offset
;
494 static void __iomem
*pmecc_get_alpha_to(struct atmel_nand_host
*host
)
498 table_size
= host
->pmecc_sector_size
== 512 ?
499 PMECC_LOOKUP_TABLE_SIZE_512
: PMECC_LOOKUP_TABLE_SIZE_1024
;
501 return host
->pmecc_rom_base
+ host
->pmecc_lookup_table_offset
+
502 table_size
* sizeof(int16_t);
505 static int pmecc_data_alloc(struct atmel_nand_host
*host
)
507 const int cap
= host
->pmecc_corr_cap
;
510 size
= (2 * cap
+ 1) * sizeof(int16_t);
511 host
->pmecc_partial_syn
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
512 host
->pmecc_si
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
513 host
->pmecc_lmu
= devm_kzalloc(host
->dev
,
514 (cap
+ 1) * sizeof(int16_t), GFP_KERNEL
);
515 host
->pmecc_smu
= devm_kzalloc(host
->dev
,
516 (cap
+ 2) * size
, GFP_KERNEL
);
518 size
= (cap
+ 1) * sizeof(int);
519 host
->pmecc_mu
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
520 host
->pmecc_dmu
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
521 host
->pmecc_delta
= devm_kzalloc(host
->dev
, size
, GFP_KERNEL
);
523 if (!host
->pmecc_partial_syn
||
535 static void pmecc_gen_syndrome(struct mtd_info
*mtd
, int sector
)
537 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
538 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
542 /* Fill odd syndromes */
543 for (i
= 0; i
< host
->pmecc_corr_cap
; i
++) {
544 value
= pmecc_readl_rem_relaxed(host
->ecc
, sector
, i
/ 2);
548 host
->pmecc_partial_syn
[(2 * i
) + 1] = (int16_t)value
;
552 static void pmecc_substitute(struct mtd_info
*mtd
)
554 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
555 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
556 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
557 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
558 int16_t *partial_syn
= host
->pmecc_partial_syn
;
559 const int cap
= host
->pmecc_corr_cap
;
563 /* si[] is a table that holds the current syndrome value,
564 * an element of that table belongs to the field
568 memset(&si
[1], 0, sizeof(int16_t) * (2 * cap
- 1));
570 /* Computation 2t syndromes based on S(x) */
572 for (i
= 1; i
< 2 * cap
; i
+= 2) {
573 for (j
= 0; j
< host
->pmecc_degree
; j
++) {
574 if (partial_syn
[i
] & ((unsigned short)0x1 << j
))
575 si
[i
] = readw_relaxed(alpha_to
+ i
* j
) ^ si
[i
];
578 /* Even syndrome = (Odd syndrome) ** 2 */
579 for (i
= 2, j
= 1; j
<= cap
; i
= ++j
<< 1) {
585 tmp
= readw_relaxed(index_of
+ si
[j
]);
586 tmp
= (tmp
* 2) % host
->pmecc_cw_len
;
587 si
[i
] = readw_relaxed(alpha_to
+ tmp
);
594 static void pmecc_get_sigma(struct mtd_info
*mtd
)
596 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
597 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
599 int16_t *lmu
= host
->pmecc_lmu
;
600 int16_t *si
= host
->pmecc_si
;
601 int *mu
= host
->pmecc_mu
;
602 int *dmu
= host
->pmecc_dmu
; /* Discrepancy */
603 int *delta
= host
->pmecc_delta
; /* Delta order */
604 int cw_len
= host
->pmecc_cw_len
;
605 const int16_t cap
= host
->pmecc_corr_cap
;
606 const int num
= 2 * cap
+ 1;
607 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
608 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
610 uint32_t dmu_0_count
, tmp
;
611 int16_t *smu
= host
->pmecc_smu
;
613 /* index of largest delta */
625 memset(smu
, 0, sizeof(int16_t) * num
);
628 /* discrepancy set to 1 */
630 /* polynom order set to 0 */
632 delta
[0] = (mu
[0] * 2 - lmu
[0]) >> 1;
638 /* Sigma(x) set to 1 */
639 memset(&smu
[num
], 0, sizeof(int16_t) * num
);
642 /* discrepancy set to S1 */
645 /* polynom order set to 0 */
648 delta
[1] = (mu
[1] * 2 - lmu
[1]) >> 1;
650 /* Init the Sigma(x) last row */
651 memset(&smu
[(cap
+ 1) * num
], 0, sizeof(int16_t) * num
);
653 for (i
= 1; i
<= cap
; i
++) {
655 /* Begin Computing Sigma (Mu+1) and L(mu) */
656 /* check if discrepancy is set to 0 */
660 tmp
= ((cap
- (lmu
[i
] >> 1) - 1) / 2);
661 if ((cap
- (lmu
[i
] >> 1) - 1) & 0x1)
666 if (dmu_0_count
== tmp
) {
667 for (j
= 0; j
<= (lmu
[i
] >> 1) + 1; j
++)
668 smu
[(cap
+ 1) * num
+ j
] =
671 lmu
[cap
+ 1] = lmu
[i
];
676 for (j
= 0; j
<= lmu
[i
] >> 1; j
++)
677 smu
[(i
+ 1) * num
+ j
] = smu
[i
* num
+ j
];
679 /* copy previous polynom order to the next */
684 /* find largest delta with dmu != 0 */
685 for (j
= 0; j
< i
; j
++) {
686 if ((dmu
[j
]) && (delta
[j
] > largest
)) {
692 /* compute difference */
693 diff
= (mu
[i
] - mu
[ro
]);
695 /* Compute degree of the new smu polynomial */
696 if ((lmu
[i
] >> 1) > ((lmu
[ro
] >> 1) + diff
))
699 lmu
[i
+ 1] = ((lmu
[ro
] >> 1) + diff
) * 2;
701 /* Init smu[i+1] with 0 */
702 for (k
= 0; k
< num
; k
++)
703 smu
[(i
+ 1) * num
+ k
] = 0;
705 /* Compute smu[i+1] */
706 for (k
= 0; k
<= lmu
[ro
] >> 1; k
++) {
709 if (!(smu
[ro
* num
+ k
] && dmu
[i
]))
711 a
= readw_relaxed(index_of
+ dmu
[i
]);
712 b
= readw_relaxed(index_of
+ dmu
[ro
]);
713 c
= readw_relaxed(index_of
+ smu
[ro
* num
+ k
]);
714 tmp
= a
+ (cw_len
- b
) + c
;
715 a
= readw_relaxed(alpha_to
+ tmp
% cw_len
);
716 smu
[(i
+ 1) * num
+ (k
+ diff
)] = a
;
719 for (k
= 0; k
<= lmu
[i
] >> 1; k
++)
720 smu
[(i
+ 1) * num
+ k
] ^= smu
[i
* num
+ k
];
723 /* End Computing Sigma (Mu+1) and L(mu) */
724 /* In either case compute delta */
725 delta
[i
+ 1] = (mu
[i
+ 1] * 2 - lmu
[i
+ 1]) >> 1;
727 /* Do not compute discrepancy for the last iteration */
731 for (k
= 0; k
<= (lmu
[i
+ 1] >> 1); k
++) {
734 dmu
[i
+ 1] = si
[tmp
+ 3];
735 } else if (smu
[(i
+ 1) * num
+ k
] && si
[tmp
+ 3 - k
]) {
737 a
= readw_relaxed(index_of
+
738 smu
[(i
+ 1) * num
+ k
]);
739 b
= si
[2 * (i
- 1) + 3 - k
];
740 c
= readw_relaxed(index_of
+ b
);
743 dmu
[i
+ 1] = readw_relaxed(alpha_to
+ tmp
) ^
752 static int pmecc_err_location(struct mtd_info
*mtd
)
754 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
755 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
756 unsigned long end_time
;
757 const int cap
= host
->pmecc_corr_cap
;
758 const int num
= 2 * cap
+ 1;
759 int sector_size
= host
->pmecc_sector_size
;
760 int err_nbr
= 0; /* number of error */
761 int roots_nbr
; /* number of roots */
764 int16_t *smu
= host
->pmecc_smu
;
766 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
, PMERRLOC_DISABLE
);
768 for (i
= 0; i
<= host
->pmecc_lmu
[cap
+ 1] >> 1; i
++) {
769 pmerrloc_writel_sigma_relaxed(host
->pmerrloc_base
, i
,
770 smu
[(cap
+ 1) * num
+ i
]);
774 val
= (err_nbr
- 1) << 16;
775 if (sector_size
== 1024)
778 pmerrloc_writel(host
->pmerrloc_base
, ELCFG
, val
);
779 pmerrloc_writel(host
->pmerrloc_base
, ELEN
,
780 sector_size
* 8 + host
->pmecc_degree
* cap
);
782 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
783 while (!(pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
784 & PMERRLOC_CALC_DONE
)) {
785 if (unlikely(time_after(jiffies
, end_time
))) {
786 dev_err(host
->dev
, "PMECC: Timeout to calculate error location.\n");
792 roots_nbr
= (pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
793 & PMERRLOC_ERR_NUM_MASK
) >> 8;
794 /* Number of roots == degree of smu hence <= cap */
795 if (roots_nbr
== host
->pmecc_lmu
[cap
+ 1] >> 1)
798 /* Number of roots does not match the degree of smu
799 * unable to correct error */
803 static void pmecc_correct_data(struct mtd_info
*mtd
, uint8_t *buf
, uint8_t *ecc
,
804 int sector_num
, int extra_bytes
, int err_nbr
)
806 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
807 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
809 int byte_pos
, bit_pos
, sector_size
, pos
;
813 sector_size
= host
->pmecc_sector_size
;
816 tmp
= pmerrloc_readl_el_relaxed(host
->pmerrloc_base
, i
) - 1;
820 if (byte_pos
>= (sector_size
+ extra_bytes
))
821 BUG(); /* should never happen */
823 if (byte_pos
< sector_size
) {
824 err_byte
= *(buf
+ byte_pos
);
825 *(buf
+ byte_pos
) ^= (1 << bit_pos
);
827 pos
= sector_num
* host
->pmecc_sector_size
+ byte_pos
;
828 dev_info(host
->dev
, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
829 pos
, bit_pos
, err_byte
, *(buf
+ byte_pos
));
831 /* Bit flip in OOB area */
832 tmp
= sector_num
* nand_chip
->ecc
.bytes
833 + (byte_pos
- sector_size
);
835 ecc
[tmp
] ^= (1 << bit_pos
);
837 pos
= tmp
+ nand_chip
->ecc
.layout
->eccpos
[0];
838 dev_info(host
->dev
, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
839 pos
, bit_pos
, err_byte
, ecc
[tmp
]);
849 static int pmecc_correction(struct mtd_info
*mtd
, u32 pmecc_stat
, uint8_t *buf
,
852 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
853 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
856 int max_bitflips
= 0;
858 /* If can correct bitfilps from erased page, do the normal check */
859 if (host
->caps
->pmecc_correct_erase_page
)
862 for (i
= 0; i
< nand_chip
->ecc
.total
; i
++)
865 /* Erased page, return OK */
869 for (i
= 0; i
< nand_chip
->ecc
.steps
; i
++) {
871 if (pmecc_stat
& 0x1) {
872 buf_pos
= buf
+ i
* host
->pmecc_sector_size
;
874 pmecc_gen_syndrome(mtd
, i
);
875 pmecc_substitute(mtd
);
876 pmecc_get_sigma(mtd
);
878 err_nbr
= pmecc_err_location(mtd
);
880 dev_err(host
->dev
, "PMECC: Too many errors\n");
881 mtd
->ecc_stats
.failed
++;
884 pmecc_correct_data(mtd
, buf_pos
, ecc
, i
,
885 nand_chip
->ecc
.bytes
, err_nbr
);
886 mtd
->ecc_stats
.corrected
+= err_nbr
;
887 max_bitflips
= max_t(int, max_bitflips
, err_nbr
);
896 static void pmecc_enable(struct atmel_nand_host
*host
, int ecc_op
)
900 if (ecc_op
!= NAND_ECC_READ
&& ecc_op
!= NAND_ECC_WRITE
) {
901 dev_err(host
->dev
, "atmel_nand: wrong pmecc operation type!");
905 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
906 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
907 val
= pmecc_readl_relaxed(host
->ecc
, CFG
);
909 if (ecc_op
== NAND_ECC_READ
)
910 pmecc_writel(host
->ecc
, CFG
, (val
& ~PMECC_CFG_WRITE_OP
)
911 | PMECC_CFG_AUTO_ENABLE
);
913 pmecc_writel(host
->ecc
, CFG
, (val
| PMECC_CFG_WRITE_OP
)
914 & ~PMECC_CFG_AUTO_ENABLE
);
916 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
917 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DATA
);
920 static int atmel_nand_pmecc_read_page(struct mtd_info
*mtd
,
921 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
923 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
924 int eccsize
= chip
->ecc
.size
* chip
->ecc
.steps
;
925 uint8_t *oob
= chip
->oob_poi
;
926 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
928 unsigned long end_time
;
931 if (!host
->nfc
|| !host
->nfc
->use_nfc_sram
)
932 pmecc_enable(host
, NAND_ECC_READ
);
934 chip
->read_buf(mtd
, buf
, eccsize
);
935 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
937 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
938 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
939 if (unlikely(time_after(jiffies
, end_time
))) {
940 dev_err(host
->dev
, "PMECC: Timeout to get error status.\n");
946 stat
= pmecc_readl_relaxed(host
->ecc
, ISR
);
948 bitflips
= pmecc_correction(mtd
, stat
, buf
, &oob
[eccpos
[0]]);
950 /* uncorrectable errors */
957 static int atmel_nand_pmecc_write_page(struct mtd_info
*mtd
,
958 struct nand_chip
*chip
, const uint8_t *buf
, int oob_required
,
961 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
962 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
964 unsigned long end_time
;
966 if (!host
->nfc
|| !host
->nfc
->write_by_sram
) {
967 pmecc_enable(host
, NAND_ECC_WRITE
);
968 chip
->write_buf(mtd
, (u8
*)buf
, mtd
->writesize
);
971 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
972 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
973 if (unlikely(time_after(jiffies
, end_time
))) {
974 dev_err(host
->dev
, "PMECC: Timeout to get ECC value.\n");
980 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
981 for (j
= 0; j
< chip
->ecc
.bytes
; j
++) {
984 pos
= i
* chip
->ecc
.bytes
+ j
;
985 chip
->oob_poi
[eccpos
[pos
]] =
986 pmecc_readb_ecc_relaxed(host
->ecc
, i
, j
);
989 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
994 static void atmel_pmecc_core_init(struct mtd_info
*mtd
)
996 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
997 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
999 struct nand_ecclayout
*ecc_layout
;
1001 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
1002 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
1004 switch (host
->pmecc_corr_cap
) {
1006 val
= PMECC_CFG_BCH_ERR2
;
1009 val
= PMECC_CFG_BCH_ERR4
;
1012 val
= PMECC_CFG_BCH_ERR8
;
1015 val
= PMECC_CFG_BCH_ERR12
;
1018 val
= PMECC_CFG_BCH_ERR24
;
1022 if (host
->pmecc_sector_size
== 512)
1023 val
|= PMECC_CFG_SECTOR512
;
1024 else if (host
->pmecc_sector_size
== 1024)
1025 val
|= PMECC_CFG_SECTOR1024
;
1027 switch (nand_chip
->ecc
.steps
) {
1029 val
|= PMECC_CFG_PAGE_1SECTOR
;
1032 val
|= PMECC_CFG_PAGE_2SECTORS
;
1035 val
|= PMECC_CFG_PAGE_4SECTORS
;
1038 val
|= PMECC_CFG_PAGE_8SECTORS
;
1042 val
|= (PMECC_CFG_READ_OP
| PMECC_CFG_SPARE_DISABLE
1043 | PMECC_CFG_AUTO_DISABLE
);
1044 pmecc_writel(host
->ecc
, CFG
, val
);
1046 ecc_layout
= nand_chip
->ecc
.layout
;
1047 pmecc_writel(host
->ecc
, SAREA
, mtd
->oobsize
- 1);
1048 pmecc_writel(host
->ecc
, SADDR
, ecc_layout
->eccpos
[0]);
1049 pmecc_writel(host
->ecc
, EADDR
,
1050 ecc_layout
->eccpos
[ecc_layout
->eccbytes
- 1]);
1051 /* See datasheet about PMECC Clock Control Register */
1052 pmecc_writel(host
->ecc
, CLK
, 2);
1053 pmecc_writel(host
->ecc
, IDR
, 0xff);
1054 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
1058 * Get minimum ecc requirements from NAND.
1059 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1060 * will set them according to minimum ecc requirement. Otherwise, use the
1061 * value in DTS file.
1062 * return 0 if success. otherwise return error code.
1064 static int pmecc_choose_ecc(struct atmel_nand_host
*host
,
1065 int *cap
, int *sector_size
)
1067 /* Get minimum ECC requirements */
1068 if (host
->nand_chip
.ecc_strength_ds
) {
1069 *cap
= host
->nand_chip
.ecc_strength_ds
;
1070 *sector_size
= host
->nand_chip
.ecc_step_ds
;
1071 dev_info(host
->dev
, "minimum ECC: %d bits in %d bytes\n",
1072 *cap
, *sector_size
);
1076 dev_info(host
->dev
, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1079 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1080 if (host
->pmecc_corr_cap
== 0) {
1081 /* use the most fitable ecc bits (the near bigger one ) */
1083 host
->pmecc_corr_cap
= 2;
1085 host
->pmecc_corr_cap
= 4;
1087 host
->pmecc_corr_cap
= 8;
1088 else if (*cap
<= 12)
1089 host
->pmecc_corr_cap
= 12;
1090 else if (*cap
<= 24)
1091 host
->pmecc_corr_cap
= 24;
1095 if (host
->pmecc_sector_size
== 0) {
1096 /* use the most fitable sector size (the near smaller one ) */
1097 if (*sector_size
>= 1024)
1098 host
->pmecc_sector_size
= 1024;
1099 else if (*sector_size
>= 512)
1100 host
->pmecc_sector_size
= 512;
1107 static inline int deg(unsigned int poly
)
1109 /* polynomial degree is the most-significant bit index */
1110 return fls(poly
) - 1;
1113 static int build_gf_tables(int mm
, unsigned int poly
,
1114 int16_t *index_of
, int16_t *alpha_to
)
1116 unsigned int i
, x
= 1;
1117 const unsigned int k
= 1 << deg(poly
);
1118 unsigned int nn
= (1 << mm
) - 1;
1120 /* primitive polynomial must be of degree m */
1121 if (k
!= (1u << mm
))
1124 for (i
= 0; i
< nn
; i
++) {
1128 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
1140 static uint16_t *create_lookup_table(struct device
*dev
, int sector_size
)
1142 int degree
= (sector_size
== 512) ?
1143 PMECC_GF_DIMENSION_13
:
1144 PMECC_GF_DIMENSION_14
;
1145 unsigned int poly
= (sector_size
== 512) ?
1146 PMECC_GF_13_PRIMITIVE_POLY
:
1147 PMECC_GF_14_PRIMITIVE_POLY
;
1148 int table_size
= (sector_size
== 512) ?
1149 PMECC_LOOKUP_TABLE_SIZE_512
:
1150 PMECC_LOOKUP_TABLE_SIZE_1024
;
1152 int16_t *addr
= devm_kzalloc(dev
, 2 * table_size
* sizeof(uint16_t),
1154 if (addr
&& build_gf_tables(degree
, poly
, addr
, addr
+ table_size
))
1160 static int atmel_pmecc_nand_init_params(struct platform_device
*pdev
,
1161 struct atmel_nand_host
*host
)
1163 struct nand_chip
*nand_chip
= &host
->nand_chip
;
1164 struct mtd_info
*mtd
= nand_to_mtd(nand_chip
);
1165 struct resource
*regs
, *regs_pmerr
, *regs_rom
;
1166 uint16_t *galois_table
;
1167 int cap
, sector_size
, err_no
;
1169 err_no
= pmecc_choose_ecc(host
, &cap
, §or_size
);
1171 dev_err(host
->dev
, "The NAND flash's ECC requirement are not support!");
1175 if (cap
> host
->pmecc_corr_cap
||
1176 sector_size
!= host
->pmecc_sector_size
)
1177 dev_info(host
->dev
, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1179 cap
= host
->pmecc_corr_cap
;
1180 sector_size
= host
->pmecc_sector_size
;
1181 host
->pmecc_lookup_table_offset
= (sector_size
== 512) ?
1182 host
->pmecc_lookup_table_offset_512
:
1183 host
->pmecc_lookup_table_offset_1024
;
1185 dev_info(host
->dev
, "Initialize PMECC params, cap: %d, sector: %d\n",
1188 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1191 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1192 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1196 host
->ecc
= devm_ioremap_resource(&pdev
->dev
, regs
);
1197 if (IS_ERR(host
->ecc
)) {
1198 err_no
= PTR_ERR(host
->ecc
);
1202 regs_pmerr
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
1203 host
->pmerrloc_base
= devm_ioremap_resource(&pdev
->dev
, regs_pmerr
);
1204 if (IS_ERR(host
->pmerrloc_base
)) {
1205 err_no
= PTR_ERR(host
->pmerrloc_base
);
1209 if (!host
->has_no_lookup_table
) {
1210 regs_rom
= platform_get_resource(pdev
, IORESOURCE_MEM
, 3);
1211 host
->pmecc_rom_base
= devm_ioremap_resource(&pdev
->dev
,
1213 if (IS_ERR(host
->pmecc_rom_base
)) {
1214 dev_err(host
->dev
, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
1215 host
->has_no_lookup_table
= true;
1219 if (host
->has_no_lookup_table
) {
1220 /* Build the look-up table in runtime */
1221 galois_table
= create_lookup_table(host
->dev
, sector_size
);
1222 if (!galois_table
) {
1223 dev_err(host
->dev
, "Failed to build a lookup table in runtime!\n");
1228 host
->pmecc_rom_base
= (void __iomem
*)galois_table
;
1229 host
->pmecc_lookup_table_offset
= 0;
1232 nand_chip
->ecc
.size
= sector_size
;
1234 /* set ECC page size and oob layout */
1235 switch (mtd
->writesize
) {
1241 if (sector_size
> mtd
->writesize
) {
1242 dev_err(host
->dev
, "pmecc sector size is bigger than the page size!\n");
1247 host
->pmecc_degree
= (sector_size
== 512) ?
1248 PMECC_GF_DIMENSION_13
: PMECC_GF_DIMENSION_14
;
1249 host
->pmecc_cw_len
= (1 << host
->pmecc_degree
) - 1;
1250 host
->pmecc_alpha_to
= pmecc_get_alpha_to(host
);
1251 host
->pmecc_index_of
= host
->pmecc_rom_base
+
1252 host
->pmecc_lookup_table_offset
;
1254 nand_chip
->ecc
.strength
= cap
;
1255 nand_chip
->ecc
.bytes
= pmecc_get_ecc_bytes(cap
, sector_size
);
1256 nand_chip
->ecc
.steps
= mtd
->writesize
/ sector_size
;
1257 nand_chip
->ecc
.total
= nand_chip
->ecc
.bytes
*
1258 nand_chip
->ecc
.steps
;
1259 if (nand_chip
->ecc
.total
>
1260 mtd
->oobsize
- PMECC_OOB_RESERVED_BYTES
) {
1261 dev_err(host
->dev
, "No room for ECC bytes\n");
1265 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo
,
1267 nand_chip
->ecc
.total
);
1269 nand_chip
->ecc
.layout
= &atmel_pmecc_oobinfo
;
1273 "Unsupported page size for PMECC, use Software ECC\n");
1274 /* page size not handled by HW ECC */
1275 /* switching back to soft ECC */
1276 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1280 /* Allocate data for PMECC computation */
1281 err_no
= pmecc_data_alloc(host
);
1284 "Cannot allocate memory for PMECC computation!\n");
1288 nand_chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
1289 nand_chip
->ecc
.read_page
= atmel_nand_pmecc_read_page
;
1290 nand_chip
->ecc
.write_page
= atmel_nand_pmecc_write_page
;
1292 atmel_pmecc_core_init(mtd
);
1303 * function called after a write
1305 * mtd: MTD block structure
1306 * dat: raw data (unused)
1307 * ecc_code: buffer for ECC
1309 static int atmel_nand_calculate(struct mtd_info
*mtd
,
1310 const u_char
*dat
, unsigned char *ecc_code
)
1312 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1313 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
1314 unsigned int ecc_value
;
1316 /* get the first 2 ECC bytes */
1317 ecc_value
= ecc_readl(host
->ecc
, PR
);
1319 ecc_code
[0] = ecc_value
& 0xFF;
1320 ecc_code
[1] = (ecc_value
>> 8) & 0xFF;
1322 /* get the last 2 ECC bytes */
1323 ecc_value
= ecc_readl(host
->ecc
, NPR
) & ATMEL_ECC_NPARITY
;
1325 ecc_code
[2] = ecc_value
& 0xFF;
1326 ecc_code
[3] = (ecc_value
>> 8) & 0xFF;
1332 * HW ECC read page function
1334 * mtd: mtd info structure
1335 * chip: nand chip info structure
1336 * buf: buffer to store read data
1337 * oob_required: caller expects OOB data read to chip->oob_poi
1339 static int atmel_nand_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1340 uint8_t *buf
, int oob_required
, int page
)
1342 int eccsize
= chip
->ecc
.size
;
1343 int eccbytes
= chip
->ecc
.bytes
;
1344 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1346 uint8_t *oob
= chip
->oob_poi
;
1349 unsigned int max_bitflips
= 0;
1352 * Errata: ALE is incorrectly wired up to the ECC controller
1353 * on the AP7000, so it will include the address cycles in the
1356 * Workaround: Reset the parity registers before reading the
1359 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
1360 if (host
->board
.need_reset_workaround
)
1361 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1364 chip
->read_buf(mtd
, p
, eccsize
);
1366 /* move to ECC position if needed */
1367 if (eccpos
[0] != 0) {
1368 /* This only works on large pages
1369 * because the ECC controller waits for
1370 * NAND_CMD_RNDOUTSTART after the
1372 * anyway, for small pages, the eccpos[0] == 0
1374 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1375 mtd
->writesize
+ eccpos
[0], -1);
1378 /* the ECC controller needs to read the ECC just after the data */
1379 ecc_pos
= oob
+ eccpos
[0];
1380 chip
->read_buf(mtd
, ecc_pos
, eccbytes
);
1382 /* check if there's an error */
1383 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1386 mtd
->ecc_stats
.failed
++;
1388 mtd
->ecc_stats
.corrected
+= stat
;
1389 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1392 /* get back to oob start (end of page) */
1393 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1396 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
1398 return max_bitflips
;
1404 * function called after a read
1406 * mtd: MTD block structure
1407 * dat: raw data read from the chip
1408 * read_ecc: ECC from the chip (unused)
1411 * Detect and correct a 1 bit error for a page
1413 static int atmel_nand_correct(struct mtd_info
*mtd
, u_char
*dat
,
1414 u_char
*read_ecc
, u_char
*isnull
)
1416 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1417 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
1418 unsigned int ecc_status
;
1419 unsigned int ecc_word
, ecc_bit
;
1421 /* get the status from the Status Register */
1422 ecc_status
= ecc_readl(host
->ecc
, SR
);
1424 /* if there's no error */
1425 if (likely(!(ecc_status
& ATMEL_ECC_RECERR
)))
1428 /* get error bit offset (4 bits) */
1429 ecc_bit
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_BITADDR
;
1430 /* get word address (12 bits) */
1431 ecc_word
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_WORDADDR
;
1434 /* if there are multiple errors */
1435 if (ecc_status
& ATMEL_ECC_MULERR
) {
1436 /* check if it is a freshly erased block
1437 * (filled with 0xff) */
1438 if ((ecc_bit
== ATMEL_ECC_BITADDR
)
1439 && (ecc_word
== (ATMEL_ECC_WORDADDR
>> 4))) {
1440 /* the block has just been erased, return OK */
1443 /* it doesn't seems to be a freshly
1445 * We can't correct so many errors */
1446 dev_dbg(host
->dev
, "atmel_nand : multiple errors detected."
1447 " Unable to correct.\n");
1451 /* if there's a single bit error : we can correct it */
1452 if (ecc_status
& ATMEL_ECC_ECCERR
) {
1453 /* there's nothing much to do here.
1454 * the bit error is on the ECC itself.
1456 dev_dbg(host
->dev
, "atmel_nand : one bit error on ECC code."
1457 " Nothing to correct\n");
1461 dev_dbg(host
->dev
, "atmel_nand : one bit error on data."
1462 " (word offset in the page :"
1463 " 0x%x bit offset : 0x%x)\n",
1465 /* correct the error */
1466 if (nand_chip
->options
& NAND_BUSWIDTH_16
) {
1468 ((unsigned short *) dat
)[ecc_word
] ^= (1 << ecc_bit
);
1471 dat
[ecc_word
] ^= (1 << ecc_bit
);
1473 dev_dbg(host
->dev
, "atmel_nand : error corrected\n");
1478 * Enable HW ECC : unused on most chips
1480 static void atmel_nand_hwctl(struct mtd_info
*mtd
, int mode
)
1482 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1483 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
1485 if (host
->board
.need_reset_workaround
)
1486 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1489 static const struct of_device_id atmel_nand_dt_ids
[];
1491 static int atmel_of_init_port(struct atmel_nand_host
*host
,
1492 struct device_node
*np
)
1497 struct atmel_nand_data
*board
= &host
->board
;
1498 enum of_gpio_flags flags
= 0;
1500 host
->caps
= (struct atmel_nand_caps
*)
1501 of_match_device(atmel_nand_dt_ids
, host
->dev
)->data
;
1503 if (of_property_read_u32(np
, "atmel,nand-addr-offset", &val
) == 0) {
1505 dev_err(host
->dev
, "invalid addr-offset %u\n", val
);
1511 if (of_property_read_u32(np
, "atmel,nand-cmd-offset", &val
) == 0) {
1513 dev_err(host
->dev
, "invalid cmd-offset %u\n", val
);
1519 ecc_mode
= of_get_nand_ecc_mode(np
);
1521 board
->ecc_mode
= ecc_mode
< 0 ? NAND_ECC_SOFT
: ecc_mode
;
1523 board
->on_flash_bbt
= of_get_nand_on_flash_bbt(np
);
1525 board
->has_dma
= of_property_read_bool(np
, "atmel,nand-has-dma");
1527 if (of_get_nand_bus_width(np
) == 16)
1528 board
->bus_width_16
= 1;
1530 board
->rdy_pin
= of_get_gpio_flags(np
, 0, &flags
);
1531 board
->rdy_pin_active_low
= (flags
== OF_GPIO_ACTIVE_LOW
);
1533 board
->enable_pin
= of_get_gpio(np
, 1);
1534 board
->det_pin
= of_get_gpio(np
, 2);
1536 host
->has_pmecc
= of_property_read_bool(np
, "atmel,has-pmecc");
1538 /* load the nfc driver if there is */
1539 of_platform_populate(np
, NULL
, NULL
, host
->dev
);
1541 if (!(board
->ecc_mode
== NAND_ECC_HW
) || !host
->has_pmecc
)
1542 return 0; /* Not using PMECC */
1544 /* use PMECC, get correction capability, sector size and lookup
1546 * If correction bits and sector size are not specified, then find
1547 * them from NAND ONFI parameters.
1549 if (of_property_read_u32(np
, "atmel,pmecc-cap", &val
) == 0) {
1550 if ((val
!= 2) && (val
!= 4) && (val
!= 8) && (val
!= 12) &&
1553 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1557 host
->pmecc_corr_cap
= (u8
)val
;
1560 if (of_property_read_u32(np
, "atmel,pmecc-sector-size", &val
) == 0) {
1561 if ((val
!= 512) && (val
!= 1024)) {
1563 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1567 host
->pmecc_sector_size
= (u16
)val
;
1570 if (of_property_read_u32_array(np
, "atmel,pmecc-lookup-table-offset",
1572 dev_err(host
->dev
, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
1573 host
->has_no_lookup_table
= true;
1574 /* Will build a lookup table and initialize the offset later */
1577 if (!offset
[0] && !offset
[1]) {
1578 dev_err(host
->dev
, "Invalid PMECC lookup table offset\n");
1581 host
->pmecc_lookup_table_offset_512
= offset
[0];
1582 host
->pmecc_lookup_table_offset_1024
= offset
[1];
1587 static int atmel_hw_nand_init_params(struct platform_device
*pdev
,
1588 struct atmel_nand_host
*host
)
1590 struct nand_chip
*nand_chip
= &host
->nand_chip
;
1591 struct mtd_info
*mtd
= nand_to_mtd(nand_chip
);
1592 struct resource
*regs
;
1594 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1597 "Can't get I/O resource regs, use software ECC\n");
1598 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1602 host
->ecc
= devm_ioremap_resource(&pdev
->dev
, regs
);
1603 if (IS_ERR(host
->ecc
))
1604 return PTR_ERR(host
->ecc
);
1606 /* ECC is calculated for the whole page (1 step) */
1607 nand_chip
->ecc
.size
= mtd
->writesize
;
1609 /* set ECC page size and oob layout */
1610 switch (mtd
->writesize
) {
1612 nand_chip
->ecc
.layout
= &atmel_oobinfo_small
;
1613 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_528
);
1616 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1617 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_1056
);
1620 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1621 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_2112
);
1624 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1625 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_4224
);
1628 /* page size not handled by HW ECC */
1629 /* switching back to soft ECC */
1630 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1634 /* set up for HW ECC */
1635 nand_chip
->ecc
.calculate
= atmel_nand_calculate
;
1636 nand_chip
->ecc
.correct
= atmel_nand_correct
;
1637 nand_chip
->ecc
.hwctl
= atmel_nand_hwctl
;
1638 nand_chip
->ecc
.read_page
= atmel_nand_read_page
;
1639 nand_chip
->ecc
.bytes
= 4;
1640 nand_chip
->ecc
.strength
= 1;
1645 static inline u32
nfc_read_status(struct atmel_nand_host
*host
)
1647 u32 err_flags
= NFC_SR_DTOE
| NFC_SR_UNDEF
| NFC_SR_AWB
| NFC_SR_ASE
;
1648 u32 nfc_status
= nfc_readl(host
->nfc
->hsmc_regs
, SR
);
1650 if (unlikely(nfc_status
& err_flags
)) {
1651 if (nfc_status
& NFC_SR_DTOE
)
1652 dev_err(host
->dev
, "NFC: Waiting Nand R/B Timeout Error\n");
1653 else if (nfc_status
& NFC_SR_UNDEF
)
1654 dev_err(host
->dev
, "NFC: Access Undefined Area Error\n");
1655 else if (nfc_status
& NFC_SR_AWB
)
1656 dev_err(host
->dev
, "NFC: Access memory While NFC is busy\n");
1657 else if (nfc_status
& NFC_SR_ASE
)
1658 dev_err(host
->dev
, "NFC: Access memory Size Error\n");
1664 /* SMC interrupt service routine */
1665 static irqreturn_t
hsmc_interrupt(int irq
, void *dev_id
)
1667 struct atmel_nand_host
*host
= dev_id
;
1668 u32 status
, mask
, pending
;
1669 irqreturn_t ret
= IRQ_NONE
;
1671 status
= nfc_read_status(host
);
1672 mask
= nfc_readl(host
->nfc
->hsmc_regs
, IMR
);
1673 pending
= status
& mask
;
1675 if (pending
& NFC_SR_XFR_DONE
) {
1676 complete(&host
->nfc
->comp_xfer_done
);
1677 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, NFC_SR_XFR_DONE
);
1680 if (pending
& NFC_SR_RB_EDGE
) {
1681 complete(&host
->nfc
->comp_ready
);
1682 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, NFC_SR_RB_EDGE
);
1685 if (pending
& NFC_SR_CMD_DONE
) {
1686 complete(&host
->nfc
->comp_cmd_done
);
1687 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, NFC_SR_CMD_DONE
);
1694 /* NFC(Nand Flash Controller) related functions */
1695 static void nfc_prepare_interrupt(struct atmel_nand_host
*host
, u32 flag
)
1697 if (flag
& NFC_SR_XFR_DONE
)
1698 init_completion(&host
->nfc
->comp_xfer_done
);
1700 if (flag
& NFC_SR_RB_EDGE
)
1701 init_completion(&host
->nfc
->comp_ready
);
1703 if (flag
& NFC_SR_CMD_DONE
)
1704 init_completion(&host
->nfc
->comp_cmd_done
);
1706 /* Enable interrupt that need to wait for */
1707 nfc_writel(host
->nfc
->hsmc_regs
, IER
, flag
);
1710 static int nfc_wait_interrupt(struct atmel_nand_host
*host
, u32 flag
)
1713 struct completion
*comp
[3]; /* Support 3 interrupt completion */
1715 if (flag
& NFC_SR_XFR_DONE
)
1716 comp
[index
++] = &host
->nfc
->comp_xfer_done
;
1718 if (flag
& NFC_SR_RB_EDGE
)
1719 comp
[index
++] = &host
->nfc
->comp_ready
;
1721 if (flag
& NFC_SR_CMD_DONE
)
1722 comp
[index
++] = &host
->nfc
->comp_cmd_done
;
1725 dev_err(host
->dev
, "Unknown interrupt flag: 0x%08x\n", flag
);
1729 for (i
= 0; i
< index
; i
++) {
1730 if (wait_for_completion_timeout(comp
[i
],
1731 msecs_to_jiffies(NFC_TIME_OUT_MS
)))
1732 continue; /* wait for next completion */
1740 dev_err(host
->dev
, "Time out to wait for interrupt: 0x%08x\n", flag
);
1741 /* Disable the interrupt as it is not handled by interrupt handler */
1742 nfc_writel(host
->nfc
->hsmc_regs
, IDR
, flag
);
1746 static int nfc_send_command(struct atmel_nand_host
*host
,
1747 unsigned int cmd
, unsigned int addr
, unsigned char cycle0
)
1749 unsigned long timeout
;
1750 u32 flag
= NFC_SR_CMD_DONE
;
1751 flag
|= cmd
& NFCADDR_CMD_DATAEN
? NFC_SR_XFR_DONE
: 0;
1754 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1757 timeout
= jiffies
+ msecs_to_jiffies(NFC_TIME_OUT_MS
);
1758 while (nfc_readl(host
->nfc
->hsmc_regs
, SR
) & NFC_SR_BUSY
) {
1759 if (time_after(jiffies
, timeout
)) {
1761 "Time out to wait for NFC ready!\n");
1766 nfc_prepare_interrupt(host
, flag
);
1767 nfc_writel(host
->nfc
->hsmc_regs
, CYCLE0
, cycle0
);
1768 nfc_cmd_addr1234_writel(cmd
, addr
, host
->nfc
->base_cmd_regs
);
1769 return nfc_wait_interrupt(host
, flag
);
1772 static int nfc_device_ready(struct mtd_info
*mtd
)
1775 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1776 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
1778 status
= nfc_read_status(host
);
1779 mask
= nfc_readl(host
->nfc
->hsmc_regs
, IMR
);
1781 /* The mask should be 0. If not we may lost interrupts */
1782 if (unlikely(mask
& status
))
1783 dev_err(host
->dev
, "Lost the interrupt flags: 0x%08x\n",
1786 return status
& NFC_SR_RB_EDGE
;
1789 static void nfc_select_chip(struct mtd_info
*mtd
, int chip
)
1791 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1792 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
1795 nfc_writel(host
->nfc
->hsmc_regs
, CTRL
, NFC_CTRL_DISABLE
);
1797 nfc_writel(host
->nfc
->hsmc_regs
, CTRL
, NFC_CTRL_ENABLE
);
1800 static int nfc_make_addr(struct mtd_info
*mtd
, int command
, int column
,
1801 int page_addr
, unsigned int *addr1234
, unsigned int *cycle0
)
1803 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1806 unsigned char addr_bytes
[8];
1807 int index
= 0, bit_shift
;
1809 BUG_ON(addr1234
== NULL
|| cycle0
== NULL
);
1815 if (chip
->options
& NAND_BUSWIDTH_16
&&
1816 !nand_opcode_8bits(command
))
1818 addr_bytes
[acycle
++] = column
& 0xff;
1819 if (mtd
->writesize
> 512)
1820 addr_bytes
[acycle
++] = (column
>> 8) & 0xff;
1823 if (page_addr
!= -1) {
1824 addr_bytes
[acycle
++] = page_addr
& 0xff;
1825 addr_bytes
[acycle
++] = (page_addr
>> 8) & 0xff;
1826 if (chip
->chipsize
> (128 << 20))
1827 addr_bytes
[acycle
++] = (page_addr
>> 16) & 0xff;
1831 *cycle0
= addr_bytes
[index
++];
1833 for (bit_shift
= 0; index
< acycle
; bit_shift
+= 8)
1834 *addr1234
+= addr_bytes
[index
++] << bit_shift
;
1836 /* return acycle in cmd register */
1837 return acycle
<< NFCADDR_CMD_ACYCLE_BIT_POS
;
1840 static void nfc_nand_command(struct mtd_info
*mtd
, unsigned int command
,
1841 int column
, int page_addr
)
1843 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1844 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
1845 unsigned long timeout
;
1846 unsigned int nfc_addr_cmd
= 0;
1848 unsigned int cmd1
= command
<< NFCADDR_CMD_CMD1_BIT_POS
;
1850 /* Set default settings: no cmd2, no addr cycle. read from nand */
1851 unsigned int cmd2
= 0;
1852 unsigned int vcmd2
= 0;
1853 int acycle
= NFCADDR_CMD_ACYCLE_NONE
;
1854 int csid
= NFCADDR_CMD_CSID_3
;
1855 int dataen
= NFCADDR_CMD_DATADIS
;
1856 int nfcwr
= NFCADDR_CMD_NFCRD
;
1857 unsigned int addr1234
= 0;
1858 unsigned int cycle0
= 0;
1859 bool do_addr
= true;
1860 host
->nfc
->data_in_sram
= NULL
;
1862 dev_dbg(host
->dev
, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1863 __func__
, command
, column
, page_addr
);
1866 case NAND_CMD_RESET
:
1867 nfc_addr_cmd
= cmd1
| acycle
| csid
| dataen
| nfcwr
;
1868 nfc_send_command(host
, nfc_addr_cmd
, addr1234
, cycle0
);
1869 udelay(chip
->chip_delay
);
1871 nfc_nand_command(mtd
, NAND_CMD_STATUS
, -1, -1);
1872 timeout
= jiffies
+ msecs_to_jiffies(NFC_TIME_OUT_MS
);
1873 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
)) {
1874 if (time_after(jiffies
, timeout
)) {
1876 "Time out to wait status ready!\n");
1881 case NAND_CMD_STATUS
:
1884 case NAND_CMD_PARAM
:
1885 case NAND_CMD_READID
:
1887 acycle
= NFCADDR_CMD_ACYCLE_1
;
1891 case NAND_CMD_RNDOUT
:
1892 cmd2
= NAND_CMD_RNDOUTSTART
<< NFCADDR_CMD_CMD2_BIT_POS
;
1893 vcmd2
= NFCADDR_CMD_VCMD2
;
1895 case NAND_CMD_READ0
:
1896 case NAND_CMD_READOOB
:
1897 if (command
== NAND_CMD_READOOB
) {
1898 column
+= mtd
->writesize
;
1899 command
= NAND_CMD_READ0
; /* only READ0 is valid */
1900 cmd1
= command
<< NFCADDR_CMD_CMD1_BIT_POS
;
1902 if (host
->nfc
->use_nfc_sram
) {
1903 /* Enable Data transfer to sram */
1904 dataen
= NFCADDR_CMD_DATAEN
;
1906 /* Need enable PMECC now, since NFC will transfer
1907 * data in bus after sending nfc read command.
1909 if (chip
->ecc
.mode
== NAND_ECC_HW
&& host
->has_pmecc
)
1910 pmecc_enable(host
, NAND_ECC_READ
);
1913 cmd2
= NAND_CMD_READSTART
<< NFCADDR_CMD_CMD2_BIT_POS
;
1914 vcmd2
= NFCADDR_CMD_VCMD2
;
1916 /* For prgramming command, the cmd need set to write enable */
1917 case NAND_CMD_PAGEPROG
:
1918 case NAND_CMD_SEQIN
:
1919 case NAND_CMD_RNDIN
:
1920 nfcwr
= NFCADDR_CMD_NFCWR
;
1921 if (host
->nfc
->will_write_sram
&& command
== NAND_CMD_SEQIN
)
1922 dataen
= NFCADDR_CMD_DATAEN
;
1929 acycle
= nfc_make_addr(mtd
, command
, column
, page_addr
,
1930 &addr1234
, &cycle0
);
1932 nfc_addr_cmd
= cmd1
| cmd2
| vcmd2
| acycle
| csid
| dataen
| nfcwr
;
1933 nfc_send_command(host
, nfc_addr_cmd
, addr1234
, cycle0
);
1936 * Program and erase have their own busy handlers status, sequential
1937 * in, and deplete1 need no delay.
1940 case NAND_CMD_CACHEDPROG
:
1941 case NAND_CMD_PAGEPROG
:
1942 case NAND_CMD_ERASE1
:
1943 case NAND_CMD_ERASE2
:
1944 case NAND_CMD_RNDIN
:
1945 case NAND_CMD_STATUS
:
1946 case NAND_CMD_RNDOUT
:
1947 case NAND_CMD_SEQIN
:
1948 case NAND_CMD_READID
:
1951 case NAND_CMD_READ0
:
1952 if (dataen
== NFCADDR_CMD_DATAEN
) {
1953 host
->nfc
->data_in_sram
= host
->nfc
->sram_bank0
+
1954 nfc_get_sram_off(host
);
1959 nfc_prepare_interrupt(host
, NFC_SR_RB_EDGE
);
1960 nfc_wait_interrupt(host
, NFC_SR_RB_EDGE
);
1964 static int nfc_sram_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1965 uint32_t offset
, int data_len
, const uint8_t *buf
,
1966 int oob_required
, int page
, int cached
, int raw
)
1970 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
1971 void *sram
= host
->nfc
->sram_bank0
+ nfc_get_sram_off(host
);
1973 /* Subpage write is not supported */
1974 if (offset
|| (data_len
< mtd
->writesize
))
1977 len
= mtd
->writesize
;
1978 /* Copy page data to sram that will write to nand via NFC */
1980 if (atmel_nand_dma_op(mtd
, (void *)buf
, len
, 0) != 0)
1981 /* Fall back to use cpu copy */
1982 memcpy(sram
, buf
, len
);
1984 memcpy(sram
, buf
, len
);
1987 cfg
= nfc_readl(host
->nfc
->hsmc_regs
, CFG
);
1988 if (unlikely(raw
) && oob_required
) {
1989 memcpy(sram
+ len
, chip
->oob_poi
, mtd
->oobsize
);
1990 len
+= mtd
->oobsize
;
1991 nfc_writel(host
->nfc
->hsmc_regs
, CFG
, cfg
| NFC_CFG_WSPARE
);
1993 nfc_writel(host
->nfc
->hsmc_regs
, CFG
, cfg
& ~NFC_CFG_WSPARE
);
1996 if (chip
->ecc
.mode
== NAND_ECC_HW
&& host
->has_pmecc
)
1998 * When use NFC sram, need set up PMECC before send
1999 * NAND_CMD_SEQIN command. Since when the nand command
2000 * is sent, nfc will do transfer from sram and nand.
2002 pmecc_enable(host
, NAND_ECC_WRITE
);
2004 host
->nfc
->will_write_sram
= true;
2005 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2006 host
->nfc
->will_write_sram
= false;
2009 /* Need to write ecc into oob */
2010 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
,
2016 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2017 status
= chip
->waitfunc(mtd
, chip
);
2019 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2020 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
, page
);
2022 if (status
& NAND_STATUS_FAIL
)
2028 static int nfc_sram_init(struct mtd_info
*mtd
)
2030 struct nand_chip
*chip
= mtd_to_nand(mtd
);
2031 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
2034 /* Initialize the NFC CFG register */
2035 unsigned int cfg_nfc
= 0;
2037 /* set page size and oob layout */
2038 switch (mtd
->writesize
) {
2040 cfg_nfc
= NFC_CFG_PAGESIZE_512
;
2043 cfg_nfc
= NFC_CFG_PAGESIZE_1024
;
2046 cfg_nfc
= NFC_CFG_PAGESIZE_2048
;
2049 cfg_nfc
= NFC_CFG_PAGESIZE_4096
;
2052 cfg_nfc
= NFC_CFG_PAGESIZE_8192
;
2055 dev_err(host
->dev
, "Unsupported page size for NFC.\n");
2060 /* oob bytes size = (NFCSPARESIZE + 1) * 4
2061 * Max support spare size is 512 bytes. */
2062 cfg_nfc
|= (((mtd
->oobsize
/ 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
2063 & NFC_CFG_NFC_SPARESIZE
);
2064 /* default set a max timeout */
2065 cfg_nfc
|= NFC_CFG_RSPARE
|
2066 NFC_CFG_NFC_DTOCYC
| NFC_CFG_NFC_DTOMUL
;
2068 nfc_writel(host
->nfc
->hsmc_regs
, CFG
, cfg_nfc
);
2070 host
->nfc
->will_write_sram
= false;
2071 nfc_set_sram_bank(host
, 0);
2073 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2074 if (host
->nfc
->write_by_sram
) {
2075 if ((chip
->ecc
.mode
== NAND_ECC_HW
&& host
->has_pmecc
) ||
2076 chip
->ecc
.mode
== NAND_ECC_NONE
)
2077 chip
->write_page
= nfc_sram_write_page
;
2079 host
->nfc
->write_by_sram
= false;
2082 dev_info(host
->dev
, "Using NFC Sram read %s\n",
2083 host
->nfc
->write_by_sram
? "and write" : "");
2087 static struct platform_driver atmel_nand_nfc_driver
;
2089 * Probe for the NAND device.
2091 static int atmel_nand_probe(struct platform_device
*pdev
)
2093 struct atmel_nand_host
*host
;
2094 struct mtd_info
*mtd
;
2095 struct nand_chip
*nand_chip
;
2096 struct resource
*mem
;
2099 /* Allocate memory for the device structure (and zero it) */
2100 host
= devm_kzalloc(&pdev
->dev
, sizeof(*host
), GFP_KERNEL
);
2104 res
= platform_driver_register(&atmel_nand_nfc_driver
);
2106 dev_err(&pdev
->dev
, "atmel_nand: can't register NFC driver\n");
2108 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2109 host
->io_base
= devm_ioremap_resource(&pdev
->dev
, mem
);
2110 if (IS_ERR(host
->io_base
)) {
2111 res
= PTR_ERR(host
->io_base
);
2112 goto err_nand_ioremap
;
2114 host
->io_phys
= (dma_addr_t
)mem
->start
;
2116 nand_chip
= &host
->nand_chip
;
2117 mtd
= nand_to_mtd(nand_chip
);
2118 host
->dev
= &pdev
->dev
;
2119 if (IS_ENABLED(CONFIG_OF
) && pdev
->dev
.of_node
) {
2120 nand_set_flash_node(nand_chip
, pdev
->dev
.of_node
);
2121 /* Only when CONFIG_OF is enabled of_node can be parsed */
2122 res
= atmel_of_init_port(host
, pdev
->dev
.of_node
);
2124 goto err_nand_ioremap
;
2126 memcpy(&host
->board
, dev_get_platdata(&pdev
->dev
),
2127 sizeof(struct atmel_nand_data
));
2130 /* link the private data structures */
2131 nand_set_controller_data(nand_chip
, host
);
2132 mtd
->dev
.parent
= &pdev
->dev
;
2134 /* Set address of NAND IO lines */
2135 nand_chip
->IO_ADDR_R
= host
->io_base
;
2136 nand_chip
->IO_ADDR_W
= host
->io_base
;
2138 if (nand_nfc
.is_initialized
) {
2139 /* NFC driver is probed and initialized */
2140 host
->nfc
= &nand_nfc
;
2142 nand_chip
->select_chip
= nfc_select_chip
;
2143 nand_chip
->dev_ready
= nfc_device_ready
;
2144 nand_chip
->cmdfunc
= nfc_nand_command
;
2146 /* Initialize the interrupt for NFC */
2147 irq
= platform_get_irq(pdev
, 0);
2149 dev_err(host
->dev
, "Cannot get HSMC irq!\n");
2151 goto err_nand_ioremap
;
2154 res
= devm_request_irq(&pdev
->dev
, irq
, hsmc_interrupt
,
2157 dev_err(&pdev
->dev
, "Unable to request HSMC irq %d\n",
2159 goto err_nand_ioremap
;
2162 res
= atmel_nand_set_enable_ready_pins(mtd
);
2164 goto err_nand_ioremap
;
2166 nand_chip
->cmd_ctrl
= atmel_nand_cmd_ctrl
;
2169 nand_chip
->ecc
.mode
= host
->board
.ecc_mode
;
2170 nand_chip
->chip_delay
= 40; /* 40us command delay time */
2172 if (host
->board
.bus_width_16
) /* 16-bit bus width */
2173 nand_chip
->options
|= NAND_BUSWIDTH_16
;
2175 nand_chip
->read_buf
= atmel_read_buf
;
2176 nand_chip
->write_buf
= atmel_write_buf
;
2178 platform_set_drvdata(pdev
, host
);
2179 atmel_nand_enable(host
);
2181 if (gpio_is_valid(host
->board
.det_pin
)) {
2182 res
= devm_gpio_request(&pdev
->dev
,
2183 host
->board
.det_pin
, "nand_det");
2186 "can't request det gpio %d\n",
2187 host
->board
.det_pin
);
2191 res
= gpio_direction_input(host
->board
.det_pin
);
2194 "can't request input direction det gpio %d\n",
2195 host
->board
.det_pin
);
2199 if (gpio_get_value(host
->board
.det_pin
)) {
2200 dev_info(&pdev
->dev
, "No SmartMedia card inserted.\n");
2206 if (host
->board
.on_flash_bbt
|| on_flash_bbt
) {
2207 dev_info(&pdev
->dev
, "Use On Flash BBT\n");
2208 nand_chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
2211 if (!host
->board
.has_dma
)
2215 dma_cap_mask_t mask
;
2218 dma_cap_set(DMA_MEMCPY
, mask
);
2219 host
->dma_chan
= dma_request_channel(mask
, NULL
, NULL
);
2220 if (!host
->dma_chan
) {
2221 dev_err(host
->dev
, "Failed to request DMA channel\n");
2226 dev_info(host
->dev
, "Using %s for DMA transfers.\n",
2227 dma_chan_name(host
->dma_chan
));
2229 dev_info(host
->dev
, "No DMA support for NAND access.\n");
2231 /* first scan to find the device and get the page size */
2232 if (nand_scan_ident(mtd
, 1, NULL
)) {
2234 goto err_scan_ident
;
2237 if (nand_chip
->ecc
.mode
== NAND_ECC_HW
) {
2238 if (host
->has_pmecc
)
2239 res
= atmel_pmecc_nand_init_params(pdev
, host
);
2241 res
= atmel_hw_nand_init_params(pdev
, host
);
2247 /* initialize the nfc configuration register */
2248 if (host
->nfc
&& host
->nfc
->use_nfc_sram
) {
2249 res
= nfc_sram_init(mtd
);
2251 host
->nfc
->use_nfc_sram
= false;
2252 dev_err(host
->dev
, "Disable use nfc sram for data transfer.\n");
2256 /* second phase scan */
2257 if (nand_scan_tail(mtd
)) {
2262 mtd
->name
= "atmel_nand";
2263 res
= mtd_device_register(mtd
, host
->board
.parts
,
2264 host
->board
.num_parts
);
2269 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
)
2270 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
2274 atmel_nand_disable(host
);
2276 dma_release_channel(host
->dma_chan
);
2282 * Remove a NAND device.
2284 static int atmel_nand_remove(struct platform_device
*pdev
)
2286 struct atmel_nand_host
*host
= platform_get_drvdata(pdev
);
2287 struct mtd_info
*mtd
= nand_to_mtd(&host
->nand_chip
);
2291 atmel_nand_disable(host
);
2293 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
) {
2294 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
2295 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
,
2300 dma_release_channel(host
->dma_chan
);
2302 platform_driver_unregister(&atmel_nand_nfc_driver
);
2307 static const struct atmel_nand_caps at91rm9200_caps
= {
2308 .pmecc_correct_erase_page
= false,
2311 static const struct atmel_nand_caps sama5d4_caps
= {
2312 .pmecc_correct_erase_page
= true,
2315 static const struct of_device_id atmel_nand_dt_ids
[] = {
2316 { .compatible
= "atmel,at91rm9200-nand", .data
= &at91rm9200_caps
},
2317 { .compatible
= "atmel,sama5d4-nand", .data
= &sama5d4_caps
},
2321 MODULE_DEVICE_TABLE(of
, atmel_nand_dt_ids
);
2323 static int atmel_nand_nfc_probe(struct platform_device
*pdev
)
2325 struct atmel_nfc
*nfc
= &nand_nfc
;
2326 struct resource
*nfc_cmd_regs
, *nfc_hsmc_regs
, *nfc_sram
;
2329 nfc_cmd_regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2330 nfc
->base_cmd_regs
= devm_ioremap_resource(&pdev
->dev
, nfc_cmd_regs
);
2331 if (IS_ERR(nfc
->base_cmd_regs
))
2332 return PTR_ERR(nfc
->base_cmd_regs
);
2334 nfc_hsmc_regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2335 nfc
->hsmc_regs
= devm_ioremap_resource(&pdev
->dev
, nfc_hsmc_regs
);
2336 if (IS_ERR(nfc
->hsmc_regs
))
2337 return PTR_ERR(nfc
->hsmc_regs
);
2339 nfc_sram
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
2341 nfc
->sram_bank0
= (void * __force
)
2342 devm_ioremap_resource(&pdev
->dev
, nfc_sram
);
2343 if (IS_ERR(nfc
->sram_bank0
)) {
2344 dev_warn(&pdev
->dev
, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2345 PTR_ERR(nfc
->sram_bank0
));
2347 nfc
->use_nfc_sram
= true;
2348 nfc
->sram_bank0_phys
= (dma_addr_t
)nfc_sram
->start
;
2350 if (pdev
->dev
.of_node
)
2351 nfc
->write_by_sram
= of_property_read_bool(
2353 "atmel,write-by-sram");
2357 nfc_writel(nfc
->hsmc_regs
, IDR
, 0xffffffff);
2358 nfc_readl(nfc
->hsmc_regs
, SR
); /* clear the NFC_SR */
2360 nfc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
2361 if (!IS_ERR(nfc
->clk
)) {
2362 ret
= clk_prepare_enable(nfc
->clk
);
2366 dev_warn(&pdev
->dev
, "NFC clock missing, update your Device Tree");
2369 nfc
->is_initialized
= true;
2370 dev_info(&pdev
->dev
, "NFC is probed.\n");
2375 static int atmel_nand_nfc_remove(struct platform_device
*pdev
)
2377 struct atmel_nfc
*nfc
= &nand_nfc
;
2379 if (!IS_ERR(nfc
->clk
))
2380 clk_disable_unprepare(nfc
->clk
);
2385 static const struct of_device_id atmel_nand_nfc_match
[] = {
2386 { .compatible
= "atmel,sama5d3-nfc" },
2389 MODULE_DEVICE_TABLE(of
, atmel_nand_nfc_match
);
2391 static struct platform_driver atmel_nand_nfc_driver
= {
2393 .name
= "atmel_nand_nfc",
2394 .of_match_table
= of_match_ptr(atmel_nand_nfc_match
),
2396 .probe
= atmel_nand_nfc_probe
,
2397 .remove
= atmel_nand_nfc_remove
,
2400 static struct platform_driver atmel_nand_driver
= {
2401 .probe
= atmel_nand_probe
,
2402 .remove
= atmel_nand_remove
,
2404 .name
= "atmel_nand",
2405 .of_match_table
= of_match_ptr(atmel_nand_dt_ids
),
2409 module_platform_driver(atmel_nand_driver
);
2411 MODULE_LICENSE("GPL");
2412 MODULE_AUTHOR("Rick Bronson");
2413 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2414 MODULE_ALIAS("platform:atmel_nand");