drivers/mtd/nand/au1550nd.c

   1 /*
   2  *  drivers/mtd/nand/au1550nd.c
   3  *
   4  *  Copyright (C) 2004 Embedded Edge, LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/slab.h>
  13 #include <linux/gpio.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/platform_device.h>
  21 #include <asm/io.h>
  22 #include <asm/mach-au1x00/au1000.h>
  23 #include <asm/mach-au1x00/au1550nd.h>
  24
  25
  26 struct au1550nd_ctx {
  27         struct mtd_info info;
  28         struct nand_chip chip;
  29
  30         int cs;
  31         void __iomem *base;
  32         void (*write_byte)(struct mtd_info *, u_char);
  33 };
  34
  35 /**
  36  * au_read_byte -  read one byte from the chip
  37  * @mtd:        MTD device structure
  38  *
  39  * read function for 8bit buswidth
  40  */
  41 static u_char au_read_byte(struct mtd_info *mtd)
  42 {
  43         struct nand_chip *this = mtd->priv;
  44         u_char ret = readb(this->IO_ADDR_R);
  45         au_sync();
  46         return ret;
  47 }
  48
  49 /**
  50  * au_write_byte -  write one byte to the chip
  51  * @mtd:        MTD device structure
  52  * @byte:       pointer to data byte to write
  53  *
  54  * write function for 8it buswidth
  55  */
  56 static void au_write_byte(struct mtd_info *mtd, u_char byte)
  57 {
  58         struct nand_chip *this = mtd->priv;
  59         writeb(byte, this->IO_ADDR_W);
  60         au_sync();
  61 }
  62
  63 /**
  64  * au_read_byte16 -  read one byte endianness aware from the chip
  65  * @mtd:        MTD device structure
  66  *
  67  * read function for 16bit buswidth with endianness conversion
  68  */
  69 static u_char au_read_byte16(struct mtd_info *mtd)
  70 {
  71         struct nand_chip *this = mtd->priv;
  72         u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
  73         au_sync();
  74         return ret;
  75 }
  76
  77 /**
  78  * au_write_byte16 -  write one byte endianness aware to the chip
  79  * @mtd:        MTD device structure
  80  * @byte:       pointer to data byte to write
  81  *
  82  * write function for 16bit buswidth with endianness conversion
  83  */
  84 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
  85 {
  86         struct nand_chip *this = mtd->priv;
  87         writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
  88         au_sync();
  89 }
  90
  91 /**
  92  * au_read_word -  read one word from the chip
  93  * @mtd:        MTD device structure
  94  *
  95  * read function for 16bit buswidth without endianness conversion
  96  */
  97 static u16 au_read_word(struct mtd_info *mtd)
  98 {
  99         struct nand_chip *this = mtd->priv;
 100         u16 ret = readw(this->IO_ADDR_R);
 101         au_sync();
 102         return ret;
 103 }
 104
 105 /**
 106  * au_write_buf -  write buffer to chip
 107  * @mtd:        MTD device structure
 108  * @buf:        data buffer
 109  * @len:        number of bytes to write
 110  *
 111  * write function for 8bit buswidth
 112  */
 113 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 114 {
 115         int i;
 116         struct nand_chip *this = mtd->priv;
 117
 118         for (i = 0; i < len; i++) {
 119                 writeb(buf[i], this->IO_ADDR_W);
 120                 au_sync();
 121         }
 122 }
 123
 124 /**
 125  * au_read_buf -  read chip data into buffer
 126  * @mtd:        MTD device structure
 127  * @buf:        buffer to store date
 128  * @len:        number of bytes to read
 129  *
 130  * read function for 8bit buswidth
 131  */
 132 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 133 {
 134         int i;
 135         struct nand_chip *this = mtd->priv;
 136
 137         for (i = 0; i < len; i++) {
 138                 buf[i] = readb(this->IO_ADDR_R);
 139                 au_sync();
 140         }
 141 }
 142
 143 /**
 144  * au_write_buf16 -  write buffer to chip
 145  * @mtd:        MTD device structure
 146  * @buf:        data buffer
 147  * @len:        number of bytes to write
 148  *
 149  * write function for 16bit buswidth
 150  */
 151 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
 152 {
 153         int i;
 154         struct nand_chip *this = mtd->priv;
 155         u16 *p = (u16 *) buf;
 156         len >>= 1;
 157
 158         for (i = 0; i < len; i++) {
 159                 writew(p[i], this->IO_ADDR_W);
 160                 au_sync();
 161         }
 162
 163 }
 164
 165 /**
 166  * au_read_buf16 -  read chip data into buffer
 167  * @mtd:        MTD device structure
 168  * @buf:        buffer to store date
 169  * @len:        number of bytes to read
 170  *
 171  * read function for 16bit buswidth
 172  */
 173 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 174 {
 175         int i;
 176         struct nand_chip *this = mtd->priv;
 177         u16 *p = (u16 *) buf;
 178         len >>= 1;
 179
 180         for (i = 0; i < len; i++) {
 181                 p[i] = readw(this->IO_ADDR_R);
 182                 au_sync();
 183         }
 184 }
 185
 186 /* Select the chip by setting nCE to low */
 187 #define NAND_CTL_SETNCE         1
 188 /* Deselect the chip by setting nCE to high */
 189 #define NAND_CTL_CLRNCE         2
 190 /* Select the command latch by setting CLE to high */
 191 #define NAND_CTL_SETCLE         3
 192 /* Deselect the command latch by setting CLE to low */
 193 #define NAND_CTL_CLRCLE         4
 194 /* Select the address latch by setting ALE to high */
 195 #define NAND_CTL_SETALE         5
 196 /* Deselect the address latch by setting ALE to low */
 197 #define NAND_CTL_CLRALE         6
 198
 199 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
 200 {
 201         struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
 202         struct nand_chip *this = mtd->priv;
 203
 204         switch (cmd) {
 205
 206         case NAND_CTL_SETCLE:
 207                 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
 208                 break;
 209
 210         case NAND_CTL_CLRCLE:
 211                 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
 212                 break;
 213
 214         case NAND_CTL_SETALE:
 215                 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
 216                 break;
 217
 218         case NAND_CTL_CLRALE:
 219                 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
 220                 /* FIXME: Nobody knows why this is necessary,
 221                  * but it works only that way */
 222                 udelay(1);
 223                 break;
 224
 225         case NAND_CTL_SETNCE:
 226                 /* assert (force assert) chip enable */
 227                 au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
 228                 break;
 229
 230         case NAND_CTL_CLRNCE:
 231                 /* deassert chip enable */
 232                 au_writel(0, MEM_STNDCTL);
 233                 break;
 234         }
 235
 236         this->IO_ADDR_R = this->IO_ADDR_W;
 237
 238         /* Drain the writebuffer */
 239         au_sync();
 240 }
 241
 242 int au1550_device_ready(struct mtd_info *mtd)
 243 {
 244         int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
 245         au_sync();
 246         return ret;
 247 }
 248
 249 /**
 250  * au1550_select_chip - control -CE line
 251  *      Forbid driving -CE manually permitting the NAND controller to do this.
 252  *      Keeping -CE asserted during the whole sector reads interferes with the
 253  *      NOR flash and PCMCIA drivers as it causes contention on the static bus.
 254  *      We only have to hold -CE low for the NAND read commands since the flash
 255  *      chip needs it to be asserted during chip not ready time but the NAND
 256  *      controller keeps it released.
 257  *
 258  * @mtd:        MTD device structure
 259  * @chip:       chipnumber to select, -1 for deselect
 260  */
 261 static void au1550_select_chip(struct mtd_info *mtd, int chip)
 262 {
 263 }
 264
 265 /**
 266  * au1550_command - Send command to NAND device
 267  * @mtd:        MTD device structure
 268  * @command:    the command to be sent
 269  * @column:     the column address for this command, -1 if none
 270  * @page_addr:  the page address for this command, -1 if none
 271  */
 272 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
 273 {
 274         struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
 275         struct nand_chip *this = mtd->priv;
 276         int ce_override = 0, i;
 277         unsigned long flags = 0;
 278
 279         /* Begin command latch cycle */
 280         au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
 281         /*
 282          * Write out the command to the device.
 283          */
 284         if (command == NAND_CMD_SEQIN) {
 285                 int readcmd;
 286
 287                 if (column >= mtd->writesize) {
 288                         /* OOB area */
 289                         column -= mtd->writesize;
 290                         readcmd = NAND_CMD_READOOB;
 291                 } else if (column < 256) {
 292                         /* First 256 bytes --> READ0 */
 293                         readcmd = NAND_CMD_READ0;
 294                 } else {
 295                         column -= 256;
 296                         readcmd = NAND_CMD_READ1;
 297                 }
 298                 ctx->write_byte(mtd, readcmd);
 299         }
 300         ctx->write_byte(mtd, command);
 301
 302         /* Set ALE and clear CLE to start address cycle */
 303         au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
 304
 305         if (column != -1 || page_addr != -1) {
 306                 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
 307
 308                 /* Serially input address */
 309                 if (column != -1) {
 310                         /* Adjust columns for 16 bit buswidth */
 311                         if (this->options & NAND_BUSWIDTH_16)
 312                                 column >>= 1;
 313                         ctx->write_byte(mtd, column);
 314                 }
 315                 if (page_addr != -1) {
 316                         ctx->write_byte(mtd, (u8)(page_addr & 0xff));
 317
 318                         if (command == NAND_CMD_READ0 ||
 319                             command == NAND_CMD_READ1 ||
 320                             command == NAND_CMD_READOOB) {
 321                                 /*
 322                                  * NAND controller will release -CE after
 323                                  * the last address byte is written, so we'll
 324                                  * have to forcibly assert it. No interrupts
 325                                  * are allowed while we do this as we don't
 326                                  * want the NOR flash or PCMCIA drivers to
 327                                  * steal our precious bytes of data...
 328                                  */
 329                                 ce_override = 1;
 330                                 local_irq_save(flags);
 331                                 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
 332                         }
 333
 334                         ctx->write_byte(mtd, (u8)(page_addr >> 8));
 335
 336                         /* One more address cycle for devices > 32MiB */
 337                         if (this->chipsize > (32 << 20))
 338                                 ctx->write_byte(mtd,
 339                                                 ((page_addr >> 16) & 0x0f));
 340                 }
 341                 /* Latch in address */
 342                 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
 343         }
 344
 345         /*
 346          * Program and erase have their own busy handlers.
 347          * Status and sequential in need no delay.
 348          */
 349         switch (command) {
 350
 351         case NAND_CMD_PAGEPROG:
 352         case NAND_CMD_ERASE1:
 353         case NAND_CMD_ERASE2:
 354         case NAND_CMD_SEQIN:
 355         case NAND_CMD_STATUS:
 356                 return;
 357
 358         case NAND_CMD_RESET:
 359                 break;
 360
 361         case NAND_CMD_READ0:
 362         case NAND_CMD_READ1:
 363         case NAND_CMD_READOOB:
 364                 /* Check if we're really driving -CE low (just in case) */
 365                 if (unlikely(!ce_override))
 366                         break;
 367
 368                 /* Apply a short delay always to ensure that we do wait tWB. */
 369                 ndelay(100);
 370                 /* Wait for a chip to become ready... */
 371                 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
 372                         udelay(1);
 373
 374                 /* Release -CE and re-enable interrupts. */
 375                 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
 376                 local_irq_restore(flags);
 377                 return;
 378         }
 379         /* Apply this short delay always to ensure that we do wait tWB. */
 380         ndelay(100);
 381
 382         while(!this->dev_ready(mtd));
 383 }
 384
 385 static int find_nand_cs(unsigned long nand_base)
 386 {
 387         void __iomem *base =
 388                         (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
 389         unsigned long addr, staddr, start, mask, end;
 390         int i;
 391
 392         for (i = 0; i < 4; i++) {
 393                 addr = 0x1000 + (i * 0x10);                     /* CSx */
 394                 staddr = __raw_readl(base + addr + 0x08);       /* STADDRx */
 395                 /* figure out the decoded range of this CS */
 396                 start = (staddr << 4) & 0xfffc0000;
 397                 mask = (staddr << 18) & 0xfffc0000;
 398                 end = (start | (start - 1)) & ~(start ^ mask);
 399                 if ((nand_base >= start) && (nand_base < end))
 400                         return i;
 401         }
 402
 403         return -ENODEV;
 404 }
 405
 406 static int au1550nd_probe(struct platform_device *pdev)
 407 {
 408         struct au1550nd_platdata *pd;
 409         struct au1550nd_ctx *ctx;
 410         struct nand_chip *this;
 411         struct resource *r;
 412         int ret, cs;
 413
 414         pd = pdev->dev.platform_data;
 415         if (!pd) {
 416                 dev_err(&pdev->dev, "missing platform data\n");
 417                 return -ENODEV;
 418         }
 419
 420         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 421         if (!ctx) {
 422                 dev_err(&pdev->dev, "no memory for NAND context\n");
 423                 return -ENOMEM;
 424         }
 425
 426         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 427         if (!r) {
 428                 dev_err(&pdev->dev, "no NAND memory resource\n");
 429                 ret = -ENODEV;
 430                 goto out1;
 431         }
 432         if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
 433                 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
 434                 ret = -ENOMEM;
 435                 goto out1;
 436         }
 437
 438         ctx->base = ioremap_nocache(r->start, 0x1000);
 439         if (!ctx->base) {
 440                 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
 441                 ret = -ENODEV;
 442                 goto out2;
 443         }
 444
 445         this = &ctx->chip;
 446         ctx->info.priv = this;
 447         ctx->info.owner = THIS_MODULE;
 448
 449         /* figure out which CS# r->start belongs to */
 450         cs = find_nand_cs(r->start);
 451         if (cs < 0) {
 452                 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
 453                 ret = -ENODEV;
 454                 goto out3;
 455         }
 456         ctx->cs = cs;
 457
 458         this->dev_ready = au1550_device_ready;
 459         this->select_chip = au1550_select_chip;
 460         this->cmdfunc = au1550_command;
 461
 462         /* 30 us command delay time */
 463         this->chip_delay = 30;
 464         this->ecc.mode = NAND_ECC_SOFT;
 465
 466         if (pd->devwidth)
 467                 this->options |= NAND_BUSWIDTH_16;
 468
 469         this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
 470         ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
 471         this->read_word = au_read_word;
 472         this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
 473         this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
 474
 475         ret = nand_scan(&ctx->info, 1);
 476         if (ret) {
 477                 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
 478                 goto out3;
 479         }
 480
 481         mtd_device_register(&ctx->info, pd->parts, pd->num_parts);
 482
 483         return 0;
 484
 485 out3:
 486         iounmap(ctx->base);
 487 out2:
 488         release_mem_region(r->start, resource_size(r));
 489 out1:
 490         kfree(ctx);
 491         return ret;
 492 }
 493
 494 static int au1550nd_remove(struct platform_device *pdev)
 495 {
 496         struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
 497         struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 498
 499         nand_release(&ctx->info);
 500         iounmap(ctx->base);
 501         release_mem_region(r->start, 0x1000);
 502         kfree(ctx);
 503         return 0;
 504 }
 505
 506 static struct platform_driver au1550nd_driver = {
 507         .driver = {
 508                 .name   = "au1550-nand",
 509                 .owner  = THIS_MODULE,
 510         },
 511         .probe          = au1550nd_probe,
 512         .remove         = au1550nd_remove,
 513 };
 514
 515 module_platform_driver(au1550nd_driver);
 516
 517 MODULE_LICENSE("GPL");
 518 MODULE_AUTHOR("Embedded Edge, LLC");
 519 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");