2 * drivers/mtd/nand/cs553x_nand.c
4 * (C) 2005, 2006 Red Hat Inc.
6 * Author: David Woodhouse <dwmw2@infradead.org>
7 * Tom Sylla <tom.sylla@amd.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * This is a device driver for the NAND flash controller found on
15 * the AMD CS5535/CS5536 companion chipsets for the Geode processor.
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/pci.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/nand_ecc.h>
27 #include <linux/mtd/partitions.h>
32 #define NR_CS553X_CONTROLLERS 4
34 /* NAND Timing MSRs */
35 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
37 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
40 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
41 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
42 #define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */
43 #define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */
44 /* Each made up of... */
45 #define FLSH_LBAR_EN (1ULL<<32)
46 #define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
47 #define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */
48 /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
49 /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
51 /* Pin function selection MSR (IDE vs. flash on the IDE pins) */
52 #define MSR_DIVIL_BALL_OPTS 0x51400015
53 #define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */
55 /* Registers within the NAND flash controller BAR -- memory mapped */
56 #define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */
57 #define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
58 #define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */
59 #define MM_NAND_STS 0x810
60 #define MM_NAND_ECC_LSB 0x811
61 #define MM_NAND_ECC_MSB 0x812
62 #define MM_NAND_ECC_COL 0x813
63 #define MM_NAND_LAC 0x814
64 #define MM_NAND_ECC_CTL 0x815
66 /* Registers within the NAND flash controller BAR -- I/O mapped */
67 #define IO_NAND_DATA 0x00 /* 0 to 3, in fact */
68 #define IO_NAND_CTL 0x04
69 #define IO_NAND_IO 0x05
70 #define IO_NAND_STS 0x06
71 #define IO_NAND_ECC_CTL 0x08
72 #define IO_NAND_ECC_LSB 0x09
73 #define IO_NAND_ECC_MSB 0x0a
74 #define IO_NAND_ECC_COL 0x0b
75 #define IO_NAND_LAC 0x0c
77 #define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */
78 #define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */
79 #define CS_NAND_CTL_ALE (1<<2)
80 #define CS_NAND_CTL_CLE (1<<1)
81 #define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */
83 #define CS_NAND_STS_FLASH_RDY (1<<3)
84 #define CS_NAND_CTLR_BUSY (1<<2)
85 #define CS_NAND_CMD_COMP (1<<1)
86 #define CS_NAND_DIST_ST (1<<0)
88 #define CS_NAND_ECC_PARITY (1<<2)
89 #define CS_NAND_ECC_CLRECC (1<<1)
90 #define CS_NAND_ECC_ENECC (1<<0)
92 static void cs553x_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
94 struct nand_chip
*this = mtd
->priv
;
96 while (unlikely(len
> 0x800)) {
97 memcpy_fromio(buf
, this->IO_ADDR_R
, 0x800);
101 memcpy_fromio(buf
, this->IO_ADDR_R
, len
);
104 static void cs553x_write_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
106 struct nand_chip
*this = mtd
->priv
;
108 while (unlikely(len
> 0x800)) {
109 memcpy_toio(this->IO_ADDR_R
, buf
, 0x800);
113 memcpy_toio(this->IO_ADDR_R
, buf
, len
);
116 static unsigned char cs553x_read_byte(struct mtd_info
*mtd
)
118 struct nand_chip
*this = mtd
->priv
;
119 return readb(this->IO_ADDR_R
);
122 static void cs553x_write_byte(struct mtd_info
*mtd
, u_char byte
)
124 struct nand_chip
*this = mtd
->priv
;
127 while (i
&& readb(this->IO_ADDR_R
+ MM_NAND_STS
) & CS_NAND_CTLR_BUSY
) {
131 writeb(byte
, this->IO_ADDR_W
+ 0x801);
134 static void cs553x_hwcontrol(struct mtd_info
*mtd
, int cmd
)
136 struct nand_chip
*this = mtd
->priv
;
137 void __iomem
*mmio_base
= this->IO_ADDR_R
;
141 case NAND_CTL_SETCLE
:
142 ctl
= CS_NAND_CTL_CLE
;
145 case NAND_CTL_CLRCLE
:
146 case NAND_CTL_CLRALE
:
147 case NAND_CTL_SETNCE
:
151 case NAND_CTL_SETALE
:
152 ctl
= CS_NAND_CTL_ALE
;
156 case NAND_CTL_CLRNCE
:
157 ctl
= CS_NAND_CTL_CE
;
160 writeb(ctl
, mmio_base
+ MM_NAND_CTL
);
163 static int cs553x_device_ready(struct mtd_info
*mtd
)
165 struct nand_chip
*this = mtd
->priv
;
166 void __iomem
*mmio_base
= this->IO_ADDR_R
;
167 unsigned char foo
= readb(mmio_base
+ MM_NAND_STS
);
169 return (foo
& CS_NAND_STS_FLASH_RDY
) && !(foo
& CS_NAND_CTLR_BUSY
);
172 static void cs_enable_hwecc(struct mtd_info
*mtd
, int mode
)
174 struct nand_chip
*this = mtd
->priv
;
175 void __iomem
*mmio_base
= this->IO_ADDR_R
;
177 writeb(0x07, mmio_base
+ MM_NAND_ECC_CTL
);
180 static int cs_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
, u_char
*ecc_code
)
183 struct nand_chip
*this = mtd
->priv
;
184 void __iomem
*mmio_base
= this->IO_ADDR_R
;
186 ecc
= readl(mmio_base
+ MM_NAND_STS
);
188 ecc_code
[1] = ecc
>> 8;
189 ecc_code
[0] = ecc
>> 16;
190 ecc_code
[2] = ecc
>> 24;
194 static struct mtd_info
*cs553x_mtd
[4];
196 static int __init
cs553x_init_one(int cs
, int mmio
, unsigned long adr
)
199 struct nand_chip
*this;
200 struct mtd_info
*new_mtd
;
202 printk(KERN_NOTICE
"Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs
, mmio
?"MM":"P", adr
);
205 printk(KERN_NOTICE
"PIO mode not yet implemented for CS553X NAND controller\n");
209 /* Allocate memory for MTD device structure and private data */
210 new_mtd
= kmalloc(sizeof(struct mtd_info
) + sizeof(struct nand_chip
), GFP_KERNEL
);
212 printk(KERN_WARNING
"Unable to allocate CS553X NAND MTD device structure.\n");
217 /* Get pointer to private data */
218 this = (struct nand_chip
*)(&new_mtd
[1]);
220 /* Initialize structures */
221 memset(new_mtd
, 0, sizeof(struct mtd_info
));
222 memset(this, 0, sizeof(struct nand_chip
));
224 /* Link the private data with the MTD structure */
225 new_mtd
->priv
= this;
226 new_mtd
->owner
= THIS_MODULE
;
228 /* map physical address */
229 this->IO_ADDR_R
= this->IO_ADDR_W
= ioremap(adr
, 4096);
230 if (!this->IO_ADDR_R
) {
231 printk(KERN_WARNING
"ioremap cs553x NAND @0x%08lx failed\n", adr
);
236 this->hwcontrol
= cs553x_hwcontrol
;
237 this->dev_ready
= cs553x_device_ready
;
238 this->read_byte
= cs553x_read_byte
;
239 this->write_byte
= cs553x_write_byte
;
240 this->read_buf
= cs553x_read_buf
;
241 this->write_buf
= cs553x_write_buf
;
243 this->chip_delay
= 0;
245 this->ecc
.mode
= NAND_ECC_HW
;
246 this->ecc
.size
= 256;
248 this->ecc
.hwctl
= cs_enable_hwecc
;
249 this->ecc
.calculate
= cs_calculate_ecc
;
250 this->ecc
.correct
= nand_correct_data
;
252 /* Enable the following for a flash based bad block table */
253 this->options
= NAND_USE_FLASH_BBT
| NAND_NO_AUTOINCR
;
255 /* Scan to find existance of the device */
256 if (nand_scan(new_mtd
, 1)) {
261 cs553x_mtd
[cs
] = new_mtd
;
265 iounmap((void *)this->IO_ADDR_R
);
272 static int __init
cs553x_init(void)
278 /* Check whether we actually have a CS5535 or CS5536 */
279 if (!pci_find_device(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, NULL
) &&
280 !pci_find_device(PCI_VENDOR_ID_NS
, PCI_DEVICE_ID_NS_CS5535_ISA
, NULL
))
283 rdmsrl(MSR_DIVIL_BALL_OPTS
, val
);
285 printk(KERN_INFO
"CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
289 for (i
= 0; i
< NR_CS553X_CONTROLLERS
; i
++) {
290 rdmsrl(MSR_DIVIL_LBAR_FLSH0
+ i
, val
);
292 if ((val
& (FLSH_LBAR_EN
|FLSH_NOR_NAND
)) == (FLSH_LBAR_EN
|FLSH_NOR_NAND
))
293 err
= cs553x_init_one(i
, !!(val
& FLSH_MEM_IO
), val
& 0xFFFFFFFF);
296 /* Register all devices together here. This means we can easily hack it to
297 do mtdconcat etc. if we want to. */
298 for (i
= 0; i
< NR_CS553X_CONTROLLERS
; i
++) {
300 add_mtd_device(cs553x_mtd
[i
]);
302 /* If any devices registered, return success. Else the last error. */
310 module_init(cs553x_init
);
312 static void __exit
cs553x_cleanup(void)
316 for (i
= 0; i
< NR_CS553X_CONTROLLERS
; i
++) {
317 struct mtd_info
*mtd
= cs553x_mtd
[i
];
318 struct nand_chip
*this;
319 void __iomem
*mmio_base
;
324 this = cs553x_mtd
[i
]->priv
;
325 mmio_base
= this->IO_ADDR_R
;
327 /* Release resources, unregister device */
328 nand_release(cs553x_mtd
[i
]);
329 cs553x_mtd
[i
] = NULL
;
331 /* unmap physical adress */
334 /* Free the MTD device structure */
339 module_exit(cs553x_cleanup
);
341 MODULE_LICENSE("GPL");
342 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
343 MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");