2 * Hisilicon NAND Flash controller driver
4 * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
5 * http://www.hisilicon.com
7 * Author: Zhou Wang <wangzhou.bry@gmail.com>
8 * The initial developer of the original code is Zhiyong Cai
9 * <caizhiyong@huawei.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/of_mtd.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/sizes.h>
25 #include <linux/clk.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/platform_device.h>
33 #include <linux/mtd/partitions.h>
35 #define HINFC504_MAX_CHIP (4)
36 #define HINFC504_W_LATCH (5)
37 #define HINFC504_R_LATCH (7)
38 #define HINFC504_RW_LATCH (3)
40 #define HINFC504_NFC_TIMEOUT (2 * HZ)
41 #define HINFC504_NFC_PM_TIMEOUT (1 * HZ)
42 #define HINFC504_NFC_DMA_TIMEOUT (5 * HZ)
43 #define HINFC504_CHIP_DELAY (25)
45 #define HINFC504_REG_BASE_ADDRESS_LEN (0x100)
46 #define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128)
48 #define HINFC504_ADDR_CYCLE_MASK 0x4
50 #define HINFC504_CON 0x00
51 #define HINFC504_CON_OP_MODE_NORMAL BIT(0)
52 #define HINFC504_CON_PAGEISZE_SHIFT (1)
53 #define HINFC504_CON_PAGESIZE_MASK (0x07)
54 #define HINFC504_CON_BUS_WIDTH BIT(4)
55 #define HINFC504_CON_READY_BUSY_SEL BIT(8)
56 #define HINFC504_CON_ECCTYPE_SHIFT (9)
57 #define HINFC504_CON_ECCTYPE_MASK (0x07)
59 #define HINFC504_PWIDTH 0x04
60 #define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
61 ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
63 #define HINFC504_CMD 0x0C
64 #define HINFC504_ADDRL 0x10
65 #define HINFC504_ADDRH 0x14
66 #define HINFC504_DATA_NUM 0x18
68 #define HINFC504_OP 0x1C
69 #define HINFC504_OP_READ_DATA_EN BIT(1)
70 #define HINFC504_OP_WAIT_READY_EN BIT(2)
71 #define HINFC504_OP_CMD2_EN BIT(3)
72 #define HINFC504_OP_WRITE_DATA_EN BIT(4)
73 #define HINFC504_OP_ADDR_EN BIT(5)
74 #define HINFC504_OP_CMD1_EN BIT(6)
75 #define HINFC504_OP_NF_CS_SHIFT (7)
76 #define HINFC504_OP_NF_CS_MASK (3)
77 #define HINFC504_OP_ADDR_CYCLE_SHIFT (9)
78 #define HINFC504_OP_ADDR_CYCLE_MASK (7)
80 #define HINFC504_STATUS 0x20
81 #define HINFC504_READY BIT(0)
83 #define HINFC504_INTEN 0x24
84 #define HINFC504_INTEN_DMA BIT(9)
85 #define HINFC504_INTEN_UE BIT(6)
86 #define HINFC504_INTEN_CE BIT(5)
88 #define HINFC504_INTS 0x28
89 #define HINFC504_INTS_DMA BIT(9)
90 #define HINFC504_INTS_UE BIT(6)
91 #define HINFC504_INTS_CE BIT(5)
93 #define HINFC504_INTCLR 0x2C
94 #define HINFC504_INTCLR_DMA BIT(9)
95 #define HINFC504_INTCLR_UE BIT(6)
96 #define HINFC504_INTCLR_CE BIT(5)
98 #define HINFC504_ECC_STATUS 0x5C
99 #define HINFC504_ECC_16_BIT_SHIFT 12
101 #define HINFC504_DMA_CTRL 0x60
102 #define HINFC504_DMA_CTRL_DMA_START BIT(0)
103 #define HINFC504_DMA_CTRL_WE BIT(1)
104 #define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2)
105 #define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3)
106 #define HINFC504_DMA_CTRL_BURST4_EN BIT(4)
107 #define HINFC504_DMA_CTRL_BURST8_EN BIT(5)
108 #define HINFC504_DMA_CTRL_BURST16_EN BIT(6)
109 #define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7)
110 #define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1)
111 #define HINFC504_DMA_CTRL_CS_SHIFT (8)
112 #define HINFC504_DMA_CTRL_CS_MASK (0x03)
114 #define HINFC504_DMA_ADDR_DATA 0x64
115 #define HINFC504_DMA_ADDR_OOB 0x68
117 #define HINFC504_DMA_LEN 0x6C
118 #define HINFC504_DMA_LEN_OOB_SHIFT (16)
119 #define HINFC504_DMA_LEN_OOB_MASK (0xFFF)
121 #define HINFC504_DMA_PARA 0x70
122 #define HINFC504_DMA_PARA_DATA_RW_EN BIT(0)
123 #define HINFC504_DMA_PARA_OOB_RW_EN BIT(1)
124 #define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2)
125 #define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3)
126 #define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4)
127 #define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5)
129 #define HINFC_VERSION 0x74
130 #define HINFC504_LOG_READ_ADDR 0x7C
131 #define HINFC504_LOG_READ_LEN 0x80
133 #define HINFC504_NANDINFO_LEN 0x10
136 struct nand_chip chip
;
138 void __iomem
*iobase
;
140 struct completion cmd_complete
;
142 unsigned int command
;
144 unsigned int addr_cycle
;
146 u32 cache_addr_value
[2];
148 dma_addr_t dma_buffer
;
151 unsigned int irq_status
; /* interrupt status */
154 static inline unsigned int hinfc_read(struct hinfc_host
*host
, unsigned int reg
)
156 return readl(host
->iobase
+ reg
);
159 static inline void hinfc_write(struct hinfc_host
*host
, unsigned int value
,
162 writel(value
, host
->iobase
+ reg
);
165 static void wait_controller_finished(struct hinfc_host
*host
)
167 unsigned long timeout
= jiffies
+ HINFC504_NFC_TIMEOUT
;
170 while (time_before(jiffies
, timeout
)) {
171 val
= hinfc_read(host
, HINFC504_STATUS
);
172 if (host
->command
== NAND_CMD_ERASE2
) {
174 while (!(val
& HINFC504_READY
)) {
175 usleep_range(500, 1000);
176 val
= hinfc_read(host
, HINFC504_STATUS
);
181 if (val
& HINFC504_READY
)
185 /* wait cmd timeout */
186 dev_err(host
->dev
, "Wait NAND controller exec cmd timeout.\n");
189 static void hisi_nfc_dma_transfer(struct hinfc_host
*host
, int todev
)
191 struct nand_chip
*chip
= &host
->chip
;
192 struct mtd_info
*mtd
= nand_to_mtd(chip
);
196 hinfc_write(host
, host
->dma_buffer
, HINFC504_DMA_ADDR_DATA
);
197 hinfc_write(host
, host
->dma_oob
, HINFC504_DMA_ADDR_OOB
);
199 if (chip
->ecc
.mode
== NAND_ECC_NONE
) {
200 hinfc_write(host
, ((mtd
->oobsize
& HINFC504_DMA_LEN_OOB_MASK
)
201 << HINFC504_DMA_LEN_OOB_SHIFT
), HINFC504_DMA_LEN
);
203 hinfc_write(host
, HINFC504_DMA_PARA_DATA_RW_EN
204 | HINFC504_DMA_PARA_OOB_RW_EN
, HINFC504_DMA_PARA
);
206 if (host
->command
== NAND_CMD_READOOB
)
207 hinfc_write(host
, HINFC504_DMA_PARA_OOB_RW_EN
208 | HINFC504_DMA_PARA_OOB_EDC_EN
209 | HINFC504_DMA_PARA_OOB_ECC_EN
, HINFC504_DMA_PARA
);
211 hinfc_write(host
, HINFC504_DMA_PARA_DATA_RW_EN
212 | HINFC504_DMA_PARA_OOB_RW_EN
213 | HINFC504_DMA_PARA_DATA_EDC_EN
214 | HINFC504_DMA_PARA_OOB_EDC_EN
215 | HINFC504_DMA_PARA_DATA_ECC_EN
216 | HINFC504_DMA_PARA_OOB_ECC_EN
, HINFC504_DMA_PARA
);
220 val
= (HINFC504_DMA_CTRL_DMA_START
| HINFC504_DMA_CTRL_BURST4_EN
221 | HINFC504_DMA_CTRL_BURST8_EN
| HINFC504_DMA_CTRL_BURST16_EN
222 | HINFC504_DMA_CTRL_DATA_AREA_EN
| HINFC504_DMA_CTRL_OOB_AREA_EN
223 | ((host
->addr_cycle
== 4 ? 1 : 0)
224 << HINFC504_DMA_CTRL_ADDR_NUM_SHIFT
)
225 | ((host
->chipselect
& HINFC504_DMA_CTRL_CS_MASK
)
226 << HINFC504_DMA_CTRL_CS_SHIFT
));
229 val
|= HINFC504_DMA_CTRL_WE
;
231 init_completion(&host
->cmd_complete
);
233 hinfc_write(host
, val
, HINFC504_DMA_CTRL
);
234 ret
= wait_for_completion_timeout(&host
->cmd_complete
,
235 HINFC504_NFC_DMA_TIMEOUT
);
238 dev_err(host
->dev
, "DMA operation(irq) timeout!\n");
240 val
= hinfc_read(host
, HINFC504_DMA_CTRL
);
241 if (!(val
& HINFC504_DMA_CTRL_DMA_START
))
242 dev_err(host
->dev
, "DMA is already done but without irq ACK!\n");
244 dev_err(host
->dev
, "DMA is really timeout!\n");
248 static int hisi_nfc_send_cmd_pageprog(struct hinfc_host
*host
)
250 host
->addr_value
[0] &= 0xffff0000;
252 hinfc_write(host
, host
->addr_value
[0], HINFC504_ADDRL
);
253 hinfc_write(host
, host
->addr_value
[1], HINFC504_ADDRH
);
254 hinfc_write(host
, NAND_CMD_PAGEPROG
<< 8 | NAND_CMD_SEQIN
,
257 hisi_nfc_dma_transfer(host
, 1);
262 static int hisi_nfc_send_cmd_readstart(struct hinfc_host
*host
)
264 struct mtd_info
*mtd
= nand_to_mtd(&host
->chip
);
266 if ((host
->addr_value
[0] == host
->cache_addr_value
[0]) &&
267 (host
->addr_value
[1] == host
->cache_addr_value
[1]))
270 host
->addr_value
[0] &= 0xffff0000;
272 hinfc_write(host
, host
->addr_value
[0], HINFC504_ADDRL
);
273 hinfc_write(host
, host
->addr_value
[1], HINFC504_ADDRH
);
274 hinfc_write(host
, NAND_CMD_READSTART
<< 8 | NAND_CMD_READ0
,
277 hinfc_write(host
, 0, HINFC504_LOG_READ_ADDR
);
278 hinfc_write(host
, mtd
->writesize
+ mtd
->oobsize
,
279 HINFC504_LOG_READ_LEN
);
281 hisi_nfc_dma_transfer(host
, 0);
283 host
->cache_addr_value
[0] = host
->addr_value
[0];
284 host
->cache_addr_value
[1] = host
->addr_value
[1];
289 static int hisi_nfc_send_cmd_erase(struct hinfc_host
*host
)
291 hinfc_write(host
, host
->addr_value
[0], HINFC504_ADDRL
);
292 hinfc_write(host
, (NAND_CMD_ERASE2
<< 8) | NAND_CMD_ERASE1
,
295 hinfc_write(host
, HINFC504_OP_WAIT_READY_EN
296 | HINFC504_OP_CMD2_EN
297 | HINFC504_OP_CMD1_EN
298 | HINFC504_OP_ADDR_EN
299 | ((host
->chipselect
& HINFC504_OP_NF_CS_MASK
)
300 << HINFC504_OP_NF_CS_SHIFT
)
301 | ((host
->addr_cycle
& HINFC504_OP_ADDR_CYCLE_MASK
)
302 << HINFC504_OP_ADDR_CYCLE_SHIFT
),
305 wait_controller_finished(host
);
310 static int hisi_nfc_send_cmd_readid(struct hinfc_host
*host
)
312 hinfc_write(host
, HINFC504_NANDINFO_LEN
, HINFC504_DATA_NUM
);
313 hinfc_write(host
, NAND_CMD_READID
, HINFC504_CMD
);
314 hinfc_write(host
, 0, HINFC504_ADDRL
);
316 hinfc_write(host
, HINFC504_OP_CMD1_EN
| HINFC504_OP_ADDR_EN
317 | HINFC504_OP_READ_DATA_EN
318 | ((host
->chipselect
& HINFC504_OP_NF_CS_MASK
)
319 << HINFC504_OP_NF_CS_SHIFT
)
320 | 1 << HINFC504_OP_ADDR_CYCLE_SHIFT
, HINFC504_OP
);
322 wait_controller_finished(host
);
327 static int hisi_nfc_send_cmd_status(struct hinfc_host
*host
)
329 hinfc_write(host
, HINFC504_NANDINFO_LEN
, HINFC504_DATA_NUM
);
330 hinfc_write(host
, NAND_CMD_STATUS
, HINFC504_CMD
);
331 hinfc_write(host
, HINFC504_OP_CMD1_EN
332 | HINFC504_OP_READ_DATA_EN
333 | ((host
->chipselect
& HINFC504_OP_NF_CS_MASK
)
334 << HINFC504_OP_NF_CS_SHIFT
),
337 wait_controller_finished(host
);
342 static int hisi_nfc_send_cmd_reset(struct hinfc_host
*host
, int chipselect
)
344 hinfc_write(host
, NAND_CMD_RESET
, HINFC504_CMD
);
346 hinfc_write(host
, HINFC504_OP_CMD1_EN
347 | ((chipselect
& HINFC504_OP_NF_CS_MASK
)
348 << HINFC504_OP_NF_CS_SHIFT
)
349 | HINFC504_OP_WAIT_READY_EN
,
352 wait_controller_finished(host
);
357 static void hisi_nfc_select_chip(struct mtd_info
*mtd
, int chipselect
)
359 struct nand_chip
*chip
= mtd_to_nand(mtd
);
360 struct hinfc_host
*host
= nand_get_controller_data(chip
);
365 host
->chipselect
= chipselect
;
368 static uint8_t hisi_nfc_read_byte(struct mtd_info
*mtd
)
370 struct nand_chip
*chip
= mtd_to_nand(mtd
);
371 struct hinfc_host
*host
= nand_get_controller_data(chip
);
373 if (host
->command
== NAND_CMD_STATUS
)
374 return *(uint8_t *)(host
->mmio
);
378 if (host
->command
== NAND_CMD_READID
)
379 return *(uint8_t *)(host
->mmio
+ host
->offset
- 1);
381 return *(uint8_t *)(host
->buffer
+ host
->offset
- 1);
384 static u16
hisi_nfc_read_word(struct mtd_info
*mtd
)
386 struct nand_chip
*chip
= mtd_to_nand(mtd
);
387 struct hinfc_host
*host
= nand_get_controller_data(chip
);
390 return *(u16
*)(host
->buffer
+ host
->offset
- 2);
394 hisi_nfc_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
396 struct nand_chip
*chip
= mtd_to_nand(mtd
);
397 struct hinfc_host
*host
= nand_get_controller_data(chip
);
399 memcpy(host
->buffer
+ host
->offset
, buf
, len
);
403 static void hisi_nfc_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
405 struct nand_chip
*chip
= mtd_to_nand(mtd
);
406 struct hinfc_host
*host
= nand_get_controller_data(chip
);
408 memcpy(buf
, host
->buffer
+ host
->offset
, len
);
412 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
)
414 struct nand_chip
*chip
= mtd_to_nand(mtd
);
415 struct hinfc_host
*host
= nand_get_controller_data(chip
);
416 unsigned int command
= host
->command
;
418 host
->addr_cycle
= 0;
419 host
->addr_value
[0] = 0;
420 host
->addr_value
[1] = 0;
422 /* Serially input address */
424 /* Adjust columns for 16 bit buswidth */
425 if (chip
->options
& NAND_BUSWIDTH_16
&&
426 !nand_opcode_8bits(command
))
429 host
->addr_value
[0] = column
& 0xffff;
430 host
->addr_cycle
= 2;
432 if (page_addr
!= -1) {
433 host
->addr_value
[0] |= (page_addr
& 0xffff)
434 << (host
->addr_cycle
* 8);
435 host
->addr_cycle
+= 2;
436 /* One more address cycle for devices > 128MiB */
437 if (chip
->chipsize
> (128 << 20)) {
438 host
->addr_cycle
+= 1;
439 if (host
->command
== NAND_CMD_ERASE1
)
440 host
->addr_value
[0] |= ((page_addr
>> 16) & 0xff) << 16;
442 host
->addr_value
[1] |= ((page_addr
>> 16) & 0xff);
447 static void hisi_nfc_cmdfunc(struct mtd_info
*mtd
, unsigned command
, int column
,
450 struct nand_chip
*chip
= mtd_to_nand(mtd
);
451 struct hinfc_host
*host
= nand_get_controller_data(chip
);
452 int is_cache_invalid
= 1;
453 unsigned int flag
= 0;
455 host
->command
= command
;
459 case NAND_CMD_READOOB
:
460 if (command
== NAND_CMD_READ0
)
461 host
->offset
= column
;
463 host
->offset
= column
+ mtd
->writesize
;
465 is_cache_invalid
= 0;
466 set_addr(mtd
, column
, page_addr
);
467 hisi_nfc_send_cmd_readstart(host
);
471 host
->offset
= column
;
472 set_addr(mtd
, column
, page_addr
);
475 case NAND_CMD_ERASE1
:
476 set_addr(mtd
, column
, page_addr
);
479 case NAND_CMD_PAGEPROG
:
480 hisi_nfc_send_cmd_pageprog(host
);
483 case NAND_CMD_ERASE2
:
484 hisi_nfc_send_cmd_erase(host
);
487 case NAND_CMD_READID
:
488 host
->offset
= column
;
489 memset(host
->mmio
, 0, 0x10);
490 hisi_nfc_send_cmd_readid(host
);
493 case NAND_CMD_STATUS
:
494 flag
= hinfc_read(host
, HINFC504_CON
);
495 if (chip
->ecc
.mode
== NAND_ECC_HW
)
497 flag
& ~(HINFC504_CON_ECCTYPE_MASK
<<
498 HINFC504_CON_ECCTYPE_SHIFT
), HINFC504_CON
);
501 memset(host
->mmio
, 0, 0x10);
502 hisi_nfc_send_cmd_status(host
);
503 hinfc_write(host
, flag
, HINFC504_CON
);
507 hisi_nfc_send_cmd_reset(host
, host
->chipselect
);
511 dev_err(host
->dev
, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
512 command
, column
, page_addr
);
515 if (is_cache_invalid
) {
516 host
->cache_addr_value
[0] = ~0;
517 host
->cache_addr_value
[1] = ~0;
521 static irqreturn_t
hinfc_irq_handle(int irq
, void *devid
)
523 struct hinfc_host
*host
= devid
;
526 flag
= hinfc_read(host
, HINFC504_INTS
);
527 /* store interrupts state */
528 host
->irq_status
|= flag
;
530 if (flag
& HINFC504_INTS_DMA
) {
531 hinfc_write(host
, HINFC504_INTCLR_DMA
, HINFC504_INTCLR
);
532 complete(&host
->cmd_complete
);
533 } else if (flag
& HINFC504_INTS_CE
) {
534 hinfc_write(host
, HINFC504_INTCLR_CE
, HINFC504_INTCLR
);
535 } else if (flag
& HINFC504_INTS_UE
) {
536 hinfc_write(host
, HINFC504_INTCLR_UE
, HINFC504_INTCLR
);
542 static int hisi_nand_read_page_hwecc(struct mtd_info
*mtd
,
543 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
545 struct hinfc_host
*host
= nand_get_controller_data(chip
);
546 int max_bitflips
= 0, stat
= 0, stat_max
= 0, status_ecc
;
549 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
550 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
552 /* errors which can not be corrected by ECC */
553 if (host
->irq_status
& HINFC504_INTS_UE
) {
554 mtd
->ecc_stats
.failed
++;
555 } else if (host
->irq_status
& HINFC504_INTS_CE
) {
556 /* TODO: need add other ECC modes! */
557 switch (chip
->ecc
.strength
) {
559 status_ecc
= hinfc_read(host
, HINFC504_ECC_STATUS
) >>
560 HINFC504_ECC_16_BIT_SHIFT
& 0x0fff;
561 stat_2
= status_ecc
& 0x3f;
562 stat_1
= status_ecc
>> 6 & 0x3f;
563 stat
= stat_1
+ stat_2
;
564 stat_max
= max_t(int, stat_1
, stat_2
);
566 mtd
->ecc_stats
.corrected
+= stat
;
567 max_bitflips
= max_t(int, max_bitflips
, stat_max
);
569 host
->irq_status
= 0;
574 static int hisi_nand_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
577 struct hinfc_host
*host
= nand_get_controller_data(chip
);
579 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
580 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
582 if (host
->irq_status
& HINFC504_INTS_UE
) {
583 host
->irq_status
= 0;
587 host
->irq_status
= 0;
591 static int hisi_nand_write_page_hwecc(struct mtd_info
*mtd
,
592 struct nand_chip
*chip
, const uint8_t *buf
, int oob_required
,
595 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
597 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
602 static void hisi_nfc_host_init(struct hinfc_host
*host
)
604 struct nand_chip
*chip
= &host
->chip
;
605 unsigned int flag
= 0;
607 host
->version
= hinfc_read(host
, HINFC_VERSION
);
608 host
->addr_cycle
= 0;
609 host
->addr_value
[0] = 0;
610 host
->addr_value
[1] = 0;
611 host
->cache_addr_value
[0] = ~0;
612 host
->cache_addr_value
[1] = ~0;
613 host
->chipselect
= 0;
615 /* default page size: 2K, ecc_none. need modify */
616 flag
= HINFC504_CON_OP_MODE_NORMAL
| HINFC504_CON_READY_BUSY_SEL
617 | ((0x001 & HINFC504_CON_PAGESIZE_MASK
)
618 << HINFC504_CON_PAGEISZE_SHIFT
)
619 | ((0x0 & HINFC504_CON_ECCTYPE_MASK
)
620 << HINFC504_CON_ECCTYPE_SHIFT
)
621 | ((chip
->options
& NAND_BUSWIDTH_16
) ?
622 HINFC504_CON_BUS_WIDTH
: 0);
623 hinfc_write(host
, flag
, HINFC504_CON
);
625 memset(host
->mmio
, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN
);
627 hinfc_write(host
, SET_HINFC504_PWIDTH(HINFC504_W_LATCH
,
628 HINFC504_R_LATCH
, HINFC504_RW_LATCH
), HINFC504_PWIDTH
);
631 hinfc_write(host
, HINFC504_INTEN_DMA
, HINFC504_INTEN
);
634 static struct nand_ecclayout nand_ecc_2K_16bits
= {
635 .oobfree
= { {2, 6} },
638 static int hisi_nfc_ecc_probe(struct hinfc_host
*host
)
641 int size
, strength
, ecc_bits
;
642 struct device
*dev
= host
->dev
;
643 struct nand_chip
*chip
= &host
->chip
;
644 struct mtd_info
*mtd
= nand_to_mtd(chip
);
645 struct device_node
*np
= host
->dev
->of_node
;
647 size
= of_get_nand_ecc_step_size(np
);
648 strength
= of_get_nand_ecc_strength(np
);
650 dev_err(dev
, "error ecc size: %d\n", size
);
654 if ((size
== 1024) && ((strength
!= 8) && (strength
!= 16) &&
655 (strength
!= 24) && (strength
!= 40))) {
656 dev_err(dev
, "ecc size and strength do not match\n");
660 chip
->ecc
.size
= size
;
661 chip
->ecc
.strength
= strength
;
663 chip
->ecc
.read_page
= hisi_nand_read_page_hwecc
;
664 chip
->ecc
.read_oob
= hisi_nand_read_oob
;
665 chip
->ecc
.write_page
= hisi_nand_write_page_hwecc
;
667 switch (chip
->ecc
.strength
) {
670 if (mtd
->writesize
== 2048)
671 chip
->ecc
.layout
= &nand_ecc_2K_16bits
;
673 /* TODO: add more page size support */
676 /* TODO: add more ecc strength support */
678 dev_err(dev
, "not support strength: %d\n", chip
->ecc
.strength
);
682 flag
= hinfc_read(host
, HINFC504_CON
);
683 /* add ecc type configure */
684 flag
|= ((ecc_bits
& HINFC504_CON_ECCTYPE_MASK
)
685 << HINFC504_CON_ECCTYPE_SHIFT
);
686 hinfc_write(host
, flag
, HINFC504_CON
);
689 flag
= hinfc_read(host
, HINFC504_INTEN
) & 0xfff;
690 hinfc_write(host
, flag
| HINFC504_INTEN_UE
| HINFC504_INTEN_CE
,
696 static int hisi_nfc_probe(struct platform_device
*pdev
)
698 int ret
= 0, irq
, buswidth
, flag
, max_chips
= HINFC504_MAX_CHIP
;
699 struct device
*dev
= &pdev
->dev
;
700 struct hinfc_host
*host
;
701 struct nand_chip
*chip
;
702 struct mtd_info
*mtd
;
703 struct resource
*res
;
704 struct device_node
*np
= dev
->of_node
;
706 host
= devm_kzalloc(dev
, sizeof(*host
), GFP_KERNEL
);
711 platform_set_drvdata(pdev
, host
);
713 mtd
= nand_to_mtd(chip
);
715 irq
= platform_get_irq(pdev
, 0);
717 dev_err(dev
, "no IRQ resource defined\n");
722 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
723 host
->iobase
= devm_ioremap_resource(dev
, res
);
724 if (IS_ERR(host
->iobase
)) {
725 ret
= PTR_ERR(host
->iobase
);
729 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
730 host
->mmio
= devm_ioremap_resource(dev
, res
);
731 if (IS_ERR(host
->mmio
)) {
732 ret
= PTR_ERR(host
->mmio
);
733 dev_err(dev
, "devm_ioremap_resource[1] fail\n");
737 mtd
->name
= "hisi_nand";
738 mtd
->dev
.parent
= &pdev
->dev
;
740 nand_set_controller_data(chip
, host
);
741 nand_set_flash_node(chip
, np
);
742 chip
->cmdfunc
= hisi_nfc_cmdfunc
;
743 chip
->select_chip
= hisi_nfc_select_chip
;
744 chip
->read_byte
= hisi_nfc_read_byte
;
745 chip
->read_word
= hisi_nfc_read_word
;
746 chip
->write_buf
= hisi_nfc_write_buf
;
747 chip
->read_buf
= hisi_nfc_read_buf
;
748 chip
->chip_delay
= HINFC504_CHIP_DELAY
;
750 chip
->ecc
.mode
= of_get_nand_ecc_mode(np
);
752 buswidth
= of_get_nand_bus_width(np
);
754 chip
->options
|= NAND_BUSWIDTH_16
;
756 hisi_nfc_host_init(host
);
758 ret
= devm_request_irq(dev
, irq
, hinfc_irq_handle
, 0x0, "nandc", host
);
760 dev_err(dev
, "failed to request IRQ\n");
764 ret
= nand_scan_ident(mtd
, max_chips
, NULL
);
770 host
->buffer
= dmam_alloc_coherent(dev
, mtd
->writesize
+ mtd
->oobsize
,
771 &host
->dma_buffer
, GFP_KERNEL
);
777 host
->dma_oob
= host
->dma_buffer
+ mtd
->writesize
;
778 memset(host
->buffer
, 0xff, mtd
->writesize
+ mtd
->oobsize
);
780 flag
= hinfc_read(host
, HINFC504_CON
);
781 flag
&= ~(HINFC504_CON_PAGESIZE_MASK
<< HINFC504_CON_PAGEISZE_SHIFT
);
782 switch (mtd
->writesize
) {
784 flag
|= (0x001 << HINFC504_CON_PAGEISZE_SHIFT
); break;
786 * TODO: add more pagesize support,
787 * default pagesize has been set in hisi_nfc_host_init
790 dev_err(dev
, "NON-2KB page size nand flash\n");
794 hinfc_write(host
, flag
, HINFC504_CON
);
796 if (chip
->ecc
.mode
== NAND_ECC_HW
)
797 hisi_nfc_ecc_probe(host
);
799 ret
= nand_scan_tail(mtd
);
801 dev_err(dev
, "nand_scan_tail failed: %d\n", ret
);
805 ret
= mtd_device_register(mtd
, NULL
, 0);
807 dev_err(dev
, "Err MTD partition=%d\n", ret
);
819 static int hisi_nfc_remove(struct platform_device
*pdev
)
821 struct hinfc_host
*host
= platform_get_drvdata(pdev
);
822 struct mtd_info
*mtd
= nand_to_mtd(&host
->chip
);
829 #ifdef CONFIG_PM_SLEEP
830 static int hisi_nfc_suspend(struct device
*dev
)
832 struct hinfc_host
*host
= dev_get_drvdata(dev
);
833 unsigned long timeout
= jiffies
+ HINFC504_NFC_PM_TIMEOUT
;
835 while (time_before(jiffies
, timeout
)) {
836 if (((hinfc_read(host
, HINFC504_STATUS
) & 0x1) == 0x0) &&
837 (hinfc_read(host
, HINFC504_DMA_CTRL
) &
838 HINFC504_DMA_CTRL_DMA_START
)) {
844 dev_err(host
->dev
, "nand controller suspend timeout.\n");
849 static int hisi_nfc_resume(struct device
*dev
)
852 struct hinfc_host
*host
= dev_get_drvdata(dev
);
853 struct nand_chip
*chip
= &host
->chip
;
855 for (cs
= 0; cs
< chip
->numchips
; cs
++)
856 hisi_nfc_send_cmd_reset(host
, cs
);
857 hinfc_write(host
, SET_HINFC504_PWIDTH(HINFC504_W_LATCH
,
858 HINFC504_R_LATCH
, HINFC504_RW_LATCH
), HINFC504_PWIDTH
);
863 static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops
, hisi_nfc_suspend
, hisi_nfc_resume
);
865 static const struct of_device_id nfc_id_table
[] = {
866 { .compatible
= "hisilicon,504-nfc" },
869 MODULE_DEVICE_TABLE(of
, nfc_id_table
);
871 static struct platform_driver hisi_nfc_driver
= {
874 .of_match_table
= nfc_id_table
,
875 .pm
= &hisi_nfc_pm_ops
,
877 .probe
= hisi_nfc_probe
,
878 .remove
= hisi_nfc_remove
,
881 module_platform_driver(hisi_nfc_driver
);
883 MODULE_LICENSE("GPL");
884 MODULE_AUTHOR("Zhou Wang");
885 MODULE_AUTHOR("Zhiyong Cai");
886 MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");