drivers/mtd/nand/lpc32xx_slc.c

   1 /*
   2  * NXP LPC32XX NAND SLC driver
   3  *
   4  * Authors:
   5  *    Kevin Wells <kevin.wells@nxp.com>
   6  *    Roland Stigge <stigge@antcom.de>
   7  *
   8  * Copyright © 2011 NXP Semiconductors
   9  * Copyright © 2012 Roland Stigge
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/slab.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/mtd/mtd.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/partitions.h>
  28 #include <linux/clk.h>
  29 #include <linux/err.h>
  30 #include <linux/delay.h>
  31 #include <linux/io.h>
  32 #include <linux/mm.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/dmaengine.h>
  35 #include <linux/mtd/nand_ecc.h>
  36 #include <linux/gpio.h>
  37 #include <linux/of.h>
  38 #include <linux/of_mtd.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mtd/lpc32xx_slc.h>
  41
  42 #define LPC32XX_MODNAME         "lpc32xx-nand"
  43
  44 /**********************************************************************
  45 * SLC NAND controller register offsets
  46 **********************************************************************/
  47
  48 #define SLC_DATA(x)             (x + 0x000)
  49 #define SLC_ADDR(x)             (x + 0x004)
  50 #define SLC_CMD(x)              (x + 0x008)
  51 #define SLC_STOP(x)             (x + 0x00C)
  52 #define SLC_CTRL(x)             (x + 0x010)
  53 #define SLC_CFG(x)              (x + 0x014)
  54 #define SLC_STAT(x)             (x + 0x018)
  55 #define SLC_INT_STAT(x)         (x + 0x01C)
  56 #define SLC_IEN(x)              (x + 0x020)
  57 #define SLC_ISR(x)              (x + 0x024)
  58 #define SLC_ICR(x)              (x + 0x028)
  59 #define SLC_TAC(x)              (x + 0x02C)
  60 #define SLC_TC(x)               (x + 0x030)
  61 #define SLC_ECC(x)              (x + 0x034)
  62 #define SLC_DMA_DATA(x)         (x + 0x038)
  63
  64 /**********************************************************************
  65 * slc_ctrl register definitions
  66 **********************************************************************/
  67 #define SLCCTRL_SW_RESET        (1 << 2) /* Reset the NAND controller bit */
  68 #define SLCCTRL_ECC_CLEAR       (1 << 1) /* Reset ECC bit */
  69 #define SLCCTRL_DMA_START       (1 << 0) /* Start DMA channel bit */
  70
  71 /**********************************************************************
  72 * slc_cfg register definitions
  73 **********************************************************************/
  74 #define SLCCFG_CE_LOW           (1 << 5) /* Force CE low bit */
  75 #define SLCCFG_DMA_ECC          (1 << 4) /* Enable DMA ECC bit */
  76 #define SLCCFG_ECC_EN           (1 << 3) /* ECC enable bit */
  77 #define SLCCFG_DMA_BURST        (1 << 2) /* DMA burst bit */
  78 #define SLCCFG_DMA_DIR          (1 << 1) /* DMA write(0)/read(1) bit */
  79 #define SLCCFG_WIDTH            (1 << 0) /* External device width, 0=8bit */
  80
  81 /**********************************************************************
  82 * slc_stat register definitions
  83 **********************************************************************/
  84 #define SLCSTAT_DMA_FIFO        (1 << 2) /* DMA FIFO has data bit */
  85 #define SLCSTAT_SLC_FIFO        (1 << 1) /* SLC FIFO has data bit */
  86 #define SLCSTAT_NAND_READY      (1 << 0) /* NAND device is ready bit */
  87
  88 /**********************************************************************
  89 * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
  90 **********************************************************************/
  91 #define SLCSTAT_INT_TC          (1 << 1) /* Transfer count bit */
  92 #define SLCSTAT_INT_RDY_EN      (1 << 0) /* Ready interrupt bit */
  93
  94 /**********************************************************************
  95 * slc_tac register definitions
  96 **********************************************************************/
  97 /* Computation of clock cycles on basis of controller and device clock rates */
  98 #define SLCTAC_CLOCKS(c, n, s)  (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
  99
 100 /* Clock setting for RDY write sample wait time in 2*n clocks */
 101 #define SLCTAC_WDR(n)           (((n) & 0xF) << 28)
 102 /* Write pulse width in clock cycles, 1 to 16 clocks */
 103 #define SLCTAC_WWIDTH(c, n)     (SLCTAC_CLOCKS(c, n, 24))
 104 /* Write hold time of control and data signals, 1 to 16 clocks */
 105 #define SLCTAC_WHOLD(c, n)      (SLCTAC_CLOCKS(c, n, 20))
 106 /* Write setup time of control and data signals, 1 to 16 clocks */
 107 #define SLCTAC_WSETUP(c, n)     (SLCTAC_CLOCKS(c, n, 16))
 108 /* Clock setting for RDY read sample wait time in 2*n clocks */
 109 #define SLCTAC_RDR(n)           (((n) & 0xF) << 12)
 110 /* Read pulse width in clock cycles, 1 to 16 clocks */
 111 #define SLCTAC_RWIDTH(c, n)     (SLCTAC_CLOCKS(c, n, 8))
 112 /* Read hold time of control and data signals, 1 to 16 clocks */
 113 #define SLCTAC_RHOLD(c, n)      (SLCTAC_CLOCKS(c, n, 4))
 114 /* Read setup time of control and data signals, 1 to 16 clocks */
 115 #define SLCTAC_RSETUP(c, n)     (SLCTAC_CLOCKS(c, n, 0))
 116
 117 /**********************************************************************
 118 * slc_ecc register definitions
 119 **********************************************************************/
 120 /* ECC line party fetch macro */
 121 #define SLCECC_TO_LINEPAR(n)    (((n) >> 6) & 0x7FFF)
 122 #define SLCECC_TO_COLPAR(n)     ((n) & 0x3F)
 123
 124 /*
 125  * DMA requires storage space for the DMA local buffer and the hardware ECC
 126  * storage area. The DMA local buffer is only used if DMA mapping fails
 127  * during runtime.
 128  */
 129 #define LPC32XX_DMA_DATA_SIZE           4096
 130 #define LPC32XX_ECC_SAVE_SIZE           ((4096 / 256) * 4)
 131
 132 /* Number of bytes used for ECC stored in NAND per 256 bytes */
 133 #define LPC32XX_SLC_DEV_ECC_BYTES       3
 134
 135 /*
 136  * If the NAND base clock frequency can't be fetched, this frequency will be
 137  * used instead as the base. This rate is used to setup the timing registers
 138  * used for NAND accesses.
 139  */
 140 #define LPC32XX_DEF_BUS_RATE            133250000
 141
 142 /* Milliseconds for DMA FIFO timeout (unlikely anyway) */
 143 #define LPC32XX_DMA_TIMEOUT             100
 144
 145 /*
 146  * NAND ECC Layout for small page NAND devices
 147  * Note: For large and huge page devices, the default layouts are used
 148  */
 149 static struct nand_ecclayout lpc32xx_nand_oob_16 = {
 150         .eccbytes = 6,
 151         .eccpos = {10, 11, 12, 13, 14, 15},
 152         .oobfree = {
 153                 { .offset = 0, .length = 4 },
 154                 { .offset = 6, .length = 4 },
 155         },
 156 };
 157
 158 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 159 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 160
 161 /*
 162  * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
 163  * Note: Large page devices used the default layout
 164  */
 165 static struct nand_bbt_descr bbt_smallpage_main_descr = {
 166         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 167                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 168         .offs = 0,
 169         .len = 4,
 170         .veroffs = 6,
 171         .maxblocks = 4,
 172         .pattern = bbt_pattern
 173 };
 174
 175 static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
 176         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 177                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 178         .offs = 0,
 179         .len = 4,
 180         .veroffs = 6,
 181         .maxblocks = 4,
 182         .pattern = mirror_pattern
 183 };
 184
 185 /*
 186  * NAND platform configuration structure
 187  */
 188 struct lpc32xx_nand_cfg_slc {
 189         uint32_t wdr_clks;
 190         uint32_t wwidth;
 191         uint32_t whold;
 192         uint32_t wsetup;
 193         uint32_t rdr_clks;
 194         uint32_t rwidth;
 195         uint32_t rhold;
 196         uint32_t rsetup;
 197         bool use_bbt;
 198         int wp_gpio;
 199         struct mtd_partition *parts;
 200         unsigned num_parts;
 201 };
 202
 203 struct lpc32xx_nand_host {
 204         struct nand_chip        nand_chip;
 205         struct lpc32xx_slc_platform_data *pdata;
 206         struct clk              *clk;
 207         void __iomem            *io_base;
 208         struct lpc32xx_nand_cfg_slc *ncfg;
 209
 210         struct completion       comp;
 211         struct dma_chan         *dma_chan;
 212         uint32_t                dma_buf_len;
 213         struct dma_slave_config dma_slave_config;
 214         struct scatterlist      sgl;
 215
 216         /*
 217          * DMA and CPU addresses of ECC work area and data buffer
 218          */
 219         uint32_t                *ecc_buf;
 220         uint8_t                 *data_buf;
 221         dma_addr_t              io_base_dma;
 222 };
 223
 224 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
 225 {
 226         uint32_t clkrate, tmp;
 227
 228         /* Reset SLC controller */
 229         writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
 230         udelay(1000);
 231
 232         /* Basic setup */
 233         writel(0, SLC_CFG(host->io_base));
 234         writel(0, SLC_IEN(host->io_base));
 235         writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
 236                 SLC_ICR(host->io_base));
 237
 238         /* Get base clock for SLC block */
 239         clkrate = clk_get_rate(host->clk);
 240         if (clkrate == 0)
 241                 clkrate = LPC32XX_DEF_BUS_RATE;
 242
 243         /* Compute clock setup values */
 244         tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
 245                 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
 246                 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
 247                 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
 248                 SLCTAC_RDR(host->ncfg->rdr_clks) |
 249                 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
 250                 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
 251                 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
 252         writel(tmp, SLC_TAC(host->io_base));
 253 }
 254
 255 /*
 256  * Hardware specific access to control lines
 257  */
 258 static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 259         unsigned int ctrl)
 260 {
 261         uint32_t tmp;
 262         struct nand_chip *chip = mtd_to_nand(mtd);
 263         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 264
 265         /* Does CE state need to be changed? */
 266         tmp = readl(SLC_CFG(host->io_base));
 267         if (ctrl & NAND_NCE)
 268                 tmp |= SLCCFG_CE_LOW;
 269         else
 270                 tmp &= ~SLCCFG_CE_LOW;
 271         writel(tmp, SLC_CFG(host->io_base));
 272
 273         if (cmd != NAND_CMD_NONE) {
 274                 if (ctrl & NAND_CLE)
 275                         writel(cmd, SLC_CMD(host->io_base));
 276                 else
 277                         writel(cmd, SLC_ADDR(host->io_base));
 278         }
 279 }
 280
 281 /*
 282  * Read the Device Ready pin
 283  */
 284 static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
 285 {
 286         struct nand_chip *chip = mtd_to_nand(mtd);
 287         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 288         int rdy = 0;
 289
 290         if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
 291                 rdy = 1;
 292
 293         return rdy;
 294 }
 295
 296 /*
 297  * Enable NAND write protect
 298  */
 299 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
 300 {
 301         if (gpio_is_valid(host->ncfg->wp_gpio))
 302                 gpio_set_value(host->ncfg->wp_gpio, 0);
 303 }
 304
 305 /*
 306  * Disable NAND write protect
 307  */
 308 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
 309 {
 310         if (gpio_is_valid(host->ncfg->wp_gpio))
 311                 gpio_set_value(host->ncfg->wp_gpio, 1);
 312 }
 313
 314 /*
 315  * Prepares SLC for transfers with H/W ECC enabled
 316  */
 317 static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
 318 {
 319         /* Hardware ECC is enabled automatically in hardware as needed */
 320 }
 321
 322 /*
 323  * Calculates the ECC for the data
 324  */
 325 static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
 326                                       const unsigned char *buf,
 327                                       unsigned char *code)
 328 {
 329         /*
 330          * ECC is calculated automatically in hardware during syndrome read
 331          * and write operations, so it doesn't need to be calculated here.
 332          */
 333         return 0;
 334 }
 335
 336 /*
 337  * Read a single byte from NAND device
 338  */
 339 static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
 340 {
 341         struct nand_chip *chip = mtd_to_nand(mtd);
 342         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 343
 344         return (uint8_t)readl(SLC_DATA(host->io_base));
 345 }
 346
 347 /*
 348  * Simple device read without ECC
 349  */
 350 static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 351 {
 352         struct nand_chip *chip = mtd_to_nand(mtd);
 353         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 354
 355         /* Direct device read with no ECC */
 356         while (len-- > 0)
 357                 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
 358 }
 359
 360 /*
 361  * Simple device write without ECC
 362  */
 363 static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 364 {
 365         struct nand_chip *chip = mtd_to_nand(mtd);
 366         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 367
 368         /* Direct device write with no ECC */
 369         while (len-- > 0)
 370                 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
 371 }
 372
 373 /*
 374  * Read the OOB data from the device without ECC using FIFO method
 375  */
 376 static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
 377                                           struct nand_chip *chip, int page)
 378 {
 379         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 380         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 381
 382         return 0;
 383 }
 384
 385 /*
 386  * Write the OOB data to the device without ECC using FIFO method
 387  */
 388 static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
 389         struct nand_chip *chip, int page)
 390 {
 391         int status;
 392
 393         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 394         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 395
 396         /* Send command to program the OOB data */
 397         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 398
 399         status = chip->waitfunc(mtd, chip);
 400
 401         return status & NAND_STATUS_FAIL ? -EIO : 0;
 402 }
 403
 404 /*
 405  * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
 406  */
 407 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
 408 {
 409         int i;
 410
 411         for (i = 0; i < (count * 3); i += 3) {
 412                 uint32_t ce = ecc[i / 3];
 413                 ce = ~(ce << 2) & 0xFFFFFF;
 414                 spare[i + 2] = (uint8_t)(ce & 0xFF);
 415                 ce >>= 8;
 416                 spare[i + 1] = (uint8_t)(ce & 0xFF);
 417                 ce >>= 8;
 418                 spare[i] = (uint8_t)(ce & 0xFF);
 419         }
 420 }
 421
 422 static void lpc32xx_dma_complete_func(void *completion)
 423 {
 424         complete(completion);
 425 }
 426
 427 static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
 428                             void *mem, int len, enum dma_transfer_direction dir)
 429 {
 430         struct nand_chip *chip = mtd_to_nand(mtd);
 431         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 432         struct dma_async_tx_descriptor *desc;
 433         int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 434         int res;
 435
 436         host->dma_slave_config.direction = dir;
 437         host->dma_slave_config.src_addr = dma;
 438         host->dma_slave_config.dst_addr = dma;
 439         host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 440         host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 441         host->dma_slave_config.src_maxburst = 4;
 442         host->dma_slave_config.dst_maxburst = 4;
 443         /* DMA controller does flow control: */
 444         host->dma_slave_config.device_fc = false;
 445         if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
 446                 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
 447                 return -ENXIO;
 448         }
 449
 450         sg_init_one(&host->sgl, mem, len);
 451
 452         res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
 453                          DMA_BIDIRECTIONAL);
 454         if (res != 1) {
 455                 dev_err(mtd->dev.parent, "Failed to map sg list\n");
 456                 return -ENXIO;
 457         }
 458         desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
 459                                        flags);
 460         if (!desc) {
 461                 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
 462                 goto out1;
 463         }
 464
 465         init_completion(&host->comp);
 466         desc->callback = lpc32xx_dma_complete_func;
 467         desc->callback_param = &host->comp;
 468
 469         dmaengine_submit(desc);
 470         dma_async_issue_pending(host->dma_chan);
 471
 472         wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
 473
 474         dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
 475                      DMA_BIDIRECTIONAL);
 476
 477         return 0;
 478 out1:
 479         dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
 480                      DMA_BIDIRECTIONAL);
 481         return -ENXIO;
 482 }
 483
 484 /*
 485  * DMA read/write transfers with ECC support
 486  */
 487 static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
 488                         int read)
 489 {
 490         struct nand_chip *chip = mtd_to_nand(mtd);
 491         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 492         int i, status = 0;
 493         unsigned long timeout;
 494         int res;
 495         enum dma_transfer_direction dir =
 496                 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 497         uint8_t *dma_buf;
 498         bool dma_mapped;
 499
 500         if ((void *)buf <= high_memory) {
 501                 dma_buf = buf;
 502                 dma_mapped = true;
 503         } else {
 504                 dma_buf = host->data_buf;
 505                 dma_mapped = false;
 506                 if (!read)
 507                         memcpy(host->data_buf, buf, mtd->writesize);
 508         }
 509
 510         if (read) {
 511                 writel(readl(SLC_CFG(host->io_base)) |
 512                        SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
 513                        SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
 514         } else {
 515                 writel((readl(SLC_CFG(host->io_base)) |
 516                         SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
 517                        ~SLCCFG_DMA_DIR,
 518                         SLC_CFG(host->io_base));
 519         }
 520
 521         /* Clear initial ECC */
 522         writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
 523
 524         /* Transfer size is data area only */
 525         writel(mtd->writesize, SLC_TC(host->io_base));
 526
 527         /* Start transfer in the NAND controller */
 528         writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
 529                SLC_CTRL(host->io_base));
 530
 531         for (i = 0; i < chip->ecc.steps; i++) {
 532                 /* Data */
 533                 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
 534                                        dma_buf + i * chip->ecc.size,
 535                                        mtd->writesize / chip->ecc.steps, dir);
 536                 if (res)
 537                         return res;
 538
 539                 /* Always _read_ ECC */
 540                 if (i == chip->ecc.steps - 1)
 541                         break;
 542                 if (!read) /* ECC availability delayed on write */
 543                         udelay(10);
 544                 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
 545                                        &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
 546                 if (res)
 547                         return res;
 548         }
 549
 550         /*
 551          * According to NXP, the DMA can be finished here, but the NAND
 552          * controller may still have buffered data. After porting to using the
 553          * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
 554          * appears to be always true, according to tests. Keeping the check for
 555          * safety reasons for now.
 556          */
 557         if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
 558                 dev_warn(mtd->dev.parent, "FIFO not empty!\n");
 559                 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
 560                 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
 561                        time_before(jiffies, timeout))
 562                         cpu_relax();
 563                 if (!time_before(jiffies, timeout)) {
 564                         dev_err(mtd->dev.parent, "FIFO held data too long\n");
 565                         status = -EIO;
 566                 }
 567         }
 568
 569         /* Read last calculated ECC value */
 570         if (!read)
 571                 udelay(10);
 572         host->ecc_buf[chip->ecc.steps - 1] =
 573                 readl(SLC_ECC(host->io_base));
 574
 575         /* Flush DMA */
 576         dmaengine_terminate_all(host->dma_chan);
 577
 578         if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
 579             readl(SLC_TC(host->io_base))) {
 580                 /* Something is left in the FIFO, something is wrong */
 581                 dev_err(mtd->dev.parent, "DMA FIFO failure\n");
 582                 status = -EIO;
 583         }
 584
 585         /* Stop DMA & HW ECC */
 586         writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
 587                SLC_CTRL(host->io_base));
 588         writel(readl(SLC_CFG(host->io_base)) &
 589                ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
 590                  SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
 591
 592         if (!dma_mapped && read)
 593                 memcpy(buf, host->data_buf, mtd->writesize);
 594
 595         return status;
 596 }
 597
 598 /*
 599  * Read the data and OOB data from the device, use ECC correction with the
 600  * data, disable ECC for the OOB data
 601  */
 602 static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
 603                                            struct nand_chip *chip, uint8_t *buf,
 604                                            int oob_required, int page)
 605 {
 606         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 607         int stat, i, status;
 608         uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
 609
 610         /* Issue read command */
 611         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 612
 613         /* Read data and oob, calculate ECC */
 614         status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
 615
 616         /* Get OOB data */
 617         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 618
 619         /* Convert to stored ECC format */
 620         lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
 621
 622         /* Pointer to ECC data retrieved from NAND spare area */
 623         oobecc = chip->oob_poi + chip->ecc.layout->eccpos[0];
 624
 625         for (i = 0; i < chip->ecc.steps; i++) {
 626                 stat = chip->ecc.correct(mtd, buf, oobecc,
 627                                          &tmpecc[i * chip->ecc.bytes]);
 628                 if (stat < 0)
 629                         mtd->ecc_stats.failed++;
 630                 else
 631                         mtd->ecc_stats.corrected += stat;
 632
 633                 buf += chip->ecc.size;
 634                 oobecc += chip->ecc.bytes;
 635         }
 636
 637         return status;
 638 }
 639
 640 /*
 641  * Read the data and OOB data from the device, no ECC correction with the
 642  * data or OOB data
 643  */
 644 static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 645                                                struct nand_chip *chip,
 646                                                uint8_t *buf, int oob_required,
 647                                                int page)
 648 {
 649         /* Issue read command */
 650         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 651
 652         /* Raw reads can just use the FIFO interface */
 653         chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
 654         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 655
 656         return 0;
 657 }
 658
 659 /*
 660  * Write the data and OOB data to the device, use ECC with the data,
 661  * disable ECC for the OOB data
 662  */
 663 static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
 664                                             struct nand_chip *chip,
 665                                             const uint8_t *buf,
 666                                             int oob_required, int page)
 667 {
 668         struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
 669         uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0];
 670         int error;
 671
 672         /* Write data, calculate ECC on outbound data */
 673         error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
 674         if (error)
 675                 return error;
 676
 677         /*
 678          * The calculated ECC needs some manual work done to it before
 679          * committing it to NAND. Process the calculated ECC and place
 680          * the resultant values directly into the OOB buffer. */
 681         lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
 682
 683         /* Write ECC data to device */
 684         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 685         return 0;
 686 }
 687
 688 /*
 689  * Write the data and OOB data to the device, no ECC correction with the
 690  * data or OOB data
 691  */
 692 static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 693                                                 struct nand_chip *chip,
 694                                                 const uint8_t *buf,
 695                                                 int oob_required, int page)
 696 {
 697         /* Raw writes can just use the FIFO interface */
 698         chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
 699         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 700         return 0;
 701 }
 702
 703 static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
 704 {
 705         struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
 706         dma_cap_mask_t mask;
 707
 708         if (!host->pdata || !host->pdata->dma_filter) {
 709                 dev_err(mtd->dev.parent, "no DMA platform data\n");
 710                 return -ENOENT;
 711         }
 712
 713         dma_cap_zero(mask);
 714         dma_cap_set(DMA_SLAVE, mask);
 715         host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
 716                                              "nand-slc");
 717         if (!host->dma_chan) {
 718                 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
 719                 return -EBUSY;
 720         }
 721
 722         return 0;
 723 }
 724
 725 static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
 726 {
 727         struct lpc32xx_nand_cfg_slc *ncfg;
 728         struct device_node *np = dev->of_node;
 729
 730         ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
 731         if (!ncfg)
 732                 return NULL;
 733
 734         of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
 735         of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
 736         of_property_read_u32(np, "nxp,whold", &ncfg->whold);
 737         of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
 738         of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
 739         of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
 740         of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
 741         of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
 742
 743         if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
 744             !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
 745             !ncfg->rhold || !ncfg->rsetup) {
 746                 dev_err(dev, "chip parameters not specified correctly\n");
 747                 return NULL;
 748         }
 749
 750         ncfg->use_bbt = of_get_nand_on_flash_bbt(np);
 751         ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0);
 752
 753         return ncfg;
 754 }
 755
 756 /*
 757  * Probe for NAND controller
 758  */
 759 static int lpc32xx_nand_probe(struct platform_device *pdev)
 760 {
 761         struct lpc32xx_nand_host *host;
 762         struct mtd_info *mtd;
 763         struct nand_chip *chip;
 764         struct resource *rc;
 765         int res;
 766
 767         rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 768         if (rc == NULL) {
 769                 dev_err(&pdev->dev, "No memory resource found for device\n");
 770                 return -EBUSY;
 771         }
 772
 773         /* Allocate memory for the device structure (and zero it) */
 774         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 775         if (!host)
 776                 return -ENOMEM;
 777         host->io_base_dma = rc->start;
 778
 779         host->io_base = devm_ioremap_resource(&pdev->dev, rc);
 780         if (IS_ERR(host->io_base))
 781                 return PTR_ERR(host->io_base);
 782
 783         if (pdev->dev.of_node)
 784                 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
 785         if (!host->ncfg) {
 786                 dev_err(&pdev->dev,
 787                         "Missing or bad NAND config from device tree\n");
 788                 return -ENOENT;
 789         }
 790         if (host->ncfg->wp_gpio == -EPROBE_DEFER)
 791                 return -EPROBE_DEFER;
 792         if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev,
 793                         host->ncfg->wp_gpio, "NAND WP")) {
 794                 dev_err(&pdev->dev, "GPIO not available\n");
 795                 return -EBUSY;
 796         }
 797         lpc32xx_wp_disable(host);
 798
 799         host->pdata = dev_get_platdata(&pdev->dev);
 800
 801         chip = &host->nand_chip;
 802         mtd = nand_to_mtd(chip);
 803         nand_set_controller_data(chip, host);
 804         nand_set_flash_node(chip, pdev->dev.of_node);
 805         mtd->owner = THIS_MODULE;
 806         mtd->dev.parent = &pdev->dev;
 807
 808         /* Get NAND clock */
 809         host->clk = devm_clk_get(&pdev->dev, NULL);
 810         if (IS_ERR(host->clk)) {
 811                 dev_err(&pdev->dev, "Clock failure\n");
 812                 res = -ENOENT;
 813                 goto err_exit1;
 814         }
 815         clk_prepare_enable(host->clk);
 816
 817         /* Set NAND IO addresses and command/ready functions */
 818         chip->IO_ADDR_R = SLC_DATA(host->io_base);
 819         chip->IO_ADDR_W = SLC_DATA(host->io_base);
 820         chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
 821         chip->dev_ready = lpc32xx_nand_device_ready;
 822         chip->chip_delay = 20; /* 20us command delay time */
 823
 824         /* Init NAND controller */
 825         lpc32xx_nand_setup(host);
 826
 827         platform_set_drvdata(pdev, host);
 828
 829         /* NAND callbacks for LPC32xx SLC hardware */
 830         chip->ecc.mode = NAND_ECC_HW_SYNDROME;
 831         chip->read_byte = lpc32xx_nand_read_byte;
 832         chip->read_buf = lpc32xx_nand_read_buf;
 833         chip->write_buf = lpc32xx_nand_write_buf;
 834         chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
 835         chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
 836         chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
 837         chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
 838         chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
 839         chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
 840         chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
 841         chip->ecc.correct = nand_correct_data;
 842         chip->ecc.strength = 1;
 843         chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
 844
 845         /*
 846          * Allocate a large enough buffer for a single huge page plus
 847          * extra space for the spare area and ECC storage area
 848          */
 849         host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
 850         host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
 851                                       GFP_KERNEL);
 852         if (host->data_buf == NULL) {
 853                 res = -ENOMEM;
 854                 goto err_exit2;
 855         }
 856
 857         res = lpc32xx_nand_dma_setup(host);
 858         if (res) {
 859                 res = -EIO;
 860                 goto err_exit2;
 861         }
 862
 863         /* Find NAND device */
 864         if (nand_scan_ident(mtd, 1, NULL)) {
 865                 res = -ENXIO;
 866                 goto err_exit3;
 867         }
 868
 869         /* OOB and ECC CPU and DMA work areas */
 870         host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
 871
 872         /*
 873          * Small page FLASH has a unique OOB layout, but large and huge
 874          * page FLASH use the standard layout. Small page FLASH uses a
 875          * custom BBT marker layout.
 876          */
 877         if (mtd->writesize <= 512)
 878                 chip->ecc.layout = &lpc32xx_nand_oob_16;
 879
 880         /* These sizes remain the same regardless of page size */
 881         chip->ecc.size = 256;
 882         chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
 883         chip->ecc.prepad = chip->ecc.postpad = 0;
 884
 885         /* Avoid extra scan if using BBT, setup BBT support */
 886         if (host->ncfg->use_bbt) {
 887                 chip->bbt_options |= NAND_BBT_USE_FLASH;
 888
 889                 /*
 890                  * Use a custom BBT marker setup for small page FLASH that
 891                  * won't interfere with the ECC layout. Large and huge page
 892                  * FLASH use the standard layout.
 893                  */
 894                 if (mtd->writesize <= 512) {
 895                         chip->bbt_td = &bbt_smallpage_main_descr;
 896                         chip->bbt_md = &bbt_smallpage_mirror_descr;
 897                 }
 898         }
 899
 900         /*
 901          * Fills out all the uninitialized function pointers with the defaults
 902          */
 903         if (nand_scan_tail(mtd)) {
 904                 res = -ENXIO;
 905                 goto err_exit3;
 906         }
 907
 908         mtd->name = "nxp_lpc3220_slc";
 909         res = mtd_device_register(mtd, host->ncfg->parts,
 910                                   host->ncfg->num_parts);
 911         if (!res)
 912                 return res;
 913
 914         nand_release(mtd);
 915
 916 err_exit3:
 917         dma_release_channel(host->dma_chan);
 918 err_exit2:
 919         clk_disable_unprepare(host->clk);
 920 err_exit1:
 921         lpc32xx_wp_enable(host);
 922
 923         return res;
 924 }
 925
 926 /*
 927  * Remove NAND device.
 928  */
 929 static int lpc32xx_nand_remove(struct platform_device *pdev)
 930 {
 931         uint32_t tmp;
 932         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 933         struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
 934
 935         nand_release(mtd);
 936         dma_release_channel(host->dma_chan);
 937
 938         /* Force CE high */
 939         tmp = readl(SLC_CTRL(host->io_base));
 940         tmp &= ~SLCCFG_CE_LOW;
 941         writel(tmp, SLC_CTRL(host->io_base));
 942
 943         clk_disable_unprepare(host->clk);
 944         lpc32xx_wp_enable(host);
 945
 946         return 0;
 947 }
 948
 949 #ifdef CONFIG_PM
 950 static int lpc32xx_nand_resume(struct platform_device *pdev)
 951 {
 952         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 953
 954         /* Re-enable NAND clock */
 955         clk_prepare_enable(host->clk);
 956
 957         /* Fresh init of NAND controller */
 958         lpc32xx_nand_setup(host);
 959
 960         /* Disable write protect */
 961         lpc32xx_wp_disable(host);
 962
 963         return 0;
 964 }
 965
 966 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
 967 {
 968         uint32_t tmp;
 969         struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
 970
 971         /* Force CE high */
 972         tmp = readl(SLC_CTRL(host->io_base));
 973         tmp &= ~SLCCFG_CE_LOW;
 974         writel(tmp, SLC_CTRL(host->io_base));
 975
 976         /* Enable write protect for safety */
 977         lpc32xx_wp_enable(host);
 978
 979         /* Disable clock */
 980         clk_disable_unprepare(host->clk);
 981
 982         return 0;
 983 }
 984
 985 #else
 986 #define lpc32xx_nand_resume NULL
 987 #define lpc32xx_nand_suspend NULL
 988 #endif
 989
 990 static const struct of_device_id lpc32xx_nand_match[] = {
 991         { .compatible = "nxp,lpc3220-slc" },
 992         { /* sentinel */ },
 993 };
 994 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
 995
 996 static struct platform_driver lpc32xx_nand_driver = {
 997         .probe          = lpc32xx_nand_probe,
 998         .remove         = lpc32xx_nand_remove,
 999         .resume         = lpc32xx_nand_resume,
1000         .suspend        = lpc32xx_nand_suspend,
1001         .driver         = {
1002                 .name   = LPC32XX_MODNAME,
1003                 .of_match_table = lpc32xx_nand_match,
1004         },
1005 };
1006
1007 module_platform_driver(lpc32xx_nand_driver);
1008
1009 MODULE_LICENSE("GPL");
1010 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1011 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1012 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");