5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ECC support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8
= {
63 static struct nand_ecclayout nand_oob_16
= {
65 .eccpos
= {0, 1, 2, 3, 6, 7},
71 static struct nand_ecclayout nand_oob_64
= {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
82 static struct nand_ecclayout nand_oob_128
= {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
96 static int nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
,
99 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
100 struct mtd_oob_ops
*ops
);
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
106 DEFINE_LED_TRIGGER(nand_led_trigger
);
108 static int check_offs_len(struct mtd_info
*mtd
,
109 loff_t ofs
, uint64_t len
)
111 struct nand_chip
*chip
= mtd
->priv
;
114 /* Start address must align on block boundary */
115 if (ofs
& ((1 << chip
->phys_erase_shift
) - 1)) {
116 pr_debug("%s: unaligned address\n", __func__
);
120 /* Length must align on block boundary */
121 if (len
& ((1 << chip
->phys_erase_shift
) - 1)) {
122 pr_debug("%s: length not block aligned\n", __func__
);
130 * nand_release_device - [GENERIC] release chip
131 * @mtd: MTD device structure
133 * Deselect, release chip lock and wake up anyone waiting on the device.
135 static void nand_release_device(struct mtd_info
*mtd
)
137 struct nand_chip
*chip
= mtd
->priv
;
139 /* De-select the NAND device */
140 chip
->select_chip(mtd
, -1);
142 /* Release the controller and the chip */
143 spin_lock(&chip
->controller
->lock
);
144 chip
->controller
->active
= NULL
;
145 chip
->state
= FL_READY
;
146 wake_up(&chip
->controller
->wq
);
147 spin_unlock(&chip
->controller
->lock
);
151 * nand_read_byte - [DEFAULT] read one byte from the chip
152 * @mtd: MTD device structure
154 * Default read function for 8bit buswidth
156 static uint8_t nand_read_byte(struct mtd_info
*mtd
)
158 struct nand_chip
*chip
= mtd
->priv
;
159 return readb(chip
->IO_ADDR_R
);
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
165 * @mtd: MTD device structure
167 * Default read function for 16bit buswidth with endianness conversion.
170 static uint8_t nand_read_byte16(struct mtd_info
*mtd
)
172 struct nand_chip
*chip
= mtd
->priv
;
173 return (uint8_t) cpu_to_le16(readw(chip
->IO_ADDR_R
));
177 * nand_read_word - [DEFAULT] read one word from the chip
178 * @mtd: MTD device structure
180 * Default read function for 16bit buswidth without endianness conversion.
182 static u16
nand_read_word(struct mtd_info
*mtd
)
184 struct nand_chip
*chip
= mtd
->priv
;
185 return readw(chip
->IO_ADDR_R
);
189 * nand_select_chip - [DEFAULT] control CE line
190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
193 * Default select function for 1 chip devices.
195 static void nand_select_chip(struct mtd_info
*mtd
, int chipnr
)
197 struct nand_chip
*chip
= mtd
->priv
;
201 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
212 * nand_write_buf - [DEFAULT] write buffer to chip
213 * @mtd: MTD device structure
215 * @len: number of bytes to write
217 * Default write function for 8bit buswidth.
219 static void nand_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
222 struct nand_chip
*chip
= mtd
->priv
;
224 for (i
= 0; i
< len
; i
++)
225 writeb(buf
[i
], chip
->IO_ADDR_W
);
229 * nand_read_buf - [DEFAULT] read chip data into buffer
230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
234 * Default read function for 8bit buswidth.
236 static void nand_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
239 struct nand_chip
*chip
= mtd
->priv
;
241 for (i
= 0; i
< len
; i
++)
242 buf
[i
] = readb(chip
->IO_ADDR_R
);
246 * nand_write_buf16 - [DEFAULT] write buffer to chip
247 * @mtd: MTD device structure
249 * @len: number of bytes to write
251 * Default write function for 16bit buswidth.
253 static void nand_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
256 struct nand_chip
*chip
= mtd
->priv
;
257 u16
*p
= (u16
*) buf
;
260 for (i
= 0; i
< len
; i
++)
261 writew(p
[i
], chip
->IO_ADDR_W
);
266 * nand_read_buf16 - [DEFAULT] read chip data into buffer
267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
271 * Default read function for 16bit buswidth.
273 static void nand_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
276 struct nand_chip
*chip
= mtd
->priv
;
277 u16
*p
= (u16
*) buf
;
280 for (i
= 0; i
< len
; i
++)
281 p
[i
] = readw(chip
->IO_ADDR_R
);
285 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
286 * @mtd: MTD device structure
287 * @ofs: offset from device start
288 * @getchip: 0, if the chip is already selected
290 * Check, if the block is bad.
292 static int nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
)
294 int page
, chipnr
, res
= 0, i
= 0;
295 struct nand_chip
*chip
= mtd
->priv
;
298 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
299 ofs
+= mtd
->erasesize
- mtd
->writesize
;
301 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
304 chipnr
= (int)(ofs
>> chip
->chip_shift
);
306 nand_get_device(chip
, mtd
, FL_READING
);
308 /* Select the NAND device */
309 chip
->select_chip(mtd
, chipnr
);
313 if (chip
->options
& NAND_BUSWIDTH_16
) {
314 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
,
315 chip
->badblockpos
& 0xFE, page
);
316 bad
= cpu_to_le16(chip
->read_word(mtd
));
317 if (chip
->badblockpos
& 0x1)
322 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, chip
->badblockpos
,
324 bad
= chip
->read_byte(mtd
);
327 if (likely(chip
->badblockbits
== 8))
330 res
= hweight8(bad
) < chip
->badblockbits
;
331 ofs
+= mtd
->writesize
;
332 page
= (int)(ofs
>> chip
->page_shift
) & chip
->pagemask
;
334 } while (!res
&& i
< 2 && (chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
));
337 nand_release_device(mtd
);
343 * nand_default_block_markbad - [DEFAULT] mark a block bad
344 * @mtd: MTD device structure
345 * @ofs: offset from device start
347 * This is the default implementation, which can be overridden by a hardware
348 * specific driver. We try operations in the following order, according to our
349 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
350 * (1) erase the affected block, to allow OOB marker to be written cleanly
351 * (2) update in-memory BBT
352 * (3) write bad block marker to OOB area of affected block
353 * (4) update flash-based BBT
354 * Note that we retain the first error encountered in (3) or (4), finish the
355 * procedures, and dump the error in the end.
357 static int nand_default_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
359 struct nand_chip
*chip
= mtd
->priv
;
360 uint8_t buf
[2] = { 0, 0 };
361 int block
, res
, ret
= 0, i
= 0;
362 int write_oob
= !(chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
);
365 struct erase_info einfo
;
367 /* Attempt erase before marking OOB */
368 memset(&einfo
, 0, sizeof(einfo
));
371 einfo
.len
= 1 << chip
->phys_erase_shift
;
372 nand_erase_nand(mtd
, &einfo
, 0);
375 /* Get block number */
376 block
= (int)(ofs
>> chip
->bbt_erase_shift
);
377 /* Mark block bad in memory-based BBT */
379 chip
->bbt
[block
>> 2] |= 0x01 << ((block
& 0x03) << 1);
381 /* Write bad block marker to OOB */
383 struct mtd_oob_ops ops
;
386 nand_get_device(chip
, mtd
, FL_WRITING
);
390 ops
.ooboffs
= chip
->badblockpos
;
391 if (chip
->options
& NAND_BUSWIDTH_16
) {
392 ops
.ooboffs
&= ~0x01;
393 ops
.len
= ops
.ooblen
= 2;
395 ops
.len
= ops
.ooblen
= 1;
397 ops
.mode
= MTD_OPS_PLACE_OOB
;
399 /* Write to first/last page(s) if necessary */
400 if (chip
->bbt_options
& NAND_BBT_SCANLASTPAGE
)
401 wr_ofs
+= mtd
->erasesize
- mtd
->writesize
;
403 res
= nand_do_write_oob(mtd
, wr_ofs
, &ops
);
408 wr_ofs
+= mtd
->writesize
;
409 } while ((chip
->bbt_options
& NAND_BBT_SCAN2NDPAGE
) && i
< 2);
411 nand_release_device(mtd
);
414 /* Update flash-based bad block table */
415 if (chip
->bbt_options
& NAND_BBT_USE_FLASH
) {
416 res
= nand_update_bbt(mtd
, ofs
);
422 mtd
->ecc_stats
.badblocks
++;
428 * nand_check_wp - [GENERIC] check if the chip is write protected
429 * @mtd: MTD device structure
431 * Check, if the device is write protected. The function expects, that the
432 * device is already selected.
434 static int nand_check_wp(struct mtd_info
*mtd
)
436 struct nand_chip
*chip
= mtd
->priv
;
438 /* Broken xD cards report WP despite being writable */
439 if (chip
->options
& NAND_BROKEN_XD
)
442 /* Check the WP bit */
443 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
444 return (chip
->read_byte(mtd
) & NAND_STATUS_WP
) ? 0 : 1;
448 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
449 * @mtd: MTD device structure
450 * @ofs: offset from device start
451 * @getchip: 0, if the chip is already selected
452 * @allowbbt: 1, if its allowed to access the bbt area
454 * Check, if the block is bad. Either by reading the bad block table or
455 * calling of the scan function.
457 static int nand_block_checkbad(struct mtd_info
*mtd
, loff_t ofs
, int getchip
,
460 struct nand_chip
*chip
= mtd
->priv
;
463 return chip
->block_bad(mtd
, ofs
, getchip
);
465 /* Return info from the table */
466 return nand_isbad_bbt(mtd
, ofs
, allowbbt
);
470 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
471 * @mtd: MTD device structure
474 * Helper function for nand_wait_ready used when needing to wait in interrupt
477 static void panic_nand_wait_ready(struct mtd_info
*mtd
, unsigned long timeo
)
479 struct nand_chip
*chip
= mtd
->priv
;
482 /* Wait for the device to get ready */
483 for (i
= 0; i
< timeo
; i
++) {
484 if (chip
->dev_ready(mtd
))
486 touch_softlockup_watchdog();
491 /* Wait for the ready pin, after a command. The timeout is caught later. */
492 void nand_wait_ready(struct mtd_info
*mtd
)
494 struct nand_chip
*chip
= mtd
->priv
;
495 unsigned long timeo
= jiffies
+ 2;
498 if (in_interrupt() || oops_in_progress
)
499 return panic_nand_wait_ready(mtd
, 400);
501 led_trigger_event(nand_led_trigger
, LED_FULL
);
502 /* Wait until command is processed or timeout occurs */
504 if (chip
->dev_ready(mtd
))
506 touch_softlockup_watchdog();
507 } while (time_before(jiffies
, timeo
));
508 led_trigger_event(nand_led_trigger
, LED_OFF
);
510 EXPORT_SYMBOL_GPL(nand_wait_ready
);
513 * nand_command - [DEFAULT] Send command to NAND device
514 * @mtd: MTD device structure
515 * @command: the command to be sent
516 * @column: the column address for this command, -1 if none
517 * @page_addr: the page address for this command, -1 if none
519 * Send command to NAND device. This function is used for small page devices
520 * (256/512 Bytes per page).
522 static void nand_command(struct mtd_info
*mtd
, unsigned int command
,
523 int column
, int page_addr
)
525 register struct nand_chip
*chip
= mtd
->priv
;
526 int ctrl
= NAND_CTRL_CLE
| NAND_CTRL_CHANGE
;
528 /* Write out the command to the device */
529 if (command
== NAND_CMD_SEQIN
) {
532 if (column
>= mtd
->writesize
) {
534 column
-= mtd
->writesize
;
535 readcmd
= NAND_CMD_READOOB
;
536 } else if (column
< 256) {
537 /* First 256 bytes --> READ0 */
538 readcmd
= NAND_CMD_READ0
;
541 readcmd
= NAND_CMD_READ1
;
543 chip
->cmd_ctrl(mtd
, readcmd
, ctrl
);
544 ctrl
&= ~NAND_CTRL_CHANGE
;
546 chip
->cmd_ctrl(mtd
, command
, ctrl
);
548 /* Address cycle, when necessary */
549 ctrl
= NAND_CTRL_ALE
| NAND_CTRL_CHANGE
;
550 /* Serially input address */
552 /* Adjust columns for 16 bit buswidth */
553 if (chip
->options
& NAND_BUSWIDTH_16
)
555 chip
->cmd_ctrl(mtd
, column
, ctrl
);
556 ctrl
&= ~NAND_CTRL_CHANGE
;
558 if (page_addr
!= -1) {
559 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
560 ctrl
&= ~NAND_CTRL_CHANGE
;
561 chip
->cmd_ctrl(mtd
, page_addr
>> 8, ctrl
);
562 /* One more address cycle for devices > 32MiB */
563 if (chip
->chipsize
> (32 << 20))
564 chip
->cmd_ctrl(mtd
, page_addr
>> 16, ctrl
);
566 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
569 * Program and erase have their own busy handlers status and sequential
574 case NAND_CMD_PAGEPROG
:
575 case NAND_CMD_ERASE1
:
576 case NAND_CMD_ERASE2
:
578 case NAND_CMD_STATUS
:
584 udelay(chip
->chip_delay
);
585 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
586 NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
588 NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
589 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
593 /* This applies to read commands */
596 * If we don't have access to the busy pin, we apply the given
599 if (!chip
->dev_ready
) {
600 udelay(chip
->chip_delay
);
605 * Apply this short delay always to ensure that we do wait tWB in
606 * any case on any machine.
610 nand_wait_ready(mtd
);
614 * nand_command_lp - [DEFAULT] Send command to NAND large page device
615 * @mtd: MTD device structure
616 * @command: the command to be sent
617 * @column: the column address for this command, -1 if none
618 * @page_addr: the page address for this command, -1 if none
620 * Send command to NAND device. This is the version for the new large page
621 * devices. We don't have the separate regions as we have in the small page
622 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
624 static void nand_command_lp(struct mtd_info
*mtd
, unsigned int command
,
625 int column
, int page_addr
)
627 register struct nand_chip
*chip
= mtd
->priv
;
629 /* Emulate NAND_CMD_READOOB */
630 if (command
== NAND_CMD_READOOB
) {
631 column
+= mtd
->writesize
;
632 command
= NAND_CMD_READ0
;
635 /* Command latch cycle */
636 chip
->cmd_ctrl(mtd
, command
& 0xff,
637 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
639 if (column
!= -1 || page_addr
!= -1) {
640 int ctrl
= NAND_CTRL_CHANGE
| NAND_NCE
| NAND_ALE
;
642 /* Serially input address */
644 /* Adjust columns for 16 bit buswidth */
645 if (chip
->options
& NAND_BUSWIDTH_16
)
647 chip
->cmd_ctrl(mtd
, column
, ctrl
);
648 ctrl
&= ~NAND_CTRL_CHANGE
;
649 chip
->cmd_ctrl(mtd
, column
>> 8, ctrl
);
651 if (page_addr
!= -1) {
652 chip
->cmd_ctrl(mtd
, page_addr
, ctrl
);
653 chip
->cmd_ctrl(mtd
, page_addr
>> 8,
654 NAND_NCE
| NAND_ALE
);
655 /* One more address cycle for devices > 128MiB */
656 if (chip
->chipsize
> (128 << 20))
657 chip
->cmd_ctrl(mtd
, page_addr
>> 16,
658 NAND_NCE
| NAND_ALE
);
661 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
664 * Program and erase have their own busy handlers status, sequential
665 * in, and deplete1 need no delay.
669 case NAND_CMD_CACHEDPROG
:
670 case NAND_CMD_PAGEPROG
:
671 case NAND_CMD_ERASE1
:
672 case NAND_CMD_ERASE2
:
675 case NAND_CMD_STATUS
:
676 case NAND_CMD_DEPLETE1
:
679 case NAND_CMD_STATUS_ERROR
:
680 case NAND_CMD_STATUS_ERROR0
:
681 case NAND_CMD_STATUS_ERROR1
:
682 case NAND_CMD_STATUS_ERROR2
:
683 case NAND_CMD_STATUS_ERROR3
:
684 /* Read error status commands require only a short delay */
685 udelay(chip
->chip_delay
);
691 udelay(chip
->chip_delay
);
692 chip
->cmd_ctrl(mtd
, NAND_CMD_STATUS
,
693 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
694 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
695 NAND_NCE
| NAND_CTRL_CHANGE
);
696 while (!(chip
->read_byte(mtd
) & NAND_STATUS_READY
))
700 case NAND_CMD_RNDOUT
:
701 /* No ready / busy check necessary */
702 chip
->cmd_ctrl(mtd
, NAND_CMD_RNDOUTSTART
,
703 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
704 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
705 NAND_NCE
| NAND_CTRL_CHANGE
);
709 chip
->cmd_ctrl(mtd
, NAND_CMD_READSTART
,
710 NAND_NCE
| NAND_CLE
| NAND_CTRL_CHANGE
);
711 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
,
712 NAND_NCE
| NAND_CTRL_CHANGE
);
714 /* This applies to read commands */
717 * If we don't have access to the busy pin, we apply the given
720 if (!chip
->dev_ready
) {
721 udelay(chip
->chip_delay
);
727 * Apply this short delay always to ensure that we do wait tWB in
728 * any case on any machine.
732 nand_wait_ready(mtd
);
736 * panic_nand_get_device - [GENERIC] Get chip for selected access
737 * @chip: the nand chip descriptor
738 * @mtd: MTD device structure
739 * @new_state: the state which is requested
741 * Used when in panic, no locks are taken.
743 static void panic_nand_get_device(struct nand_chip
*chip
,
744 struct mtd_info
*mtd
, int new_state
)
746 /* Hardware controller shared among independent devices */
747 chip
->controller
->active
= chip
;
748 chip
->state
= new_state
;
752 * nand_get_device - [GENERIC] Get chip for selected access
753 * @chip: the nand chip descriptor
754 * @mtd: MTD device structure
755 * @new_state: the state which is requested
757 * Get the device and lock it for exclusive access
760 nand_get_device(struct nand_chip
*chip
, struct mtd_info
*mtd
, int new_state
)
762 spinlock_t
*lock
= &chip
->controller
->lock
;
763 wait_queue_head_t
*wq
= &chip
->controller
->wq
;
764 DECLARE_WAITQUEUE(wait
, current
);
768 /* Hardware controller shared among independent devices */
769 if (!chip
->controller
->active
)
770 chip
->controller
->active
= chip
;
772 if (chip
->controller
->active
== chip
&& chip
->state
== FL_READY
) {
773 chip
->state
= new_state
;
777 if (new_state
== FL_PM_SUSPENDED
) {
778 if (chip
->controller
->active
->state
== FL_PM_SUSPENDED
) {
779 chip
->state
= FL_PM_SUSPENDED
;
784 set_current_state(TASK_UNINTERRUPTIBLE
);
785 add_wait_queue(wq
, &wait
);
788 remove_wait_queue(wq
, &wait
);
793 * panic_nand_wait - [GENERIC] wait until the command is done
794 * @mtd: MTD device structure
795 * @chip: NAND chip structure
798 * Wait for command done. This is a helper function for nand_wait used when
799 * we are in interrupt context. May happen when in panic and trying to write
800 * an oops through mtdoops.
802 static void panic_nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
,
806 for (i
= 0; i
< timeo
; i
++) {
807 if (chip
->dev_ready
) {
808 if (chip
->dev_ready(mtd
))
811 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
819 * nand_wait - [DEFAULT] wait until the command is done
820 * @mtd: MTD device structure
821 * @chip: NAND chip structure
823 * Wait for command done. This applies to erase and program only. Erase can
824 * take up to 400ms and program up to 20ms according to general NAND and
827 static int nand_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
830 unsigned long timeo
= jiffies
;
831 int status
, state
= chip
->state
;
833 if (state
== FL_ERASING
)
834 timeo
+= (HZ
* 400) / 1000;
836 timeo
+= (HZ
* 20) / 1000;
838 led_trigger_event(nand_led_trigger
, LED_FULL
);
841 * Apply this short delay always to ensure that we do wait tWB in any
842 * case on any machine.
846 if ((state
== FL_ERASING
) && (chip
->options
& NAND_IS_AND
))
847 chip
->cmdfunc(mtd
, NAND_CMD_STATUS_MULTI
, -1, -1);
849 chip
->cmdfunc(mtd
, NAND_CMD_STATUS
, -1, -1);
851 if (in_interrupt() || oops_in_progress
)
852 panic_nand_wait(mtd
, chip
, timeo
);
854 while (time_before(jiffies
, timeo
)) {
855 if (chip
->dev_ready
) {
856 if (chip
->dev_ready(mtd
))
859 if (chip
->read_byte(mtd
) & NAND_STATUS_READY
)
865 led_trigger_event(nand_led_trigger
, LED_OFF
);
867 status
= (int)chip
->read_byte(mtd
);
872 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
874 * @ofs: offset to start unlock from
875 * @len: length to unlock
876 * @invert: when = 0, unlock the range of blocks within the lower and
877 * upper boundary address
878 * when = 1, unlock the range of blocks outside the boundaries
879 * of the lower and upper boundary address
881 * Returs unlock status.
883 static int __nand_unlock(struct mtd_info
*mtd
, loff_t ofs
,
884 uint64_t len
, int invert
)
888 struct nand_chip
*chip
= mtd
->priv
;
890 /* Submit address of first page to unlock */
891 page
= ofs
>> chip
->page_shift
;
892 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK1
, -1, page
& chip
->pagemask
);
894 /* Submit address of last page to unlock */
895 page
= (ofs
+ len
) >> chip
->page_shift
;
896 chip
->cmdfunc(mtd
, NAND_CMD_UNLOCK2
, -1,
897 (page
| invert
) & chip
->pagemask
);
899 /* Call wait ready function */
900 status
= chip
->waitfunc(mtd
, chip
);
901 /* See if device thinks it succeeded */
903 pr_debug("%s: error status = 0x%08x\n",
912 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
914 * @ofs: offset to start unlock from
915 * @len: length to unlock
917 * Returns unlock status.
919 int nand_unlock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
923 struct nand_chip
*chip
= mtd
->priv
;
925 pr_debug("%s: start = 0x%012llx, len = %llu\n",
926 __func__
, (unsigned long long)ofs
, len
);
928 if (check_offs_len(mtd
, ofs
, len
))
931 /* Align to last block address if size addresses end of the device */
932 if (ofs
+ len
== mtd
->size
)
933 len
-= mtd
->erasesize
;
935 nand_get_device(chip
, mtd
, FL_UNLOCKING
);
937 /* Shift to get chip number */
938 chipnr
= ofs
>> chip
->chip_shift
;
940 chip
->select_chip(mtd
, chipnr
);
942 /* Check, if it is write protected */
943 if (nand_check_wp(mtd
)) {
944 pr_debug("%s: device is write protected!\n",
950 ret
= __nand_unlock(mtd
, ofs
, len
, 0);
953 nand_release_device(mtd
);
957 EXPORT_SYMBOL(nand_unlock
);
960 * nand_lock - [REPLACEABLE] locks all blocks present in the device
962 * @ofs: offset to start unlock from
963 * @len: length to unlock
965 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
966 * have this feature, but it allows only to lock all blocks, not for specified
967 * range for block. Implementing 'lock' feature by making use of 'unlock', for
970 * Returns lock status.
972 int nand_lock(struct mtd_info
*mtd
, loff_t ofs
, uint64_t len
)
975 int chipnr
, status
, page
;
976 struct nand_chip
*chip
= mtd
->priv
;
978 pr_debug("%s: start = 0x%012llx, len = %llu\n",
979 __func__
, (unsigned long long)ofs
, len
);
981 if (check_offs_len(mtd
, ofs
, len
))
984 nand_get_device(chip
, mtd
, FL_LOCKING
);
986 /* Shift to get chip number */
987 chipnr
= ofs
>> chip
->chip_shift
;
989 chip
->select_chip(mtd
, chipnr
);
991 /* Check, if it is write protected */
992 if (nand_check_wp(mtd
)) {
993 pr_debug("%s: device is write protected!\n",
995 status
= MTD_ERASE_FAILED
;
1000 /* Submit address of first page to lock */
1001 page
= ofs
>> chip
->page_shift
;
1002 chip
->cmdfunc(mtd
, NAND_CMD_LOCK
, -1, page
& chip
->pagemask
);
1004 /* Call wait ready function */
1005 status
= chip
->waitfunc(mtd
, chip
);
1006 /* See if device thinks it succeeded */
1007 if (status
& 0x01) {
1008 pr_debug("%s: error status = 0x%08x\n",
1014 ret
= __nand_unlock(mtd
, ofs
, len
, 0x1);
1017 nand_release_device(mtd
);
1021 EXPORT_SYMBOL(nand_lock
);
1024 * nand_read_page_raw - [INTERN] read raw page data without ecc
1025 * @mtd: mtd info structure
1026 * @chip: nand chip info structure
1027 * @buf: buffer to store read data
1028 * @oob_required: caller requires OOB data read to chip->oob_poi
1029 * @page: page number to read
1031 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1033 static int nand_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1034 uint8_t *buf
, int oob_required
, int page
)
1036 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
1038 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1043 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1044 * @mtd: mtd info structure
1045 * @chip: nand chip info structure
1046 * @buf: buffer to store read data
1047 * @oob_required: caller requires OOB data read to chip->oob_poi
1048 * @page: page number to read
1050 * We need a special oob layout and handling even when OOB isn't used.
1052 static int nand_read_page_raw_syndrome(struct mtd_info
*mtd
,
1053 struct nand_chip
*chip
, uint8_t *buf
,
1054 int oob_required
, int page
)
1056 int eccsize
= chip
->ecc
.size
;
1057 int eccbytes
= chip
->ecc
.bytes
;
1058 uint8_t *oob
= chip
->oob_poi
;
1061 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1062 chip
->read_buf(mtd
, buf
, eccsize
);
1065 if (chip
->ecc
.prepad
) {
1066 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1067 oob
+= chip
->ecc
.prepad
;
1070 chip
->read_buf(mtd
, oob
, eccbytes
);
1073 if (chip
->ecc
.postpad
) {
1074 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1075 oob
+= chip
->ecc
.postpad
;
1079 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1081 chip
->read_buf(mtd
, oob
, size
);
1087 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1088 * @mtd: mtd info structure
1089 * @chip: nand chip info structure
1090 * @buf: buffer to store read data
1091 * @oob_required: caller requires OOB data read to chip->oob_poi
1092 * @page: page number to read
1094 static int nand_read_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1095 uint8_t *buf
, int oob_required
, int page
)
1097 int i
, eccsize
= chip
->ecc
.size
;
1098 int eccbytes
= chip
->ecc
.bytes
;
1099 int eccsteps
= chip
->ecc
.steps
;
1101 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1102 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1103 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1104 unsigned int max_bitflips
= 0;
1106 chip
->ecc
.read_page_raw(mtd
, chip
, buf
, 1, page
);
1108 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1109 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1111 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1112 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1114 eccsteps
= chip
->ecc
.steps
;
1117 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1120 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1122 mtd
->ecc_stats
.failed
++;
1124 mtd
->ecc_stats
.corrected
+= stat
;
1125 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1128 return max_bitflips
;
1132 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1133 * @mtd: mtd info structure
1134 * @chip: nand chip info structure
1135 * @data_offs: offset of requested data within the page
1136 * @readlen: data length
1137 * @bufpoi: buffer to store read data
1139 static int nand_read_subpage(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1140 uint32_t data_offs
, uint32_t readlen
, uint8_t *bufpoi
)
1142 int start_step
, end_step
, num_steps
;
1143 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1145 int data_col_addr
, i
, gaps
= 0;
1146 int datafrag_len
, eccfrag_len
, aligned_len
, aligned_pos
;
1147 int busw
= (chip
->options
& NAND_BUSWIDTH_16
) ? 2 : 1;
1149 unsigned int max_bitflips
= 0;
1151 /* Column address within the page aligned to ECC size (256bytes) */
1152 start_step
= data_offs
/ chip
->ecc
.size
;
1153 end_step
= (data_offs
+ readlen
- 1) / chip
->ecc
.size
;
1154 num_steps
= end_step
- start_step
+ 1;
1156 /* Data size aligned to ECC ecc.size */
1157 datafrag_len
= num_steps
* chip
->ecc
.size
;
1158 eccfrag_len
= num_steps
* chip
->ecc
.bytes
;
1160 data_col_addr
= start_step
* chip
->ecc
.size
;
1161 /* If we read not a page aligned data */
1162 if (data_col_addr
!= 0)
1163 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_col_addr
, -1);
1165 p
= bufpoi
+ data_col_addr
;
1166 chip
->read_buf(mtd
, p
, datafrag_len
);
1169 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
)
1170 chip
->ecc
.calculate(mtd
, p
, &chip
->buffers
->ecccalc
[i
]);
1173 * The performance is faster if we position offsets according to
1174 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1176 for (i
= 0; i
< eccfrag_len
- 1; i
++) {
1177 if (eccpos
[i
+ start_step
* chip
->ecc
.bytes
] + 1 !=
1178 eccpos
[i
+ start_step
* chip
->ecc
.bytes
+ 1]) {
1184 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1185 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1188 * Send the command to read the particular ECC bytes take care
1189 * about buswidth alignment in read_buf.
1191 index
= start_step
* chip
->ecc
.bytes
;
1193 aligned_pos
= eccpos
[index
] & ~(busw
- 1);
1194 aligned_len
= eccfrag_len
;
1195 if (eccpos
[index
] & (busw
- 1))
1197 if (eccpos
[index
+ (num_steps
* chip
->ecc
.bytes
)] & (busw
- 1))
1200 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1201 mtd
->writesize
+ aligned_pos
, -1);
1202 chip
->read_buf(mtd
, &chip
->oob_poi
[aligned_pos
], aligned_len
);
1205 for (i
= 0; i
< eccfrag_len
; i
++)
1206 chip
->buffers
->ecccode
[i
] = chip
->oob_poi
[eccpos
[i
+ index
]];
1208 p
= bufpoi
+ data_col_addr
;
1209 for (i
= 0; i
< eccfrag_len
; i
+= chip
->ecc
.bytes
, p
+= chip
->ecc
.size
) {
1212 stat
= chip
->ecc
.correct(mtd
, p
,
1213 &chip
->buffers
->ecccode
[i
], &chip
->buffers
->ecccalc
[i
]);
1215 mtd
->ecc_stats
.failed
++;
1217 mtd
->ecc_stats
.corrected
+= stat
;
1218 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1221 return max_bitflips
;
1225 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1226 * @mtd: mtd info structure
1227 * @chip: nand chip info structure
1228 * @buf: buffer to store read data
1229 * @oob_required: caller requires OOB data read to chip->oob_poi
1230 * @page: page number to read
1232 * Not for syndrome calculating ECC controllers which need a special oob layout.
1234 static int nand_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1235 uint8_t *buf
, int oob_required
, int page
)
1237 int i
, eccsize
= chip
->ecc
.size
;
1238 int eccbytes
= chip
->ecc
.bytes
;
1239 int eccsteps
= chip
->ecc
.steps
;
1241 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1242 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1243 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1244 unsigned int max_bitflips
= 0;
1246 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1247 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1248 chip
->read_buf(mtd
, p
, eccsize
);
1249 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1251 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1253 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1254 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1256 eccsteps
= chip
->ecc
.steps
;
1259 for (i
= 0 ; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1262 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1264 mtd
->ecc_stats
.failed
++;
1266 mtd
->ecc_stats
.corrected
+= stat
;
1267 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1270 return max_bitflips
;
1274 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1275 * @mtd: mtd info structure
1276 * @chip: nand chip info structure
1277 * @buf: buffer to store read data
1278 * @oob_required: caller requires OOB data read to chip->oob_poi
1279 * @page: page number to read
1281 * Hardware ECC for large page chips, require OOB to be read first. For this
1282 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1283 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1284 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1285 * the data area, by overwriting the NAND manufacturer bad block markings.
1287 static int nand_read_page_hwecc_oob_first(struct mtd_info
*mtd
,
1288 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
1290 int i
, eccsize
= chip
->ecc
.size
;
1291 int eccbytes
= chip
->ecc
.bytes
;
1292 int eccsteps
= chip
->ecc
.steps
;
1294 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
1295 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1296 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1297 unsigned int max_bitflips
= 0;
1299 /* Read the OOB area first */
1300 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1301 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1302 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0, page
);
1304 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1305 ecc_code
[i
] = chip
->oob_poi
[eccpos
[i
]];
1307 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1310 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1311 chip
->read_buf(mtd
, p
, eccsize
);
1312 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1314 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], NULL
);
1316 mtd
->ecc_stats
.failed
++;
1318 mtd
->ecc_stats
.corrected
+= stat
;
1319 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1322 return max_bitflips
;
1326 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1327 * @mtd: mtd info structure
1328 * @chip: nand chip info structure
1329 * @buf: buffer to store read data
1330 * @oob_required: caller requires OOB data read to chip->oob_poi
1331 * @page: page number to read
1333 * The hw generator calculates the error syndrome automatically. Therefore we
1334 * need a special oob layout and handling.
1336 static int nand_read_page_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1337 uint8_t *buf
, int oob_required
, int page
)
1339 int i
, eccsize
= chip
->ecc
.size
;
1340 int eccbytes
= chip
->ecc
.bytes
;
1341 int eccsteps
= chip
->ecc
.steps
;
1343 uint8_t *oob
= chip
->oob_poi
;
1344 unsigned int max_bitflips
= 0;
1346 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1349 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1350 chip
->read_buf(mtd
, p
, eccsize
);
1352 if (chip
->ecc
.prepad
) {
1353 chip
->read_buf(mtd
, oob
, chip
->ecc
.prepad
);
1354 oob
+= chip
->ecc
.prepad
;
1357 chip
->ecc
.hwctl(mtd
, NAND_ECC_READSYN
);
1358 chip
->read_buf(mtd
, oob
, eccbytes
);
1359 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1362 mtd
->ecc_stats
.failed
++;
1364 mtd
->ecc_stats
.corrected
+= stat
;
1365 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1370 if (chip
->ecc
.postpad
) {
1371 chip
->read_buf(mtd
, oob
, chip
->ecc
.postpad
);
1372 oob
+= chip
->ecc
.postpad
;
1376 /* Calculate remaining oob bytes */
1377 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1379 chip
->read_buf(mtd
, oob
, i
);
1381 return max_bitflips
;
1385 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1386 * @chip: nand chip structure
1387 * @oob: oob destination address
1388 * @ops: oob ops structure
1389 * @len: size of oob to transfer
1391 static uint8_t *nand_transfer_oob(struct nand_chip
*chip
, uint8_t *oob
,
1392 struct mtd_oob_ops
*ops
, size_t len
)
1394 switch (ops
->mode
) {
1396 case MTD_OPS_PLACE_OOB
:
1398 memcpy(oob
, chip
->oob_poi
+ ops
->ooboffs
, len
);
1401 case MTD_OPS_AUTO_OOB
: {
1402 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
1403 uint32_t boffs
= 0, roffs
= ops
->ooboffs
;
1406 for (; free
->length
&& len
; free
++, len
-= bytes
) {
1407 /* Read request not from offset 0? */
1408 if (unlikely(roffs
)) {
1409 if (roffs
>= free
->length
) {
1410 roffs
-= free
->length
;
1413 boffs
= free
->offset
+ roffs
;
1414 bytes
= min_t(size_t, len
,
1415 (free
->length
- roffs
));
1418 bytes
= min_t(size_t, len
, free
->length
);
1419 boffs
= free
->offset
;
1421 memcpy(oob
, chip
->oob_poi
+ boffs
, bytes
);
1433 * nand_do_read_ops - [INTERN] Read data with ECC
1434 * @mtd: MTD device structure
1435 * @from: offset to read from
1436 * @ops: oob ops structure
1438 * Internal function. Called with chip held.
1440 static int nand_do_read_ops(struct mtd_info
*mtd
, loff_t from
,
1441 struct mtd_oob_ops
*ops
)
1443 int chipnr
, page
, realpage
, col
, bytes
, aligned
, oob_required
;
1444 struct nand_chip
*chip
= mtd
->priv
;
1445 struct mtd_ecc_stats stats
;
1447 uint32_t readlen
= ops
->len
;
1448 uint32_t oobreadlen
= ops
->ooblen
;
1449 uint32_t max_oobsize
= ops
->mode
== MTD_OPS_AUTO_OOB
?
1450 mtd
->oobavail
: mtd
->oobsize
;
1452 uint8_t *bufpoi
, *oob
, *buf
;
1453 unsigned int max_bitflips
= 0;
1455 stats
= mtd
->ecc_stats
;
1457 chipnr
= (int)(from
>> chip
->chip_shift
);
1458 chip
->select_chip(mtd
, chipnr
);
1460 realpage
= (int)(from
>> chip
->page_shift
);
1461 page
= realpage
& chip
->pagemask
;
1463 col
= (int)(from
& (mtd
->writesize
- 1));
1467 oob_required
= oob
? 1 : 0;
1470 bytes
= min(mtd
->writesize
- col
, readlen
);
1471 aligned
= (bytes
== mtd
->writesize
);
1473 /* Is the current page in the buffer? */
1474 if (realpage
!= chip
->pagebuf
|| oob
) {
1475 bufpoi
= aligned
? buf
: chip
->buffers
->databuf
;
1477 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, 0x00, page
);
1480 * Now read the page into the buffer. Absent an error,
1481 * the read methods return max bitflips per ecc step.
1483 if (unlikely(ops
->mode
== MTD_OPS_RAW
))
1484 ret
= chip
->ecc
.read_page_raw(mtd
, chip
, bufpoi
,
1487 else if (!aligned
&& NAND_HAS_SUBPAGE_READ(chip
) &&
1489 ret
= chip
->ecc
.read_subpage(mtd
, chip
,
1490 col
, bytes
, bufpoi
);
1492 ret
= chip
->ecc
.read_page(mtd
, chip
, bufpoi
,
1493 oob_required
, page
);
1496 /* Invalidate page cache */
1501 max_bitflips
= max_t(unsigned int, max_bitflips
, ret
);
1503 /* Transfer not aligned data */
1505 if (!NAND_HAS_SUBPAGE_READ(chip
) && !oob
&&
1506 !(mtd
->ecc_stats
.failed
- stats
.failed
) &&
1507 (ops
->mode
!= MTD_OPS_RAW
)) {
1508 chip
->pagebuf
= realpage
;
1509 chip
->pagebuf_bitflips
= ret
;
1511 /* Invalidate page cache */
1514 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1519 if (unlikely(oob
)) {
1520 int toread
= min(oobreadlen
, max_oobsize
);
1523 oob
= nand_transfer_oob(chip
,
1525 oobreadlen
-= toread
;
1529 memcpy(buf
, chip
->buffers
->databuf
+ col
, bytes
);
1531 max_bitflips
= max_t(unsigned int, max_bitflips
,
1532 chip
->pagebuf_bitflips
);
1540 /* For subsequent reads align to page boundary */
1542 /* Increment page address */
1545 page
= realpage
& chip
->pagemask
;
1546 /* Check, if we cross a chip boundary */
1549 chip
->select_chip(mtd
, -1);
1550 chip
->select_chip(mtd
, chipnr
);
1554 ops
->retlen
= ops
->len
- (size_t) readlen
;
1556 ops
->oobretlen
= ops
->ooblen
- oobreadlen
;
1561 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1564 return max_bitflips
;
1568 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1569 * @mtd: MTD device structure
1570 * @from: offset to read from
1571 * @len: number of bytes to read
1572 * @retlen: pointer to variable to store the number of read bytes
1573 * @buf: the databuffer to put data
1575 * Get hold of the chip and call nand_do_read.
1577 static int nand_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
1578 size_t *retlen
, uint8_t *buf
)
1580 struct nand_chip
*chip
= mtd
->priv
;
1581 struct mtd_oob_ops ops
;
1584 nand_get_device(chip
, mtd
, FL_READING
);
1588 ops
.mode
= MTD_OPS_PLACE_OOB
;
1589 ret
= nand_do_read_ops(mtd
, from
, &ops
);
1590 *retlen
= ops
.retlen
;
1591 nand_release_device(mtd
);
1596 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1597 * @mtd: mtd info structure
1598 * @chip: nand chip info structure
1599 * @page: page number to read
1601 static int nand_read_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1604 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
1605 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1610 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1612 * @mtd: mtd info structure
1613 * @chip: nand chip info structure
1614 * @page: page number to read
1616 static int nand_read_oob_syndrome(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1619 uint8_t *buf
= chip
->oob_poi
;
1620 int length
= mtd
->oobsize
;
1621 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1622 int eccsize
= chip
->ecc
.size
;
1623 uint8_t *bufpoi
= buf
;
1624 int i
, toread
, sndrnd
= 0, pos
;
1626 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, chip
->ecc
.size
, page
);
1627 for (i
= 0; i
< chip
->ecc
.steps
; i
++) {
1629 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1630 if (mtd
->writesize
> 512)
1631 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, pos
, -1);
1633 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, pos
, page
);
1636 toread
= min_t(int, length
, chunk
);
1637 chip
->read_buf(mtd
, bufpoi
, toread
);
1642 chip
->read_buf(mtd
, bufpoi
, length
);
1648 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1649 * @mtd: mtd info structure
1650 * @chip: nand chip info structure
1651 * @page: page number to write
1653 static int nand_write_oob_std(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1657 const uint8_t *buf
= chip
->oob_poi
;
1658 int length
= mtd
->oobsize
;
1660 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
1661 chip
->write_buf(mtd
, buf
, length
);
1662 /* Send command to program the OOB data */
1663 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1665 status
= chip
->waitfunc(mtd
, chip
);
1667 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1671 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1672 * with syndrome - only for large page flash
1673 * @mtd: mtd info structure
1674 * @chip: nand chip info structure
1675 * @page: page number to write
1677 static int nand_write_oob_syndrome(struct mtd_info
*mtd
,
1678 struct nand_chip
*chip
, int page
)
1680 int chunk
= chip
->ecc
.bytes
+ chip
->ecc
.prepad
+ chip
->ecc
.postpad
;
1681 int eccsize
= chip
->ecc
.size
, length
= mtd
->oobsize
;
1682 int i
, len
, pos
, status
= 0, sndcmd
= 0, steps
= chip
->ecc
.steps
;
1683 const uint8_t *bufpoi
= chip
->oob_poi
;
1686 * data-ecc-data-ecc ... ecc-oob
1688 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1690 if (!chip
->ecc
.prepad
&& !chip
->ecc
.postpad
) {
1691 pos
= steps
* (eccsize
+ chunk
);
1696 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, pos
, page
);
1697 for (i
= 0; i
< steps
; i
++) {
1699 if (mtd
->writesize
<= 512) {
1700 uint32_t fill
= 0xFFFFFFFF;
1704 int num
= min_t(int, len
, 4);
1705 chip
->write_buf(mtd
, (uint8_t *)&fill
,
1710 pos
= eccsize
+ i
* (eccsize
+ chunk
);
1711 chip
->cmdfunc(mtd
, NAND_CMD_RNDIN
, pos
, -1);
1715 len
= min_t(int, length
, chunk
);
1716 chip
->write_buf(mtd
, bufpoi
, len
);
1721 chip
->write_buf(mtd
, bufpoi
, length
);
1723 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
1724 status
= chip
->waitfunc(mtd
, chip
);
1726 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
1730 * nand_do_read_oob - [INTERN] NAND read out-of-band
1731 * @mtd: MTD device structure
1732 * @from: offset to read from
1733 * @ops: oob operations description structure
1735 * NAND read out-of-band data from the spare area.
1737 static int nand_do_read_oob(struct mtd_info
*mtd
, loff_t from
,
1738 struct mtd_oob_ops
*ops
)
1740 int page
, realpage
, chipnr
;
1741 struct nand_chip
*chip
= mtd
->priv
;
1742 struct mtd_ecc_stats stats
;
1743 int readlen
= ops
->ooblen
;
1745 uint8_t *buf
= ops
->oobbuf
;
1748 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1749 __func__
, (unsigned long long)from
, readlen
);
1751 stats
= mtd
->ecc_stats
;
1753 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
1754 len
= chip
->ecc
.layout
->oobavail
;
1758 if (unlikely(ops
->ooboffs
>= len
)) {
1759 pr_debug("%s: attempt to start read outside oob\n",
1764 /* Do not allow reads past end of device */
1765 if (unlikely(from
>= mtd
->size
||
1766 ops
->ooboffs
+ readlen
> ((mtd
->size
>> chip
->page_shift
) -
1767 (from
>> chip
->page_shift
)) * len
)) {
1768 pr_debug("%s: attempt to read beyond end of device\n",
1773 chipnr
= (int)(from
>> chip
->chip_shift
);
1774 chip
->select_chip(mtd
, chipnr
);
1776 /* Shift to get page */
1777 realpage
= (int)(from
>> chip
->page_shift
);
1778 page
= realpage
& chip
->pagemask
;
1781 if (ops
->mode
== MTD_OPS_RAW
)
1782 ret
= chip
->ecc
.read_oob_raw(mtd
, chip
, page
);
1784 ret
= chip
->ecc
.read_oob(mtd
, chip
, page
);
1789 len
= min(len
, readlen
);
1790 buf
= nand_transfer_oob(chip
, buf
, ops
, len
);
1796 /* Increment page address */
1799 page
= realpage
& chip
->pagemask
;
1800 /* Check, if we cross a chip boundary */
1803 chip
->select_chip(mtd
, -1);
1804 chip
->select_chip(mtd
, chipnr
);
1808 ops
->oobretlen
= ops
->ooblen
- readlen
;
1813 if (mtd
->ecc_stats
.failed
- stats
.failed
)
1816 return mtd
->ecc_stats
.corrected
- stats
.corrected
? -EUCLEAN
: 0;
1820 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1821 * @mtd: MTD device structure
1822 * @from: offset to read from
1823 * @ops: oob operation description structure
1825 * NAND read data and/or out-of-band data.
1827 static int nand_read_oob(struct mtd_info
*mtd
, loff_t from
,
1828 struct mtd_oob_ops
*ops
)
1830 struct nand_chip
*chip
= mtd
->priv
;
1831 int ret
= -ENOTSUPP
;
1835 /* Do not allow reads past end of device */
1836 if (ops
->datbuf
&& (from
+ ops
->len
) > mtd
->size
) {
1837 pr_debug("%s: attempt to read beyond end of device\n",
1842 nand_get_device(chip
, mtd
, FL_READING
);
1844 switch (ops
->mode
) {
1845 case MTD_OPS_PLACE_OOB
:
1846 case MTD_OPS_AUTO_OOB
:
1855 ret
= nand_do_read_oob(mtd
, from
, ops
);
1857 ret
= nand_do_read_ops(mtd
, from
, ops
);
1860 nand_release_device(mtd
);
1866 * nand_write_page_raw - [INTERN] raw page write function
1867 * @mtd: mtd info structure
1868 * @chip: nand chip info structure
1870 * @oob_required: must write chip->oob_poi to OOB
1872 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1874 static int nand_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1875 const uint8_t *buf
, int oob_required
)
1877 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
1879 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1885 * nand_write_page_raw_syndrome - [INTERN] raw page write function
1886 * @mtd: mtd info structure
1887 * @chip: nand chip info structure
1889 * @oob_required: must write chip->oob_poi to OOB
1891 * We need a special oob layout and handling even when ECC isn't checked.
1893 static int nand_write_page_raw_syndrome(struct mtd_info
*mtd
,
1894 struct nand_chip
*chip
,
1895 const uint8_t *buf
, int oob_required
)
1897 int eccsize
= chip
->ecc
.size
;
1898 int eccbytes
= chip
->ecc
.bytes
;
1899 uint8_t *oob
= chip
->oob_poi
;
1902 for (steps
= chip
->ecc
.steps
; steps
> 0; steps
--) {
1903 chip
->write_buf(mtd
, buf
, eccsize
);
1906 if (chip
->ecc
.prepad
) {
1907 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
1908 oob
+= chip
->ecc
.prepad
;
1911 chip
->read_buf(mtd
, oob
, eccbytes
);
1914 if (chip
->ecc
.postpad
) {
1915 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
1916 oob
+= chip
->ecc
.postpad
;
1920 size
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
1922 chip
->write_buf(mtd
, oob
, size
);
1927 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1928 * @mtd: mtd info structure
1929 * @chip: nand chip info structure
1931 * @oob_required: must write chip->oob_poi to OOB
1933 static int nand_write_page_swecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1934 const uint8_t *buf
, int oob_required
)
1936 int i
, eccsize
= chip
->ecc
.size
;
1937 int eccbytes
= chip
->ecc
.bytes
;
1938 int eccsteps
= chip
->ecc
.steps
;
1939 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1940 const uint8_t *p
= buf
;
1941 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1943 /* Software ECC calculation */
1944 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1945 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1947 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1948 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1950 return chip
->ecc
.write_page_raw(mtd
, chip
, buf
, 1);
1954 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1955 * @mtd: mtd info structure
1956 * @chip: nand chip info structure
1958 * @oob_required: must write chip->oob_poi to OOB
1960 static int nand_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1961 const uint8_t *buf
, int oob_required
)
1963 int i
, eccsize
= chip
->ecc
.size
;
1964 int eccbytes
= chip
->ecc
.bytes
;
1965 int eccsteps
= chip
->ecc
.steps
;
1966 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
1967 const uint8_t *p
= buf
;
1968 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1970 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1971 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
1972 chip
->write_buf(mtd
, p
, eccsize
);
1973 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1976 for (i
= 0; i
< chip
->ecc
.total
; i
++)
1977 chip
->oob_poi
[eccpos
[i
]] = ecc_calc
[i
];
1979 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
1985 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1986 * @mtd: mtd info structure
1987 * @chip: nand chip info structure
1989 * @oob_required: must write chip->oob_poi to OOB
1991 * The hw generator calculates the error syndrome automatically. Therefore we
1992 * need a special oob layout and handling.
1994 static int nand_write_page_syndrome(struct mtd_info
*mtd
,
1995 struct nand_chip
*chip
,
1996 const uint8_t *buf
, int oob_required
)
1998 int i
, eccsize
= chip
->ecc
.size
;
1999 int eccbytes
= chip
->ecc
.bytes
;
2000 int eccsteps
= chip
->ecc
.steps
;
2001 const uint8_t *p
= buf
;
2002 uint8_t *oob
= chip
->oob_poi
;
2004 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
2006 chip
->ecc
.hwctl(mtd
, NAND_ECC_WRITE
);
2007 chip
->write_buf(mtd
, p
, eccsize
);
2009 if (chip
->ecc
.prepad
) {
2010 chip
->write_buf(mtd
, oob
, chip
->ecc
.prepad
);
2011 oob
+= chip
->ecc
.prepad
;
2014 chip
->ecc
.calculate(mtd
, p
, oob
);
2015 chip
->write_buf(mtd
, oob
, eccbytes
);
2018 if (chip
->ecc
.postpad
) {
2019 chip
->write_buf(mtd
, oob
, chip
->ecc
.postpad
);
2020 oob
+= chip
->ecc
.postpad
;
2024 /* Calculate remaining oob bytes */
2025 i
= mtd
->oobsize
- (oob
- chip
->oob_poi
);
2027 chip
->write_buf(mtd
, oob
, i
);
2033 * nand_write_page - [REPLACEABLE] write one page
2034 * @mtd: MTD device structure
2035 * @chip: NAND chip descriptor
2036 * @buf: the data to write
2037 * @oob_required: must write chip->oob_poi to OOB
2038 * @page: page number to write
2039 * @cached: cached programming
2040 * @raw: use _raw version of write_page
2042 static int nand_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2043 const uint8_t *buf
, int oob_required
, int page
,
2044 int cached
, int raw
)
2048 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, 0x00, page
);
2051 status
= chip
->ecc
.write_page_raw(mtd
, chip
, buf
, oob_required
);
2053 status
= chip
->ecc
.write_page(mtd
, chip
, buf
, oob_required
);
2059 * Cached progamming disabled for now. Not sure if it's worth the
2060 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2064 if (!cached
|| !(chip
->options
& NAND_CACHEPRG
)) {
2066 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
2067 status
= chip
->waitfunc(mtd
, chip
);
2069 * See if operation failed and additional status checks are
2072 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2073 status
= chip
->errstat(mtd
, chip
, FL_WRITING
, status
,
2076 if (status
& NAND_STATUS_FAIL
)
2079 chip
->cmdfunc(mtd
, NAND_CMD_CACHEDPROG
, -1, -1);
2080 status
= chip
->waitfunc(mtd
, chip
);
2087 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2088 * @mtd: MTD device structure
2089 * @oob: oob data buffer
2090 * @len: oob data write length
2091 * @ops: oob ops structure
2093 static uint8_t *nand_fill_oob(struct mtd_info
*mtd
, uint8_t *oob
, size_t len
,
2094 struct mtd_oob_ops
*ops
)
2096 struct nand_chip
*chip
= mtd
->priv
;
2099 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2100 * data from a previous OOB read.
2102 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2104 switch (ops
->mode
) {
2106 case MTD_OPS_PLACE_OOB
:
2108 memcpy(chip
->oob_poi
+ ops
->ooboffs
, oob
, len
);
2111 case MTD_OPS_AUTO_OOB
: {
2112 struct nand_oobfree
*free
= chip
->ecc
.layout
->oobfree
;
2113 uint32_t boffs
= 0, woffs
= ops
->ooboffs
;
2116 for (; free
->length
&& len
; free
++, len
-= bytes
) {
2117 /* Write request not from offset 0? */
2118 if (unlikely(woffs
)) {
2119 if (woffs
>= free
->length
) {
2120 woffs
-= free
->length
;
2123 boffs
= free
->offset
+ woffs
;
2124 bytes
= min_t(size_t, len
,
2125 (free
->length
- woffs
));
2128 bytes
= min_t(size_t, len
, free
->length
);
2129 boffs
= free
->offset
;
2131 memcpy(chip
->oob_poi
+ boffs
, oob
, bytes
);
2142 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2145 * nand_do_write_ops - [INTERN] NAND write with ECC
2146 * @mtd: MTD device structure
2147 * @to: offset to write to
2148 * @ops: oob operations description structure
2150 * NAND write with ECC.
2152 static int nand_do_write_ops(struct mtd_info
*mtd
, loff_t to
,
2153 struct mtd_oob_ops
*ops
)
2155 int chipnr
, realpage
, page
, blockmask
, column
;
2156 struct nand_chip
*chip
= mtd
->priv
;
2157 uint32_t writelen
= ops
->len
;
2159 uint32_t oobwritelen
= ops
->ooblen
;
2160 uint32_t oobmaxlen
= ops
->mode
== MTD_OPS_AUTO_OOB
?
2161 mtd
->oobavail
: mtd
->oobsize
;
2163 uint8_t *oob
= ops
->oobbuf
;
2164 uint8_t *buf
= ops
->datbuf
;
2166 int oob_required
= oob
? 1 : 0;
2172 /* Reject writes, which are not page aligned */
2173 if (NOTALIGNED(to
) || NOTALIGNED(ops
->len
)) {
2174 pr_notice("%s: attempt to write non page aligned data\n",
2179 column
= to
& (mtd
->writesize
- 1);
2180 subpage
= column
|| (writelen
& (mtd
->writesize
- 1));
2185 chipnr
= (int)(to
>> chip
->chip_shift
);
2186 chip
->select_chip(mtd
, chipnr
);
2188 /* Check, if it is write protected */
2189 if (nand_check_wp(mtd
))
2192 realpage
= (int)(to
>> chip
->page_shift
);
2193 page
= realpage
& chip
->pagemask
;
2194 blockmask
= (1 << (chip
->phys_erase_shift
- chip
->page_shift
)) - 1;
2196 /* Invalidate the page cache, when we write to the cached page */
2197 if (to
<= (chip
->pagebuf
<< chip
->page_shift
) &&
2198 (chip
->pagebuf
<< chip
->page_shift
) < (to
+ ops
->len
))
2201 /* Don't allow multipage oob writes with offset */
2202 if (oob
&& ops
->ooboffs
&& (ops
->ooboffs
+ ops
->ooblen
> oobmaxlen
))
2206 int bytes
= mtd
->writesize
;
2207 int cached
= writelen
> bytes
&& page
!= blockmask
;
2208 uint8_t *wbuf
= buf
;
2210 /* Partial page write? */
2211 if (unlikely(column
|| writelen
< (mtd
->writesize
- 1))) {
2213 bytes
= min_t(int, bytes
- column
, (int) writelen
);
2215 memset(chip
->buffers
->databuf
, 0xff, mtd
->writesize
);
2216 memcpy(&chip
->buffers
->databuf
[column
], buf
, bytes
);
2217 wbuf
= chip
->buffers
->databuf
;
2220 if (unlikely(oob
)) {
2221 size_t len
= min(oobwritelen
, oobmaxlen
);
2222 oob
= nand_fill_oob(mtd
, oob
, len
, ops
);
2225 /* We still need to erase leftover OOB data */
2226 memset(chip
->oob_poi
, 0xff, mtd
->oobsize
);
2229 ret
= chip
->write_page(mtd
, chip
, wbuf
, oob_required
, page
,
2230 cached
, (ops
->mode
== MTD_OPS_RAW
));
2242 page
= realpage
& chip
->pagemask
;
2243 /* Check, if we cross a chip boundary */
2246 chip
->select_chip(mtd
, -1);
2247 chip
->select_chip(mtd
, chipnr
);
2251 ops
->retlen
= ops
->len
- writelen
;
2253 ops
->oobretlen
= ops
->ooblen
;
2258 * panic_nand_write - [MTD Interface] NAND write with ECC
2259 * @mtd: MTD device structure
2260 * @to: offset to write to
2261 * @len: number of bytes to write
2262 * @retlen: pointer to variable to store the number of written bytes
2263 * @buf: the data to write
2265 * NAND write with ECC. Used when performing writes in interrupt context, this
2266 * may for example be called by mtdoops when writing an oops while in panic.
2268 static int panic_nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2269 size_t *retlen
, const uint8_t *buf
)
2271 struct nand_chip
*chip
= mtd
->priv
;
2272 struct mtd_oob_ops ops
;
2275 /* Wait for the device to get ready */
2276 panic_nand_wait(mtd
, chip
, 400);
2278 /* Grab the device */
2279 panic_nand_get_device(chip
, mtd
, FL_WRITING
);
2282 ops
.datbuf
= (uint8_t *)buf
;
2284 ops
.mode
= MTD_OPS_PLACE_OOB
;
2286 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2288 *retlen
= ops
.retlen
;
2293 * nand_write - [MTD Interface] NAND write with ECC
2294 * @mtd: MTD device structure
2295 * @to: offset to write to
2296 * @len: number of bytes to write
2297 * @retlen: pointer to variable to store the number of written bytes
2298 * @buf: the data to write
2300 * NAND write with ECC.
2302 static int nand_write(struct mtd_info
*mtd
, loff_t to
, size_t len
,
2303 size_t *retlen
, const uint8_t *buf
)
2305 struct nand_chip
*chip
= mtd
->priv
;
2306 struct mtd_oob_ops ops
;
2309 nand_get_device(chip
, mtd
, FL_WRITING
);
2311 ops
.datbuf
= (uint8_t *)buf
;
2313 ops
.mode
= MTD_OPS_PLACE_OOB
;
2314 ret
= nand_do_write_ops(mtd
, to
, &ops
);
2315 *retlen
= ops
.retlen
;
2316 nand_release_device(mtd
);
2321 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2322 * @mtd: MTD device structure
2323 * @to: offset to write to
2324 * @ops: oob operation description structure
2326 * NAND write out-of-band.
2328 static int nand_do_write_oob(struct mtd_info
*mtd
, loff_t to
,
2329 struct mtd_oob_ops
*ops
)
2331 int chipnr
, page
, status
, len
;
2332 struct nand_chip
*chip
= mtd
->priv
;
2334 pr_debug("%s: to = 0x%08x, len = %i\n",
2335 __func__
, (unsigned int)to
, (int)ops
->ooblen
);
2337 if (ops
->mode
== MTD_OPS_AUTO_OOB
)
2338 len
= chip
->ecc
.layout
->oobavail
;
2342 /* Do not allow write past end of page */
2343 if ((ops
->ooboffs
+ ops
->ooblen
) > len
) {
2344 pr_debug("%s: attempt to write past end of page\n",
2349 if (unlikely(ops
->ooboffs
>= len
)) {
2350 pr_debug("%s: attempt to start write outside oob\n",
2355 /* Do not allow write past end of device */
2356 if (unlikely(to
>= mtd
->size
||
2357 ops
->ooboffs
+ ops
->ooblen
>
2358 ((mtd
->size
>> chip
->page_shift
) -
2359 (to
>> chip
->page_shift
)) * len
)) {
2360 pr_debug("%s: attempt to write beyond end of device\n",
2365 chipnr
= (int)(to
>> chip
->chip_shift
);
2366 chip
->select_chip(mtd
, chipnr
);
2368 /* Shift to get page */
2369 page
= (int)(to
>> chip
->page_shift
);
2372 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2373 * of my DiskOnChip 2000 test units) will clear the whole data page too
2374 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2375 * it in the doc2000 driver in August 1999. dwmw2.
2377 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
2379 /* Check, if it is write protected */
2380 if (nand_check_wp(mtd
))
2383 /* Invalidate the page cache, if we write to the cached page */
2384 if (page
== chip
->pagebuf
)
2387 nand_fill_oob(mtd
, ops
->oobbuf
, ops
->ooblen
, ops
);
2389 if (ops
->mode
== MTD_OPS_RAW
)
2390 status
= chip
->ecc
.write_oob_raw(mtd
, chip
, page
& chip
->pagemask
);
2392 status
= chip
->ecc
.write_oob(mtd
, chip
, page
& chip
->pagemask
);
2397 ops
->oobretlen
= ops
->ooblen
;
2403 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2404 * @mtd: MTD device structure
2405 * @to: offset to write to
2406 * @ops: oob operation description structure
2408 static int nand_write_oob(struct mtd_info
*mtd
, loff_t to
,
2409 struct mtd_oob_ops
*ops
)
2411 struct nand_chip
*chip
= mtd
->priv
;
2412 int ret
= -ENOTSUPP
;
2416 /* Do not allow writes past end of device */
2417 if (ops
->datbuf
&& (to
+ ops
->len
) > mtd
->size
) {
2418 pr_debug("%s: attempt to write beyond end of device\n",
2423 nand_get_device(chip
, mtd
, FL_WRITING
);
2425 switch (ops
->mode
) {
2426 case MTD_OPS_PLACE_OOB
:
2427 case MTD_OPS_AUTO_OOB
:
2436 ret
= nand_do_write_oob(mtd
, to
, ops
);
2438 ret
= nand_do_write_ops(mtd
, to
, ops
);
2441 nand_release_device(mtd
);
2446 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2447 * @mtd: MTD device structure
2448 * @page: the page address of the block which will be erased
2450 * Standard erase command for NAND chips.
2452 static void single_erase_cmd(struct mtd_info
*mtd
, int page
)
2454 struct nand_chip
*chip
= mtd
->priv
;
2455 /* Send commands to erase a block */
2456 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2457 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2461 * multi_erase_cmd - [GENERIC] AND specific block erase command function
2462 * @mtd: MTD device structure
2463 * @page: the page address of the block which will be erased
2465 * AND multi block erase command function. Erase 4 consecutive blocks.
2467 static void multi_erase_cmd(struct mtd_info
*mtd
, int page
)
2469 struct nand_chip
*chip
= mtd
->priv
;
2470 /* Send commands to erase a block */
2471 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2472 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2473 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
++);
2474 chip
->cmdfunc(mtd
, NAND_CMD_ERASE1
, -1, page
);
2475 chip
->cmdfunc(mtd
, NAND_CMD_ERASE2
, -1, -1);
2479 * nand_erase - [MTD Interface] erase block(s)
2480 * @mtd: MTD device structure
2481 * @instr: erase instruction
2483 * Erase one ore more blocks.
2485 static int nand_erase(struct mtd_info
*mtd
, struct erase_info
*instr
)
2487 return nand_erase_nand(mtd
, instr
, 0);
2490 #define BBT_PAGE_MASK 0xffffff3f
2492 * nand_erase_nand - [INTERN] erase block(s)
2493 * @mtd: MTD device structure
2494 * @instr: erase instruction
2495 * @allowbbt: allow erasing the bbt area
2497 * Erase one ore more blocks.
2499 int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
2502 int page
, status
, pages_per_block
, ret
, chipnr
;
2503 struct nand_chip
*chip
= mtd
->priv
;
2504 loff_t rewrite_bbt
[NAND_MAX_CHIPS
] = {0};
2505 unsigned int bbt_masked_page
= 0xffffffff;
2508 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2509 __func__
, (unsigned long long)instr
->addr
,
2510 (unsigned long long)instr
->len
);
2512 if (check_offs_len(mtd
, instr
->addr
, instr
->len
))
2515 /* Grab the lock and see if the device is available */
2516 nand_get_device(chip
, mtd
, FL_ERASING
);
2518 /* Shift to get first page */
2519 page
= (int)(instr
->addr
>> chip
->page_shift
);
2520 chipnr
= (int)(instr
->addr
>> chip
->chip_shift
);
2522 /* Calculate pages in each block */
2523 pages_per_block
= 1 << (chip
->phys_erase_shift
- chip
->page_shift
);
2525 /* Select the NAND device */
2526 chip
->select_chip(mtd
, chipnr
);
2528 /* Check, if it is write protected */
2529 if (nand_check_wp(mtd
)) {
2530 pr_debug("%s: device is write protected!\n",
2532 instr
->state
= MTD_ERASE_FAILED
;
2537 * If BBT requires refresh, set the BBT page mask to see if the BBT
2538 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2539 * can not be matched. This is also done when the bbt is actually
2540 * erased to avoid recursive updates.
2542 if (chip
->options
& BBT_AUTO_REFRESH
&& !allowbbt
)
2543 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] & BBT_PAGE_MASK
;
2545 /* Loop through the pages */
2548 instr
->state
= MTD_ERASING
;
2551 /* Check if we have a bad block, we do not erase bad blocks! */
2552 if (nand_block_checkbad(mtd
, ((loff_t
) page
) <<
2553 chip
->page_shift
, 0, allowbbt
)) {
2554 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2556 instr
->state
= MTD_ERASE_FAILED
;
2561 * Invalidate the page cache, if we erase the block which
2562 * contains the current cached page.
2564 if (page
<= chip
->pagebuf
&& chip
->pagebuf
<
2565 (page
+ pages_per_block
))
2568 chip
->erase_cmd(mtd
, page
& chip
->pagemask
);
2570 status
= chip
->waitfunc(mtd
, chip
);
2573 * See if operation failed and additional status checks are
2576 if ((status
& NAND_STATUS_FAIL
) && (chip
->errstat
))
2577 status
= chip
->errstat(mtd
, chip
, FL_ERASING
,
2580 /* See if block erase succeeded */
2581 if (status
& NAND_STATUS_FAIL
) {
2582 pr_debug("%s: failed erase, page 0x%08x\n",
2584 instr
->state
= MTD_ERASE_FAILED
;
2586 ((loff_t
)page
<< chip
->page_shift
);
2591 * If BBT requires refresh, set the BBT rewrite flag to the
2592 * page being erased.
2594 if (bbt_masked_page
!= 0xffffffff &&
2595 (page
& BBT_PAGE_MASK
) == bbt_masked_page
)
2596 rewrite_bbt
[chipnr
] =
2597 ((loff_t
)page
<< chip
->page_shift
);
2599 /* Increment page address and decrement length */
2600 len
-= (1 << chip
->phys_erase_shift
);
2601 page
+= pages_per_block
;
2603 /* Check, if we cross a chip boundary */
2604 if (len
&& !(page
& chip
->pagemask
)) {
2606 chip
->select_chip(mtd
, -1);
2607 chip
->select_chip(mtd
, chipnr
);
2610 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2611 * page mask to see if this BBT should be rewritten.
2613 if (bbt_masked_page
!= 0xffffffff &&
2614 (chip
->bbt_td
->options
& NAND_BBT_PERCHIP
))
2615 bbt_masked_page
= chip
->bbt_td
->pages
[chipnr
] &
2619 instr
->state
= MTD_ERASE_DONE
;
2623 ret
= instr
->state
== MTD_ERASE_DONE
? 0 : -EIO
;
2625 /* Deselect and wake up anyone waiting on the device */
2626 nand_release_device(mtd
);
2628 /* Do call back function */
2630 mtd_erase_callback(instr
);
2633 * If BBT requires refresh and erase was successful, rewrite any
2634 * selected bad block tables.
2636 if (bbt_masked_page
== 0xffffffff || ret
)
2639 for (chipnr
= 0; chipnr
< chip
->numchips
; chipnr
++) {
2640 if (!rewrite_bbt
[chipnr
])
2642 /* Update the BBT for chip */
2643 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2644 __func__
, chipnr
, rewrite_bbt
[chipnr
],
2645 chip
->bbt_td
->pages
[chipnr
]);
2646 nand_update_bbt(mtd
, rewrite_bbt
[chipnr
]);
2649 /* Return more or less happy */
2654 * nand_sync - [MTD Interface] sync
2655 * @mtd: MTD device structure
2657 * Sync is actually a wait for chip ready function.
2659 static void nand_sync(struct mtd_info
*mtd
)
2661 struct nand_chip
*chip
= mtd
->priv
;
2663 pr_debug("%s: called\n", __func__
);
2665 /* Grab the lock and see if the device is available */
2666 nand_get_device(chip
, mtd
, FL_SYNCING
);
2667 /* Release it and go back */
2668 nand_release_device(mtd
);
2672 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2673 * @mtd: MTD device structure
2674 * @offs: offset relative to mtd start
2676 static int nand_block_isbad(struct mtd_info
*mtd
, loff_t offs
)
2678 return nand_block_checkbad(mtd
, offs
, 1, 0);
2682 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2683 * @mtd: MTD device structure
2684 * @ofs: offset relative to mtd start
2686 static int nand_block_markbad(struct mtd_info
*mtd
, loff_t ofs
)
2688 struct nand_chip
*chip
= mtd
->priv
;
2691 ret
= nand_block_isbad(mtd
, ofs
);
2693 /* If it was bad already, return success and do nothing */
2699 return chip
->block_markbad(mtd
, ofs
);
2703 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2704 * @mtd: MTD device structure
2705 * @chip: nand chip info structure
2706 * @addr: feature address.
2707 * @subfeature_param: the subfeature parameters, a four bytes array.
2709 static int nand_onfi_set_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2710 int addr
, uint8_t *subfeature_param
)
2714 if (!chip
->onfi_version
)
2717 chip
->cmdfunc(mtd
, NAND_CMD_SET_FEATURES
, addr
, -1);
2718 chip
->write_buf(mtd
, subfeature_param
, ONFI_SUBFEATURE_PARAM_LEN
);
2719 status
= chip
->waitfunc(mtd
, chip
);
2720 if (status
& NAND_STATUS_FAIL
)
2726 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2727 * @mtd: MTD device structure
2728 * @chip: nand chip info structure
2729 * @addr: feature address.
2730 * @subfeature_param: the subfeature parameters, a four bytes array.
2732 static int nand_onfi_get_features(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2733 int addr
, uint8_t *subfeature_param
)
2735 if (!chip
->onfi_version
)
2738 /* clear the sub feature parameters */
2739 memset(subfeature_param
, 0, ONFI_SUBFEATURE_PARAM_LEN
);
2741 chip
->cmdfunc(mtd
, NAND_CMD_GET_FEATURES
, addr
, -1);
2742 chip
->read_buf(mtd
, subfeature_param
, ONFI_SUBFEATURE_PARAM_LEN
);
2747 * nand_suspend - [MTD Interface] Suspend the NAND flash
2748 * @mtd: MTD device structure
2750 static int nand_suspend(struct mtd_info
*mtd
)
2752 struct nand_chip
*chip
= mtd
->priv
;
2754 return nand_get_device(chip
, mtd
, FL_PM_SUSPENDED
);
2758 * nand_resume - [MTD Interface] Resume the NAND flash
2759 * @mtd: MTD device structure
2761 static void nand_resume(struct mtd_info
*mtd
)
2763 struct nand_chip
*chip
= mtd
->priv
;
2765 if (chip
->state
== FL_PM_SUSPENDED
)
2766 nand_release_device(mtd
);
2768 pr_err("%s called for a chip which is not in suspended state\n",
2772 /* Set default functions */
2773 static void nand_set_defaults(struct nand_chip
*chip
, int busw
)
2775 /* check for proper chip_delay setup, set 20us if not */
2776 if (!chip
->chip_delay
)
2777 chip
->chip_delay
= 20;
2779 /* check, if a user supplied command function given */
2780 if (chip
->cmdfunc
== NULL
)
2781 chip
->cmdfunc
= nand_command
;
2783 /* check, if a user supplied wait function given */
2784 if (chip
->waitfunc
== NULL
)
2785 chip
->waitfunc
= nand_wait
;
2787 if (!chip
->select_chip
)
2788 chip
->select_chip
= nand_select_chip
;
2789 if (!chip
->read_byte
)
2790 chip
->read_byte
= busw
? nand_read_byte16
: nand_read_byte
;
2791 if (!chip
->read_word
)
2792 chip
->read_word
= nand_read_word
;
2793 if (!chip
->block_bad
)
2794 chip
->block_bad
= nand_block_bad
;
2795 if (!chip
->block_markbad
)
2796 chip
->block_markbad
= nand_default_block_markbad
;
2797 if (!chip
->write_buf
)
2798 chip
->write_buf
= busw
? nand_write_buf16
: nand_write_buf
;
2799 if (!chip
->read_buf
)
2800 chip
->read_buf
= busw
? nand_read_buf16
: nand_read_buf
;
2801 if (!chip
->scan_bbt
)
2802 chip
->scan_bbt
= nand_default_bbt
;
2804 if (!chip
->controller
) {
2805 chip
->controller
= &chip
->hwcontrol
;
2806 spin_lock_init(&chip
->controller
->lock
);
2807 init_waitqueue_head(&chip
->controller
->wq
);
2812 /* Sanitize ONFI strings so we can safely print them */
2813 static void sanitize_string(uint8_t *s
, size_t len
)
2817 /* Null terminate */
2820 /* Remove non printable chars */
2821 for (i
= 0; i
< len
- 1; i
++) {
2822 if (s
[i
] < ' ' || s
[i
] > 127)
2826 /* Remove trailing spaces */
2830 static u16
onfi_crc16(u16 crc
, u8
const *p
, size_t len
)
2835 for (i
= 0; i
< 8; i
++)
2836 crc
= (crc
<< 1) ^ ((crc
& 0x8000) ? 0x8005 : 0);
2843 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2845 static int nand_flash_detect_onfi(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2848 struct nand_onfi_params
*p
= &chip
->onfi_params
;
2852 /* Try ONFI for unknown chip or LP */
2853 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x20, -1);
2854 if (chip
->read_byte(mtd
) != 'O' || chip
->read_byte(mtd
) != 'N' ||
2855 chip
->read_byte(mtd
) != 'F' || chip
->read_byte(mtd
) != 'I')
2858 chip
->cmdfunc(mtd
, NAND_CMD_PARAM
, 0, -1);
2859 for (i
= 0; i
< 3; i
++) {
2860 chip
->read_buf(mtd
, (uint8_t *)p
, sizeof(*p
));
2861 if (onfi_crc16(ONFI_CRC_BASE
, (uint8_t *)p
, 254) ==
2862 le16_to_cpu(p
->crc
)) {
2863 pr_info("ONFI param page %d valid\n", i
);
2872 val
= le16_to_cpu(p
->revision
);
2874 chip
->onfi_version
= 23;
2875 else if (val
& (1 << 4))
2876 chip
->onfi_version
= 22;
2877 else if (val
& (1 << 3))
2878 chip
->onfi_version
= 21;
2879 else if (val
& (1 << 2))
2880 chip
->onfi_version
= 20;
2881 else if (val
& (1 << 1))
2882 chip
->onfi_version
= 10;
2884 chip
->onfi_version
= 0;
2886 if (!chip
->onfi_version
) {
2887 pr_info("%s: unsupported ONFI version: %d\n", __func__
, val
);
2891 sanitize_string(p
->manufacturer
, sizeof(p
->manufacturer
));
2892 sanitize_string(p
->model
, sizeof(p
->model
));
2894 mtd
->name
= p
->model
;
2895 mtd
->writesize
= le32_to_cpu(p
->byte_per_page
);
2896 mtd
->erasesize
= le32_to_cpu(p
->pages_per_block
) * mtd
->writesize
;
2897 mtd
->oobsize
= le16_to_cpu(p
->spare_bytes_per_page
);
2898 chip
->chipsize
= le32_to_cpu(p
->blocks_per_lun
);
2899 chip
->chipsize
*= (uint64_t)mtd
->erasesize
* p
->lun_count
;
2901 if (le16_to_cpu(p
->features
) & 1)
2902 *busw
= NAND_BUSWIDTH_16
;
2904 pr_info("ONFI flash detected\n");
2909 * nand_id_has_period - Check if an ID string has a given wraparound period
2910 * @id_data: the ID string
2911 * @arrlen: the length of the @id_data array
2912 * @period: the period of repitition
2914 * Check if an ID string is repeated within a given sequence of bytes at
2915 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2916 * period of 2). This is a helper function for nand_id_len(). Returns non-zero
2917 * if the repetition has a period of @period; otherwise, returns zero.
2919 static int nand_id_has_period(u8
*id_data
, int arrlen
, int period
)
2922 for (i
= 0; i
< period
; i
++)
2923 for (j
= i
+ period
; j
< arrlen
; j
+= period
)
2924 if (id_data
[i
] != id_data
[j
])
2930 * nand_id_len - Get the length of an ID string returned by CMD_READID
2931 * @id_data: the ID string
2932 * @arrlen: the length of the @id_data array
2934 * Returns the length of the ID string, according to known wraparound/trailing
2935 * zero patterns. If no pattern exists, returns the length of the array.
2937 static int nand_id_len(u8
*id_data
, int arrlen
)
2939 int last_nonzero
, period
;
2941 /* Find last non-zero byte */
2942 for (last_nonzero
= arrlen
- 1; last_nonzero
>= 0; last_nonzero
--)
2943 if (id_data
[last_nonzero
])
2947 if (last_nonzero
< 0)
2950 /* Calculate wraparound period */
2951 for (period
= 1; period
< arrlen
; period
++)
2952 if (nand_id_has_period(id_data
, arrlen
, period
))
2955 /* There's a repeated pattern */
2956 if (period
< arrlen
)
2959 /* There are trailing zeros */
2960 if (last_nonzero
< arrlen
- 1)
2961 return last_nonzero
+ 1;
2963 /* No pattern detected */
2968 * Many new NAND share similar device ID codes, which represent the size of the
2969 * chip. The rest of the parameters must be decoded according to generic or
2970 * manufacturer-specific "extended ID" decoding patterns.
2972 static void nand_decode_ext_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
2973 u8 id_data
[8], int *busw
)
2976 /* The 3rd id byte holds MLC / multichip data */
2977 chip
->cellinfo
= id_data
[2];
2978 /* The 4th id byte is the important one */
2981 id_len
= nand_id_len(id_data
, 8);
2984 * Field definitions are in the following datasheets:
2985 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2986 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2987 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
2989 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2990 * ID to decide what to do.
2992 if (id_len
== 6 && id_data
[0] == NAND_MFR_SAMSUNG
&&
2993 (chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
2994 id_data
[5] != 0x00) {
2996 mtd
->writesize
= 2048 << (extid
& 0x03);
2999 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3016 default: /* Other cases are "reserved" (unknown) */
3021 /* Calc blocksize */
3022 mtd
->erasesize
= (128 * 1024) <<
3023 (((extid
>> 1) & 0x04) | (extid
& 0x03));
3025 } else if (id_len
== 6 && id_data
[0] == NAND_MFR_HYNIX
&&
3026 (chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
)) {
3030 mtd
->writesize
= 2048 << (extid
& 0x03);
3033 switch (((extid
>> 2) & 0x04) | (extid
& 0x03)) {
3057 /* Calc blocksize */
3058 tmp
= ((extid
>> 1) & 0x04) | (extid
& 0x03);
3060 mtd
->erasesize
= (128 * 1024) << tmp
;
3061 else if (tmp
== 0x03)
3062 mtd
->erasesize
= 768 * 1024;
3064 mtd
->erasesize
= (64 * 1024) << tmp
;
3068 mtd
->writesize
= 1024 << (extid
& 0x03);
3071 mtd
->oobsize
= (8 << (extid
& 0x01)) *
3072 (mtd
->writesize
>> 9);
3074 /* Calc blocksize. Blocksize is multiples of 64KiB */
3075 mtd
->erasesize
= (64 * 1024) << (extid
& 0x03);
3077 /* Get buswidth information */
3078 *busw
= (extid
& 0x01) ? NAND_BUSWIDTH_16
: 0;
3083 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3084 * decodes a matching ID table entry and assigns the MTD size parameters for
3087 static void nand_decode_id(struct mtd_info
*mtd
, struct nand_chip
*chip
,
3088 struct nand_flash_dev
*type
, u8 id_data
[8],
3091 int maf_id
= id_data
[0];
3093 mtd
->erasesize
= type
->erasesize
;
3094 mtd
->writesize
= type
->pagesize
;
3095 mtd
->oobsize
= mtd
->writesize
/ 32;
3096 *busw
= type
->options
& NAND_BUSWIDTH_16
;
3099 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3100 * some Spansion chips have erasesize that conflicts with size
3101 * listed in nand_ids table.
3102 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3104 if (maf_id
== NAND_MFR_AMD
&& id_data
[4] != 0x00 && id_data
[5] == 0x00
3105 && id_data
[6] == 0x00 && id_data
[7] == 0x00
3106 && mtd
->writesize
== 512) {
3107 mtd
->erasesize
= 128 * 1024;
3108 mtd
->erasesize
<<= ((id_data
[3] & 0x03) << 1);
3113 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3114 * heuristic patterns using various detected parameters (e.g., manufacturer,
3115 * page size, cell-type information).
3117 static void nand_decode_bbm_options(struct mtd_info
*mtd
,
3118 struct nand_chip
*chip
, u8 id_data
[8])
3120 int maf_id
= id_data
[0];
3122 /* Set the bad block position */
3123 if (mtd
->writesize
> 512 || (chip
->options
& NAND_BUSWIDTH_16
))
3124 chip
->badblockpos
= NAND_LARGE_BADBLOCK_POS
;
3126 chip
->badblockpos
= NAND_SMALL_BADBLOCK_POS
;
3129 * Bad block marker is stored in the last page of each block on Samsung
3130 * and Hynix MLC devices; stored in first two pages of each block on
3131 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3132 * AMD/Spansion, and Macronix. All others scan only the first page.
3134 if ((chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3135 (maf_id
== NAND_MFR_SAMSUNG
||
3136 maf_id
== NAND_MFR_HYNIX
))
3137 chip
->bbt_options
|= NAND_BBT_SCANLASTPAGE
;
3138 else if ((!(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
) &&
3139 (maf_id
== NAND_MFR_SAMSUNG
||
3140 maf_id
== NAND_MFR_HYNIX
||
3141 maf_id
== NAND_MFR_TOSHIBA
||
3142 maf_id
== NAND_MFR_AMD
||
3143 maf_id
== NAND_MFR_MACRONIX
)) ||
3144 (mtd
->writesize
== 2048 &&
3145 maf_id
== NAND_MFR_MICRON
))
3146 chip
->bbt_options
|= NAND_BBT_SCAN2NDPAGE
;
3150 * Get the flash and manufacturer id and lookup if the type is supported.
3152 static struct nand_flash_dev
*nand_get_flash_type(struct mtd_info
*mtd
,
3153 struct nand_chip
*chip
,
3155 int *maf_id
, int *dev_id
,
3156 struct nand_flash_dev
*type
)
3161 /* Select the device */
3162 chip
->select_chip(mtd
, 0);
3165 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3168 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3170 /* Send the command for reading device ID */
3171 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3173 /* Read manufacturer and device IDs */
3174 *maf_id
= chip
->read_byte(mtd
);
3175 *dev_id
= chip
->read_byte(mtd
);
3178 * Try again to make sure, as some systems the bus-hold or other
3179 * interface concerns can cause random data which looks like a
3180 * possibly credible NAND flash to appear. If the two results do
3181 * not match, ignore the device completely.
3184 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3186 /* Read entire ID string */
3187 for (i
= 0; i
< 8; i
++)
3188 id_data
[i
] = chip
->read_byte(mtd
);
3190 if (id_data
[0] != *maf_id
|| id_data
[1] != *dev_id
) {
3191 pr_info("%s: second ID read did not match "
3192 "%02x,%02x against %02x,%02x\n", __func__
,
3193 *maf_id
, *dev_id
, id_data
[0], id_data
[1]);
3194 return ERR_PTR(-ENODEV
);
3198 type
= nand_flash_ids
;
3200 for (; type
->name
!= NULL
; type
++)
3201 if (*dev_id
== type
->id
)
3204 chip
->onfi_version
= 0;
3205 if (!type
->name
|| !type
->pagesize
) {
3206 /* Check is chip is ONFI compliant */
3207 if (nand_flash_detect_onfi(mtd
, chip
, &busw
))
3212 return ERR_PTR(-ENODEV
);
3215 mtd
->name
= type
->name
;
3217 chip
->chipsize
= (uint64_t)type
->chipsize
<< 20;
3219 if (!type
->pagesize
&& chip
->init_size
) {
3220 /* Set the pagesize, oobsize, erasesize by the driver */
3221 busw
= chip
->init_size(mtd
, chip
, id_data
);
3222 } else if (!type
->pagesize
) {
3223 /* Decode parameters from extended ID */
3224 nand_decode_ext_id(mtd
, chip
, id_data
, &busw
);
3226 nand_decode_id(mtd
, chip
, type
, id_data
, &busw
);
3228 /* Get chip options */
3229 chip
->options
|= type
->options
;
3232 * Check if chip is not a Samsung device. Do not clear the
3233 * options for chips which do not have an extended id.
3235 if (*maf_id
!= NAND_MFR_SAMSUNG
&& !type
->pagesize
)
3236 chip
->options
&= ~NAND_SAMSUNG_LP_OPTIONS
;
3239 /* Try to identify manufacturer */
3240 for (maf_idx
= 0; nand_manuf_ids
[maf_idx
].id
!= 0x0; maf_idx
++) {
3241 if (nand_manuf_ids
[maf_idx
].id
== *maf_id
)
3246 * Check, if buswidth is correct. Hardware drivers should set
3249 if (busw
!= (chip
->options
& NAND_BUSWIDTH_16
)) {
3250 pr_info("NAND device: Manufacturer ID:"
3251 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id
,
3252 *dev_id
, nand_manuf_ids
[maf_idx
].name
, mtd
->name
);
3253 pr_warn("NAND bus width %d instead %d bit\n",
3254 (chip
->options
& NAND_BUSWIDTH_16
) ? 16 : 8,
3256 return ERR_PTR(-EINVAL
);
3259 nand_decode_bbm_options(mtd
, chip
, id_data
);
3261 /* Calculate the address shift from the page size */
3262 chip
->page_shift
= ffs(mtd
->writesize
) - 1;
3263 /* Convert chipsize to number of pages per chip -1 */
3264 chip
->pagemask
= (chip
->chipsize
>> chip
->page_shift
) - 1;
3266 chip
->bbt_erase_shift
= chip
->phys_erase_shift
=
3267 ffs(mtd
->erasesize
) - 1;
3268 if (chip
->chipsize
& 0xffffffff)
3269 chip
->chip_shift
= ffs((unsigned)chip
->chipsize
) - 1;
3271 chip
->chip_shift
= ffs((unsigned)(chip
->chipsize
>> 32));
3272 chip
->chip_shift
+= 32 - 1;
3275 chip
->badblockbits
= 8;
3277 /* Check for AND chips with 4 page planes */
3278 if (chip
->options
& NAND_4PAGE_ARRAY
)
3279 chip
->erase_cmd
= multi_erase_cmd
;
3281 chip
->erase_cmd
= single_erase_cmd
;
3283 /* Do not replace user supplied command function! */
3284 if (mtd
->writesize
> 512 && chip
->cmdfunc
== nand_command
)
3285 chip
->cmdfunc
= nand_command_lp
;
3287 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3288 " page size: %d, OOB size: %d\n",
3289 *maf_id
, *dev_id
, nand_manuf_ids
[maf_idx
].name
,
3290 chip
->onfi_version
? chip
->onfi_params
.model
: type
->name
,
3291 mtd
->writesize
, mtd
->oobsize
);
3297 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3298 * @mtd: MTD device structure
3299 * @maxchips: number of chips to scan for
3300 * @table: alternative NAND ID table
3302 * This is the first phase of the normal nand_scan() function. It reads the
3303 * flash ID and sets up MTD fields accordingly.
3305 * The mtd->owner field must be set to the module of the caller.
3307 int nand_scan_ident(struct mtd_info
*mtd
, int maxchips
,
3308 struct nand_flash_dev
*table
)
3310 int i
, busw
, nand_maf_id
, nand_dev_id
;
3311 struct nand_chip
*chip
= mtd
->priv
;
3312 struct nand_flash_dev
*type
;
3314 /* Get buswidth to select the correct functions */
3315 busw
= chip
->options
& NAND_BUSWIDTH_16
;
3316 /* Set the default functions */
3317 nand_set_defaults(chip
, busw
);
3319 /* Read the flash type */
3320 type
= nand_get_flash_type(mtd
, chip
, busw
,
3321 &nand_maf_id
, &nand_dev_id
, table
);
3324 if (!(chip
->options
& NAND_SCAN_SILENT_NODEV
))
3325 pr_warn("No NAND device found\n");
3326 chip
->select_chip(mtd
, -1);
3327 return PTR_ERR(type
);
3330 /* Check for a chip array */
3331 for (i
= 1; i
< maxchips
; i
++) {
3332 chip
->select_chip(mtd
, i
);
3333 /* See comment in nand_get_flash_type for reset */
3334 chip
->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
3335 /* Send the command for reading device ID */
3336 chip
->cmdfunc(mtd
, NAND_CMD_READID
, 0x00, -1);
3337 /* Read manufacturer and device IDs */
3338 if (nand_maf_id
!= chip
->read_byte(mtd
) ||
3339 nand_dev_id
!= chip
->read_byte(mtd
))
3343 pr_info("%d NAND chips detected\n", i
);
3345 /* Store the number of chips and calc total size for mtd */
3347 mtd
->size
= i
* chip
->chipsize
;
3351 EXPORT_SYMBOL(nand_scan_ident
);
3355 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3356 * @mtd: MTD device structure
3358 * This is the second phase of the normal nand_scan() function. It fills out
3359 * all the uninitialized function pointers with the defaults and scans for a
3360 * bad block table if appropriate.
3362 int nand_scan_tail(struct mtd_info
*mtd
)
3365 struct nand_chip
*chip
= mtd
->priv
;
3367 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3368 BUG_ON((chip
->bbt_options
& NAND_BBT_NO_OOB_BBM
) &&
3369 !(chip
->bbt_options
& NAND_BBT_USE_FLASH
));
3371 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3372 chip
->buffers
= kmalloc(sizeof(*chip
->buffers
), GFP_KERNEL
);
3376 /* Set the internal oob buffer location, just after the page data */
3377 chip
->oob_poi
= chip
->buffers
->databuf
+ mtd
->writesize
;
3380 * If no default placement scheme is given, select an appropriate one.
3382 if (!chip
->ecc
.layout
&& (chip
->ecc
.mode
!= NAND_ECC_SOFT_BCH
)) {
3383 switch (mtd
->oobsize
) {
3385 chip
->ecc
.layout
= &nand_oob_8
;
3388 chip
->ecc
.layout
= &nand_oob_16
;
3391 chip
->ecc
.layout
= &nand_oob_64
;
3394 chip
->ecc
.layout
= &nand_oob_128
;
3397 pr_warn("No oob scheme defined for oobsize %d\n",
3403 if (!chip
->write_page
)
3404 chip
->write_page
= nand_write_page
;
3406 /* set for ONFI nand */
3407 if (!chip
->onfi_set_features
)
3408 chip
->onfi_set_features
= nand_onfi_set_features
;
3409 if (!chip
->onfi_get_features
)
3410 chip
->onfi_get_features
= nand_onfi_get_features
;
3413 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3414 * selected and we have 256 byte pagesize fallback to software ECC
3417 switch (chip
->ecc
.mode
) {
3418 case NAND_ECC_HW_OOB_FIRST
:
3419 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3420 if (!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3422 pr_warn("No ECC functions supplied; "
3423 "hardware ECC not possible\n");
3426 if (!chip
->ecc
.read_page
)
3427 chip
->ecc
.read_page
= nand_read_page_hwecc_oob_first
;
3430 /* Use standard hwecc read page function? */
3431 if (!chip
->ecc
.read_page
)
3432 chip
->ecc
.read_page
= nand_read_page_hwecc
;
3433 if (!chip
->ecc
.write_page
)
3434 chip
->ecc
.write_page
= nand_write_page_hwecc
;
3435 if (!chip
->ecc
.read_page_raw
)
3436 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3437 if (!chip
->ecc
.write_page_raw
)
3438 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3439 if (!chip
->ecc
.read_oob
)
3440 chip
->ecc
.read_oob
= nand_read_oob_std
;
3441 if (!chip
->ecc
.write_oob
)
3442 chip
->ecc
.write_oob
= nand_write_oob_std
;
3444 case NAND_ECC_HW_SYNDROME
:
3445 if ((!chip
->ecc
.calculate
|| !chip
->ecc
.correct
||
3446 !chip
->ecc
.hwctl
) &&
3447 (!chip
->ecc
.read_page
||
3448 chip
->ecc
.read_page
== nand_read_page_hwecc
||
3449 !chip
->ecc
.write_page
||
3450 chip
->ecc
.write_page
== nand_write_page_hwecc
)) {
3451 pr_warn("No ECC functions supplied; "
3452 "hardware ECC not possible\n");
3455 /* Use standard syndrome read/write page function? */
3456 if (!chip
->ecc
.read_page
)
3457 chip
->ecc
.read_page
= nand_read_page_syndrome
;
3458 if (!chip
->ecc
.write_page
)
3459 chip
->ecc
.write_page
= nand_write_page_syndrome
;
3460 if (!chip
->ecc
.read_page_raw
)
3461 chip
->ecc
.read_page_raw
= nand_read_page_raw_syndrome
;
3462 if (!chip
->ecc
.write_page_raw
)
3463 chip
->ecc
.write_page_raw
= nand_write_page_raw_syndrome
;
3464 if (!chip
->ecc
.read_oob
)
3465 chip
->ecc
.read_oob
= nand_read_oob_syndrome
;
3466 if (!chip
->ecc
.write_oob
)
3467 chip
->ecc
.write_oob
= nand_write_oob_syndrome
;
3469 if (mtd
->writesize
>= chip
->ecc
.size
) {
3470 if (!chip
->ecc
.strength
) {
3471 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3476 pr_warn("%d byte HW ECC not possible on "
3477 "%d byte page size, fallback to SW ECC\n",
3478 chip
->ecc
.size
, mtd
->writesize
);
3479 chip
->ecc
.mode
= NAND_ECC_SOFT
;
3482 chip
->ecc
.calculate
= nand_calculate_ecc
;
3483 chip
->ecc
.correct
= nand_correct_data
;
3484 chip
->ecc
.read_page
= nand_read_page_swecc
;
3485 chip
->ecc
.read_subpage
= nand_read_subpage
;
3486 chip
->ecc
.write_page
= nand_write_page_swecc
;
3487 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3488 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3489 chip
->ecc
.read_oob
= nand_read_oob_std
;
3490 chip
->ecc
.write_oob
= nand_write_oob_std
;
3491 if (!chip
->ecc
.size
)
3492 chip
->ecc
.size
= 256;
3493 chip
->ecc
.bytes
= 3;
3494 chip
->ecc
.strength
= 1;
3497 case NAND_ECC_SOFT_BCH
:
3498 if (!mtd_nand_has_bch()) {
3499 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3502 chip
->ecc
.calculate
= nand_bch_calculate_ecc
;
3503 chip
->ecc
.correct
= nand_bch_correct_data
;
3504 chip
->ecc
.read_page
= nand_read_page_swecc
;
3505 chip
->ecc
.read_subpage
= nand_read_subpage
;
3506 chip
->ecc
.write_page
= nand_write_page_swecc
;
3507 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3508 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3509 chip
->ecc
.read_oob
= nand_read_oob_std
;
3510 chip
->ecc
.write_oob
= nand_write_oob_std
;
3512 * Board driver should supply ecc.size and ecc.bytes values to
3513 * select how many bits are correctable; see nand_bch_init()
3514 * for details. Otherwise, default to 4 bits for large page
3517 if (!chip
->ecc
.size
&& (mtd
->oobsize
>= 64)) {
3518 chip
->ecc
.size
= 512;
3519 chip
->ecc
.bytes
= 7;
3521 chip
->ecc
.priv
= nand_bch_init(mtd
,
3525 if (!chip
->ecc
.priv
) {
3526 pr_warn("BCH ECC initialization failed!\n");
3529 chip
->ecc
.strength
=
3530 chip
->ecc
.bytes
* 8 / fls(8 * chip
->ecc
.size
);
3534 pr_warn("NAND_ECC_NONE selected by board driver. "
3535 "This is not recommended!\n");
3536 chip
->ecc
.read_page
= nand_read_page_raw
;
3537 chip
->ecc
.write_page
= nand_write_page_raw
;
3538 chip
->ecc
.read_oob
= nand_read_oob_std
;
3539 chip
->ecc
.read_page_raw
= nand_read_page_raw
;
3540 chip
->ecc
.write_page_raw
= nand_write_page_raw
;
3541 chip
->ecc
.write_oob
= nand_write_oob_std
;
3542 chip
->ecc
.size
= mtd
->writesize
;
3543 chip
->ecc
.bytes
= 0;
3544 chip
->ecc
.strength
= 0;
3548 pr_warn("Invalid NAND_ECC_MODE %d\n", chip
->ecc
.mode
);
3552 /* For many systems, the standard OOB write also works for raw */
3553 if (!chip
->ecc
.read_oob_raw
)
3554 chip
->ecc
.read_oob_raw
= chip
->ecc
.read_oob
;
3555 if (!chip
->ecc
.write_oob_raw
)
3556 chip
->ecc
.write_oob_raw
= chip
->ecc
.write_oob
;
3559 * The number of bytes available for a client to place data into
3560 * the out of band area.
3562 chip
->ecc
.layout
->oobavail
= 0;
3563 for (i
= 0; chip
->ecc
.layout
->oobfree
[i
].length
3564 && i
< ARRAY_SIZE(chip
->ecc
.layout
->oobfree
); i
++)
3565 chip
->ecc
.layout
->oobavail
+=
3566 chip
->ecc
.layout
->oobfree
[i
].length
;
3567 mtd
->oobavail
= chip
->ecc
.layout
->oobavail
;
3570 * Set the number of read / write steps for one page depending on ECC
3573 chip
->ecc
.steps
= mtd
->writesize
/ chip
->ecc
.size
;
3574 if (chip
->ecc
.steps
* chip
->ecc
.size
!= mtd
->writesize
) {
3575 pr_warn("Invalid ECC parameters\n");
3578 chip
->ecc
.total
= chip
->ecc
.steps
* chip
->ecc
.bytes
;
3580 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3581 if (!(chip
->options
& NAND_NO_SUBPAGE_WRITE
) &&
3582 !(chip
->cellinfo
& NAND_CI_CELLTYPE_MSK
)) {
3583 switch (chip
->ecc
.steps
) {
3585 mtd
->subpage_sft
= 1;
3590 mtd
->subpage_sft
= 2;
3594 chip
->subpagesize
= mtd
->writesize
>> mtd
->subpage_sft
;
3596 /* Initialize state */
3597 chip
->state
= FL_READY
;
3599 /* De-select the device */
3600 chip
->select_chip(mtd
, -1);
3602 /* Invalidate the pagebuffer reference */
3605 /* Large page NAND with SOFT_ECC should support subpage reads */
3606 if ((chip
->ecc
.mode
== NAND_ECC_SOFT
) && (chip
->page_shift
> 9))
3607 chip
->options
|= NAND_SUBPAGE_READ
;
3609 /* Fill in remaining MTD driver data */
3610 mtd
->type
= MTD_NANDFLASH
;
3611 mtd
->flags
= (chip
->options
& NAND_ROM
) ? MTD_CAP_ROM
:
3613 mtd
->_erase
= nand_erase
;
3615 mtd
->_unpoint
= NULL
;
3616 mtd
->_read
= nand_read
;
3617 mtd
->_write
= nand_write
;
3618 mtd
->_panic_write
= panic_nand_write
;
3619 mtd
->_read_oob
= nand_read_oob
;
3620 mtd
->_write_oob
= nand_write_oob
;
3621 mtd
->_sync
= nand_sync
;
3623 mtd
->_unlock
= NULL
;
3624 mtd
->_suspend
= nand_suspend
;
3625 mtd
->_resume
= nand_resume
;
3626 mtd
->_block_isbad
= nand_block_isbad
;
3627 mtd
->_block_markbad
= nand_block_markbad
;
3628 mtd
->writebufsize
= mtd
->writesize
;
3630 /* propagate ecc info to mtd_info */
3631 mtd
->ecclayout
= chip
->ecc
.layout
;
3632 mtd
->ecc_strength
= chip
->ecc
.strength
;
3634 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3635 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3638 if (!mtd
->bitflip_threshold
)
3639 mtd
->bitflip_threshold
= mtd
->ecc_strength
;
3641 /* Check, if we should skip the bad block table scan */
3642 if (chip
->options
& NAND_SKIP_BBTSCAN
)
3645 /* Build bad block table */
3646 return chip
->scan_bbt(mtd
);
3648 EXPORT_SYMBOL(nand_scan_tail
);
3651 * is_module_text_address() isn't exported, and it's mostly a pointless
3652 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3653 * to call us from in-kernel code if the core NAND support is modular.
3656 #define caller_is_module() (1)
3658 #define caller_is_module() \
3659 is_module_text_address((unsigned long)__builtin_return_address(0))
3663 * nand_scan - [NAND Interface] Scan for the NAND device
3664 * @mtd: MTD device structure
3665 * @maxchips: number of chips to scan for
3667 * This fills out all the uninitialized function pointers with the defaults.
3668 * The flash ID is read and the mtd/chip structures are filled with the
3669 * appropriate values. The mtd->owner field must be set to the module of the
3672 int nand_scan(struct mtd_info
*mtd
, int maxchips
)
3676 /* Many callers got this wrong, so check for it for a while... */
3677 if (!mtd
->owner
&& caller_is_module()) {
3678 pr_crit("%s called with NULL mtd->owner!\n", __func__
);
3682 ret
= nand_scan_ident(mtd
, maxchips
, NULL
);
3684 ret
= nand_scan_tail(mtd
);
3687 EXPORT_SYMBOL(nand_scan
);
3690 * nand_release - [NAND Interface] Free resources held by the NAND device
3691 * @mtd: MTD device structure
3693 void nand_release(struct mtd_info
*mtd
)
3695 struct nand_chip
*chip
= mtd
->priv
;
3697 if (chip
->ecc
.mode
== NAND_ECC_SOFT_BCH
)
3698 nand_bch_free((struct nand_bch_control
*)chip
->ecc
.priv
);
3700 mtd_device_unregister(mtd
);
3702 /* Free bad block table memory */
3704 if (!(chip
->options
& NAND_OWN_BUFFERS
))
3705 kfree(chip
->buffers
);
3707 /* Free bad block descriptor memory */
3708 if (chip
->badblock_pattern
&& chip
->badblock_pattern
->options
3709 & NAND_BBT_DYNAMICSTRUCT
)
3710 kfree(chip
->badblock_pattern
);
3712 EXPORT_SYMBOL_GPL(nand_release
);
3714 static int __init
nand_base_init(void)
3716 led_trigger_register_simple("nand-disk", &nand_led_trigger
);
3720 static void __exit
nand_base_exit(void)
3722 led_trigger_unregister_simple(nand_led_trigger
);
3725 module_init(nand_base_init
);
3726 module_exit(nand_base_exit
);
3728 MODULE_LICENSE("GPL");
3729 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3730 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3731 MODULE_DESCRIPTION("Generic NAND flash driver code");