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Merge branches 'iommu/fixes', 'dma-debug', 'x86/amd', 'x86/vt-d', 'arm/tegra' and...
[deliverable/linux.git] / drivers / mtd / nand / nandsim.c
1 /*
2 * NAND flash simulator.
3 *
4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 *
8 * Note: NS means "NAND Simulator".
9 * Note: Input means input TO flash chip, output means output FROM chip.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2, or (at your option) any later
14 * version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
19 * Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
24 */
25
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/vmalloc.h>
31 #include <linux/math64.h>
32 #include <linux/slab.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
35 #include <linux/mtd/mtd.h>
36 #include <linux/mtd/nand.h>
37 #include <linux/mtd/nand_bch.h>
38 #include <linux/mtd/partitions.h>
39 #include <linux/delay.h>
40 #include <linux/list.h>
41 #include <linux/random.h>
42 #include <linux/sched.h>
43 #include <linux/fs.h>
44 #include <linux/pagemap.h>
45
46 /* Default simulator parameters values */
47 #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
48 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
49 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
50 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
51 #define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
52 #define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
53 #define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
54 #define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
55 #endif
56
57 #ifndef CONFIG_NANDSIM_ACCESS_DELAY
58 #define CONFIG_NANDSIM_ACCESS_DELAY 25
59 #endif
60 #ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
61 #define CONFIG_NANDSIM_PROGRAMM_DELAY 200
62 #endif
63 #ifndef CONFIG_NANDSIM_ERASE_DELAY
64 #define CONFIG_NANDSIM_ERASE_DELAY 2
65 #endif
66 #ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
67 #define CONFIG_NANDSIM_OUTPUT_CYCLE 40
68 #endif
69 #ifndef CONFIG_NANDSIM_INPUT_CYCLE
70 #define CONFIG_NANDSIM_INPUT_CYCLE 50
71 #endif
72 #ifndef CONFIG_NANDSIM_BUS_WIDTH
73 #define CONFIG_NANDSIM_BUS_WIDTH 8
74 #endif
75 #ifndef CONFIG_NANDSIM_DO_DELAYS
76 #define CONFIG_NANDSIM_DO_DELAYS 0
77 #endif
78 #ifndef CONFIG_NANDSIM_LOG
79 #define CONFIG_NANDSIM_LOG 0
80 #endif
81 #ifndef CONFIG_NANDSIM_DBG
82 #define CONFIG_NANDSIM_DBG 0
83 #endif
84 #ifndef CONFIG_NANDSIM_MAX_PARTS
85 #define CONFIG_NANDSIM_MAX_PARTS 32
86 #endif
87
88 static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
89 static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
90 static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
91 static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
92 static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
93 static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
94 static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
95 static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
96 static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
97 static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
98 static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
99 static uint log = CONFIG_NANDSIM_LOG;
100 static uint dbg = CONFIG_NANDSIM_DBG;
101 static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS];
102 static unsigned int parts_num;
103 static char *badblocks = NULL;
104 static char *weakblocks = NULL;
105 static char *weakpages = NULL;
106 static unsigned int bitflips = 0;
107 static char *gravepages = NULL;
108 static unsigned int rptwear = 0;
109 static unsigned int overridesize = 0;
110 static char *cache_file = NULL;
111 static unsigned int bbt;
112 static unsigned int bch;
113
114 module_param(first_id_byte, uint, 0400);
115 module_param(second_id_byte, uint, 0400);
116 module_param(third_id_byte, uint, 0400);
117 module_param(fourth_id_byte, uint, 0400);
118 module_param(access_delay, uint, 0400);
119 module_param(programm_delay, uint, 0400);
120 module_param(erase_delay, uint, 0400);
121 module_param(output_cycle, uint, 0400);
122 module_param(input_cycle, uint, 0400);
123 module_param(bus_width, uint, 0400);
124 module_param(do_delays, uint, 0400);
125 module_param(log, uint, 0400);
126 module_param(dbg, uint, 0400);
127 module_param_array(parts, ulong, &parts_num, 0400);
128 module_param(badblocks, charp, 0400);
129 module_param(weakblocks, charp, 0400);
130 module_param(weakpages, charp, 0400);
131 module_param(bitflips, uint, 0400);
132 module_param(gravepages, charp, 0400);
133 module_param(rptwear, uint, 0400);
134 module_param(overridesize, uint, 0400);
135 module_param(cache_file, charp, 0400);
136 module_param(bbt, uint, 0400);
137 module_param(bch, uint, 0400);
138
139 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID)");
140 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
141 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command");
142 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command");
143 MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
144 MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
145 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
146 MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)");
147 MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)");
148 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
149 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
150 MODULE_PARM_DESC(log, "Perform logging if not zero");
151 MODULE_PARM_DESC(dbg, "Output debug information if not zero");
152 MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
153 /* Page and erase block positions for the following parameters are independent of any partitions */
154 MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
155 MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
156 " separated by commas e.g. 113:2 means eb 113"
157 " can be erased only twice before failing");
158 MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
159 " separated by commas e.g. 1401:2 means page 1401"
160 " can be written only twice before failing");
161 MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
162 MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
163 " separated by commas e.g. 1401:2 means page 1401"
164 " can be read only twice before failing");
165 MODULE_PARM_DESC(rptwear, "Number of erases between reporting wear, if not zero");
166 MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
167 "The size is specified in erase blocks and as the exponent of a power of two"
168 " e.g. 5 means a size of 32 erase blocks");
169 MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
170 MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
171 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
172 "be correctable in 512-byte blocks");
173
174 /* The largest possible page size */
175 #define NS_LARGEST_PAGE_SIZE 4096
176
177 /* The prefix for simulator output */
178 #define NS_OUTPUT_PREFIX "[nandsim]"
179
180 /* Simulator's output macros (logging, debugging, warning, error) */
181 #define NS_LOG(args...) \
182 do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0)
183 #define NS_DBG(args...) \
184 do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0)
185 #define NS_WARN(args...) \
186 do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warning: " args); } while(0)
187 #define NS_ERR(args...) \
188 do { printk(KERN_ERR NS_OUTPUT_PREFIX " error: " args); } while(0)
189 #define NS_INFO(args...) \
190 do { printk(KERN_INFO NS_OUTPUT_PREFIX " " args); } while(0)
191
192 /* Busy-wait delay macros (microseconds, milliseconds) */
193 #define NS_UDELAY(us) \
194 do { if (do_delays) udelay(us); } while(0)
195 #define NS_MDELAY(us) \
196 do { if (do_delays) mdelay(us); } while(0)
197
198 /* Is the nandsim structure initialized ? */
199 #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
200
201 /* Good operation completion status */
202 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
203
204 /* Operation failed completion status */
205 #define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
206
207 /* Calculate the page offset in flash RAM image by (row, column) address */
208 #define NS_RAW_OFFSET(ns) \
209 (((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column)
210
211 /* Calculate the OOB offset in flash RAM image by (row, column) address */
212 #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
213
214 /* After a command is input, the simulator goes to one of the following states */
215 #define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
216 #define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
217 #define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
218 #define STATE_CMD_PAGEPROG 0x00000004 /* start page program */
219 #define STATE_CMD_READOOB 0x00000005 /* read OOB area */
220 #define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
221 #define STATE_CMD_STATUS 0x00000007 /* read status */
222 #define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */
223 #define STATE_CMD_SEQIN 0x00000009 /* sequential data input */
224 #define STATE_CMD_READID 0x0000000A /* read ID */
225 #define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
226 #define STATE_CMD_RESET 0x0000000C /* reset */
227 #define STATE_CMD_RNDOUT 0x0000000D /* random output command */
228 #define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
229 #define STATE_CMD_MASK 0x0000000F /* command states mask */
230
231 /* After an address is input, the simulator goes to one of these states */
232 #define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
233 #define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
234 #define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
235 #define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
236 #define STATE_ADDR_MASK 0x00000070 /* address states mask */
237
238 /* During data input/output the simulator is in these states */
239 #define STATE_DATAIN 0x00000100 /* waiting for data input */
240 #define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
241
242 #define STATE_DATAOUT 0x00001000 /* waiting for page data output */
243 #define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
244 #define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
245 #define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */
246 #define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
247
248 /* Previous operation is done, ready to accept new requests */
249 #define STATE_READY 0x00000000
250
251 /* This state is used to mark that the next state isn't known yet */
252 #define STATE_UNKNOWN 0x10000000
253
254 /* Simulator's actions bit masks */
255 #define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
256 #define ACTION_PRGPAGE 0x00200000 /* program the internal buffer to flash */
257 #define ACTION_SECERASE 0x00300000 /* erase sector */
258 #define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
259 #define ACTION_HALFOFF 0x00500000 /* add to address half of page */
260 #define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
261 #define ACTION_MASK 0x00700000 /* action mask */
262
263 #define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
264 #define NS_OPER_STATES 6 /* Maximum number of states in operation */
265
266 #define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
267 #define OPT_PAGE256 0x00000001 /* 256-byte page chips */
268 #define OPT_PAGE512 0x00000002 /* 512-byte page chips */
269 #define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
270 #define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
271 #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
272 #define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
273 #define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
274 #define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */
275
276 /* Remove action bits from state */
277 #define NS_STATE(x) ((x) & ~ACTION_MASK)
278
279 /*
280 * Maximum previous states which need to be saved. Currently saving is
281 * only needed for page program operation with preceded read command
282 * (which is only valid for 512-byte pages).
283 */
284 #define NS_MAX_PREVSTATES 1
285
286 /* Maximum page cache pages needed to read or write a NAND page to the cache_file */
287 #define NS_MAX_HELD_PAGES 16
288
289 /*
290 * A union to represent flash memory contents and flash buffer.
291 */
292 union ns_mem {
293 u_char *byte; /* for byte access */
294 uint16_t *word; /* for 16-bit word access */
295 };
296
297 /*
298 * The structure which describes all the internal simulator data.
299 */
300 struct nandsim {
301 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS];
302 unsigned int nbparts;
303
304 uint busw; /* flash chip bus width (8 or 16) */
305 u_char ids[4]; /* chip's ID bytes */
306 uint32_t options; /* chip's characteristic bits */
307 uint32_t state; /* current chip state */
308 uint32_t nxstate; /* next expected state */
309
310 uint32_t *op; /* current operation, NULL operations isn't known yet */
311 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
312 uint16_t npstates; /* number of previous states saved */
313 uint16_t stateidx; /* current state index */
314
315 /* The simulated NAND flash pages array */
316 union ns_mem *pages;
317
318 /* Slab allocator for nand pages */
319 struct kmem_cache *nand_pages_slab;
320
321 /* Internal buffer of page + OOB size bytes */
322 union ns_mem buf;
323
324 /* NAND flash "geometry" */
325 struct {
326 uint64_t totsz; /* total flash size, bytes */
327 uint32_t secsz; /* flash sector (erase block) size, bytes */
328 uint pgsz; /* NAND flash page size, bytes */
329 uint oobsz; /* page OOB area size, bytes */
330 uint64_t totszoob; /* total flash size including OOB, bytes */
331 uint pgszoob; /* page size including OOB , bytes*/
332 uint secszoob; /* sector size including OOB, bytes */
333 uint pgnum; /* total number of pages */
334 uint pgsec; /* number of pages per sector */
335 uint secshift; /* bits number in sector size */
336 uint pgshift; /* bits number in page size */
337 uint oobshift; /* bits number in OOB size */
338 uint pgaddrbytes; /* bytes per page address */
339 uint secaddrbytes; /* bytes per sector address */
340 uint idbytes; /* the number ID bytes that this chip outputs */
341 } geom;
342
343 /* NAND flash internal registers */
344 struct {
345 unsigned command; /* the command register */
346 u_char status; /* the status register */
347 uint row; /* the page number */
348 uint column; /* the offset within page */
349 uint count; /* internal counter */
350 uint num; /* number of bytes which must be processed */
351 uint off; /* fixed page offset */
352 } regs;
353
354 /* NAND flash lines state */
355 struct {
356 int ce; /* chip Enable */
357 int cle; /* command Latch Enable */
358 int ale; /* address Latch Enable */
359 int wp; /* write Protect */
360 } lines;
361
362 /* Fields needed when using a cache file */
363 struct file *cfile; /* Open file */
364 unsigned char *pages_written; /* Which pages have been written */
365 void *file_buf;
366 struct page *held_pages[NS_MAX_HELD_PAGES];
367 int held_cnt;
368 };
369
370 /*
371 * Operations array. To perform any operation the simulator must pass
372 * through the correspondent states chain.
373 */
374 static struct nandsim_operations {
375 uint32_t reqopts; /* options which are required to perform the operation */
376 uint32_t states[NS_OPER_STATES]; /* operation's states */
377 } ops[NS_OPER_NUM] = {
378 /* Read page + OOB from the beginning */
379 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
380 STATE_DATAOUT, STATE_READY}},
381 /* Read page + OOB from the second half */
382 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
383 STATE_DATAOUT, STATE_READY}},
384 /* Read OOB */
385 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
386 STATE_DATAOUT, STATE_READY}},
387 /* Program page starting from the beginning */
388 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
389 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
390 /* Program page starting from the beginning */
391 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
392 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
393 /* Program page starting from the second half */
394 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
395 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
396 /* Program OOB */
397 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
398 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
399 /* Erase sector */
400 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
401 /* Read status */
402 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
403 /* Read multi-plane status */
404 {OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}},
405 /* Read ID */
406 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
407 /* Large page devices read page */
408 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
409 STATE_DATAOUT, STATE_READY}},
410 /* Large page devices random page read */
411 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
412 STATE_DATAOUT, STATE_READY}},
413 };
414
415 struct weak_block {
416 struct list_head list;
417 unsigned int erase_block_no;
418 unsigned int max_erases;
419 unsigned int erases_done;
420 };
421
422 static LIST_HEAD(weak_blocks);
423
424 struct weak_page {
425 struct list_head list;
426 unsigned int page_no;
427 unsigned int max_writes;
428 unsigned int writes_done;
429 };
430
431 static LIST_HEAD(weak_pages);
432
433 struct grave_page {
434 struct list_head list;
435 unsigned int page_no;
436 unsigned int max_reads;
437 unsigned int reads_done;
438 };
439
440 static LIST_HEAD(grave_pages);
441
442 static unsigned long *erase_block_wear = NULL;
443 static unsigned int wear_eb_count = 0;
444 static unsigned long total_wear = 0;
445 static unsigned int rptwear_cnt = 0;
446
447 /* MTD structure for NAND controller */
448 static struct mtd_info *nsmtd;
449
450 /*
451 * Allocate array of page pointers, create slab allocation for an array
452 * and initialize the array by NULL pointers.
453 *
454 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
455 */
456 static int alloc_device(struct nandsim *ns)
457 {
458 struct file *cfile;
459 int i, err;
460
461 if (cache_file) {
462 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
463 if (IS_ERR(cfile))
464 return PTR_ERR(cfile);
465 if (!cfile->f_op || (!cfile->f_op->read && !cfile->f_op->aio_read)) {
466 NS_ERR("alloc_device: cache file not readable\n");
467 err = -EINVAL;
468 goto err_close;
469 }
470 if (!cfile->f_op->write && !cfile->f_op->aio_write) {
471 NS_ERR("alloc_device: cache file not writeable\n");
472 err = -EINVAL;
473 goto err_close;
474 }
475 ns->pages_written = vzalloc(ns->geom.pgnum);
476 if (!ns->pages_written) {
477 NS_ERR("alloc_device: unable to allocate pages written array\n");
478 err = -ENOMEM;
479 goto err_close;
480 }
481 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
482 if (!ns->file_buf) {
483 NS_ERR("alloc_device: unable to allocate file buf\n");
484 err = -ENOMEM;
485 goto err_free;
486 }
487 ns->cfile = cfile;
488 return 0;
489 }
490
491 ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem));
492 if (!ns->pages) {
493 NS_ERR("alloc_device: unable to allocate page array\n");
494 return -ENOMEM;
495 }
496 for (i = 0; i < ns->geom.pgnum; i++) {
497 ns->pages[i].byte = NULL;
498 }
499 ns->nand_pages_slab = kmem_cache_create("nandsim",
500 ns->geom.pgszoob, 0, 0, NULL);
501 if (!ns->nand_pages_slab) {
502 NS_ERR("cache_create: unable to create kmem_cache\n");
503 return -ENOMEM;
504 }
505
506 return 0;
507
508 err_free:
509 vfree(ns->pages_written);
510 err_close:
511 filp_close(cfile, NULL);
512 return err;
513 }
514
515 /*
516 * Free any allocated pages, and free the array of page pointers.
517 */
518 static void free_device(struct nandsim *ns)
519 {
520 int i;
521
522 if (ns->cfile) {
523 kfree(ns->file_buf);
524 vfree(ns->pages_written);
525 filp_close(ns->cfile, NULL);
526 return;
527 }
528
529 if (ns->pages) {
530 for (i = 0; i < ns->geom.pgnum; i++) {
531 if (ns->pages[i].byte)
532 kmem_cache_free(ns->nand_pages_slab,
533 ns->pages[i].byte);
534 }
535 kmem_cache_destroy(ns->nand_pages_slab);
536 vfree(ns->pages);
537 }
538 }
539
540 static char *get_partition_name(int i)
541 {
542 char buf[64];
543 sprintf(buf, "NAND simulator partition %d", i);
544 return kstrdup(buf, GFP_KERNEL);
545 }
546
547 /*
548 * Initialize the nandsim structure.
549 *
550 * RETURNS: 0 if success, -ERRNO if failure.
551 */
552 static int init_nandsim(struct mtd_info *mtd)
553 {
554 struct nand_chip *chip = mtd->priv;
555 struct nandsim *ns = chip->priv;
556 int i, ret = 0;
557 uint64_t remains;
558 uint64_t next_offset;
559
560 if (NS_IS_INITIALIZED(ns)) {
561 NS_ERR("init_nandsim: nandsim is already initialized\n");
562 return -EIO;
563 }
564
565 /* Force mtd to not do delays */
566 chip->chip_delay = 0;
567
568 /* Initialize the NAND flash parameters */
569 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
570 ns->geom.totsz = mtd->size;
571 ns->geom.pgsz = mtd->writesize;
572 ns->geom.oobsz = mtd->oobsize;
573 ns->geom.secsz = mtd->erasesize;
574 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
575 ns->geom.pgnum = div_u64(ns->geom.totsz, ns->geom.pgsz);
576 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
577 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
578 ns->geom.pgshift = chip->page_shift;
579 ns->geom.oobshift = ffs(ns->geom.oobsz) - 1;
580 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
581 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
582 ns->options = 0;
583
584 if (ns->geom.pgsz == 256) {
585 ns->options |= OPT_PAGE256;
586 }
587 else if (ns->geom.pgsz == 512) {
588 ns->options |= OPT_PAGE512;
589 if (ns->busw == 8)
590 ns->options |= OPT_PAGE512_8BIT;
591 } else if (ns->geom.pgsz == 2048) {
592 ns->options |= OPT_PAGE2048;
593 } else if (ns->geom.pgsz == 4096) {
594 ns->options |= OPT_PAGE4096;
595 } else {
596 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
597 return -EIO;
598 }
599
600 if (ns->options & OPT_SMALLPAGE) {
601 if (ns->geom.totsz <= (32 << 20)) {
602 ns->geom.pgaddrbytes = 3;
603 ns->geom.secaddrbytes = 2;
604 } else {
605 ns->geom.pgaddrbytes = 4;
606 ns->geom.secaddrbytes = 3;
607 }
608 } else {
609 if (ns->geom.totsz <= (128 << 20)) {
610 ns->geom.pgaddrbytes = 4;
611 ns->geom.secaddrbytes = 2;
612 } else {
613 ns->geom.pgaddrbytes = 5;
614 ns->geom.secaddrbytes = 3;
615 }
616 }
617
618 /* Fill the partition_info structure */
619 if (parts_num > ARRAY_SIZE(ns->partitions)) {
620 NS_ERR("too many partitions.\n");
621 ret = -EINVAL;
622 goto error;
623 }
624 remains = ns->geom.totsz;
625 next_offset = 0;
626 for (i = 0; i < parts_num; ++i) {
627 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
628
629 if (!part_sz || part_sz > remains) {
630 NS_ERR("bad partition size.\n");
631 ret = -EINVAL;
632 goto error;
633 }
634 ns->partitions[i].name = get_partition_name(i);
635 ns->partitions[i].offset = next_offset;
636 ns->partitions[i].size = part_sz;
637 next_offset += ns->partitions[i].size;
638 remains -= ns->partitions[i].size;
639 }
640 ns->nbparts = parts_num;
641 if (remains) {
642 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
643 NS_ERR("too many partitions.\n");
644 ret = -EINVAL;
645 goto error;
646 }
647 ns->partitions[i].name = get_partition_name(i);
648 ns->partitions[i].offset = next_offset;
649 ns->partitions[i].size = remains;
650 ns->nbparts += 1;
651 }
652
653 /* Detect how many ID bytes the NAND chip outputs */
654 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
655 if (second_id_byte != nand_flash_ids[i].id)
656 continue;
657 }
658
659 if (ns->busw == 16)
660 NS_WARN("16-bit flashes support wasn't tested\n");
661
662 printk("flash size: %llu MiB\n",
663 (unsigned long long)ns->geom.totsz >> 20);
664 printk("page size: %u bytes\n", ns->geom.pgsz);
665 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
666 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
667 printk("pages number: %u\n", ns->geom.pgnum);
668 printk("pages per sector: %u\n", ns->geom.pgsec);
669 printk("bus width: %u\n", ns->busw);
670 printk("bits in sector size: %u\n", ns->geom.secshift);
671 printk("bits in page size: %u\n", ns->geom.pgshift);
672 printk("bits in OOB size: %u\n", ns->geom.oobshift);
673 printk("flash size with OOB: %llu KiB\n",
674 (unsigned long long)ns->geom.totszoob >> 10);
675 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
676 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
677 printk("options: %#x\n", ns->options);
678
679 if ((ret = alloc_device(ns)) != 0)
680 goto error;
681
682 /* Allocate / initialize the internal buffer */
683 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
684 if (!ns->buf.byte) {
685 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
686 ns->geom.pgszoob);
687 ret = -ENOMEM;
688 goto error;
689 }
690 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
691
692 return 0;
693
694 error:
695 free_device(ns);
696
697 return ret;
698 }
699
700 /*
701 * Free the nandsim structure.
702 */
703 static void free_nandsim(struct nandsim *ns)
704 {
705 kfree(ns->buf.byte);
706 free_device(ns);
707
708 return;
709 }
710
711 static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
712 {
713 char *w;
714 int zero_ok;
715 unsigned int erase_block_no;
716 loff_t offset;
717
718 if (!badblocks)
719 return 0;
720 w = badblocks;
721 do {
722 zero_ok = (*w == '0' ? 1 : 0);
723 erase_block_no = simple_strtoul(w, &w, 0);
724 if (!zero_ok && !erase_block_no) {
725 NS_ERR("invalid badblocks.\n");
726 return -EINVAL;
727 }
728 offset = erase_block_no * ns->geom.secsz;
729 if (mtd_block_markbad(mtd, offset)) {
730 NS_ERR("invalid badblocks.\n");
731 return -EINVAL;
732 }
733 if (*w == ',')
734 w += 1;
735 } while (*w);
736 return 0;
737 }
738
739 static int parse_weakblocks(void)
740 {
741 char *w;
742 int zero_ok;
743 unsigned int erase_block_no;
744 unsigned int max_erases;
745 struct weak_block *wb;
746
747 if (!weakblocks)
748 return 0;
749 w = weakblocks;
750 do {
751 zero_ok = (*w == '0' ? 1 : 0);
752 erase_block_no = simple_strtoul(w, &w, 0);
753 if (!zero_ok && !erase_block_no) {
754 NS_ERR("invalid weakblocks.\n");
755 return -EINVAL;
756 }
757 max_erases = 3;
758 if (*w == ':') {
759 w += 1;
760 max_erases = simple_strtoul(w, &w, 0);
761 }
762 if (*w == ',')
763 w += 1;
764 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
765 if (!wb) {
766 NS_ERR("unable to allocate memory.\n");
767 return -ENOMEM;
768 }
769 wb->erase_block_no = erase_block_no;
770 wb->max_erases = max_erases;
771 list_add(&wb->list, &weak_blocks);
772 } while (*w);
773 return 0;
774 }
775
776 static int erase_error(unsigned int erase_block_no)
777 {
778 struct weak_block *wb;
779
780 list_for_each_entry(wb, &weak_blocks, list)
781 if (wb->erase_block_no == erase_block_no) {
782 if (wb->erases_done >= wb->max_erases)
783 return 1;
784 wb->erases_done += 1;
785 return 0;
786 }
787 return 0;
788 }
789
790 static int parse_weakpages(void)
791 {
792 char *w;
793 int zero_ok;
794 unsigned int page_no;
795 unsigned int max_writes;
796 struct weak_page *wp;
797
798 if (!weakpages)
799 return 0;
800 w = weakpages;
801 do {
802 zero_ok = (*w == '0' ? 1 : 0);
803 page_no = simple_strtoul(w, &w, 0);
804 if (!zero_ok && !page_no) {
805 NS_ERR("invalid weakpagess.\n");
806 return -EINVAL;
807 }
808 max_writes = 3;
809 if (*w == ':') {
810 w += 1;
811 max_writes = simple_strtoul(w, &w, 0);
812 }
813 if (*w == ',')
814 w += 1;
815 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
816 if (!wp) {
817 NS_ERR("unable to allocate memory.\n");
818 return -ENOMEM;
819 }
820 wp->page_no = page_no;
821 wp->max_writes = max_writes;
822 list_add(&wp->list, &weak_pages);
823 } while (*w);
824 return 0;
825 }
826
827 static int write_error(unsigned int page_no)
828 {
829 struct weak_page *wp;
830
831 list_for_each_entry(wp, &weak_pages, list)
832 if (wp->page_no == page_no) {
833 if (wp->writes_done >= wp->max_writes)
834 return 1;
835 wp->writes_done += 1;
836 return 0;
837 }
838 return 0;
839 }
840
841 static int parse_gravepages(void)
842 {
843 char *g;
844 int zero_ok;
845 unsigned int page_no;
846 unsigned int max_reads;
847 struct grave_page *gp;
848
849 if (!gravepages)
850 return 0;
851 g = gravepages;
852 do {
853 zero_ok = (*g == '0' ? 1 : 0);
854 page_no = simple_strtoul(g, &g, 0);
855 if (!zero_ok && !page_no) {
856 NS_ERR("invalid gravepagess.\n");
857 return -EINVAL;
858 }
859 max_reads = 3;
860 if (*g == ':') {
861 g += 1;
862 max_reads = simple_strtoul(g, &g, 0);
863 }
864 if (*g == ',')
865 g += 1;
866 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
867 if (!gp) {
868 NS_ERR("unable to allocate memory.\n");
869 return -ENOMEM;
870 }
871 gp->page_no = page_no;
872 gp->max_reads = max_reads;
873 list_add(&gp->list, &grave_pages);
874 } while (*g);
875 return 0;
876 }
877
878 static int read_error(unsigned int page_no)
879 {
880 struct grave_page *gp;
881
882 list_for_each_entry(gp, &grave_pages, list)
883 if (gp->page_no == page_no) {
884 if (gp->reads_done >= gp->max_reads)
885 return 1;
886 gp->reads_done += 1;
887 return 0;
888 }
889 return 0;
890 }
891
892 static void free_lists(void)
893 {
894 struct list_head *pos, *n;
895 list_for_each_safe(pos, n, &weak_blocks) {
896 list_del(pos);
897 kfree(list_entry(pos, struct weak_block, list));
898 }
899 list_for_each_safe(pos, n, &weak_pages) {
900 list_del(pos);
901 kfree(list_entry(pos, struct weak_page, list));
902 }
903 list_for_each_safe(pos, n, &grave_pages) {
904 list_del(pos);
905 kfree(list_entry(pos, struct grave_page, list));
906 }
907 kfree(erase_block_wear);
908 }
909
910 static int setup_wear_reporting(struct mtd_info *mtd)
911 {
912 size_t mem;
913
914 if (!rptwear)
915 return 0;
916 wear_eb_count = div_u64(mtd->size, mtd->erasesize);
917 mem = wear_eb_count * sizeof(unsigned long);
918 if (mem / sizeof(unsigned long) != wear_eb_count) {
919 NS_ERR("Too many erase blocks for wear reporting\n");
920 return -ENOMEM;
921 }
922 erase_block_wear = kzalloc(mem, GFP_KERNEL);
923 if (!erase_block_wear) {
924 NS_ERR("Too many erase blocks for wear reporting\n");
925 return -ENOMEM;
926 }
927 return 0;
928 }
929
930 static void update_wear(unsigned int erase_block_no)
931 {
932 unsigned long wmin = -1, wmax = 0, avg;
933 unsigned long deciles[10], decile_max[10], tot = 0;
934 unsigned int i;
935
936 if (!erase_block_wear)
937 return;
938 total_wear += 1;
939 if (total_wear == 0)
940 NS_ERR("Erase counter total overflow\n");
941 erase_block_wear[erase_block_no] += 1;
942 if (erase_block_wear[erase_block_no] == 0)
943 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
944 rptwear_cnt += 1;
945 if (rptwear_cnt < rptwear)
946 return;
947 rptwear_cnt = 0;
948 /* Calc wear stats */
949 for (i = 0; i < wear_eb_count; ++i) {
950 unsigned long wear = erase_block_wear[i];
951 if (wear < wmin)
952 wmin = wear;
953 if (wear > wmax)
954 wmax = wear;
955 tot += wear;
956 }
957 for (i = 0; i < 9; ++i) {
958 deciles[i] = 0;
959 decile_max[i] = (wmax * (i + 1) + 5) / 10;
960 }
961 deciles[9] = 0;
962 decile_max[9] = wmax;
963 for (i = 0; i < wear_eb_count; ++i) {
964 int d;
965 unsigned long wear = erase_block_wear[i];
966 for (d = 0; d < 10; ++d)
967 if (wear <= decile_max[d]) {
968 deciles[d] += 1;
969 break;
970 }
971 }
972 avg = tot / wear_eb_count;
973 /* Output wear report */
974 NS_INFO("*** Wear Report ***\n");
975 NS_INFO("Total numbers of erases: %lu\n", tot);
976 NS_INFO("Number of erase blocks: %u\n", wear_eb_count);
977 NS_INFO("Average number of erases: %lu\n", avg);
978 NS_INFO("Maximum number of erases: %lu\n", wmax);
979 NS_INFO("Minimum number of erases: %lu\n", wmin);
980 for (i = 0; i < 10; ++i) {
981 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
982 if (from > decile_max[i])
983 continue;
984 NS_INFO("Number of ebs with erase counts from %lu to %lu : %lu\n",
985 from,
986 decile_max[i],
987 deciles[i]);
988 }
989 NS_INFO("*** End of Wear Report ***\n");
990 }
991
992 /*
993 * Returns the string representation of 'state' state.
994 */
995 static char *get_state_name(uint32_t state)
996 {
997 switch (NS_STATE(state)) {
998 case STATE_CMD_READ0:
999 return "STATE_CMD_READ0";
1000 case STATE_CMD_READ1:
1001 return "STATE_CMD_READ1";
1002 case STATE_CMD_PAGEPROG:
1003 return "STATE_CMD_PAGEPROG";
1004 case STATE_CMD_READOOB:
1005 return "STATE_CMD_READOOB";
1006 case STATE_CMD_READSTART:
1007 return "STATE_CMD_READSTART";
1008 case STATE_CMD_ERASE1:
1009 return "STATE_CMD_ERASE1";
1010 case STATE_CMD_STATUS:
1011 return "STATE_CMD_STATUS";
1012 case STATE_CMD_STATUS_M:
1013 return "STATE_CMD_STATUS_M";
1014 case STATE_CMD_SEQIN:
1015 return "STATE_CMD_SEQIN";
1016 case STATE_CMD_READID:
1017 return "STATE_CMD_READID";
1018 case STATE_CMD_ERASE2:
1019 return "STATE_CMD_ERASE2";
1020 case STATE_CMD_RESET:
1021 return "STATE_CMD_RESET";
1022 case STATE_CMD_RNDOUT:
1023 return "STATE_CMD_RNDOUT";
1024 case STATE_CMD_RNDOUTSTART:
1025 return "STATE_CMD_RNDOUTSTART";
1026 case STATE_ADDR_PAGE:
1027 return "STATE_ADDR_PAGE";
1028 case STATE_ADDR_SEC:
1029 return "STATE_ADDR_SEC";
1030 case STATE_ADDR_ZERO:
1031 return "STATE_ADDR_ZERO";
1032 case STATE_ADDR_COLUMN:
1033 return "STATE_ADDR_COLUMN";
1034 case STATE_DATAIN:
1035 return "STATE_DATAIN";
1036 case STATE_DATAOUT:
1037 return "STATE_DATAOUT";
1038 case STATE_DATAOUT_ID:
1039 return "STATE_DATAOUT_ID";
1040 case STATE_DATAOUT_STATUS:
1041 return "STATE_DATAOUT_STATUS";
1042 case STATE_DATAOUT_STATUS_M:
1043 return "STATE_DATAOUT_STATUS_M";
1044 case STATE_READY:
1045 return "STATE_READY";
1046 case STATE_UNKNOWN:
1047 return "STATE_UNKNOWN";
1048 }
1049
1050 NS_ERR("get_state_name: unknown state, BUG\n");
1051 return NULL;
1052 }
1053
1054 /*
1055 * Check if command is valid.
1056 *
1057 * RETURNS: 1 if wrong command, 0 if right.
1058 */
1059 static int check_command(int cmd)
1060 {
1061 switch (cmd) {
1062
1063 case NAND_CMD_READ0:
1064 case NAND_CMD_READ1:
1065 case NAND_CMD_READSTART:
1066 case NAND_CMD_PAGEPROG:
1067 case NAND_CMD_READOOB:
1068 case NAND_CMD_ERASE1:
1069 case NAND_CMD_STATUS:
1070 case NAND_CMD_SEQIN:
1071 case NAND_CMD_READID:
1072 case NAND_CMD_ERASE2:
1073 case NAND_CMD_RESET:
1074 case NAND_CMD_RNDOUT:
1075 case NAND_CMD_RNDOUTSTART:
1076 return 0;
1077
1078 case NAND_CMD_STATUS_MULTI:
1079 default:
1080 return 1;
1081 }
1082 }
1083
1084 /*
1085 * Returns state after command is accepted by command number.
1086 */
1087 static uint32_t get_state_by_command(unsigned command)
1088 {
1089 switch (command) {
1090 case NAND_CMD_READ0:
1091 return STATE_CMD_READ0;
1092 case NAND_CMD_READ1:
1093 return STATE_CMD_READ1;
1094 case NAND_CMD_PAGEPROG:
1095 return STATE_CMD_PAGEPROG;
1096 case NAND_CMD_READSTART:
1097 return STATE_CMD_READSTART;
1098 case NAND_CMD_READOOB:
1099 return STATE_CMD_READOOB;
1100 case NAND_CMD_ERASE1:
1101 return STATE_CMD_ERASE1;
1102 case NAND_CMD_STATUS:
1103 return STATE_CMD_STATUS;
1104 case NAND_CMD_STATUS_MULTI:
1105 return STATE_CMD_STATUS_M;
1106 case NAND_CMD_SEQIN:
1107 return STATE_CMD_SEQIN;
1108 case NAND_CMD_READID:
1109 return STATE_CMD_READID;
1110 case NAND_CMD_ERASE2:
1111 return STATE_CMD_ERASE2;
1112 case NAND_CMD_RESET:
1113 return STATE_CMD_RESET;
1114 case NAND_CMD_RNDOUT:
1115 return STATE_CMD_RNDOUT;
1116 case NAND_CMD_RNDOUTSTART:
1117 return STATE_CMD_RNDOUTSTART;
1118 }
1119
1120 NS_ERR("get_state_by_command: unknown command, BUG\n");
1121 return 0;
1122 }
1123
1124 /*
1125 * Move an address byte to the correspondent internal register.
1126 */
1127 static inline void accept_addr_byte(struct nandsim *ns, u_char bt)
1128 {
1129 uint byte = (uint)bt;
1130
1131 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1132 ns->regs.column |= (byte << 8 * ns->regs.count);
1133 else {
1134 ns->regs.row |= (byte << 8 * (ns->regs.count -
1135 ns->geom.pgaddrbytes +
1136 ns->geom.secaddrbytes));
1137 }
1138
1139 return;
1140 }
1141
1142 /*
1143 * Switch to STATE_READY state.
1144 */
1145 static inline void switch_to_ready_state(struct nandsim *ns, u_char status)
1146 {
1147 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
1148
1149 ns->state = STATE_READY;
1150 ns->nxstate = STATE_UNKNOWN;
1151 ns->op = NULL;
1152 ns->npstates = 0;
1153 ns->stateidx = 0;
1154 ns->regs.num = 0;
1155 ns->regs.count = 0;
1156 ns->regs.off = 0;
1157 ns->regs.row = 0;
1158 ns->regs.column = 0;
1159 ns->regs.status = status;
1160 }
1161
1162 /*
1163 * If the operation isn't known yet, try to find it in the global array
1164 * of supported operations.
1165 *
1166 * Operation can be unknown because of the following.
1167 * 1. New command was accepted and this is the first call to find the
1168 * correspondent states chain. In this case ns->npstates = 0;
1169 * 2. There are several operations which begin with the same command(s)
1170 * (for example program from the second half and read from the
1171 * second half operations both begin with the READ1 command). In this
1172 * case the ns->pstates[] array contains previous states.
1173 *
1174 * Thus, the function tries to find operation containing the following
1175 * states (if the 'flag' parameter is 0):
1176 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1177 *
1178 * If (one and only one) matching operation is found, it is accepted (
1179 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1180 * zeroed).
1181 *
1182 * If there are several matches, the current state is pushed to the
1183 * ns->pstates.
1184 *
1185 * The operation can be unknown only while commands are input to the chip.
1186 * As soon as address command is accepted, the operation must be known.
1187 * In such situation the function is called with 'flag' != 0, and the
1188 * operation is searched using the following pattern:
1189 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
1190 *
1191 * It is supposed that this pattern must either match one operation or
1192 * none. There can't be ambiguity in that case.
1193 *
1194 * If no matches found, the function does the following:
1195 * 1. if there are saved states present, try to ignore them and search
1196 * again only using the last command. If nothing was found, switch
1197 * to the STATE_READY state.
1198 * 2. if there are no saved states, switch to the STATE_READY state.
1199 *
1200 * RETURNS: -2 - no matched operations found.
1201 * -1 - several matches.
1202 * 0 - operation is found.
1203 */
1204 static int find_operation(struct nandsim *ns, uint32_t flag)
1205 {
1206 int opsfound = 0;
1207 int i, j, idx = 0;
1208
1209 for (i = 0; i < NS_OPER_NUM; i++) {
1210
1211 int found = 1;
1212
1213 if (!(ns->options & ops[i].reqopts))
1214 /* Ignore operations we can't perform */
1215 continue;
1216
1217 if (flag) {
1218 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1219 continue;
1220 } else {
1221 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1222 continue;
1223 }
1224
1225 for (j = 0; j < ns->npstates; j++)
1226 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1227 && (ns->options & ops[idx].reqopts)) {
1228 found = 0;
1229 break;
1230 }
1231
1232 if (found) {
1233 idx = i;
1234 opsfound += 1;
1235 }
1236 }
1237
1238 if (opsfound == 1) {
1239 /* Exact match */
1240 ns->op = &ops[idx].states[0];
1241 if (flag) {
1242 /*
1243 * In this case the find_operation function was
1244 * called when address has just began input. But it isn't
1245 * yet fully input and the current state must
1246 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1247 * state must be the next state (ns->nxstate).
1248 */
1249 ns->stateidx = ns->npstates - 1;
1250 } else {
1251 ns->stateidx = ns->npstates;
1252 }
1253 ns->npstates = 0;
1254 ns->state = ns->op[ns->stateidx];
1255 ns->nxstate = ns->op[ns->stateidx + 1];
1256 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1257 idx, get_state_name(ns->state), get_state_name(ns->nxstate));
1258 return 0;
1259 }
1260
1261 if (opsfound == 0) {
1262 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1263 if (ns->npstates != 0) {
1264 NS_DBG("find_operation: no operation found, try again with state %s\n",
1265 get_state_name(ns->state));
1266 ns->npstates = 0;
1267 return find_operation(ns, 0);
1268
1269 }
1270 NS_DBG("find_operation: no operations found\n");
1271 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1272 return -2;
1273 }
1274
1275 if (flag) {
1276 /* This shouldn't happen */
1277 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1278 return -2;
1279 }
1280
1281 NS_DBG("find_operation: there is still ambiguity\n");
1282
1283 ns->pstates[ns->npstates++] = ns->state;
1284
1285 return -1;
1286 }
1287
1288 static void put_pages(struct nandsim *ns)
1289 {
1290 int i;
1291
1292 for (i = 0; i < ns->held_cnt; i++)
1293 page_cache_release(ns->held_pages[i]);
1294 }
1295
1296 /* Get page cache pages in advance to provide NOFS memory allocation */
1297 static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos)
1298 {
1299 pgoff_t index, start_index, end_index;
1300 struct page *page;
1301 struct address_space *mapping = file->f_mapping;
1302
1303 start_index = pos >> PAGE_CACHE_SHIFT;
1304 end_index = (pos + count - 1) >> PAGE_CACHE_SHIFT;
1305 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1306 return -EINVAL;
1307 ns->held_cnt = 0;
1308 for (index = start_index; index <= end_index; index++) {
1309 page = find_get_page(mapping, index);
1310 if (page == NULL) {
1311 page = find_or_create_page(mapping, index, GFP_NOFS);
1312 if (page == NULL) {
1313 write_inode_now(mapping->host, 1);
1314 page = find_or_create_page(mapping, index, GFP_NOFS);
1315 }
1316 if (page == NULL) {
1317 put_pages(ns);
1318 return -ENOMEM;
1319 }
1320 unlock_page(page);
1321 }
1322 ns->held_pages[ns->held_cnt++] = page;
1323 }
1324 return 0;
1325 }
1326
1327 static int set_memalloc(void)
1328 {
1329 if (current->flags & PF_MEMALLOC)
1330 return 0;
1331 current->flags |= PF_MEMALLOC;
1332 return 1;
1333 }
1334
1335 static void clear_memalloc(int memalloc)
1336 {
1337 if (memalloc)
1338 current->flags &= ~PF_MEMALLOC;
1339 }
1340
1341 static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1342 {
1343 mm_segment_t old_fs;
1344 ssize_t tx;
1345 int err, memalloc;
1346
1347 err = get_pages(ns, file, count, *pos);
1348 if (err)
1349 return err;
1350 old_fs = get_fs();
1351 set_fs(get_ds());
1352 memalloc = set_memalloc();
1353 tx = vfs_read(file, (char __user *)buf, count, pos);
1354 clear_memalloc(memalloc);
1355 set_fs(old_fs);
1356 put_pages(ns);
1357 return tx;
1358 }
1359
1360 static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1361 {
1362 mm_segment_t old_fs;
1363 ssize_t tx;
1364 int err, memalloc;
1365
1366 err = get_pages(ns, file, count, *pos);
1367 if (err)
1368 return err;
1369 old_fs = get_fs();
1370 set_fs(get_ds());
1371 memalloc = set_memalloc();
1372 tx = vfs_write(file, (char __user *)buf, count, pos);
1373 clear_memalloc(memalloc);
1374 set_fs(old_fs);
1375 put_pages(ns);
1376 return tx;
1377 }
1378
1379 /*
1380 * Returns a pointer to the current page.
1381 */
1382 static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1383 {
1384 return &(ns->pages[ns->regs.row]);
1385 }
1386
1387 /*
1388 * Retuns a pointer to the current byte, within the current page.
1389 */
1390 static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1391 {
1392 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1393 }
1394
1395 int do_read_error(struct nandsim *ns, int num)
1396 {
1397 unsigned int page_no = ns->regs.row;
1398
1399 if (read_error(page_no)) {
1400 int i;
1401 memset(ns->buf.byte, 0xFF, num);
1402 for (i = 0; i < num; ++i)
1403 ns->buf.byte[i] = random32();
1404 NS_WARN("simulating read error in page %u\n", page_no);
1405 return 1;
1406 }
1407 return 0;
1408 }
1409
1410 void do_bit_flips(struct nandsim *ns, int num)
1411 {
1412 if (bitflips && random32() < (1 << 22)) {
1413 int flips = 1;
1414 if (bitflips > 1)
1415 flips = (random32() % (int) bitflips) + 1;
1416 while (flips--) {
1417 int pos = random32() % (num * 8);
1418 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1419 NS_WARN("read_page: flipping bit %d in page %d "
1420 "reading from %d ecc: corrected=%u failed=%u\n",
1421 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1422 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1423 }
1424 }
1425 }
1426
1427 /*
1428 * Fill the NAND buffer with data read from the specified page.
1429 */
1430 static void read_page(struct nandsim *ns, int num)
1431 {
1432 union ns_mem *mypage;
1433
1434 if (ns->cfile) {
1435 if (!ns->pages_written[ns->regs.row]) {
1436 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1437 memset(ns->buf.byte, 0xFF, num);
1438 } else {
1439 loff_t pos;
1440 ssize_t tx;
1441
1442 NS_DBG("read_page: page %d written, reading from %d\n",
1443 ns->regs.row, ns->regs.column + ns->regs.off);
1444 if (do_read_error(ns, num))
1445 return;
1446 pos = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1447 tx = read_file(ns, ns->cfile, ns->buf.byte, num, &pos);
1448 if (tx != num) {
1449 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1450 return;
1451 }
1452 do_bit_flips(ns, num);
1453 }
1454 return;
1455 }
1456
1457 mypage = NS_GET_PAGE(ns);
1458 if (mypage->byte == NULL) {
1459 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1460 memset(ns->buf.byte, 0xFF, num);
1461 } else {
1462 NS_DBG("read_page: page %d allocated, reading from %d\n",
1463 ns->regs.row, ns->regs.column + ns->regs.off);
1464 if (do_read_error(ns, num))
1465 return;
1466 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
1467 do_bit_flips(ns, num);
1468 }
1469 }
1470
1471 /*
1472 * Erase all pages in the specified sector.
1473 */
1474 static void erase_sector(struct nandsim *ns)
1475 {
1476 union ns_mem *mypage;
1477 int i;
1478
1479 if (ns->cfile) {
1480 for (i = 0; i < ns->geom.pgsec; i++)
1481 if (ns->pages_written[ns->regs.row + i]) {
1482 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1483 ns->pages_written[ns->regs.row + i] = 0;
1484 }
1485 return;
1486 }
1487
1488 mypage = NS_GET_PAGE(ns);
1489 for (i = 0; i < ns->geom.pgsec; i++) {
1490 if (mypage->byte != NULL) {
1491 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
1492 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
1493 mypage->byte = NULL;
1494 }
1495 mypage++;
1496 }
1497 }
1498
1499 /*
1500 * Program the specified page with the contents from the NAND buffer.
1501 */
1502 static int prog_page(struct nandsim *ns, int num)
1503 {
1504 int i;
1505 union ns_mem *mypage;
1506 u_char *pg_off;
1507
1508 if (ns->cfile) {
1509 loff_t off, pos;
1510 ssize_t tx;
1511 int all;
1512
1513 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1514 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1515 off = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1516 if (!ns->pages_written[ns->regs.row]) {
1517 all = 1;
1518 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1519 } else {
1520 all = 0;
1521 pos = off;
1522 tx = read_file(ns, ns->cfile, pg_off, num, &pos);
1523 if (tx != num) {
1524 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1525 return -1;
1526 }
1527 }
1528 for (i = 0; i < num; i++)
1529 pg_off[i] &= ns->buf.byte[i];
1530 if (all) {
1531 pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1532 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, &pos);
1533 if (tx != ns->geom.pgszoob) {
1534 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1535 return -1;
1536 }
1537 ns->pages_written[ns->regs.row] = 1;
1538 } else {
1539 pos = off;
1540 tx = write_file(ns, ns->cfile, pg_off, num, &pos);
1541 if (tx != num) {
1542 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1543 return -1;
1544 }
1545 }
1546 return 0;
1547 }
1548
1549 mypage = NS_GET_PAGE(ns);
1550 if (mypage->byte == NULL) {
1551 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
1552 /*
1553 * We allocate memory with GFP_NOFS because a flash FS may
1554 * utilize this. If it is holding an FS lock, then gets here,
1555 * then kernel memory alloc runs writeback which goes to the FS
1556 * again and deadlocks. This was seen in practice.
1557 */
1558 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
1559 if (mypage->byte == NULL) {
1560 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1561 return -1;
1562 }
1563 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1564 }
1565
1566 pg_off = NS_PAGE_BYTE_OFF(ns);
1567 for (i = 0; i < num; i++)
1568 pg_off[i] &= ns->buf.byte[i];
1569
1570 return 0;
1571 }
1572
1573 /*
1574 * If state has any action bit, perform this action.
1575 *
1576 * RETURNS: 0 if success, -1 if error.
1577 */
1578 static int do_state_action(struct nandsim *ns, uint32_t action)
1579 {
1580 int num;
1581 int busdiv = ns->busw == 8 ? 1 : 2;
1582 unsigned int erase_block_no, page_no;
1583
1584 action &= ACTION_MASK;
1585
1586 /* Check that page address input is correct */
1587 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1588 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1589 return -1;
1590 }
1591
1592 switch (action) {
1593
1594 case ACTION_CPY:
1595 /*
1596 * Copy page data to the internal buffer.
1597 */
1598
1599 /* Column shouldn't be very large */
1600 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1601 NS_ERR("do_state_action: column number is too large\n");
1602 break;
1603 }
1604 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1605 read_page(ns, num);
1606
1607 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1608 num, NS_RAW_OFFSET(ns) + ns->regs.off);
1609
1610 if (ns->regs.off == 0)
1611 NS_LOG("read page %d\n", ns->regs.row);
1612 else if (ns->regs.off < ns->geom.pgsz)
1613 NS_LOG("read page %d (second half)\n", ns->regs.row);
1614 else
1615 NS_LOG("read OOB of page %d\n", ns->regs.row);
1616
1617 NS_UDELAY(access_delay);
1618 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1619
1620 break;
1621
1622 case ACTION_SECERASE:
1623 /*
1624 * Erase sector.
1625 */
1626
1627 if (ns->lines.wp) {
1628 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1629 return -1;
1630 }
1631
1632 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1633 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1634 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1635 return -1;
1636 }
1637
1638 ns->regs.row = (ns->regs.row <<
1639 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1640 ns->regs.column = 0;
1641
1642 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1643
1644 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1645 ns->regs.row, NS_RAW_OFFSET(ns));
1646 NS_LOG("erase sector %u\n", erase_block_no);
1647
1648 erase_sector(ns);
1649
1650 NS_MDELAY(erase_delay);
1651
1652 if (erase_block_wear)
1653 update_wear(erase_block_no);
1654
1655 if (erase_error(erase_block_no)) {
1656 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1657 return -1;
1658 }
1659
1660 break;
1661
1662 case ACTION_PRGPAGE:
1663 /*
1664 * Program page - move internal buffer data to the page.
1665 */
1666
1667 if (ns->lines.wp) {
1668 NS_WARN("do_state_action: device is write-protected, programm\n");
1669 return -1;
1670 }
1671
1672 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1673 if (num != ns->regs.count) {
1674 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1675 ns->regs.count, num);
1676 return -1;
1677 }
1678
1679 if (prog_page(ns, num) == -1)
1680 return -1;
1681
1682 page_no = ns->regs.row;
1683
1684 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1685 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1686 NS_LOG("programm page %d\n", ns->regs.row);
1687
1688 NS_UDELAY(programm_delay);
1689 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
1690
1691 if (write_error(page_no)) {
1692 NS_WARN("simulating write failure in page %u\n", page_no);
1693 return -1;
1694 }
1695
1696 break;
1697
1698 case ACTION_ZEROOFF:
1699 NS_DBG("do_state_action: set internal offset to 0\n");
1700 ns->regs.off = 0;
1701 break;
1702
1703 case ACTION_HALFOFF:
1704 if (!(ns->options & OPT_PAGE512_8BIT)) {
1705 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1706 "byte page size 8x chips\n");
1707 return -1;
1708 }
1709 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1710 ns->regs.off = ns->geom.pgsz/2;
1711 break;
1712
1713 case ACTION_OOBOFF:
1714 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1715 ns->regs.off = ns->geom.pgsz;
1716 break;
1717
1718 default:
1719 NS_DBG("do_state_action: BUG! unknown action\n");
1720 }
1721
1722 return 0;
1723 }
1724
1725 /*
1726 * Switch simulator's state.
1727 */
1728 static void switch_state(struct nandsim *ns)
1729 {
1730 if (ns->op) {
1731 /*
1732 * The current operation have already been identified.
1733 * Just follow the states chain.
1734 */
1735
1736 ns->stateidx += 1;
1737 ns->state = ns->nxstate;
1738 ns->nxstate = ns->op[ns->stateidx + 1];
1739
1740 NS_DBG("switch_state: operation is known, switch to the next state, "
1741 "state: %s, nxstate: %s\n",
1742 get_state_name(ns->state), get_state_name(ns->nxstate));
1743
1744 /* See, whether we need to do some action */
1745 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1746 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1747 return;
1748 }
1749
1750 } else {
1751 /*
1752 * We don't yet know which operation we perform.
1753 * Try to identify it.
1754 */
1755
1756 /*
1757 * The only event causing the switch_state function to
1758 * be called with yet unknown operation is new command.
1759 */
1760 ns->state = get_state_by_command(ns->regs.command);
1761
1762 NS_DBG("switch_state: operation is unknown, try to find it\n");
1763
1764 if (find_operation(ns, 0) != 0)
1765 return;
1766
1767 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1768 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1769 return;
1770 }
1771 }
1772
1773 /* For 16x devices column means the page offset in words */
1774 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1775 NS_DBG("switch_state: double the column number for 16x device\n");
1776 ns->regs.column <<= 1;
1777 }
1778
1779 if (NS_STATE(ns->nxstate) == STATE_READY) {
1780 /*
1781 * The current state is the last. Return to STATE_READY
1782 */
1783
1784 u_char status = NS_STATUS_OK(ns);
1785
1786 /* In case of data states, see if all bytes were input/output */
1787 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1788 && ns->regs.count != ns->regs.num) {
1789 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1790 ns->regs.num - ns->regs.count);
1791 status = NS_STATUS_FAILED(ns);
1792 }
1793
1794 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1795
1796 switch_to_ready_state(ns, status);
1797
1798 return;
1799 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
1800 /*
1801 * If the next state is data input/output, switch to it now
1802 */
1803
1804 ns->state = ns->nxstate;
1805 ns->nxstate = ns->op[++ns->stateidx + 1];
1806 ns->regs.num = ns->regs.count = 0;
1807
1808 NS_DBG("switch_state: the next state is data I/O, switch, "
1809 "state: %s, nxstate: %s\n",
1810 get_state_name(ns->state), get_state_name(ns->nxstate));
1811
1812 /*
1813 * Set the internal register to the count of bytes which
1814 * are expected to be input or output
1815 */
1816 switch (NS_STATE(ns->state)) {
1817 case STATE_DATAIN:
1818 case STATE_DATAOUT:
1819 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1820 break;
1821
1822 case STATE_DATAOUT_ID:
1823 ns->regs.num = ns->geom.idbytes;
1824 break;
1825
1826 case STATE_DATAOUT_STATUS:
1827 case STATE_DATAOUT_STATUS_M:
1828 ns->regs.count = ns->regs.num = 0;
1829 break;
1830
1831 default:
1832 NS_ERR("switch_state: BUG! unknown data state\n");
1833 }
1834
1835 } else if (ns->nxstate & STATE_ADDR_MASK) {
1836 /*
1837 * If the next state is address input, set the internal
1838 * register to the number of expected address bytes
1839 */
1840
1841 ns->regs.count = 0;
1842
1843 switch (NS_STATE(ns->nxstate)) {
1844 case STATE_ADDR_PAGE:
1845 ns->regs.num = ns->geom.pgaddrbytes;
1846
1847 break;
1848 case STATE_ADDR_SEC:
1849 ns->regs.num = ns->geom.secaddrbytes;
1850 break;
1851
1852 case STATE_ADDR_ZERO:
1853 ns->regs.num = 1;
1854 break;
1855
1856 case STATE_ADDR_COLUMN:
1857 /* Column address is always 2 bytes */
1858 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1859 break;
1860
1861 default:
1862 NS_ERR("switch_state: BUG! unknown address state\n");
1863 }
1864 } else {
1865 /*
1866 * Just reset internal counters.
1867 */
1868
1869 ns->regs.num = 0;
1870 ns->regs.count = 0;
1871 }
1872 }
1873
1874 static u_char ns_nand_read_byte(struct mtd_info *mtd)
1875 {
1876 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1877 u_char outb = 0x00;
1878
1879 /* Sanity and correctness checks */
1880 if (!ns->lines.ce) {
1881 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1882 return outb;
1883 }
1884 if (ns->lines.ale || ns->lines.cle) {
1885 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1886 return outb;
1887 }
1888 if (!(ns->state & STATE_DATAOUT_MASK)) {
1889 NS_WARN("read_byte: unexpected data output cycle, state is %s "
1890 "return %#x\n", get_state_name(ns->state), (uint)outb);
1891 return outb;
1892 }
1893
1894 /* Status register may be read as many times as it is wanted */
1895 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1896 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1897 return ns->regs.status;
1898 }
1899
1900 /* Check if there is any data in the internal buffer which may be read */
1901 if (ns->regs.count == ns->regs.num) {
1902 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1903 return outb;
1904 }
1905
1906 switch (NS_STATE(ns->state)) {
1907 case STATE_DATAOUT:
1908 if (ns->busw == 8) {
1909 outb = ns->buf.byte[ns->regs.count];
1910 ns->regs.count += 1;
1911 } else {
1912 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1913 ns->regs.count += 2;
1914 }
1915 break;
1916 case STATE_DATAOUT_ID:
1917 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1918 outb = ns->ids[ns->regs.count];
1919 ns->regs.count += 1;
1920 break;
1921 default:
1922 BUG();
1923 }
1924
1925 if (ns->regs.count == ns->regs.num) {
1926 NS_DBG("read_byte: all bytes were read\n");
1927
1928 if (NS_STATE(ns->nxstate) == STATE_READY)
1929 switch_state(ns);
1930 }
1931
1932 return outb;
1933 }
1934
1935 static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1936 {
1937 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1938
1939 /* Sanity and correctness checks */
1940 if (!ns->lines.ce) {
1941 NS_ERR("write_byte: chip is disabled, ignore write\n");
1942 return;
1943 }
1944 if (ns->lines.ale && ns->lines.cle) {
1945 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1946 return;
1947 }
1948
1949 if (ns->lines.cle == 1) {
1950 /*
1951 * The byte written is a command.
1952 */
1953
1954 if (byte == NAND_CMD_RESET) {
1955 NS_LOG("reset chip\n");
1956 switch_to_ready_state(ns, NS_STATUS_OK(ns));
1957 return;
1958 }
1959
1960 /* Check that the command byte is correct */
1961 if (check_command(byte)) {
1962 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1963 return;
1964 }
1965
1966 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1967 || NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M
1968 || NS_STATE(ns->state) == STATE_DATAOUT) {
1969 int row = ns->regs.row;
1970
1971 switch_state(ns);
1972 if (byte == NAND_CMD_RNDOUT)
1973 ns->regs.row = row;
1974 }
1975
1976 /* Check if chip is expecting command */
1977 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
1978 /* Do not warn if only 2 id bytes are read */
1979 if (!(ns->regs.command == NAND_CMD_READID &&
1980 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
1981 /*
1982 * We are in situation when something else (not command)
1983 * was expected but command was input. In this case ignore
1984 * previous command(s)/state(s) and accept the last one.
1985 */
1986 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
1987 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
1988 }
1989 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1990 }
1991
1992 NS_DBG("command byte corresponding to %s state accepted\n",
1993 get_state_name(get_state_by_command(byte)));
1994 ns->regs.command = byte;
1995 switch_state(ns);
1996
1997 } else if (ns->lines.ale == 1) {
1998 /*
1999 * The byte written is an address.
2000 */
2001
2002 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2003
2004 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2005
2006 if (find_operation(ns, 1) < 0)
2007 return;
2008
2009 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
2010 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2011 return;
2012 }
2013
2014 ns->regs.count = 0;
2015 switch (NS_STATE(ns->nxstate)) {
2016 case STATE_ADDR_PAGE:
2017 ns->regs.num = ns->geom.pgaddrbytes;
2018 break;
2019 case STATE_ADDR_SEC:
2020 ns->regs.num = ns->geom.secaddrbytes;
2021 break;
2022 case STATE_ADDR_ZERO:
2023 ns->regs.num = 1;
2024 break;
2025 default:
2026 BUG();
2027 }
2028 }
2029
2030 /* Check that chip is expecting address */
2031 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2032 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
2033 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
2034 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2035 return;
2036 }
2037
2038 /* Check if this is expected byte */
2039 if (ns->regs.count == ns->regs.num) {
2040 NS_ERR("write_byte: no more address bytes expected\n");
2041 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2042 return;
2043 }
2044
2045 accept_addr_byte(ns, byte);
2046
2047 ns->regs.count += 1;
2048
2049 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2050 (uint)byte, ns->regs.count, ns->regs.num);
2051
2052 if (ns->regs.count == ns->regs.num) {
2053 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2054 switch_state(ns);
2055 }
2056
2057 } else {
2058 /*
2059 * The byte written is an input data.
2060 */
2061
2062 /* Check that chip is expecting data input */
2063 if (!(ns->state & STATE_DATAIN_MASK)) {
2064 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
2065 "switch to %s\n", (uint)byte,
2066 get_state_name(ns->state), get_state_name(STATE_READY));
2067 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2068 return;
2069 }
2070
2071 /* Check if this is expected byte */
2072 if (ns->regs.count == ns->regs.num) {
2073 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2074 ns->regs.num);
2075 return;
2076 }
2077
2078 if (ns->busw == 8) {
2079 ns->buf.byte[ns->regs.count] = byte;
2080 ns->regs.count += 1;
2081 } else {
2082 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2083 ns->regs.count += 2;
2084 }
2085 }
2086
2087 return;
2088 }
2089
2090 static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
2091 {
2092 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2093
2094 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
2095 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
2096 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
2097
2098 if (cmd != NAND_CMD_NONE)
2099 ns_nand_write_byte(mtd, cmd);
2100 }
2101
2102 static int ns_device_ready(struct mtd_info *mtd)
2103 {
2104 NS_DBG("device_ready\n");
2105 return 1;
2106 }
2107
2108 static uint16_t ns_nand_read_word(struct mtd_info *mtd)
2109 {
2110 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2111
2112 NS_DBG("read_word\n");
2113
2114 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
2115 }
2116
2117 static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
2118 {
2119 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2120
2121 /* Check that chip is expecting data input */
2122 if (!(ns->state & STATE_DATAIN_MASK)) {
2123 NS_ERR("write_buf: data input isn't expected, state is %s, "
2124 "switch to STATE_READY\n", get_state_name(ns->state));
2125 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2126 return;
2127 }
2128
2129 /* Check if these are expected bytes */
2130 if (ns->regs.count + len > ns->regs.num) {
2131 NS_ERR("write_buf: too many input bytes\n");
2132 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2133 return;
2134 }
2135
2136 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2137 ns->regs.count += len;
2138
2139 if (ns->regs.count == ns->regs.num) {
2140 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2141 }
2142 }
2143
2144 static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
2145 {
2146 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2147
2148 /* Sanity and correctness checks */
2149 if (!ns->lines.ce) {
2150 NS_ERR("read_buf: chip is disabled\n");
2151 return;
2152 }
2153 if (ns->lines.ale || ns->lines.cle) {
2154 NS_ERR("read_buf: ALE or CLE pin is high\n");
2155 return;
2156 }
2157 if (!(ns->state & STATE_DATAOUT_MASK)) {
2158 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2159 get_state_name(ns->state));
2160 return;
2161 }
2162
2163 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2164 int i;
2165
2166 for (i = 0; i < len; i++)
2167 buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd);
2168
2169 return;
2170 }
2171
2172 /* Check if these are expected bytes */
2173 if (ns->regs.count + len > ns->regs.num) {
2174 NS_ERR("read_buf: too many bytes to read\n");
2175 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2176 return;
2177 }
2178
2179 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2180 ns->regs.count += len;
2181
2182 if (ns->regs.count == ns->regs.num) {
2183 if (NS_STATE(ns->nxstate) == STATE_READY)
2184 switch_state(ns);
2185 }
2186
2187 return;
2188 }
2189
2190 /*
2191 * Module initialization function
2192 */
2193 static int __init ns_init_module(void)
2194 {
2195 struct nand_chip *chip;
2196 struct nandsim *nand;
2197 int retval = -ENOMEM, i;
2198
2199 if (bus_width != 8 && bus_width != 16) {
2200 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2201 return -EINVAL;
2202 }
2203
2204 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */
2205 nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip)
2206 + sizeof(struct nandsim), GFP_KERNEL);
2207 if (!nsmtd) {
2208 NS_ERR("unable to allocate core structures.\n");
2209 return -ENOMEM;
2210 }
2211 chip = (struct nand_chip *)(nsmtd + 1);
2212 nsmtd->priv = (void *)chip;
2213 nand = (struct nandsim *)(chip + 1);
2214 chip->priv = (void *)nand;
2215
2216 /*
2217 * Register simulator's callbacks.
2218 */
2219 chip->cmd_ctrl = ns_hwcontrol;
2220 chip->read_byte = ns_nand_read_byte;
2221 chip->dev_ready = ns_device_ready;
2222 chip->write_buf = ns_nand_write_buf;
2223 chip->read_buf = ns_nand_read_buf;
2224 chip->read_word = ns_nand_read_word;
2225 chip->ecc.mode = NAND_ECC_SOFT;
2226 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2227 /* and 'badblocks' parameters to work */
2228 chip->options |= NAND_SKIP_BBTSCAN;
2229
2230 switch (bbt) {
2231 case 2:
2232 chip->bbt_options |= NAND_BBT_NO_OOB;
2233 case 1:
2234 chip->bbt_options |= NAND_BBT_USE_FLASH;
2235 case 0:
2236 break;
2237 default:
2238 NS_ERR("bbt has to be 0..2\n");
2239 retval = -EINVAL;
2240 goto error;
2241 }
2242 /*
2243 * Perform minimum nandsim structure initialization to handle
2244 * the initial ID read command correctly
2245 */
2246 if (third_id_byte != 0xFF || fourth_id_byte != 0xFF)
2247 nand->geom.idbytes = 4;
2248 else
2249 nand->geom.idbytes = 2;
2250 nand->regs.status = NS_STATUS_OK(nand);
2251 nand->nxstate = STATE_UNKNOWN;
2252 nand->options |= OPT_PAGE256; /* temporary value */
2253 nand->ids[0] = first_id_byte;
2254 nand->ids[1] = second_id_byte;
2255 nand->ids[2] = third_id_byte;
2256 nand->ids[3] = fourth_id_byte;
2257 if (bus_width == 16) {
2258 nand->busw = 16;
2259 chip->options |= NAND_BUSWIDTH_16;
2260 }
2261
2262 nsmtd->owner = THIS_MODULE;
2263
2264 if ((retval = parse_weakblocks()) != 0)
2265 goto error;
2266
2267 if ((retval = parse_weakpages()) != 0)
2268 goto error;
2269
2270 if ((retval = parse_gravepages()) != 0)
2271 goto error;
2272
2273 retval = nand_scan_ident(nsmtd, 1, NULL);
2274 if (retval) {
2275 NS_ERR("cannot scan NAND Simulator device\n");
2276 if (retval > 0)
2277 retval = -ENXIO;
2278 goto error;
2279 }
2280
2281 if (bch) {
2282 unsigned int eccsteps, eccbytes;
2283 if (!mtd_nand_has_bch()) {
2284 NS_ERR("BCH ECC support is disabled\n");
2285 retval = -EINVAL;
2286 goto error;
2287 }
2288 /* use 512-byte ecc blocks */
2289 eccsteps = nsmtd->writesize/512;
2290 eccbytes = (bch*13+7)/8;
2291 /* do not bother supporting small page devices */
2292 if ((nsmtd->oobsize < 64) || !eccsteps) {
2293 NS_ERR("bch not available on small page devices\n");
2294 retval = -EINVAL;
2295 goto error;
2296 }
2297 if ((eccbytes*eccsteps+2) > nsmtd->oobsize) {
2298 NS_ERR("invalid bch value %u\n", bch);
2299 retval = -EINVAL;
2300 goto error;
2301 }
2302 chip->ecc.mode = NAND_ECC_SOFT_BCH;
2303 chip->ecc.size = 512;
2304 chip->ecc.bytes = eccbytes;
2305 NS_INFO("using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size);
2306 }
2307
2308 retval = nand_scan_tail(nsmtd);
2309 if (retval) {
2310 NS_ERR("can't register NAND Simulator\n");
2311 if (retval > 0)
2312 retval = -ENXIO;
2313 goto error;
2314 }
2315
2316 if (overridesize) {
2317 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
2318 if (new_size >> overridesize != nsmtd->erasesize) {
2319 NS_ERR("overridesize is too big\n");
2320 retval = -EINVAL;
2321 goto err_exit;
2322 }
2323 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2324 nsmtd->size = new_size;
2325 chip->chipsize = new_size;
2326 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
2327 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2328 }
2329
2330 if ((retval = setup_wear_reporting(nsmtd)) != 0)
2331 goto err_exit;
2332
2333 if ((retval = init_nandsim(nsmtd)) != 0)
2334 goto err_exit;
2335
2336 if ((retval = nand_default_bbt(nsmtd)) != 0)
2337 goto err_exit;
2338
2339 if ((retval = parse_badblocks(nand, nsmtd)) != 0)
2340 goto err_exit;
2341
2342 /* Register NAND partitions */
2343 retval = mtd_device_register(nsmtd, &nand->partitions[0],
2344 nand->nbparts);
2345 if (retval != 0)
2346 goto err_exit;
2347
2348 return 0;
2349
2350 err_exit:
2351 free_nandsim(nand);
2352 nand_release(nsmtd);
2353 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
2354 kfree(nand->partitions[i].name);
2355 error:
2356 kfree(nsmtd);
2357 free_lists();
2358
2359 return retval;
2360 }
2361
2362 module_init(ns_init_module);
2363
2364 /*
2365 * Module clean-up function
2366 */
2367 static void __exit ns_cleanup_module(void)
2368 {
2369 struct nandsim *ns = ((struct nand_chip *)nsmtd->priv)->priv;
2370 int i;
2371
2372 free_nandsim(ns); /* Free nandsim private resources */
2373 nand_release(nsmtd); /* Unregister driver */
2374 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
2375 kfree(ns->partitions[i].name);
2376 kfree(nsmtd); /* Free other structures */
2377 free_lists();
2378 }
2379
2380 module_exit(ns_cleanup_module);
2381
2382 MODULE_LICENSE ("GPL");
2383 MODULE_AUTHOR ("Artem B. Bityuckiy");
2384 MODULE_DESCRIPTION ("The NAND flash simulator");
Linux kernel - Deliverables
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