2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
24 #include <linux/slab.h>
26 #ifdef CONFIG_MTD_NAND_OMAP_BCH
27 #include <linux/bch.h>
31 #include <plat/gpmc.h>
32 #include <linux/platform_data/mtd-nand-omap2.h>
34 #define DRIVER_NAME "omap2-nand"
35 #define OMAP_NAND_TIMEOUT_MS 5000
37 #define NAND_Ecc_P1e (1 << 0)
38 #define NAND_Ecc_P2e (1 << 1)
39 #define NAND_Ecc_P4e (1 << 2)
40 #define NAND_Ecc_P8e (1 << 3)
41 #define NAND_Ecc_P16e (1 << 4)
42 #define NAND_Ecc_P32e (1 << 5)
43 #define NAND_Ecc_P64e (1 << 6)
44 #define NAND_Ecc_P128e (1 << 7)
45 #define NAND_Ecc_P256e (1 << 8)
46 #define NAND_Ecc_P512e (1 << 9)
47 #define NAND_Ecc_P1024e (1 << 10)
48 #define NAND_Ecc_P2048e (1 << 11)
50 #define NAND_Ecc_P1o (1 << 16)
51 #define NAND_Ecc_P2o (1 << 17)
52 #define NAND_Ecc_P4o (1 << 18)
53 #define NAND_Ecc_P8o (1 << 19)
54 #define NAND_Ecc_P16o (1 << 20)
55 #define NAND_Ecc_P32o (1 << 21)
56 #define NAND_Ecc_P64o (1 << 22)
57 #define NAND_Ecc_P128o (1 << 23)
58 #define NAND_Ecc_P256o (1 << 24)
59 #define NAND_Ecc_P512o (1 << 25)
60 #define NAND_Ecc_P1024o (1 << 26)
61 #define NAND_Ecc_P2048o (1 << 27)
63 #define TF(value) (value ? 1 : 0)
65 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
66 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
67 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
68 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
69 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
70 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
71 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
72 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
74 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
75 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
76 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
77 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
78 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
79 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
80 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
81 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
83 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
84 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
85 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
86 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
87 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
88 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
89 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
90 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
92 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
93 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
94 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
95 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
96 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
97 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
98 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
99 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
101 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
102 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
104 #define PREFETCH_CONFIG1_CS_SHIFT 24
105 #define ECC_CONFIG_CS_SHIFT 1
107 #define ENABLE_PREFETCH (0x1 << 7)
108 #define DMA_MPU_MODE_SHIFT 2
109 #define ECCSIZE1_SHIFT 22
110 #define ECC1RESULTSIZE 0x1
111 #define ECCCLEAR 0x100
114 /* oob info generated runtime depending on ecc algorithm and layout selected */
115 static struct nand_ecclayout omap_oobinfo
;
116 /* Define some generic bad / good block scan pattern which are used
117 * while scanning a device for factory marked good / bad blocks
119 static uint8_t scan_ff_pattern
[] = { 0xff };
120 static struct nand_bbt_descr bb_descrip_flashbased
= {
121 .options
= NAND_BBT_SCANEMPTY
| NAND_BBT_SCANALLPAGES
,
124 .pattern
= scan_ff_pattern
,
128 struct omap_nand_info
{
129 struct nand_hw_control controller
;
130 struct omap_nand_platform_data
*pdata
;
132 struct nand_chip nand
;
133 struct platform_device
*pdev
;
136 unsigned long phys_base
;
137 unsigned long mem_size
;
138 struct completion comp
;
139 struct dma_chan
*dma
;
143 OMAP_NAND_IO_READ
= 0, /* read */
144 OMAP_NAND_IO_WRITE
, /* write */
148 struct gpmc_nand_regs reg
;
150 #ifdef CONFIG_MTD_NAND_OMAP_BCH
151 struct bch_control
*bch
;
152 struct nand_ecclayout ecclayout
;
157 * omap_prefetch_enable - configures and starts prefetch transfer
158 * @cs: cs (chip select) number
159 * @fifo_th: fifo threshold to be used for read/ write
160 * @dma_mode: dma mode enable (1) or disable (0)
161 * @u32_count: number of bytes to be transferred
162 * @is_write: prefetch read(0) or write post(1) mode
164 static int omap_prefetch_enable(int cs
, int fifo_th
, int dma_mode
,
165 unsigned int u32_count
, int is_write
, struct omap_nand_info
*info
)
169 if (fifo_th
> PREFETCH_FIFOTHRESHOLD_MAX
)
172 if (readl(info
->reg
.gpmc_prefetch_control
))
175 /* Set the amount of bytes to be prefetched */
176 writel(u32_count
, info
->reg
.gpmc_prefetch_config2
);
178 /* Set dma/mpu mode, the prefetch read / post write and
179 * enable the engine. Set which cs is has requested for.
181 val
= ((cs
<< PREFETCH_CONFIG1_CS_SHIFT
) |
182 PREFETCH_FIFOTHRESHOLD(fifo_th
) | ENABLE_PREFETCH
|
183 (dma_mode
<< DMA_MPU_MODE_SHIFT
) | (0x1 & is_write
));
184 writel(val
, info
->reg
.gpmc_prefetch_config1
);
186 /* Start the prefetch engine */
187 writel(0x1, info
->reg
.gpmc_prefetch_control
);
193 * omap_prefetch_reset - disables and stops the prefetch engine
195 static int omap_prefetch_reset(int cs
, struct omap_nand_info
*info
)
199 /* check if the same module/cs is trying to reset */
200 config1
= readl(info
->reg
.gpmc_prefetch_config1
);
201 if (((config1
>> PREFETCH_CONFIG1_CS_SHIFT
) & CS_MASK
) != cs
)
204 /* Stop the PFPW engine */
205 writel(0x0, info
->reg
.gpmc_prefetch_control
);
207 /* Reset/disable the PFPW engine */
208 writel(0x0, info
->reg
.gpmc_prefetch_config1
);
214 * omap_hwcontrol - hardware specific access to control-lines
215 * @mtd: MTD device structure
216 * @cmd: command to device
218 * NAND_NCE: bit 0 -> don't care
219 * NAND_CLE: bit 1 -> Command Latch
220 * NAND_ALE: bit 2 -> Address Latch
222 * NOTE: boards may use different bits for these!!
224 static void omap_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
226 struct omap_nand_info
*info
= container_of(mtd
,
227 struct omap_nand_info
, mtd
);
229 if (cmd
!= NAND_CMD_NONE
) {
231 writeb(cmd
, info
->reg
.gpmc_nand_command
);
233 else if (ctrl
& NAND_ALE
)
234 writeb(cmd
, info
->reg
.gpmc_nand_address
);
237 writeb(cmd
, info
->reg
.gpmc_nand_data
);
242 * omap_read_buf8 - read data from NAND controller into buffer
243 * @mtd: MTD device structure
244 * @buf: buffer to store date
245 * @len: number of bytes to read
247 static void omap_read_buf8(struct mtd_info
*mtd
, u_char
*buf
, int len
)
249 struct nand_chip
*nand
= mtd
->priv
;
251 ioread8_rep(nand
->IO_ADDR_R
, buf
, len
);
255 * omap_write_buf8 - write buffer to NAND controller
256 * @mtd: MTD device structure
258 * @len: number of bytes to write
260 static void omap_write_buf8(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
262 struct omap_nand_info
*info
= container_of(mtd
,
263 struct omap_nand_info
, mtd
);
264 u_char
*p
= (u_char
*)buf
;
268 iowrite8(*p
++, info
->nand
.IO_ADDR_W
);
269 /* wait until buffer is available for write */
271 status
= readl(info
->reg
.gpmc_status
) &
272 GPMC_STATUS_BUFF_EMPTY
;
278 * omap_read_buf16 - read data from NAND controller into buffer
279 * @mtd: MTD device structure
280 * @buf: buffer to store date
281 * @len: number of bytes to read
283 static void omap_read_buf16(struct mtd_info
*mtd
, u_char
*buf
, int len
)
285 struct nand_chip
*nand
= mtd
->priv
;
287 ioread16_rep(nand
->IO_ADDR_R
, buf
, len
/ 2);
291 * omap_write_buf16 - write buffer to NAND controller
292 * @mtd: MTD device structure
294 * @len: number of bytes to write
296 static void omap_write_buf16(struct mtd_info
*mtd
, const u_char
* buf
, int len
)
298 struct omap_nand_info
*info
= container_of(mtd
,
299 struct omap_nand_info
, mtd
);
300 u16
*p
= (u16
*) buf
;
302 /* FIXME try bursts of writesw() or DMA ... */
306 iowrite16(*p
++, info
->nand
.IO_ADDR_W
);
307 /* wait until buffer is available for write */
309 status
= readl(info
->reg
.gpmc_status
) &
310 GPMC_STATUS_BUFF_EMPTY
;
316 * omap_read_buf_pref - read data from NAND controller into buffer
317 * @mtd: MTD device structure
318 * @buf: buffer to store date
319 * @len: number of bytes to read
321 static void omap_read_buf_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
323 struct omap_nand_info
*info
= container_of(mtd
,
324 struct omap_nand_info
, mtd
);
325 uint32_t r_count
= 0;
329 /* take care of subpage reads */
331 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
332 omap_read_buf16(mtd
, buf
, len
% 4);
334 omap_read_buf8(mtd
, buf
, len
% 4);
335 p
= (u32
*) (buf
+ len
% 4);
339 /* configure and start prefetch transfer */
340 ret
= omap_prefetch_enable(info
->gpmc_cs
,
341 PREFETCH_FIFOTHRESHOLD_MAX
, 0x0, len
, 0x0, info
);
343 /* PFPW engine is busy, use cpu copy method */
344 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
345 omap_read_buf16(mtd
, (u_char
*)p
, len
);
347 omap_read_buf8(mtd
, (u_char
*)p
, len
);
350 r_count
= readl(info
->reg
.gpmc_prefetch_status
);
351 r_count
= GPMC_PREFETCH_STATUS_FIFO_CNT(r_count
);
352 r_count
= r_count
>> 2;
353 ioread32_rep(info
->nand
.IO_ADDR_R
, p
, r_count
);
357 /* disable and stop the PFPW engine */
358 omap_prefetch_reset(info
->gpmc_cs
, info
);
363 * omap_write_buf_pref - write buffer to NAND controller
364 * @mtd: MTD device structure
366 * @len: number of bytes to write
368 static void omap_write_buf_pref(struct mtd_info
*mtd
,
369 const u_char
*buf
, int len
)
371 struct omap_nand_info
*info
= container_of(mtd
,
372 struct omap_nand_info
, mtd
);
373 uint32_t w_count
= 0;
376 unsigned long tim
, limit
;
379 /* take care of subpage writes */
381 writeb(*buf
, info
->nand
.IO_ADDR_W
);
382 p
= (u16
*)(buf
+ 1);
386 /* configure and start prefetch transfer */
387 ret
= omap_prefetch_enable(info
->gpmc_cs
,
388 PREFETCH_FIFOTHRESHOLD_MAX
, 0x0, len
, 0x1, info
);
390 /* PFPW engine is busy, use cpu copy method */
391 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
392 omap_write_buf16(mtd
, (u_char
*)p
, len
);
394 omap_write_buf8(mtd
, (u_char
*)p
, len
);
397 w_count
= readl(info
->reg
.gpmc_prefetch_status
);
398 w_count
= GPMC_PREFETCH_STATUS_FIFO_CNT(w_count
);
399 w_count
= w_count
>> 1;
400 for (i
= 0; (i
< w_count
) && len
; i
++, len
-= 2)
401 iowrite16(*p
++, info
->nand
.IO_ADDR_W
);
403 /* wait for data to flushed-out before reset the prefetch */
405 limit
= (loops_per_jiffy
*
406 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
409 val
= readl(info
->reg
.gpmc_prefetch_status
);
410 val
= GPMC_PREFETCH_STATUS_COUNT(val
);
411 } while (val
&& (tim
++ < limit
));
413 /* disable and stop the PFPW engine */
414 omap_prefetch_reset(info
->gpmc_cs
, info
);
419 * omap_nand_dma_callback: callback on the completion of dma transfer
420 * @data: pointer to completion data structure
422 static void omap_nand_dma_callback(void *data
)
424 complete((struct completion
*) data
);
428 * omap_nand_dma_transfer: configure and start dma transfer
429 * @mtd: MTD device structure
430 * @addr: virtual address in RAM of source/destination
431 * @len: number of data bytes to be transferred
432 * @is_write: flag for read/write operation
434 static inline int omap_nand_dma_transfer(struct mtd_info
*mtd
, void *addr
,
435 unsigned int len
, int is_write
)
437 struct omap_nand_info
*info
= container_of(mtd
,
438 struct omap_nand_info
, mtd
);
439 struct dma_async_tx_descriptor
*tx
;
440 enum dma_data_direction dir
= is_write
? DMA_TO_DEVICE
:
442 struct scatterlist sg
;
443 unsigned long tim
, limit
;
448 if (addr
>= high_memory
) {
451 if (((size_t)addr
& PAGE_MASK
) !=
452 ((size_t)(addr
+ len
- 1) & PAGE_MASK
))
454 p1
= vmalloc_to_page(addr
);
457 addr
= page_address(p1
) + ((size_t)addr
& ~PAGE_MASK
);
460 sg_init_one(&sg
, addr
, len
);
461 n
= dma_map_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
463 dev_err(&info
->pdev
->dev
,
464 "Couldn't DMA map a %d byte buffer\n", len
);
468 tx
= dmaengine_prep_slave_sg(info
->dma
, &sg
, n
,
469 is_write
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
470 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
474 tx
->callback
= omap_nand_dma_callback
;
475 tx
->callback_param
= &info
->comp
;
476 dmaengine_submit(tx
);
478 /* configure and start prefetch transfer */
479 ret
= omap_prefetch_enable(info
->gpmc_cs
,
480 PREFETCH_FIFOTHRESHOLD_MAX
, 0x1, len
, is_write
, info
);
482 /* PFPW engine is busy, use cpu copy method */
485 init_completion(&info
->comp
);
486 dma_async_issue_pending(info
->dma
);
488 /* setup and start DMA using dma_addr */
489 wait_for_completion(&info
->comp
);
491 limit
= (loops_per_jiffy
* msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
495 val
= readl(info
->reg
.gpmc_prefetch_status
);
496 val
= GPMC_PREFETCH_STATUS_COUNT(val
);
497 } while (val
&& (tim
++ < limit
));
499 /* disable and stop the PFPW engine */
500 omap_prefetch_reset(info
->gpmc_cs
, info
);
502 dma_unmap_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
506 dma_unmap_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
508 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
509 is_write
== 0 ? omap_read_buf16(mtd
, (u_char
*) addr
, len
)
510 : omap_write_buf16(mtd
, (u_char
*) addr
, len
);
512 is_write
== 0 ? omap_read_buf8(mtd
, (u_char
*) addr
, len
)
513 : omap_write_buf8(mtd
, (u_char
*) addr
, len
);
518 * omap_read_buf_dma_pref - read data from NAND controller into buffer
519 * @mtd: MTD device structure
520 * @buf: buffer to store date
521 * @len: number of bytes to read
523 static void omap_read_buf_dma_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
525 if (len
<= mtd
->oobsize
)
526 omap_read_buf_pref(mtd
, buf
, len
);
528 /* start transfer in DMA mode */
529 omap_nand_dma_transfer(mtd
, buf
, len
, 0x0);
533 * omap_write_buf_dma_pref - write buffer to NAND controller
534 * @mtd: MTD device structure
536 * @len: number of bytes to write
538 static void omap_write_buf_dma_pref(struct mtd_info
*mtd
,
539 const u_char
*buf
, int len
)
541 if (len
<= mtd
->oobsize
)
542 omap_write_buf_pref(mtd
, buf
, len
);
544 /* start transfer in DMA mode */
545 omap_nand_dma_transfer(mtd
, (u_char
*) buf
, len
, 0x1);
549 * omap_nand_irq - GPMC irq handler
550 * @this_irq: gpmc irq number
551 * @dev: omap_nand_info structure pointer is passed here
553 static irqreturn_t
omap_nand_irq(int this_irq
, void *dev
)
555 struct omap_nand_info
*info
= (struct omap_nand_info
*) dev
;
558 bytes
= readl(info
->reg
.gpmc_prefetch_status
);
559 bytes
= GPMC_PREFETCH_STATUS_FIFO_CNT(bytes
);
560 bytes
= bytes
& 0xFFFC; /* io in multiple of 4 bytes */
561 if (info
->iomode
== OMAP_NAND_IO_WRITE
) { /* checks for write io */
562 if (this_irq
== info
->gpmc_irq_count
)
565 if (info
->buf_len
&& (info
->buf_len
< bytes
))
566 bytes
= info
->buf_len
;
567 else if (!info
->buf_len
)
569 iowrite32_rep(info
->nand
.IO_ADDR_W
,
570 (u32
*)info
->buf
, bytes
>> 2);
571 info
->buf
= info
->buf
+ bytes
;
572 info
->buf_len
-= bytes
;
575 ioread32_rep(info
->nand
.IO_ADDR_R
,
576 (u32
*)info
->buf
, bytes
>> 2);
577 info
->buf
= info
->buf
+ bytes
;
579 if (this_irq
== info
->gpmc_irq_count
)
586 complete(&info
->comp
);
588 disable_irq_nosync(info
->gpmc_irq_fifo
);
589 disable_irq_nosync(info
->gpmc_irq_count
);
595 * omap_read_buf_irq_pref - read data from NAND controller into buffer
596 * @mtd: MTD device structure
597 * @buf: buffer to store date
598 * @len: number of bytes to read
600 static void omap_read_buf_irq_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
602 struct omap_nand_info
*info
= container_of(mtd
,
603 struct omap_nand_info
, mtd
);
606 if (len
<= mtd
->oobsize
) {
607 omap_read_buf_pref(mtd
, buf
, len
);
611 info
->iomode
= OMAP_NAND_IO_READ
;
613 init_completion(&info
->comp
);
615 /* configure and start prefetch transfer */
616 ret
= omap_prefetch_enable(info
->gpmc_cs
,
617 PREFETCH_FIFOTHRESHOLD_MAX
/2, 0x0, len
, 0x0, info
);
619 /* PFPW engine is busy, use cpu copy method */
624 enable_irq(info
->gpmc_irq_count
);
625 enable_irq(info
->gpmc_irq_fifo
);
627 /* waiting for read to complete */
628 wait_for_completion(&info
->comp
);
630 /* disable and stop the PFPW engine */
631 omap_prefetch_reset(info
->gpmc_cs
, info
);
635 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
636 omap_read_buf16(mtd
, buf
, len
);
638 omap_read_buf8(mtd
, buf
, len
);
642 * omap_write_buf_irq_pref - write buffer to NAND controller
643 * @mtd: MTD device structure
645 * @len: number of bytes to write
647 static void omap_write_buf_irq_pref(struct mtd_info
*mtd
,
648 const u_char
*buf
, int len
)
650 struct omap_nand_info
*info
= container_of(mtd
,
651 struct omap_nand_info
, mtd
);
653 unsigned long tim
, limit
;
656 if (len
<= mtd
->oobsize
) {
657 omap_write_buf_pref(mtd
, buf
, len
);
661 info
->iomode
= OMAP_NAND_IO_WRITE
;
662 info
->buf
= (u_char
*) buf
;
663 init_completion(&info
->comp
);
665 /* configure and start prefetch transfer : size=24 */
666 ret
= omap_prefetch_enable(info
->gpmc_cs
,
667 (PREFETCH_FIFOTHRESHOLD_MAX
* 3) / 8, 0x0, len
, 0x1, info
);
669 /* PFPW engine is busy, use cpu copy method */
674 enable_irq(info
->gpmc_irq_count
);
675 enable_irq(info
->gpmc_irq_fifo
);
677 /* waiting for write to complete */
678 wait_for_completion(&info
->comp
);
680 /* wait for data to flushed-out before reset the prefetch */
682 limit
= (loops_per_jiffy
* msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
684 val
= readl(info
->reg
.gpmc_prefetch_status
);
685 val
= GPMC_PREFETCH_STATUS_COUNT(val
);
687 } while (val
&& (tim
++ < limit
));
689 /* disable and stop the PFPW engine */
690 omap_prefetch_reset(info
->gpmc_cs
, info
);
694 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
695 omap_write_buf16(mtd
, buf
, len
);
697 omap_write_buf8(mtd
, buf
, len
);
701 * gen_true_ecc - This function will generate true ECC value
702 * @ecc_buf: buffer to store ecc code
704 * This generated true ECC value can be used when correcting
705 * data read from NAND flash memory core
707 static void gen_true_ecc(u8
*ecc_buf
)
709 u32 tmp
= ecc_buf
[0] | (ecc_buf
[1] << 16) |
710 ((ecc_buf
[2] & 0xF0) << 20) | ((ecc_buf
[2] & 0x0F) << 8);
712 ecc_buf
[0] = ~(P64o(tmp
) | P64e(tmp
) | P32o(tmp
) | P32e(tmp
) |
713 P16o(tmp
) | P16e(tmp
) | P8o(tmp
) | P8e(tmp
));
714 ecc_buf
[1] = ~(P1024o(tmp
) | P1024e(tmp
) | P512o(tmp
) | P512e(tmp
) |
715 P256o(tmp
) | P256e(tmp
) | P128o(tmp
) | P128e(tmp
));
716 ecc_buf
[2] = ~(P4o(tmp
) | P4e(tmp
) | P2o(tmp
) | P2e(tmp
) | P1o(tmp
) |
717 P1e(tmp
) | P2048o(tmp
) | P2048e(tmp
));
721 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
722 * @ecc_data1: ecc code from nand spare area
723 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
724 * @page_data: page data
726 * This function compares two ECC's and indicates if there is an error.
727 * If the error can be corrected it will be corrected to the buffer.
728 * If there is no error, %0 is returned. If there is an error but it
729 * was corrected, %1 is returned. Otherwise, %-1 is returned.
731 static int omap_compare_ecc(u8
*ecc_data1
, /* read from NAND memory */
732 u8
*ecc_data2
, /* read from register */
736 u8 tmp0_bit
[8], tmp1_bit
[8], tmp2_bit
[8];
737 u8 comp0_bit
[8], comp1_bit
[8], comp2_bit
[8];
744 isEccFF
= ((*(u32
*)ecc_data1
& 0xFFFFFF) == 0xFFFFFF);
746 gen_true_ecc(ecc_data1
);
747 gen_true_ecc(ecc_data2
);
749 for (i
= 0; i
<= 2; i
++) {
750 *(ecc_data1
+ i
) = ~(*(ecc_data1
+ i
));
751 *(ecc_data2
+ i
) = ~(*(ecc_data2
+ i
));
754 for (i
= 0; i
< 8; i
++) {
755 tmp0_bit
[i
] = *ecc_data1
% 2;
756 *ecc_data1
= *ecc_data1
/ 2;
759 for (i
= 0; i
< 8; i
++) {
760 tmp1_bit
[i
] = *(ecc_data1
+ 1) % 2;
761 *(ecc_data1
+ 1) = *(ecc_data1
+ 1) / 2;
764 for (i
= 0; i
< 8; i
++) {
765 tmp2_bit
[i
] = *(ecc_data1
+ 2) % 2;
766 *(ecc_data1
+ 2) = *(ecc_data1
+ 2) / 2;
769 for (i
= 0; i
< 8; i
++) {
770 comp0_bit
[i
] = *ecc_data2
% 2;
771 *ecc_data2
= *ecc_data2
/ 2;
774 for (i
= 0; i
< 8; i
++) {
775 comp1_bit
[i
] = *(ecc_data2
+ 1) % 2;
776 *(ecc_data2
+ 1) = *(ecc_data2
+ 1) / 2;
779 for (i
= 0; i
< 8; i
++) {
780 comp2_bit
[i
] = *(ecc_data2
+ 2) % 2;
781 *(ecc_data2
+ 2) = *(ecc_data2
+ 2) / 2;
784 for (i
= 0; i
< 6; i
++)
785 ecc_bit
[i
] = tmp2_bit
[i
+ 2] ^ comp2_bit
[i
+ 2];
787 for (i
= 0; i
< 8; i
++)
788 ecc_bit
[i
+ 6] = tmp0_bit
[i
] ^ comp0_bit
[i
];
790 for (i
= 0; i
< 8; i
++)
791 ecc_bit
[i
+ 14] = tmp1_bit
[i
] ^ comp1_bit
[i
];
793 ecc_bit
[22] = tmp2_bit
[0] ^ comp2_bit
[0];
794 ecc_bit
[23] = tmp2_bit
[1] ^ comp2_bit
[1];
796 for (i
= 0; i
< 24; i
++)
797 ecc_sum
+= ecc_bit
[i
];
801 /* Not reached because this function is not called if
802 * ECC values are equal
807 /* Uncorrectable error */
808 pr_debug("ECC UNCORRECTED_ERROR 1\n");
812 /* UN-Correctable error */
813 pr_debug("ECC UNCORRECTED_ERROR B\n");
817 /* Correctable error */
818 find_byte
= (ecc_bit
[23] << 8) +
828 find_bit
= (ecc_bit
[5] << 2) + (ecc_bit
[3] << 1) + ecc_bit
[1];
830 pr_debug("Correcting single bit ECC error at offset: "
831 "%d, bit: %d\n", find_byte
, find_bit
);
833 page_data
[find_byte
] ^= (1 << find_bit
);
838 if (ecc_data2
[0] == 0 &&
843 pr_debug("UNCORRECTED_ERROR default\n");
849 * omap_correct_data - Compares the ECC read with HW generated ECC
850 * @mtd: MTD device structure
852 * @read_ecc: ecc read from nand flash
853 * @calc_ecc: ecc read from HW ECC registers
855 * Compares the ecc read from nand spare area with ECC registers values
856 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
857 * detection and correction. If there are no errors, %0 is returned. If
858 * there were errors and all of the errors were corrected, the number of
859 * corrected errors is returned. If uncorrectable errors exist, %-1 is
862 static int omap_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
863 u_char
*read_ecc
, u_char
*calc_ecc
)
865 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
867 int blockCnt
= 0, i
= 0, ret
= 0;
870 /* Ex NAND_ECC_HW12_2048 */
871 if ((info
->nand
.ecc
.mode
== NAND_ECC_HW
) &&
872 (info
->nand
.ecc
.size
== 2048))
877 for (i
= 0; i
< blockCnt
; i
++) {
878 if (memcmp(read_ecc
, calc_ecc
, 3) != 0) {
879 ret
= omap_compare_ecc(read_ecc
, calc_ecc
, dat
);
882 /* keep track of the number of corrected errors */
893 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
894 * @mtd: MTD device structure
895 * @dat: The pointer to data on which ecc is computed
896 * @ecc_code: The ecc_code buffer
898 * Using noninverted ECC can be considered ugly since writing a blank
899 * page ie. padding will clear the ECC bytes. This is no problem as long
900 * nobody is trying to write data on the seemingly unused page. Reading
901 * an erased page will produce an ECC mismatch between generated and read
902 * ECC bytes that has to be dealt with separately.
904 static int omap_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
907 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
911 val
= readl(info
->reg
.gpmc_ecc_config
);
912 if (((val
>> ECC_CONFIG_CS_SHIFT
) & ~CS_MASK
) != info
->gpmc_cs
)
915 /* read ecc result */
916 val
= readl(info
->reg
.gpmc_ecc1_result
);
917 *ecc_code
++ = val
; /* P128e, ..., P1e */
918 *ecc_code
++ = val
>> 16; /* P128o, ..., P1o */
919 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
920 *ecc_code
++ = ((val
>> 8) & 0x0f) | ((val
>> 20) & 0xf0);
926 * omap_enable_hwecc - This function enables the hardware ecc functionality
927 * @mtd: MTD device structure
928 * @mode: Read/Write mode
930 static void omap_enable_hwecc(struct mtd_info
*mtd
, int mode
)
932 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
934 struct nand_chip
*chip
= mtd
->priv
;
935 unsigned int dev_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
938 /* clear ecc and enable bits */
939 val
= ECCCLEAR
| ECC1
;
940 writel(val
, info
->reg
.gpmc_ecc_control
);
942 /* program ecc and result sizes */
943 val
= ((((info
->nand
.ecc
.size
>> 1) - 1) << ECCSIZE1_SHIFT
) |
945 writel(val
, info
->reg
.gpmc_ecc_size_config
);
950 writel(ECCCLEAR
| ECC1
, info
->reg
.gpmc_ecc_control
);
952 case NAND_ECC_READSYN
:
953 writel(ECCCLEAR
, info
->reg
.gpmc_ecc_control
);
956 dev_info(&info
->pdev
->dev
,
957 "error: unrecognized Mode[%d]!\n", mode
);
961 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
962 val
= (dev_width
<< 7) | (info
->gpmc_cs
<< 1) | (0x1);
963 writel(val
, info
->reg
.gpmc_ecc_config
);
967 * omap_wait - wait until the command is done
968 * @mtd: MTD device structure
969 * @chip: NAND Chip structure
971 * Wait function is called during Program and erase operations and
972 * the way it is called from MTD layer, we should wait till the NAND
973 * chip is ready after the programming/erase operation has completed.
975 * Erase can take up to 400ms and program up to 20ms according to
976 * general NAND and SmartMedia specs
978 static int omap_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
980 struct nand_chip
*this = mtd
->priv
;
981 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
983 unsigned long timeo
= jiffies
;
984 int status
, state
= this->state
;
986 if (state
== FL_ERASING
)
987 timeo
+= (HZ
* 400) / 1000;
989 timeo
+= (HZ
* 20) / 1000;
991 writeb(NAND_CMD_STATUS
& 0xFF, info
->reg
.gpmc_nand_command
);
992 while (time_before(jiffies
, timeo
)) {
993 status
= readb(info
->reg
.gpmc_nand_data
);
994 if (status
& NAND_STATUS_READY
)
999 status
= gpmc_nand_read(info
->gpmc_cs
, GPMC_NAND_DATA
);
1004 * omap_dev_ready - calls the platform specific dev_ready function
1005 * @mtd: MTD device structure
1007 static int omap_dev_ready(struct mtd_info
*mtd
)
1009 unsigned int val
= 0;
1010 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1013 val
= readl(info
->reg
.gpmc_status
);
1015 if ((val
& 0x100) == 0x100) {
1022 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1025 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1026 * @mtd: MTD device structure
1027 * @mode: Read/Write mode
1029 static void omap3_enable_hwecc_bch(struct mtd_info
*mtd
, int mode
)
1032 unsigned int dev_width
;
1033 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1035 struct nand_chip
*chip
= mtd
->priv
;
1037 nerrors
= (info
->nand
.ecc
.bytes
== 13) ? 8 : 4;
1038 dev_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
1040 * Program GPMC to perform correction on one 512-byte sector at a time.
1041 * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
1042 * gives a slight (5%) performance gain (but requires additional code).
1044 (void)gpmc_enable_hwecc_bch(info
->gpmc_cs
, mode
, dev_width
, 1, nerrors
);
1048 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1049 * @mtd: MTD device structure
1050 * @dat: The pointer to data on which ecc is computed
1051 * @ecc_code: The ecc_code buffer
1053 static int omap3_calculate_ecc_bch4(struct mtd_info
*mtd
, const u_char
*dat
,
1056 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1058 return gpmc_calculate_ecc_bch4(info
->gpmc_cs
, dat
, ecc_code
);
1062 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1063 * @mtd: MTD device structure
1064 * @dat: The pointer to data on which ecc is computed
1065 * @ecc_code: The ecc_code buffer
1067 static int omap3_calculate_ecc_bch8(struct mtd_info
*mtd
, const u_char
*dat
,
1070 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1072 return gpmc_calculate_ecc_bch8(info
->gpmc_cs
, dat
, ecc_code
);
1076 * omap3_correct_data_bch - Decode received data and correct errors
1077 * @mtd: MTD device structure
1079 * @read_ecc: ecc read from nand flash
1080 * @calc_ecc: ecc read from HW ECC registers
1082 static int omap3_correct_data_bch(struct mtd_info
*mtd
, u_char
*data
,
1083 u_char
*read_ecc
, u_char
*calc_ecc
)
1086 /* cannot correct more than 8 errors */
1087 unsigned int errloc
[8];
1088 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1091 count
= decode_bch(info
->bch
, NULL
, 512, read_ecc
, calc_ecc
, NULL
,
1094 /* correct errors */
1095 for (i
= 0; i
< count
; i
++) {
1096 /* correct data only, not ecc bytes */
1097 if (errloc
[i
] < 8*512)
1098 data
[errloc
[i
]/8] ^= 1 << (errloc
[i
] & 7);
1099 pr_debug("corrected bitflip %u\n", errloc
[i
]);
1101 } else if (count
< 0) {
1102 pr_err("ecc unrecoverable error\n");
1108 * omap3_free_bch - Release BCH ecc resources
1109 * @mtd: MTD device structure
1111 static void omap3_free_bch(struct mtd_info
*mtd
)
1113 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1116 free_bch(info
->bch
);
1122 * omap3_init_bch - Initialize BCH ECC
1123 * @mtd: MTD device structure
1124 * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
1126 static int omap3_init_bch(struct mtd_info
*mtd
, int ecc_opt
)
1128 int ret
, max_errors
;
1129 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1131 #ifdef CONFIG_MTD_NAND_OMAP_BCH8
1132 const int hw_errors
= 8;
1134 const int hw_errors
= 4;
1138 max_errors
= (ecc_opt
== OMAP_ECC_BCH8_CODE_HW
) ? 8 : 4;
1139 if (max_errors
!= hw_errors
) {
1140 pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
1141 max_errors
, hw_errors
);
1145 /* initialize GPMC BCH engine */
1146 ret
= gpmc_init_hwecc_bch(info
->gpmc_cs
, 1, max_errors
);
1150 /* software bch library is only used to detect and locate errors */
1151 info
->bch
= init_bch(13, max_errors
, 0x201b /* hw polynomial */);
1155 info
->nand
.ecc
.size
= 512;
1156 info
->nand
.ecc
.hwctl
= omap3_enable_hwecc_bch
;
1157 info
->nand
.ecc
.correct
= omap3_correct_data_bch
;
1158 info
->nand
.ecc
.mode
= NAND_ECC_HW
;
1161 * The number of corrected errors in an ecc block that will trigger
1162 * block scrubbing defaults to the ecc strength (4 or 8).
1163 * Set mtd->bitflip_threshold here to define a custom threshold.
1166 if (max_errors
== 8) {
1167 info
->nand
.ecc
.strength
= 8;
1168 info
->nand
.ecc
.bytes
= 13;
1169 info
->nand
.ecc
.calculate
= omap3_calculate_ecc_bch8
;
1171 info
->nand
.ecc
.strength
= 4;
1172 info
->nand
.ecc
.bytes
= 7;
1173 info
->nand
.ecc
.calculate
= omap3_calculate_ecc_bch4
;
1176 pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors
);
1179 omap3_free_bch(mtd
);
1184 * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
1185 * @mtd: MTD device structure
1187 static int omap3_init_bch_tail(struct mtd_info
*mtd
)
1190 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1192 struct nand_ecclayout
*layout
= &info
->ecclayout
;
1194 /* build oob layout */
1195 steps
= mtd
->writesize
/info
->nand
.ecc
.size
;
1196 layout
->eccbytes
= steps
*info
->nand
.ecc
.bytes
;
1198 /* do not bother creating special oob layouts for small page devices */
1199 if (mtd
->oobsize
< 64) {
1200 pr_err("BCH ecc is not supported on small page devices\n");
1204 /* reserve 2 bytes for bad block marker */
1205 if (layout
->eccbytes
+2 > mtd
->oobsize
) {
1206 pr_err("no oob layout available for oobsize %d eccbytes %u\n",
1207 mtd
->oobsize
, layout
->eccbytes
);
1211 /* put ecc bytes at oob tail */
1212 for (i
= 0; i
< layout
->eccbytes
; i
++)
1213 layout
->eccpos
[i
] = mtd
->oobsize
-layout
->eccbytes
+i
;
1215 layout
->oobfree
[0].offset
= 2;
1216 layout
->oobfree
[0].length
= mtd
->oobsize
-2-layout
->eccbytes
;
1217 info
->nand
.ecc
.layout
= layout
;
1219 if (!(info
->nand
.options
& NAND_BUSWIDTH_16
))
1220 info
->nand
.badblock_pattern
= &bb_descrip_flashbased
;
1223 omap3_free_bch(mtd
);
1228 static int omap3_init_bch(struct mtd_info
*mtd
, int ecc_opt
)
1230 pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
1233 static int omap3_init_bch_tail(struct mtd_info
*mtd
)
1237 static void omap3_free_bch(struct mtd_info
*mtd
)
1240 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
1242 static int __devinit
omap_nand_probe(struct platform_device
*pdev
)
1244 struct omap_nand_info
*info
;
1245 struct omap_nand_platform_data
*pdata
;
1248 dma_cap_mask_t mask
;
1250 struct resource
*res
;
1252 pdata
= pdev
->dev
.platform_data
;
1253 if (pdata
== NULL
) {
1254 dev_err(&pdev
->dev
, "platform data missing\n");
1258 info
= kzalloc(sizeof(struct omap_nand_info
), GFP_KERNEL
);
1262 platform_set_drvdata(pdev
, info
);
1264 spin_lock_init(&info
->controller
.lock
);
1265 init_waitqueue_head(&info
->controller
.wq
);
1269 info
->gpmc_cs
= pdata
->cs
;
1270 info
->reg
= pdata
->reg
;
1272 info
->mtd
.priv
= &info
->nand
;
1273 info
->mtd
.name
= dev_name(&pdev
->dev
);
1274 info
->mtd
.owner
= THIS_MODULE
;
1276 info
->nand
.options
= pdata
->devsize
;
1277 info
->nand
.options
|= NAND_SKIP_BBTSCAN
;
1279 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1282 dev_err(&pdev
->dev
, "error getting memory resource\n");
1286 info
->phys_base
= res
->start
;
1287 info
->mem_size
= resource_size(res
);
1289 if (!request_mem_region(info
->phys_base
, info
->mem_size
,
1290 pdev
->dev
.driver
->name
)) {
1295 info
->nand
.IO_ADDR_R
= ioremap(info
->phys_base
, info
->mem_size
);
1296 if (!info
->nand
.IO_ADDR_R
) {
1298 goto out_release_mem_region
;
1301 info
->nand
.controller
= &info
->controller
;
1303 info
->nand
.IO_ADDR_W
= info
->nand
.IO_ADDR_R
;
1304 info
->nand
.cmd_ctrl
= omap_hwcontrol
;
1307 * If RDY/BSY line is connected to OMAP then use the omap ready
1308 * function and the generic nand_wait function which reads the status
1309 * register after monitoring the RDY/BSY line. Otherwise use a standard
1310 * chip delay which is slightly more than tR (AC Timing) of the NAND
1311 * device and read status register until you get a failure or success
1313 if (pdata
->dev_ready
) {
1314 info
->nand
.dev_ready
= omap_dev_ready
;
1315 info
->nand
.chip_delay
= 0;
1317 info
->nand
.waitfunc
= omap_wait
;
1318 info
->nand
.chip_delay
= 50;
1321 switch (pdata
->xfer_type
) {
1322 case NAND_OMAP_PREFETCH_POLLED
:
1323 info
->nand
.read_buf
= omap_read_buf_pref
;
1324 info
->nand
.write_buf
= omap_write_buf_pref
;
1327 case NAND_OMAP_POLLED
:
1328 if (info
->nand
.options
& NAND_BUSWIDTH_16
) {
1329 info
->nand
.read_buf
= omap_read_buf16
;
1330 info
->nand
.write_buf
= omap_write_buf16
;
1332 info
->nand
.read_buf
= omap_read_buf8
;
1333 info
->nand
.write_buf
= omap_write_buf8
;
1337 case NAND_OMAP_PREFETCH_DMA
:
1339 dma_cap_set(DMA_SLAVE
, mask
);
1340 sig
= OMAP24XX_DMA_GPMC
;
1341 info
->dma
= dma_request_channel(mask
, omap_dma_filter_fn
, &sig
);
1343 dev_err(&pdev
->dev
, "DMA engine request failed\n");
1345 goto out_release_mem_region
;
1347 struct dma_slave_config cfg
;
1349 memset(&cfg
, 0, sizeof(cfg
));
1350 cfg
.src_addr
= info
->phys_base
;
1351 cfg
.dst_addr
= info
->phys_base
;
1352 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1353 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1354 cfg
.src_maxburst
= 16;
1355 cfg
.dst_maxburst
= 16;
1356 err
= dmaengine_slave_config(info
->dma
, &cfg
);
1358 dev_err(&pdev
->dev
, "DMA engine slave config failed: %d\n",
1360 goto out_release_mem_region
;
1362 info
->nand
.read_buf
= omap_read_buf_dma_pref
;
1363 info
->nand
.write_buf
= omap_write_buf_dma_pref
;
1367 case NAND_OMAP_PREFETCH_IRQ
:
1368 info
->gpmc_irq_fifo
= platform_get_irq(pdev
, 0);
1369 if (info
->gpmc_irq_fifo
<= 0) {
1370 dev_err(&pdev
->dev
, "error getting fifo irq\n");
1372 goto out_release_mem_region
;
1374 err
= request_irq(info
->gpmc_irq_fifo
, omap_nand_irq
,
1375 IRQF_SHARED
, "gpmc-nand-fifo", info
);
1377 dev_err(&pdev
->dev
, "requesting irq(%d) error:%d",
1378 info
->gpmc_irq_fifo
, err
);
1379 info
->gpmc_irq_fifo
= 0;
1380 goto out_release_mem_region
;
1383 info
->gpmc_irq_count
= platform_get_irq(pdev
, 1);
1384 if (info
->gpmc_irq_count
<= 0) {
1385 dev_err(&pdev
->dev
, "error getting count irq\n");
1387 goto out_release_mem_region
;
1389 err
= request_irq(info
->gpmc_irq_count
, omap_nand_irq
,
1390 IRQF_SHARED
, "gpmc-nand-count", info
);
1392 dev_err(&pdev
->dev
, "requesting irq(%d) error:%d",
1393 info
->gpmc_irq_count
, err
);
1394 info
->gpmc_irq_count
= 0;
1395 goto out_release_mem_region
;
1398 info
->nand
.read_buf
= omap_read_buf_irq_pref
;
1399 info
->nand
.write_buf
= omap_write_buf_irq_pref
;
1405 "xfer_type(%d) not supported!\n", pdata
->xfer_type
);
1407 goto out_release_mem_region
;
1410 /* select the ecc type */
1411 if (pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_DEFAULT
)
1412 info
->nand
.ecc
.mode
= NAND_ECC_SOFT
;
1413 else if ((pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_HW
) ||
1414 (pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_HW_ROMCODE
)) {
1415 info
->nand
.ecc
.bytes
= 3;
1416 info
->nand
.ecc
.size
= 512;
1417 info
->nand
.ecc
.strength
= 1;
1418 info
->nand
.ecc
.calculate
= omap_calculate_ecc
;
1419 info
->nand
.ecc
.hwctl
= omap_enable_hwecc
;
1420 info
->nand
.ecc
.correct
= omap_correct_data
;
1421 info
->nand
.ecc
.mode
= NAND_ECC_HW
;
1422 } else if ((pdata
->ecc_opt
== OMAP_ECC_BCH4_CODE_HW
) ||
1423 (pdata
->ecc_opt
== OMAP_ECC_BCH8_CODE_HW
)) {
1424 err
= omap3_init_bch(&info
->mtd
, pdata
->ecc_opt
);
1427 goto out_release_mem_region
;
1431 /* DIP switches on some boards change between 8 and 16 bit
1432 * bus widths for flash. Try the other width if the first try fails.
1434 if (nand_scan_ident(&info
->mtd
, 1, NULL
)) {
1435 info
->nand
.options
^= NAND_BUSWIDTH_16
;
1436 if (nand_scan_ident(&info
->mtd
, 1, NULL
)) {
1438 goto out_release_mem_region
;
1442 /* rom code layout */
1443 if (pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_HW_ROMCODE
) {
1445 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
1449 info
->nand
.badblock_pattern
= &bb_descrip_flashbased
;
1451 omap_oobinfo
.eccbytes
= 3 * (info
->mtd
.oobsize
/16);
1452 for (i
= 0; i
< omap_oobinfo
.eccbytes
; i
++)
1453 omap_oobinfo
.eccpos
[i
] = i
+offset
;
1455 omap_oobinfo
.oobfree
->offset
= offset
+ omap_oobinfo
.eccbytes
;
1456 omap_oobinfo
.oobfree
->length
= info
->mtd
.oobsize
-
1457 (offset
+ omap_oobinfo
.eccbytes
);
1459 info
->nand
.ecc
.layout
= &omap_oobinfo
;
1460 } else if ((pdata
->ecc_opt
== OMAP_ECC_BCH4_CODE_HW
) ||
1461 (pdata
->ecc_opt
== OMAP_ECC_BCH8_CODE_HW
)) {
1462 /* build OOB layout for BCH ECC correction */
1463 err
= omap3_init_bch_tail(&info
->mtd
);
1466 goto out_release_mem_region
;
1470 /* second phase scan */
1471 if (nand_scan_tail(&info
->mtd
)) {
1473 goto out_release_mem_region
;
1476 mtd_device_parse_register(&info
->mtd
, NULL
, NULL
, pdata
->parts
,
1479 platform_set_drvdata(pdev
, &info
->mtd
);
1483 out_release_mem_region
:
1485 dma_release_channel(info
->dma
);
1486 if (info
->gpmc_irq_count
> 0)
1487 free_irq(info
->gpmc_irq_count
, info
);
1488 if (info
->gpmc_irq_fifo
> 0)
1489 free_irq(info
->gpmc_irq_fifo
, info
);
1490 release_mem_region(info
->phys_base
, info
->mem_size
);
1497 static int omap_nand_remove(struct platform_device
*pdev
)
1499 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1500 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1502 omap3_free_bch(&info
->mtd
);
1504 platform_set_drvdata(pdev
, NULL
);
1506 dma_release_channel(info
->dma
);
1508 if (info
->gpmc_irq_count
> 0)
1509 free_irq(info
->gpmc_irq_count
, info
);
1510 if (info
->gpmc_irq_fifo
> 0)
1511 free_irq(info
->gpmc_irq_fifo
, info
);
1513 /* Release NAND device, its internal structures and partitions */
1514 nand_release(&info
->mtd
);
1515 iounmap(info
->nand
.IO_ADDR_R
);
1516 release_mem_region(info
->phys_base
, NAND_IO_SIZE
);
1521 static struct platform_driver omap_nand_driver
= {
1522 .probe
= omap_nand_probe
,
1523 .remove
= omap_nand_remove
,
1525 .name
= DRIVER_NAME
,
1526 .owner
= THIS_MODULE
,
1530 module_platform_driver(omap_nand_driver
);
1532 MODULE_ALIAS("platform:" DRIVER_NAME
);
1533 MODULE_LICENSE("GPL");
1534 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");