2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
24 #include <linux/slab.h>
26 #ifdef CONFIG_MTD_NAND_OMAP_BCH
27 #include <linux/bch.h>
30 #include <plat-omap/dma-omap.h>
31 #include <linux/platform_data/mtd-nand-omap2.h>
33 #define DRIVER_NAME "omap2-nand"
34 #define OMAP_NAND_TIMEOUT_MS 5000
36 #define NAND_Ecc_P1e (1 << 0)
37 #define NAND_Ecc_P2e (1 << 1)
38 #define NAND_Ecc_P4e (1 << 2)
39 #define NAND_Ecc_P8e (1 << 3)
40 #define NAND_Ecc_P16e (1 << 4)
41 #define NAND_Ecc_P32e (1 << 5)
42 #define NAND_Ecc_P64e (1 << 6)
43 #define NAND_Ecc_P128e (1 << 7)
44 #define NAND_Ecc_P256e (1 << 8)
45 #define NAND_Ecc_P512e (1 << 9)
46 #define NAND_Ecc_P1024e (1 << 10)
47 #define NAND_Ecc_P2048e (1 << 11)
49 #define NAND_Ecc_P1o (1 << 16)
50 #define NAND_Ecc_P2o (1 << 17)
51 #define NAND_Ecc_P4o (1 << 18)
52 #define NAND_Ecc_P8o (1 << 19)
53 #define NAND_Ecc_P16o (1 << 20)
54 #define NAND_Ecc_P32o (1 << 21)
55 #define NAND_Ecc_P64o (1 << 22)
56 #define NAND_Ecc_P128o (1 << 23)
57 #define NAND_Ecc_P256o (1 << 24)
58 #define NAND_Ecc_P512o (1 << 25)
59 #define NAND_Ecc_P1024o (1 << 26)
60 #define NAND_Ecc_P2048o (1 << 27)
62 #define TF(value) (value ? 1 : 0)
64 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
73 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
82 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
91 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
100 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
103 #define PREFETCH_CONFIG1_CS_SHIFT 24
104 #define ECC_CONFIG_CS_SHIFT 1
106 #define ENABLE_PREFETCH (0x1 << 7)
107 #define DMA_MPU_MODE_SHIFT 2
108 #define ECCSIZE0_SHIFT 12
109 #define ECCSIZE1_SHIFT 22
110 #define ECC1RESULTSIZE 0x1
111 #define ECCCLEAR 0x100
113 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117 #define STATUS_BUFF_EMPTY 0x00000001
119 #define OMAP24XX_DMA_GPMC 4
121 /* oob info generated runtime depending on ecc algorithm and layout selected */
122 static struct nand_ecclayout omap_oobinfo
;
123 /* Define some generic bad / good block scan pattern which are used
124 * while scanning a device for factory marked good / bad blocks
126 static uint8_t scan_ff_pattern
[] = { 0xff };
127 static struct nand_bbt_descr bb_descrip_flashbased
= {
128 .options
= NAND_BBT_SCANEMPTY
| NAND_BBT_SCANALLPAGES
,
131 .pattern
= scan_ff_pattern
,
135 struct omap_nand_info
{
136 struct nand_hw_control controller
;
137 struct omap_nand_platform_data
*pdata
;
139 struct nand_chip nand
;
140 struct platform_device
*pdev
;
143 unsigned long phys_base
;
144 unsigned long mem_size
;
145 struct completion comp
;
146 struct dma_chan
*dma
;
150 OMAP_NAND_IO_READ
= 0, /* read */
151 OMAP_NAND_IO_WRITE
, /* write */
155 struct gpmc_nand_regs reg
;
157 #ifdef CONFIG_MTD_NAND_OMAP_BCH
158 struct bch_control
*bch
;
159 struct nand_ecclayout ecclayout
;
164 * omap_prefetch_enable - configures and starts prefetch transfer
165 * @cs: cs (chip select) number
166 * @fifo_th: fifo threshold to be used for read/ write
167 * @dma_mode: dma mode enable (1) or disable (0)
168 * @u32_count: number of bytes to be transferred
169 * @is_write: prefetch read(0) or write post(1) mode
171 static int omap_prefetch_enable(int cs
, int fifo_th
, int dma_mode
,
172 unsigned int u32_count
, int is_write
, struct omap_nand_info
*info
)
176 if (fifo_th
> PREFETCH_FIFOTHRESHOLD_MAX
)
179 if (readl(info
->reg
.gpmc_prefetch_control
))
182 /* Set the amount of bytes to be prefetched */
183 writel(u32_count
, info
->reg
.gpmc_prefetch_config2
);
185 /* Set dma/mpu mode, the prefetch read / post write and
186 * enable the engine. Set which cs is has requested for.
188 val
= ((cs
<< PREFETCH_CONFIG1_CS_SHIFT
) |
189 PREFETCH_FIFOTHRESHOLD(fifo_th
) | ENABLE_PREFETCH
|
190 (dma_mode
<< DMA_MPU_MODE_SHIFT
) | (0x1 & is_write
));
191 writel(val
, info
->reg
.gpmc_prefetch_config1
);
193 /* Start the prefetch engine */
194 writel(0x1, info
->reg
.gpmc_prefetch_control
);
200 * omap_prefetch_reset - disables and stops the prefetch engine
202 static int omap_prefetch_reset(int cs
, struct omap_nand_info
*info
)
206 /* check if the same module/cs is trying to reset */
207 config1
= readl(info
->reg
.gpmc_prefetch_config1
);
208 if (((config1
>> PREFETCH_CONFIG1_CS_SHIFT
) & CS_MASK
) != cs
)
211 /* Stop the PFPW engine */
212 writel(0x0, info
->reg
.gpmc_prefetch_control
);
214 /* Reset/disable the PFPW engine */
215 writel(0x0, info
->reg
.gpmc_prefetch_config1
);
221 * omap_hwcontrol - hardware specific access to control-lines
222 * @mtd: MTD device structure
223 * @cmd: command to device
225 * NAND_NCE: bit 0 -> don't care
226 * NAND_CLE: bit 1 -> Command Latch
227 * NAND_ALE: bit 2 -> Address Latch
229 * NOTE: boards may use different bits for these!!
231 static void omap_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
233 struct omap_nand_info
*info
= container_of(mtd
,
234 struct omap_nand_info
, mtd
);
236 if (cmd
!= NAND_CMD_NONE
) {
238 writeb(cmd
, info
->reg
.gpmc_nand_command
);
240 else if (ctrl
& NAND_ALE
)
241 writeb(cmd
, info
->reg
.gpmc_nand_address
);
244 writeb(cmd
, info
->reg
.gpmc_nand_data
);
249 * omap_read_buf8 - read data from NAND controller into buffer
250 * @mtd: MTD device structure
251 * @buf: buffer to store date
252 * @len: number of bytes to read
254 static void omap_read_buf8(struct mtd_info
*mtd
, u_char
*buf
, int len
)
256 struct nand_chip
*nand
= mtd
->priv
;
258 ioread8_rep(nand
->IO_ADDR_R
, buf
, len
);
262 * omap_write_buf8 - write buffer to NAND controller
263 * @mtd: MTD device structure
265 * @len: number of bytes to write
267 static void omap_write_buf8(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
269 struct omap_nand_info
*info
= container_of(mtd
,
270 struct omap_nand_info
, mtd
);
271 u_char
*p
= (u_char
*)buf
;
275 iowrite8(*p
++, info
->nand
.IO_ADDR_W
);
276 /* wait until buffer is available for write */
278 status
= readl(info
->reg
.gpmc_status
) &
285 * omap_read_buf16 - read data from NAND controller into buffer
286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
290 static void omap_read_buf16(struct mtd_info
*mtd
, u_char
*buf
, int len
)
292 struct nand_chip
*nand
= mtd
->priv
;
294 ioread16_rep(nand
->IO_ADDR_R
, buf
, len
/ 2);
298 * omap_write_buf16 - write buffer to NAND controller
299 * @mtd: MTD device structure
301 * @len: number of bytes to write
303 static void omap_write_buf16(struct mtd_info
*mtd
, const u_char
* buf
, int len
)
305 struct omap_nand_info
*info
= container_of(mtd
,
306 struct omap_nand_info
, mtd
);
307 u16
*p
= (u16
*) buf
;
309 /* FIXME try bursts of writesw() or DMA ... */
313 iowrite16(*p
++, info
->nand
.IO_ADDR_W
);
314 /* wait until buffer is available for write */
316 status
= readl(info
->reg
.gpmc_status
) &
323 * omap_read_buf_pref - read data from NAND controller into buffer
324 * @mtd: MTD device structure
325 * @buf: buffer to store date
326 * @len: number of bytes to read
328 static void omap_read_buf_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
330 struct omap_nand_info
*info
= container_of(mtd
,
331 struct omap_nand_info
, mtd
);
332 uint32_t r_count
= 0;
336 /* take care of subpage reads */
338 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
339 omap_read_buf16(mtd
, buf
, len
% 4);
341 omap_read_buf8(mtd
, buf
, len
% 4);
342 p
= (u32
*) (buf
+ len
% 4);
346 /* configure and start prefetch transfer */
347 ret
= omap_prefetch_enable(info
->gpmc_cs
,
348 PREFETCH_FIFOTHRESHOLD_MAX
, 0x0, len
, 0x0, info
);
350 /* PFPW engine is busy, use cpu copy method */
351 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
352 omap_read_buf16(mtd
, (u_char
*)p
, len
);
354 omap_read_buf8(mtd
, (u_char
*)p
, len
);
357 r_count
= readl(info
->reg
.gpmc_prefetch_status
);
358 r_count
= PREFETCH_STATUS_FIFO_CNT(r_count
);
359 r_count
= r_count
>> 2;
360 ioread32_rep(info
->nand
.IO_ADDR_R
, p
, r_count
);
364 /* disable and stop the PFPW engine */
365 omap_prefetch_reset(info
->gpmc_cs
, info
);
370 * omap_write_buf_pref - write buffer to NAND controller
371 * @mtd: MTD device structure
373 * @len: number of bytes to write
375 static void omap_write_buf_pref(struct mtd_info
*mtd
,
376 const u_char
*buf
, int len
)
378 struct omap_nand_info
*info
= container_of(mtd
,
379 struct omap_nand_info
, mtd
);
380 uint32_t w_count
= 0;
383 unsigned long tim
, limit
;
386 /* take care of subpage writes */
388 writeb(*buf
, info
->nand
.IO_ADDR_W
);
389 p
= (u16
*)(buf
+ 1);
393 /* configure and start prefetch transfer */
394 ret
= omap_prefetch_enable(info
->gpmc_cs
,
395 PREFETCH_FIFOTHRESHOLD_MAX
, 0x0, len
, 0x1, info
);
397 /* PFPW engine is busy, use cpu copy method */
398 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
399 omap_write_buf16(mtd
, (u_char
*)p
, len
);
401 omap_write_buf8(mtd
, (u_char
*)p
, len
);
404 w_count
= readl(info
->reg
.gpmc_prefetch_status
);
405 w_count
= PREFETCH_STATUS_FIFO_CNT(w_count
);
406 w_count
= w_count
>> 1;
407 for (i
= 0; (i
< w_count
) && len
; i
++, len
-= 2)
408 iowrite16(*p
++, info
->nand
.IO_ADDR_W
);
410 /* wait for data to flushed-out before reset the prefetch */
412 limit
= (loops_per_jiffy
*
413 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
416 val
= readl(info
->reg
.gpmc_prefetch_status
);
417 val
= PREFETCH_STATUS_COUNT(val
);
418 } while (val
&& (tim
++ < limit
));
420 /* disable and stop the PFPW engine */
421 omap_prefetch_reset(info
->gpmc_cs
, info
);
426 * omap_nand_dma_callback: callback on the completion of dma transfer
427 * @data: pointer to completion data structure
429 static void omap_nand_dma_callback(void *data
)
431 complete((struct completion
*) data
);
435 * omap_nand_dma_transfer: configure and start dma transfer
436 * @mtd: MTD device structure
437 * @addr: virtual address in RAM of source/destination
438 * @len: number of data bytes to be transferred
439 * @is_write: flag for read/write operation
441 static inline int omap_nand_dma_transfer(struct mtd_info
*mtd
, void *addr
,
442 unsigned int len
, int is_write
)
444 struct omap_nand_info
*info
= container_of(mtd
,
445 struct omap_nand_info
, mtd
);
446 struct dma_async_tx_descriptor
*tx
;
447 enum dma_data_direction dir
= is_write
? DMA_TO_DEVICE
:
449 struct scatterlist sg
;
450 unsigned long tim
, limit
;
455 if (addr
>= high_memory
) {
458 if (((size_t)addr
& PAGE_MASK
) !=
459 ((size_t)(addr
+ len
- 1) & PAGE_MASK
))
461 p1
= vmalloc_to_page(addr
);
464 addr
= page_address(p1
) + ((size_t)addr
& ~PAGE_MASK
);
467 sg_init_one(&sg
, addr
, len
);
468 n
= dma_map_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
470 dev_err(&info
->pdev
->dev
,
471 "Couldn't DMA map a %d byte buffer\n", len
);
475 tx
= dmaengine_prep_slave_sg(info
->dma
, &sg
, n
,
476 is_write
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
477 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
481 tx
->callback
= omap_nand_dma_callback
;
482 tx
->callback_param
= &info
->comp
;
483 dmaengine_submit(tx
);
485 /* configure and start prefetch transfer */
486 ret
= omap_prefetch_enable(info
->gpmc_cs
,
487 PREFETCH_FIFOTHRESHOLD_MAX
, 0x1, len
, is_write
, info
);
489 /* PFPW engine is busy, use cpu copy method */
492 init_completion(&info
->comp
);
493 dma_async_issue_pending(info
->dma
);
495 /* setup and start DMA using dma_addr */
496 wait_for_completion(&info
->comp
);
498 limit
= (loops_per_jiffy
* msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
502 val
= readl(info
->reg
.gpmc_prefetch_status
);
503 val
= PREFETCH_STATUS_COUNT(val
);
504 } while (val
&& (tim
++ < limit
));
506 /* disable and stop the PFPW engine */
507 omap_prefetch_reset(info
->gpmc_cs
, info
);
509 dma_unmap_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
513 dma_unmap_sg(info
->dma
->device
->dev
, &sg
, 1, dir
);
515 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
516 is_write
== 0 ? omap_read_buf16(mtd
, (u_char
*) addr
, len
)
517 : omap_write_buf16(mtd
, (u_char
*) addr
, len
);
519 is_write
== 0 ? omap_read_buf8(mtd
, (u_char
*) addr
, len
)
520 : omap_write_buf8(mtd
, (u_char
*) addr
, len
);
525 * omap_read_buf_dma_pref - read data from NAND controller into buffer
526 * @mtd: MTD device structure
527 * @buf: buffer to store date
528 * @len: number of bytes to read
530 static void omap_read_buf_dma_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
532 if (len
<= mtd
->oobsize
)
533 omap_read_buf_pref(mtd
, buf
, len
);
535 /* start transfer in DMA mode */
536 omap_nand_dma_transfer(mtd
, buf
, len
, 0x0);
540 * omap_write_buf_dma_pref - write buffer to NAND controller
541 * @mtd: MTD device structure
543 * @len: number of bytes to write
545 static void omap_write_buf_dma_pref(struct mtd_info
*mtd
,
546 const u_char
*buf
, int len
)
548 if (len
<= mtd
->oobsize
)
549 omap_write_buf_pref(mtd
, buf
, len
);
551 /* start transfer in DMA mode */
552 omap_nand_dma_transfer(mtd
, (u_char
*) buf
, len
, 0x1);
556 * omap_nand_irq - GPMC irq handler
557 * @this_irq: gpmc irq number
558 * @dev: omap_nand_info structure pointer is passed here
560 static irqreturn_t
omap_nand_irq(int this_irq
, void *dev
)
562 struct omap_nand_info
*info
= (struct omap_nand_info
*) dev
;
565 bytes
= readl(info
->reg
.gpmc_prefetch_status
);
566 bytes
= PREFETCH_STATUS_FIFO_CNT(bytes
);
567 bytes
= bytes
& 0xFFFC; /* io in multiple of 4 bytes */
568 if (info
->iomode
== OMAP_NAND_IO_WRITE
) { /* checks for write io */
569 if (this_irq
== info
->gpmc_irq_count
)
572 if (info
->buf_len
&& (info
->buf_len
< bytes
))
573 bytes
= info
->buf_len
;
574 else if (!info
->buf_len
)
576 iowrite32_rep(info
->nand
.IO_ADDR_W
,
577 (u32
*)info
->buf
, bytes
>> 2);
578 info
->buf
= info
->buf
+ bytes
;
579 info
->buf_len
-= bytes
;
582 ioread32_rep(info
->nand
.IO_ADDR_R
,
583 (u32
*)info
->buf
, bytes
>> 2);
584 info
->buf
= info
->buf
+ bytes
;
586 if (this_irq
== info
->gpmc_irq_count
)
593 complete(&info
->comp
);
595 disable_irq_nosync(info
->gpmc_irq_fifo
);
596 disable_irq_nosync(info
->gpmc_irq_count
);
602 * omap_read_buf_irq_pref - read data from NAND controller into buffer
603 * @mtd: MTD device structure
604 * @buf: buffer to store date
605 * @len: number of bytes to read
607 static void omap_read_buf_irq_pref(struct mtd_info
*mtd
, u_char
*buf
, int len
)
609 struct omap_nand_info
*info
= container_of(mtd
,
610 struct omap_nand_info
, mtd
);
613 if (len
<= mtd
->oobsize
) {
614 omap_read_buf_pref(mtd
, buf
, len
);
618 info
->iomode
= OMAP_NAND_IO_READ
;
620 init_completion(&info
->comp
);
622 /* configure and start prefetch transfer */
623 ret
= omap_prefetch_enable(info
->gpmc_cs
,
624 PREFETCH_FIFOTHRESHOLD_MAX
/2, 0x0, len
, 0x0, info
);
626 /* PFPW engine is busy, use cpu copy method */
631 enable_irq(info
->gpmc_irq_count
);
632 enable_irq(info
->gpmc_irq_fifo
);
634 /* waiting for read to complete */
635 wait_for_completion(&info
->comp
);
637 /* disable and stop the PFPW engine */
638 omap_prefetch_reset(info
->gpmc_cs
, info
);
642 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
643 omap_read_buf16(mtd
, buf
, len
);
645 omap_read_buf8(mtd
, buf
, len
);
649 * omap_write_buf_irq_pref - write buffer to NAND controller
650 * @mtd: MTD device structure
652 * @len: number of bytes to write
654 static void omap_write_buf_irq_pref(struct mtd_info
*mtd
,
655 const u_char
*buf
, int len
)
657 struct omap_nand_info
*info
= container_of(mtd
,
658 struct omap_nand_info
, mtd
);
660 unsigned long tim
, limit
;
663 if (len
<= mtd
->oobsize
) {
664 omap_write_buf_pref(mtd
, buf
, len
);
668 info
->iomode
= OMAP_NAND_IO_WRITE
;
669 info
->buf
= (u_char
*) buf
;
670 init_completion(&info
->comp
);
672 /* configure and start prefetch transfer : size=24 */
673 ret
= omap_prefetch_enable(info
->gpmc_cs
,
674 (PREFETCH_FIFOTHRESHOLD_MAX
* 3) / 8, 0x0, len
, 0x1, info
);
676 /* PFPW engine is busy, use cpu copy method */
681 enable_irq(info
->gpmc_irq_count
);
682 enable_irq(info
->gpmc_irq_fifo
);
684 /* waiting for write to complete */
685 wait_for_completion(&info
->comp
);
687 /* wait for data to flushed-out before reset the prefetch */
689 limit
= (loops_per_jiffy
* msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS
));
691 val
= readl(info
->reg
.gpmc_prefetch_status
);
692 val
= PREFETCH_STATUS_COUNT(val
);
694 } while (val
&& (tim
++ < limit
));
696 /* disable and stop the PFPW engine */
697 omap_prefetch_reset(info
->gpmc_cs
, info
);
701 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
702 omap_write_buf16(mtd
, buf
, len
);
704 omap_write_buf8(mtd
, buf
, len
);
708 * gen_true_ecc - This function will generate true ECC value
709 * @ecc_buf: buffer to store ecc code
711 * This generated true ECC value can be used when correcting
712 * data read from NAND flash memory core
714 static void gen_true_ecc(u8
*ecc_buf
)
716 u32 tmp
= ecc_buf
[0] | (ecc_buf
[1] << 16) |
717 ((ecc_buf
[2] & 0xF0) << 20) | ((ecc_buf
[2] & 0x0F) << 8);
719 ecc_buf
[0] = ~(P64o(tmp
) | P64e(tmp
) | P32o(tmp
) | P32e(tmp
) |
720 P16o(tmp
) | P16e(tmp
) | P8o(tmp
) | P8e(tmp
));
721 ecc_buf
[1] = ~(P1024o(tmp
) | P1024e(tmp
) | P512o(tmp
) | P512e(tmp
) |
722 P256o(tmp
) | P256e(tmp
) | P128o(tmp
) | P128e(tmp
));
723 ecc_buf
[2] = ~(P4o(tmp
) | P4e(tmp
) | P2o(tmp
) | P2e(tmp
) | P1o(tmp
) |
724 P1e(tmp
) | P2048o(tmp
) | P2048e(tmp
));
728 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
729 * @ecc_data1: ecc code from nand spare area
730 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
731 * @page_data: page data
733 * This function compares two ECC's and indicates if there is an error.
734 * If the error can be corrected it will be corrected to the buffer.
735 * If there is no error, %0 is returned. If there is an error but it
736 * was corrected, %1 is returned. Otherwise, %-1 is returned.
738 static int omap_compare_ecc(u8
*ecc_data1
, /* read from NAND memory */
739 u8
*ecc_data2
, /* read from register */
743 u8 tmp0_bit
[8], tmp1_bit
[8], tmp2_bit
[8];
744 u8 comp0_bit
[8], comp1_bit
[8], comp2_bit
[8];
751 isEccFF
= ((*(u32
*)ecc_data1
& 0xFFFFFF) == 0xFFFFFF);
753 gen_true_ecc(ecc_data1
);
754 gen_true_ecc(ecc_data2
);
756 for (i
= 0; i
<= 2; i
++) {
757 *(ecc_data1
+ i
) = ~(*(ecc_data1
+ i
));
758 *(ecc_data2
+ i
) = ~(*(ecc_data2
+ i
));
761 for (i
= 0; i
< 8; i
++) {
762 tmp0_bit
[i
] = *ecc_data1
% 2;
763 *ecc_data1
= *ecc_data1
/ 2;
766 for (i
= 0; i
< 8; i
++) {
767 tmp1_bit
[i
] = *(ecc_data1
+ 1) % 2;
768 *(ecc_data1
+ 1) = *(ecc_data1
+ 1) / 2;
771 for (i
= 0; i
< 8; i
++) {
772 tmp2_bit
[i
] = *(ecc_data1
+ 2) % 2;
773 *(ecc_data1
+ 2) = *(ecc_data1
+ 2) / 2;
776 for (i
= 0; i
< 8; i
++) {
777 comp0_bit
[i
] = *ecc_data2
% 2;
778 *ecc_data2
= *ecc_data2
/ 2;
781 for (i
= 0; i
< 8; i
++) {
782 comp1_bit
[i
] = *(ecc_data2
+ 1) % 2;
783 *(ecc_data2
+ 1) = *(ecc_data2
+ 1) / 2;
786 for (i
= 0; i
< 8; i
++) {
787 comp2_bit
[i
] = *(ecc_data2
+ 2) % 2;
788 *(ecc_data2
+ 2) = *(ecc_data2
+ 2) / 2;
791 for (i
= 0; i
< 6; i
++)
792 ecc_bit
[i
] = tmp2_bit
[i
+ 2] ^ comp2_bit
[i
+ 2];
794 for (i
= 0; i
< 8; i
++)
795 ecc_bit
[i
+ 6] = tmp0_bit
[i
] ^ comp0_bit
[i
];
797 for (i
= 0; i
< 8; i
++)
798 ecc_bit
[i
+ 14] = tmp1_bit
[i
] ^ comp1_bit
[i
];
800 ecc_bit
[22] = tmp2_bit
[0] ^ comp2_bit
[0];
801 ecc_bit
[23] = tmp2_bit
[1] ^ comp2_bit
[1];
803 for (i
= 0; i
< 24; i
++)
804 ecc_sum
+= ecc_bit
[i
];
808 /* Not reached because this function is not called if
809 * ECC values are equal
814 /* Uncorrectable error */
815 pr_debug("ECC UNCORRECTED_ERROR 1\n");
819 /* UN-Correctable error */
820 pr_debug("ECC UNCORRECTED_ERROR B\n");
824 /* Correctable error */
825 find_byte
= (ecc_bit
[23] << 8) +
835 find_bit
= (ecc_bit
[5] << 2) + (ecc_bit
[3] << 1) + ecc_bit
[1];
837 pr_debug("Correcting single bit ECC error at offset: "
838 "%d, bit: %d\n", find_byte
, find_bit
);
840 page_data
[find_byte
] ^= (1 << find_bit
);
845 if (ecc_data2
[0] == 0 &&
850 pr_debug("UNCORRECTED_ERROR default\n");
856 * omap_correct_data - Compares the ECC read with HW generated ECC
857 * @mtd: MTD device structure
859 * @read_ecc: ecc read from nand flash
860 * @calc_ecc: ecc read from HW ECC registers
862 * Compares the ecc read from nand spare area with ECC registers values
863 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
864 * detection and correction. If there are no errors, %0 is returned. If
865 * there were errors and all of the errors were corrected, the number of
866 * corrected errors is returned. If uncorrectable errors exist, %-1 is
869 static int omap_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
870 u_char
*read_ecc
, u_char
*calc_ecc
)
872 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
874 int blockCnt
= 0, i
= 0, ret
= 0;
877 /* Ex NAND_ECC_HW12_2048 */
878 if ((info
->nand
.ecc
.mode
== NAND_ECC_HW
) &&
879 (info
->nand
.ecc
.size
== 2048))
884 for (i
= 0; i
< blockCnt
; i
++) {
885 if (memcmp(read_ecc
, calc_ecc
, 3) != 0) {
886 ret
= omap_compare_ecc(read_ecc
, calc_ecc
, dat
);
889 /* keep track of the number of corrected errors */
900 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
901 * @mtd: MTD device structure
902 * @dat: The pointer to data on which ecc is computed
903 * @ecc_code: The ecc_code buffer
905 * Using noninverted ECC can be considered ugly since writing a blank
906 * page ie. padding will clear the ECC bytes. This is no problem as long
907 * nobody is trying to write data on the seemingly unused page. Reading
908 * an erased page will produce an ECC mismatch between generated and read
909 * ECC bytes that has to be dealt with separately.
911 static int omap_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
914 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
918 val
= readl(info
->reg
.gpmc_ecc_config
);
919 if (((val
>> ECC_CONFIG_CS_SHIFT
) & ~CS_MASK
) != info
->gpmc_cs
)
922 /* read ecc result */
923 val
= readl(info
->reg
.gpmc_ecc1_result
);
924 *ecc_code
++ = val
; /* P128e, ..., P1e */
925 *ecc_code
++ = val
>> 16; /* P128o, ..., P1o */
926 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
927 *ecc_code
++ = ((val
>> 8) & 0x0f) | ((val
>> 20) & 0xf0);
933 * omap_enable_hwecc - This function enables the hardware ecc functionality
934 * @mtd: MTD device structure
935 * @mode: Read/Write mode
937 static void omap_enable_hwecc(struct mtd_info
*mtd
, int mode
)
939 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
941 struct nand_chip
*chip
= mtd
->priv
;
942 unsigned int dev_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
945 /* clear ecc and enable bits */
946 val
= ECCCLEAR
| ECC1
;
947 writel(val
, info
->reg
.gpmc_ecc_control
);
949 /* program ecc and result sizes */
950 val
= ((((info
->nand
.ecc
.size
>> 1) - 1) << ECCSIZE1_SHIFT
) |
952 writel(val
, info
->reg
.gpmc_ecc_size_config
);
957 writel(ECCCLEAR
| ECC1
, info
->reg
.gpmc_ecc_control
);
959 case NAND_ECC_READSYN
:
960 writel(ECCCLEAR
, info
->reg
.gpmc_ecc_control
);
963 dev_info(&info
->pdev
->dev
,
964 "error: unrecognized Mode[%d]!\n", mode
);
968 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
969 val
= (dev_width
<< 7) | (info
->gpmc_cs
<< 1) | (0x1);
970 writel(val
, info
->reg
.gpmc_ecc_config
);
974 * omap_wait - wait until the command is done
975 * @mtd: MTD device structure
976 * @chip: NAND Chip structure
978 * Wait function is called during Program and erase operations and
979 * the way it is called from MTD layer, we should wait till the NAND
980 * chip is ready after the programming/erase operation has completed.
982 * Erase can take up to 400ms and program up to 20ms according to
983 * general NAND and SmartMedia specs
985 static int omap_wait(struct mtd_info
*mtd
, struct nand_chip
*chip
)
987 struct nand_chip
*this = mtd
->priv
;
988 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
990 unsigned long timeo
= jiffies
;
991 int status
, state
= this->state
;
993 if (state
== FL_ERASING
)
994 timeo
+= (HZ
* 400) / 1000;
996 timeo
+= (HZ
* 20) / 1000;
998 writeb(NAND_CMD_STATUS
& 0xFF, info
->reg
.gpmc_nand_command
);
999 while (time_before(jiffies
, timeo
)) {
1000 status
= readb(info
->reg
.gpmc_nand_data
);
1001 if (status
& NAND_STATUS_READY
)
1006 status
= readb(info
->reg
.gpmc_nand_data
);
1011 * omap_dev_ready - calls the platform specific dev_ready function
1012 * @mtd: MTD device structure
1014 static int omap_dev_ready(struct mtd_info
*mtd
)
1016 unsigned int val
= 0;
1017 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1020 val
= readl(info
->reg
.gpmc_status
);
1022 if ((val
& 0x100) == 0x100) {
1029 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1032 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1033 * @mtd: MTD device structure
1034 * @mode: Read/Write mode
1036 static void omap3_enable_hwecc_bch(struct mtd_info
*mtd
, int mode
)
1039 unsigned int dev_width
, nsectors
;
1040 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1042 struct nand_chip
*chip
= mtd
->priv
;
1045 nerrors
= (info
->nand
.ecc
.bytes
== 13) ? 8 : 4;
1046 dev_width
= (chip
->options
& NAND_BUSWIDTH_16
) ? 1 : 0;
1049 * Program GPMC to perform correction on one 512-byte sector at a time.
1050 * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
1051 * gives a slight (5%) performance gain (but requires additional code).
1054 writel(ECC1
, info
->reg
.gpmc_ecc_control
);
1057 * When using BCH, sector size is hardcoded to 512 bytes.
1058 * Here we are using wrapping mode 6 both for reading and writing, with:
1059 * size0 = 0 (no additional protected byte in spare area)
1060 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1062 val
= (32 << ECCSIZE1_SHIFT
) | (0 << ECCSIZE0_SHIFT
);
1063 writel(val
, info
->reg
.gpmc_ecc_size_config
);
1065 /* BCH configuration */
1066 val
= ((1 << 16) | /* enable BCH */
1067 (((nerrors
== 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1068 (0x06 << 8) | /* wrap mode = 6 */
1069 (dev_width
<< 7) | /* bus width */
1070 (((nsectors
-1) & 0x7) << 4) | /* number of sectors */
1071 (info
->gpmc_cs
<< 1) | /* ECC CS */
1072 (0x1)); /* enable ECC */
1074 writel(val
, info
->reg
.gpmc_ecc_config
);
1076 /* clear ecc and enable bits */
1077 writel(ECCCLEAR
| ECC1
, info
->reg
.gpmc_ecc_control
);
1081 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1082 * @mtd: MTD device structure
1083 * @dat: The pointer to data on which ecc is computed
1084 * @ecc_code: The ecc_code buffer
1086 static int omap3_calculate_ecc_bch4(struct mtd_info
*mtd
, const u_char
*dat
,
1089 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1091 unsigned long nsectors
, val1
, val2
;
1094 nsectors
= ((readl(info
->reg
.gpmc_ecc_config
) >> 4) & 0x7) + 1;
1096 for (i
= 0; i
< nsectors
; i
++) {
1098 /* Read hw-computed remainder */
1099 val1
= readl(info
->reg
.gpmc_bch_result0
[i
]);
1100 val2
= readl(info
->reg
.gpmc_bch_result1
[i
]);
1103 * Add constant polynomial to remainder, in order to get an ecc
1104 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1105 * left-justify the resulting polynomial.
1107 *ecc_code
++ = 0x28 ^ ((val2
>> 12) & 0xFF);
1108 *ecc_code
++ = 0x13 ^ ((val2
>> 4) & 0xFF);
1109 *ecc_code
++ = 0xcc ^ (((val2
& 0xF) << 4)|((val1
>> 28) & 0xF));
1110 *ecc_code
++ = 0x39 ^ ((val1
>> 20) & 0xFF);
1111 *ecc_code
++ = 0x96 ^ ((val1
>> 12) & 0xFF);
1112 *ecc_code
++ = 0xac ^ ((val1
>> 4) & 0xFF);
1113 *ecc_code
++ = 0x7f ^ ((val1
& 0xF) << 4);
1120 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1121 * @mtd: MTD device structure
1122 * @dat: The pointer to data on which ecc is computed
1123 * @ecc_code: The ecc_code buffer
1125 static int omap3_calculate_ecc_bch8(struct mtd_info
*mtd
, const u_char
*dat
,
1128 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1130 unsigned long nsectors
, val1
, val2
, val3
, val4
;
1133 nsectors
= ((readl(info
->reg
.gpmc_ecc_config
) >> 4) & 0x7) + 1;
1135 for (i
= 0; i
< nsectors
; i
++) {
1137 /* Read hw-computed remainder */
1138 val1
= readl(info
->reg
.gpmc_bch_result0
[i
]);
1139 val2
= readl(info
->reg
.gpmc_bch_result1
[i
]);
1140 val3
= readl(info
->reg
.gpmc_bch_result2
[i
]);
1141 val4
= readl(info
->reg
.gpmc_bch_result3
[i
]);
1144 * Add constant polynomial to remainder, in order to get an ecc
1145 * sequence of 0xFFs for a buffer filled with 0xFFs.
1147 *ecc_code
++ = 0xef ^ (val4
& 0xFF);
1148 *ecc_code
++ = 0x51 ^ ((val3
>> 24) & 0xFF);
1149 *ecc_code
++ = 0x2e ^ ((val3
>> 16) & 0xFF);
1150 *ecc_code
++ = 0x09 ^ ((val3
>> 8) & 0xFF);
1151 *ecc_code
++ = 0xed ^ (val3
& 0xFF);
1152 *ecc_code
++ = 0x93 ^ ((val2
>> 24) & 0xFF);
1153 *ecc_code
++ = 0x9a ^ ((val2
>> 16) & 0xFF);
1154 *ecc_code
++ = 0xc2 ^ ((val2
>> 8) & 0xFF);
1155 *ecc_code
++ = 0x97 ^ (val2
& 0xFF);
1156 *ecc_code
++ = 0x79 ^ ((val1
>> 24) & 0xFF);
1157 *ecc_code
++ = 0xe5 ^ ((val1
>> 16) & 0xFF);
1158 *ecc_code
++ = 0x24 ^ ((val1
>> 8) & 0xFF);
1159 *ecc_code
++ = 0xb5 ^ (val1
& 0xFF);
1166 * omap3_correct_data_bch - Decode received data and correct errors
1167 * @mtd: MTD device structure
1169 * @read_ecc: ecc read from nand flash
1170 * @calc_ecc: ecc read from HW ECC registers
1172 static int omap3_correct_data_bch(struct mtd_info
*mtd
, u_char
*data
,
1173 u_char
*read_ecc
, u_char
*calc_ecc
)
1176 /* cannot correct more than 8 errors */
1177 unsigned int errloc
[8];
1178 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1181 count
= decode_bch(info
->bch
, NULL
, 512, read_ecc
, calc_ecc
, NULL
,
1184 /* correct errors */
1185 for (i
= 0; i
< count
; i
++) {
1186 /* correct data only, not ecc bytes */
1187 if (errloc
[i
] < 8*512)
1188 data
[errloc
[i
]/8] ^= 1 << (errloc
[i
] & 7);
1189 pr_debug("corrected bitflip %u\n", errloc
[i
]);
1191 } else if (count
< 0) {
1192 pr_err("ecc unrecoverable error\n");
1198 * omap3_free_bch - Release BCH ecc resources
1199 * @mtd: MTD device structure
1201 static void omap3_free_bch(struct mtd_info
*mtd
)
1203 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1206 free_bch(info
->bch
);
1212 * omap3_init_bch - Initialize BCH ECC
1213 * @mtd: MTD device structure
1214 * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
1216 static int omap3_init_bch(struct mtd_info
*mtd
, int ecc_opt
)
1219 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1221 #ifdef CONFIG_MTD_NAND_OMAP_BCH8
1222 const int hw_errors
= 8;
1224 const int hw_errors
= 4;
1228 max_errors
= (ecc_opt
== OMAP_ECC_BCH8_CODE_HW
) ? 8 : 4;
1229 if (max_errors
!= hw_errors
) {
1230 pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
1231 max_errors
, hw_errors
);
1235 /* software bch library is only used to detect and locate errors */
1236 info
->bch
= init_bch(13, max_errors
, 0x201b /* hw polynomial */);
1240 info
->nand
.ecc
.size
= 512;
1241 info
->nand
.ecc
.hwctl
= omap3_enable_hwecc_bch
;
1242 info
->nand
.ecc
.correct
= omap3_correct_data_bch
;
1243 info
->nand
.ecc
.mode
= NAND_ECC_HW
;
1246 * The number of corrected errors in an ecc block that will trigger
1247 * block scrubbing defaults to the ecc strength (4 or 8).
1248 * Set mtd->bitflip_threshold here to define a custom threshold.
1251 if (max_errors
== 8) {
1252 info
->nand
.ecc
.strength
= 8;
1253 info
->nand
.ecc
.bytes
= 13;
1254 info
->nand
.ecc
.calculate
= omap3_calculate_ecc_bch8
;
1256 info
->nand
.ecc
.strength
= 4;
1257 info
->nand
.ecc
.bytes
= 7;
1258 info
->nand
.ecc
.calculate
= omap3_calculate_ecc_bch4
;
1261 pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors
);
1264 omap3_free_bch(mtd
);
1269 * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
1270 * @mtd: MTD device structure
1272 static int omap3_init_bch_tail(struct mtd_info
*mtd
)
1275 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1277 struct nand_ecclayout
*layout
= &info
->ecclayout
;
1279 /* build oob layout */
1280 steps
= mtd
->writesize
/info
->nand
.ecc
.size
;
1281 layout
->eccbytes
= steps
*info
->nand
.ecc
.bytes
;
1283 /* do not bother creating special oob layouts for small page devices */
1284 if (mtd
->oobsize
< 64) {
1285 pr_err("BCH ecc is not supported on small page devices\n");
1289 /* reserve 2 bytes for bad block marker */
1290 if (layout
->eccbytes
+2 > mtd
->oobsize
) {
1291 pr_err("no oob layout available for oobsize %d eccbytes %u\n",
1292 mtd
->oobsize
, layout
->eccbytes
);
1296 /* put ecc bytes at oob tail */
1297 for (i
= 0; i
< layout
->eccbytes
; i
++)
1298 layout
->eccpos
[i
] = mtd
->oobsize
-layout
->eccbytes
+i
;
1300 layout
->oobfree
[0].offset
= 2;
1301 layout
->oobfree
[0].length
= mtd
->oobsize
-2-layout
->eccbytes
;
1302 info
->nand
.ecc
.layout
= layout
;
1304 if (!(info
->nand
.options
& NAND_BUSWIDTH_16
))
1305 info
->nand
.badblock_pattern
= &bb_descrip_flashbased
;
1308 omap3_free_bch(mtd
);
1313 static int omap3_init_bch(struct mtd_info
*mtd
, int ecc_opt
)
1315 pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
1318 static int omap3_init_bch_tail(struct mtd_info
*mtd
)
1322 static void omap3_free_bch(struct mtd_info
*mtd
)
1325 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
1327 static int __devinit
omap_nand_probe(struct platform_device
*pdev
)
1329 struct omap_nand_info
*info
;
1330 struct omap_nand_platform_data
*pdata
;
1333 dma_cap_mask_t mask
;
1335 struct resource
*res
;
1337 pdata
= pdev
->dev
.platform_data
;
1338 if (pdata
== NULL
) {
1339 dev_err(&pdev
->dev
, "platform data missing\n");
1343 info
= kzalloc(sizeof(struct omap_nand_info
), GFP_KERNEL
);
1347 platform_set_drvdata(pdev
, info
);
1349 spin_lock_init(&info
->controller
.lock
);
1350 init_waitqueue_head(&info
->controller
.wq
);
1354 info
->gpmc_cs
= pdata
->cs
;
1355 info
->reg
= pdata
->reg
;
1357 info
->mtd
.priv
= &info
->nand
;
1358 info
->mtd
.name
= dev_name(&pdev
->dev
);
1359 info
->mtd
.owner
= THIS_MODULE
;
1361 info
->nand
.options
= pdata
->devsize
;
1362 info
->nand
.options
|= NAND_SKIP_BBTSCAN
;
1364 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1367 dev_err(&pdev
->dev
, "error getting memory resource\n");
1371 info
->phys_base
= res
->start
;
1372 info
->mem_size
= resource_size(res
);
1374 if (!request_mem_region(info
->phys_base
, info
->mem_size
,
1375 pdev
->dev
.driver
->name
)) {
1380 info
->nand
.IO_ADDR_R
= ioremap(info
->phys_base
, info
->mem_size
);
1381 if (!info
->nand
.IO_ADDR_R
) {
1383 goto out_release_mem_region
;
1386 info
->nand
.controller
= &info
->controller
;
1388 info
->nand
.IO_ADDR_W
= info
->nand
.IO_ADDR_R
;
1389 info
->nand
.cmd_ctrl
= omap_hwcontrol
;
1392 * If RDY/BSY line is connected to OMAP then use the omap ready
1393 * function and the generic nand_wait function which reads the status
1394 * register after monitoring the RDY/BSY line. Otherwise use a standard
1395 * chip delay which is slightly more than tR (AC Timing) of the NAND
1396 * device and read status register until you get a failure or success
1398 if (pdata
->dev_ready
) {
1399 info
->nand
.dev_ready
= omap_dev_ready
;
1400 info
->nand
.chip_delay
= 0;
1402 info
->nand
.waitfunc
= omap_wait
;
1403 info
->nand
.chip_delay
= 50;
1406 switch (pdata
->xfer_type
) {
1407 case NAND_OMAP_PREFETCH_POLLED
:
1408 info
->nand
.read_buf
= omap_read_buf_pref
;
1409 info
->nand
.write_buf
= omap_write_buf_pref
;
1412 case NAND_OMAP_POLLED
:
1413 if (info
->nand
.options
& NAND_BUSWIDTH_16
) {
1414 info
->nand
.read_buf
= omap_read_buf16
;
1415 info
->nand
.write_buf
= omap_write_buf16
;
1417 info
->nand
.read_buf
= omap_read_buf8
;
1418 info
->nand
.write_buf
= omap_write_buf8
;
1422 case NAND_OMAP_PREFETCH_DMA
:
1424 dma_cap_set(DMA_SLAVE
, mask
);
1425 sig
= OMAP24XX_DMA_GPMC
;
1426 info
->dma
= dma_request_channel(mask
, omap_dma_filter_fn
, &sig
);
1428 dev_err(&pdev
->dev
, "DMA engine request failed\n");
1430 goto out_release_mem_region
;
1432 struct dma_slave_config cfg
;
1434 memset(&cfg
, 0, sizeof(cfg
));
1435 cfg
.src_addr
= info
->phys_base
;
1436 cfg
.dst_addr
= info
->phys_base
;
1437 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1438 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1439 cfg
.src_maxburst
= 16;
1440 cfg
.dst_maxburst
= 16;
1441 err
= dmaengine_slave_config(info
->dma
, &cfg
);
1443 dev_err(&pdev
->dev
, "DMA engine slave config failed: %d\n",
1445 goto out_release_mem_region
;
1447 info
->nand
.read_buf
= omap_read_buf_dma_pref
;
1448 info
->nand
.write_buf
= omap_write_buf_dma_pref
;
1452 case NAND_OMAP_PREFETCH_IRQ
:
1453 info
->gpmc_irq_fifo
= platform_get_irq(pdev
, 0);
1454 if (info
->gpmc_irq_fifo
<= 0) {
1455 dev_err(&pdev
->dev
, "error getting fifo irq\n");
1457 goto out_release_mem_region
;
1459 err
= request_irq(info
->gpmc_irq_fifo
, omap_nand_irq
,
1460 IRQF_SHARED
, "gpmc-nand-fifo", info
);
1462 dev_err(&pdev
->dev
, "requesting irq(%d) error:%d",
1463 info
->gpmc_irq_fifo
, err
);
1464 info
->gpmc_irq_fifo
= 0;
1465 goto out_release_mem_region
;
1468 info
->gpmc_irq_count
= platform_get_irq(pdev
, 1);
1469 if (info
->gpmc_irq_count
<= 0) {
1470 dev_err(&pdev
->dev
, "error getting count irq\n");
1472 goto out_release_mem_region
;
1474 err
= request_irq(info
->gpmc_irq_count
, omap_nand_irq
,
1475 IRQF_SHARED
, "gpmc-nand-count", info
);
1477 dev_err(&pdev
->dev
, "requesting irq(%d) error:%d",
1478 info
->gpmc_irq_count
, err
);
1479 info
->gpmc_irq_count
= 0;
1480 goto out_release_mem_region
;
1483 info
->nand
.read_buf
= omap_read_buf_irq_pref
;
1484 info
->nand
.write_buf
= omap_write_buf_irq_pref
;
1490 "xfer_type(%d) not supported!\n", pdata
->xfer_type
);
1492 goto out_release_mem_region
;
1495 /* select the ecc type */
1496 if (pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_DEFAULT
)
1497 info
->nand
.ecc
.mode
= NAND_ECC_SOFT
;
1498 else if ((pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_HW
) ||
1499 (pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_HW_ROMCODE
)) {
1500 info
->nand
.ecc
.bytes
= 3;
1501 info
->nand
.ecc
.size
= 512;
1502 info
->nand
.ecc
.strength
= 1;
1503 info
->nand
.ecc
.calculate
= omap_calculate_ecc
;
1504 info
->nand
.ecc
.hwctl
= omap_enable_hwecc
;
1505 info
->nand
.ecc
.correct
= omap_correct_data
;
1506 info
->nand
.ecc
.mode
= NAND_ECC_HW
;
1507 } else if ((pdata
->ecc_opt
== OMAP_ECC_BCH4_CODE_HW
) ||
1508 (pdata
->ecc_opt
== OMAP_ECC_BCH8_CODE_HW
)) {
1509 err
= omap3_init_bch(&info
->mtd
, pdata
->ecc_opt
);
1512 goto out_release_mem_region
;
1516 /* DIP switches on some boards change between 8 and 16 bit
1517 * bus widths for flash. Try the other width if the first try fails.
1519 if (nand_scan_ident(&info
->mtd
, 1, NULL
)) {
1520 info
->nand
.options
^= NAND_BUSWIDTH_16
;
1521 if (nand_scan_ident(&info
->mtd
, 1, NULL
)) {
1523 goto out_release_mem_region
;
1527 /* rom code layout */
1528 if (pdata
->ecc_opt
== OMAP_ECC_HAMMING_CODE_HW_ROMCODE
) {
1530 if (info
->nand
.options
& NAND_BUSWIDTH_16
)
1534 info
->nand
.badblock_pattern
= &bb_descrip_flashbased
;
1536 omap_oobinfo
.eccbytes
= 3 * (info
->mtd
.oobsize
/16);
1537 for (i
= 0; i
< omap_oobinfo
.eccbytes
; i
++)
1538 omap_oobinfo
.eccpos
[i
] = i
+offset
;
1540 omap_oobinfo
.oobfree
->offset
= offset
+ omap_oobinfo
.eccbytes
;
1541 omap_oobinfo
.oobfree
->length
= info
->mtd
.oobsize
-
1542 (offset
+ omap_oobinfo
.eccbytes
);
1544 info
->nand
.ecc
.layout
= &omap_oobinfo
;
1545 } else if ((pdata
->ecc_opt
== OMAP_ECC_BCH4_CODE_HW
) ||
1546 (pdata
->ecc_opt
== OMAP_ECC_BCH8_CODE_HW
)) {
1547 /* build OOB layout for BCH ECC correction */
1548 err
= omap3_init_bch_tail(&info
->mtd
);
1551 goto out_release_mem_region
;
1555 /* second phase scan */
1556 if (nand_scan_tail(&info
->mtd
)) {
1558 goto out_release_mem_region
;
1561 mtd_device_parse_register(&info
->mtd
, NULL
, NULL
, pdata
->parts
,
1564 platform_set_drvdata(pdev
, &info
->mtd
);
1568 out_release_mem_region
:
1570 dma_release_channel(info
->dma
);
1571 if (info
->gpmc_irq_count
> 0)
1572 free_irq(info
->gpmc_irq_count
, info
);
1573 if (info
->gpmc_irq_fifo
> 0)
1574 free_irq(info
->gpmc_irq_fifo
, info
);
1575 release_mem_region(info
->phys_base
, info
->mem_size
);
1582 static int omap_nand_remove(struct platform_device
*pdev
)
1584 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1585 struct omap_nand_info
*info
= container_of(mtd
, struct omap_nand_info
,
1587 omap3_free_bch(&info
->mtd
);
1589 platform_set_drvdata(pdev
, NULL
);
1591 dma_release_channel(info
->dma
);
1593 if (info
->gpmc_irq_count
> 0)
1594 free_irq(info
->gpmc_irq_count
, info
);
1595 if (info
->gpmc_irq_fifo
> 0)
1596 free_irq(info
->gpmc_irq_fifo
, info
);
1598 /* Release NAND device, its internal structures and partitions */
1599 nand_release(&info
->mtd
);
1600 iounmap(info
->nand
.IO_ADDR_R
);
1601 release_mem_region(info
->phys_base
, info
->mem_size
);
1606 static struct platform_driver omap_nand_driver
= {
1607 .probe
= omap_nand_probe
,
1608 .remove
= omap_nand_remove
,
1610 .name
= DRIVER_NAME
,
1611 .owner
= THIS_MODULE
,
1615 module_platform_driver(omap_nand_driver
);
1617 MODULE_ALIAS("platform:" DRIVER_NAME
);
1618 MODULE_LICENSE("GPL");
1619 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");