1 /* linux/drivers/mtd/nand/s3c2410.c
3 * Copyright © 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * Samsung S3C2410/S3C2440/S3C2412 NAND driver
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #define pr_fmt(fmt) "nand-s3c2410: " fmt
26 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/init.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
36 #include <linux/ioport.h>
37 #include <linux/platform_device.h>
38 #include <linux/delay.h>
39 #include <linux/err.h>
40 #include <linux/slab.h>
41 #include <linux/clk.h>
42 #include <linux/cpufreq.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/nand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/partitions.h>
49 #include <plat/regs-nand.h>
50 #include <linux/platform_data/mtd-nand-s3c2410.h>
52 /* new oob placement block for use with hardware ecc generation
55 static struct nand_ecclayout nand_hw_eccoob
= {
61 /* controller and mtd information */
63 struct s3c2410_nand_info
;
66 * struct s3c2410_nand_mtd - driver MTD structure
67 * @mtd: The MTD instance to pass to the MTD layer.
68 * @chip: The NAND chip information.
69 * @set: The platform information supplied for this set of NAND chips.
70 * @info: Link back to the hardware information.
71 * @scan_res: The result from calling nand_scan_ident().
73 struct s3c2410_nand_mtd
{
75 struct nand_chip chip
;
76 struct s3c2410_nand_set
*set
;
77 struct s3c2410_nand_info
*info
;
87 enum s3c_nand_clk_state
{
93 /* overview of the s3c2410 nand state */
96 * struct s3c2410_nand_info - NAND controller state.
97 * @mtds: An array of MTD instances on this controoler.
98 * @platform: The platform data for this board.
99 * @device: The platform device we bound to.
100 * @clk: The clock resource for this controller.
101 * @regs: The area mapped for the hardware registers.
102 * @sel_reg: Pointer to the register controlling the NAND selection.
103 * @sel_bit: The bit in @sel_reg to select the NAND chip.
104 * @mtd_count: The number of MTDs created from this controller.
105 * @save_sel: The contents of @sel_reg to be saved over suspend.
106 * @clk_rate: The clock rate from @clk.
107 * @clk_state: The current clock state.
108 * @cpu_type: The exact type of this controller.
110 struct s3c2410_nand_info
{
112 struct nand_hw_control controller
;
113 struct s3c2410_nand_mtd
*mtds
;
114 struct s3c2410_platform_nand
*platform
;
117 struct device
*device
;
120 void __iomem
*sel_reg
;
123 unsigned long save_sel
;
124 unsigned long clk_rate
;
125 enum s3c_nand_clk_state clk_state
;
127 enum s3c_cpu_type cpu_type
;
129 #ifdef CONFIG_CPU_FREQ
130 struct notifier_block freq_transition
;
134 /* conversion functions */
136 static struct s3c2410_nand_mtd
*s3c2410_nand_mtd_toours(struct mtd_info
*mtd
)
138 return container_of(mtd
, struct s3c2410_nand_mtd
, mtd
);
141 static struct s3c2410_nand_info
*s3c2410_nand_mtd_toinfo(struct mtd_info
*mtd
)
143 return s3c2410_nand_mtd_toours(mtd
)->info
;
146 static struct s3c2410_nand_info
*to_nand_info(struct platform_device
*dev
)
148 return platform_get_drvdata(dev
);
151 static struct s3c2410_platform_nand
*to_nand_plat(struct platform_device
*dev
)
153 return dev
->dev
.platform_data
;
156 static inline int allow_clk_suspend(struct s3c2410_nand_info
*info
)
158 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
166 * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock.
167 * @info: The controller instance.
168 * @new_state: State to which clock should be set.
170 static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info
*info
,
171 enum s3c_nand_clk_state new_state
)
173 if (!allow_clk_suspend(info
) && new_state
== CLOCK_SUSPEND
)
176 if (info
->clk_state
== CLOCK_ENABLE
) {
177 if (new_state
!= CLOCK_ENABLE
)
178 clk_disable(info
->clk
);
180 if (new_state
== CLOCK_ENABLE
)
181 clk_enable(info
->clk
);
184 info
->clk_state
= new_state
;
187 /* timing calculations */
189 #define NS_IN_KHZ 1000000
192 * s3c_nand_calc_rate - calculate timing data.
193 * @wanted: The cycle time in nanoseconds.
194 * @clk: The clock rate in kHz.
195 * @max: The maximum divider value.
197 * Calculate the timing value from the given parameters.
199 static int s3c_nand_calc_rate(int wanted
, unsigned long clk
, int max
)
203 result
= DIV_ROUND_UP((wanted
* clk
), NS_IN_KHZ
);
205 pr_debug("result %d from %ld, %d\n", result
, clk
, wanted
);
208 pr_err("%d ns is too big for current clock rate %ld\n",
219 #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
221 /* controller setup */
224 * s3c2410_nand_setrate - setup controller timing information.
225 * @info: The controller instance.
227 * Given the information supplied by the platform, calculate and set
228 * the necessary timing registers in the hardware to generate the
229 * necessary timing cycles to the hardware.
231 static int s3c2410_nand_setrate(struct s3c2410_nand_info
*info
)
233 struct s3c2410_platform_nand
*plat
= info
->platform
;
234 int tacls_max
= (info
->cpu_type
== TYPE_S3C2412
) ? 8 : 4;
235 int tacls
, twrph0
, twrph1
;
236 unsigned long clkrate
= clk_get_rate(info
->clk
);
237 unsigned long uninitialized_var(set
), cfg
, uninitialized_var(mask
);
240 /* calculate the timing information for the controller */
242 info
->clk_rate
= clkrate
;
243 clkrate
/= 1000; /* turn clock into kHz for ease of use */
246 tacls
= s3c_nand_calc_rate(plat
->tacls
, clkrate
, tacls_max
);
247 twrph0
= s3c_nand_calc_rate(plat
->twrph0
, clkrate
, 8);
248 twrph1
= s3c_nand_calc_rate(plat
->twrph1
, clkrate
, 8);
250 /* default timings */
256 if (tacls
< 0 || twrph0
< 0 || twrph1
< 0) {
257 dev_err(info
->device
, "cannot get suitable timings\n");
261 dev_info(info
->device
, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
262 tacls
, to_ns(tacls
, clkrate
), twrph0
, to_ns(twrph0
, clkrate
),
263 twrph1
, to_ns(twrph1
, clkrate
));
265 switch (info
->cpu_type
) {
267 mask
= (S3C2410_NFCONF_TACLS(3) |
268 S3C2410_NFCONF_TWRPH0(7) |
269 S3C2410_NFCONF_TWRPH1(7));
270 set
= S3C2410_NFCONF_EN
;
271 set
|= S3C2410_NFCONF_TACLS(tacls
- 1);
272 set
|= S3C2410_NFCONF_TWRPH0(twrph0
- 1);
273 set
|= S3C2410_NFCONF_TWRPH1(twrph1
- 1);
278 mask
= (S3C2440_NFCONF_TACLS(tacls_max
- 1) |
279 S3C2440_NFCONF_TWRPH0(7) |
280 S3C2440_NFCONF_TWRPH1(7));
282 set
= S3C2440_NFCONF_TACLS(tacls
- 1);
283 set
|= S3C2440_NFCONF_TWRPH0(twrph0
- 1);
284 set
|= S3C2440_NFCONF_TWRPH1(twrph1
- 1);
291 local_irq_save(flags
);
293 cfg
= readl(info
->regs
+ S3C2410_NFCONF
);
296 writel(cfg
, info
->regs
+ S3C2410_NFCONF
);
298 local_irq_restore(flags
);
300 dev_dbg(info
->device
, "NF_CONF is 0x%lx\n", cfg
);
306 * s3c2410_nand_inithw - basic hardware initialisation
307 * @info: The hardware state.
309 * Do the basic initialisation of the hardware, using s3c2410_nand_setrate()
310 * to setup the hardware access speeds and set the controller to be enabled.
312 static int s3c2410_nand_inithw(struct s3c2410_nand_info
*info
)
316 ret
= s3c2410_nand_setrate(info
);
320 switch (info
->cpu_type
) {
327 /* enable the controller and de-assert nFCE */
329 writel(S3C2440_NFCONT_ENABLE
, info
->regs
+ S3C2440_NFCONT
);
336 * s3c2410_nand_select_chip - select the given nand chip
337 * @mtd: The MTD instance for this chip.
338 * @chip: The chip number.
340 * This is called by the MTD layer to either select a given chip for the
341 * @mtd instance, or to indicate that the access has finished and the
342 * chip can be de-selected.
344 * The routine ensures that the nFCE line is correctly setup, and any
345 * platform specific selection code is called to route nFCE to the specific
348 static void s3c2410_nand_select_chip(struct mtd_info
*mtd
, int chip
)
350 struct s3c2410_nand_info
*info
;
351 struct s3c2410_nand_mtd
*nmtd
;
352 struct nand_chip
*this = mtd
->priv
;
359 s3c2410_nand_clk_set_state(info
, CLOCK_ENABLE
);
361 cur
= readl(info
->sel_reg
);
364 cur
|= info
->sel_bit
;
366 if (nmtd
->set
!= NULL
&& chip
> nmtd
->set
->nr_chips
) {
367 dev_err(info
->device
, "invalid chip %d\n", chip
);
371 if (info
->platform
!= NULL
) {
372 if (info
->platform
->select_chip
!= NULL
)
373 (info
->platform
->select_chip
) (nmtd
->set
, chip
);
376 cur
&= ~info
->sel_bit
;
379 writel(cur
, info
->sel_reg
);
382 s3c2410_nand_clk_set_state(info
, CLOCK_SUSPEND
);
385 /* s3c2410_nand_hwcontrol
387 * Issue command and address cycles to the chip
390 static void s3c2410_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
,
393 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
395 if (cmd
== NAND_CMD_NONE
)
399 writeb(cmd
, info
->regs
+ S3C2410_NFCMD
);
401 writeb(cmd
, info
->regs
+ S3C2410_NFADDR
);
404 /* command and control functions */
406 static void s3c2440_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
,
409 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
411 if (cmd
== NAND_CMD_NONE
)
415 writeb(cmd
, info
->regs
+ S3C2440_NFCMD
);
417 writeb(cmd
, info
->regs
+ S3C2440_NFADDR
);
420 /* s3c2410_nand_devready()
422 * returns 0 if the nand is busy, 1 if it is ready
425 static int s3c2410_nand_devready(struct mtd_info
*mtd
)
427 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
428 return readb(info
->regs
+ S3C2410_NFSTAT
) & S3C2410_NFSTAT_BUSY
;
431 static int s3c2440_nand_devready(struct mtd_info
*mtd
)
433 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
434 return readb(info
->regs
+ S3C2440_NFSTAT
) & S3C2440_NFSTAT_READY
;
437 static int s3c2412_nand_devready(struct mtd_info
*mtd
)
439 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
440 return readb(info
->regs
+ S3C2412_NFSTAT
) & S3C2412_NFSTAT_READY
;
443 /* ECC handling functions */
445 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
446 static int s3c2410_nand_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
447 u_char
*read_ecc
, u_char
*calc_ecc
)
449 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
450 unsigned int diff0
, diff1
, diff2
;
451 unsigned int bit
, byte
;
453 pr_debug("%s(%p,%p,%p,%p)\n", __func__
, mtd
, dat
, read_ecc
, calc_ecc
);
455 diff0
= read_ecc
[0] ^ calc_ecc
[0];
456 diff1
= read_ecc
[1] ^ calc_ecc
[1];
457 diff2
= read_ecc
[2] ^ calc_ecc
[2];
459 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
460 __func__
, 3, read_ecc
, 3, calc_ecc
,
461 diff0
, diff1
, diff2
);
463 if (diff0
== 0 && diff1
== 0 && diff2
== 0)
464 return 0; /* ECC is ok */
466 /* sometimes people do not think about using the ECC, so check
467 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
468 * the error, on the assumption that this is an un-eccd page.
470 if (read_ecc
[0] == 0xff && read_ecc
[1] == 0xff && read_ecc
[2] == 0xff
471 && info
->platform
->ignore_unset_ecc
)
474 /* Can we correct this ECC (ie, one row and column change).
475 * Note, this is similar to the 256 error code on smartmedia */
477 if (((diff0
^ (diff0
>> 1)) & 0x55) == 0x55 &&
478 ((diff1
^ (diff1
>> 1)) & 0x55) == 0x55 &&
479 ((diff2
^ (diff2
>> 1)) & 0x55) == 0x55) {
480 /* calculate the bit position of the error */
482 bit
= ((diff2
>> 3) & 1) |
486 /* calculate the byte position of the error */
488 byte
= ((diff2
<< 7) & 0x100) |
489 ((diff1
<< 0) & 0x80) |
490 ((diff1
<< 1) & 0x40) |
491 ((diff1
<< 2) & 0x20) |
492 ((diff1
<< 3) & 0x10) |
493 ((diff0
>> 4) & 0x08) |
494 ((diff0
>> 3) & 0x04) |
495 ((diff0
>> 2) & 0x02) |
496 ((diff0
>> 1) & 0x01);
498 dev_dbg(info
->device
, "correcting error bit %d, byte %d\n",
501 dat
[byte
] ^= (1 << bit
);
505 /* if there is only one bit difference in the ECC, then
506 * one of only a row or column parity has changed, which
507 * means the error is most probably in the ECC itself */
509 diff0
|= (diff1
<< 8);
510 diff0
|= (diff2
<< 16);
512 if ((diff0
& ~(1<<fls(diff0
))) == 0)
520 * These allow the s3c2410 and s3c2440 to use the controller's ECC
521 * generator block to ECC the data as it passes through]
524 static void s3c2410_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
526 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
529 ctrl
= readl(info
->regs
+ S3C2410_NFCONF
);
530 ctrl
|= S3C2410_NFCONF_INITECC
;
531 writel(ctrl
, info
->regs
+ S3C2410_NFCONF
);
534 static void s3c2412_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
536 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
539 ctrl
= readl(info
->regs
+ S3C2440_NFCONT
);
540 writel(ctrl
| S3C2412_NFCONT_INIT_MAIN_ECC
,
541 info
->regs
+ S3C2440_NFCONT
);
544 static void s3c2440_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
546 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
549 ctrl
= readl(info
->regs
+ S3C2440_NFCONT
);
550 writel(ctrl
| S3C2440_NFCONT_INITECC
, info
->regs
+ S3C2440_NFCONT
);
553 static int s3c2410_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
556 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
558 ecc_code
[0] = readb(info
->regs
+ S3C2410_NFECC
+ 0);
559 ecc_code
[1] = readb(info
->regs
+ S3C2410_NFECC
+ 1);
560 ecc_code
[2] = readb(info
->regs
+ S3C2410_NFECC
+ 2);
562 pr_debug("%s: returning ecc %*phN\n", __func__
, 3, ecc_code
);
567 static int s3c2412_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
570 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
571 unsigned long ecc
= readl(info
->regs
+ S3C2412_NFMECC0
);
574 ecc_code
[1] = ecc
>> 8;
575 ecc_code
[2] = ecc
>> 16;
577 pr_debug("%s: returning ecc %*phN\n", __func__
, 3, ecc_code
);
582 static int s3c2440_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
585 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
586 unsigned long ecc
= readl(info
->regs
+ S3C2440_NFMECC0
);
589 ecc_code
[1] = ecc
>> 8;
590 ecc_code
[2] = ecc
>> 16;
592 pr_debug("%s: returning ecc %06lx\n", __func__
, ecc
& 0xffffff);
598 /* over-ride the standard functions for a little more speed. We can
599 * use read/write block to move the data buffers to/from the controller
602 static void s3c2410_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
604 struct nand_chip
*this = mtd
->priv
;
605 readsb(this->IO_ADDR_R
, buf
, len
);
608 static void s3c2440_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
610 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
612 readsl(info
->regs
+ S3C2440_NFDATA
, buf
, len
>> 2);
614 /* cleanup if we've got less than a word to do */
618 for (; len
& 3; len
--)
619 *buf
++ = readb(info
->regs
+ S3C2440_NFDATA
);
623 static void s3c2410_nand_write_buf(struct mtd_info
*mtd
, const u_char
*buf
,
626 struct nand_chip
*this = mtd
->priv
;
627 writesb(this->IO_ADDR_W
, buf
, len
);
630 static void s3c2440_nand_write_buf(struct mtd_info
*mtd
, const u_char
*buf
,
633 struct s3c2410_nand_info
*info
= s3c2410_nand_mtd_toinfo(mtd
);
635 writesl(info
->regs
+ S3C2440_NFDATA
, buf
, len
>> 2);
637 /* cleanup any fractional write */
641 for (; len
& 3; len
--, buf
++)
642 writeb(*buf
, info
->regs
+ S3C2440_NFDATA
);
646 /* cpufreq driver support */
648 #ifdef CONFIG_CPU_FREQ
650 static int s3c2410_nand_cpufreq_transition(struct notifier_block
*nb
,
651 unsigned long val
, void *data
)
653 struct s3c2410_nand_info
*info
;
654 unsigned long newclk
;
656 info
= container_of(nb
, struct s3c2410_nand_info
, freq_transition
);
657 newclk
= clk_get_rate(info
->clk
);
659 if ((val
== CPUFREQ_POSTCHANGE
&& newclk
< info
->clk_rate
) ||
660 (val
== CPUFREQ_PRECHANGE
&& newclk
> info
->clk_rate
)) {
661 s3c2410_nand_setrate(info
);
667 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info
*info
)
669 info
->freq_transition
.notifier_call
= s3c2410_nand_cpufreq_transition
;
671 return cpufreq_register_notifier(&info
->freq_transition
,
672 CPUFREQ_TRANSITION_NOTIFIER
);
676 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info
*info
)
678 cpufreq_unregister_notifier(&info
->freq_transition
,
679 CPUFREQ_TRANSITION_NOTIFIER
);
683 static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info
*info
)
689 s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info
*info
)
694 /* device management functions */
696 static int s3c24xx_nand_remove(struct platform_device
*pdev
)
698 struct s3c2410_nand_info
*info
= to_nand_info(pdev
);
700 platform_set_drvdata(pdev
, NULL
);
705 s3c2410_nand_cpufreq_deregister(info
);
707 /* Release all our mtds and their partitions, then go through
708 * freeing the resources used
711 if (info
->mtds
!= NULL
) {
712 struct s3c2410_nand_mtd
*ptr
= info
->mtds
;
715 for (mtdno
= 0; mtdno
< info
->mtd_count
; mtdno
++, ptr
++) {
716 pr_debug("releasing mtd %d (%p)\n", mtdno
, ptr
);
717 nand_release(&ptr
->mtd
);
721 /* free the common resources */
723 if (!IS_ERR(info
->clk
))
724 s3c2410_nand_clk_set_state(info
, CLOCK_DISABLE
);
729 static int s3c2410_nand_add_partition(struct s3c2410_nand_info
*info
,
730 struct s3c2410_nand_mtd
*mtd
,
731 struct s3c2410_nand_set
*set
)
734 mtd
->mtd
.name
= set
->name
;
736 return mtd_device_parse_register(&mtd
->mtd
, NULL
, NULL
,
737 set
->partitions
, set
->nr_partitions
);
744 * s3c2410_nand_init_chip - initialise a single instance of an chip
745 * @info: The base NAND controller the chip is on.
746 * @nmtd: The new controller MTD instance to fill in.
747 * @set: The information passed from the board specific platform data.
749 * Initialise the given @nmtd from the information in @info and @set. This
750 * readies the structure for use with the MTD layer functions by ensuring
751 * all pointers are setup and the necessary control routines selected.
753 static void s3c2410_nand_init_chip(struct s3c2410_nand_info
*info
,
754 struct s3c2410_nand_mtd
*nmtd
,
755 struct s3c2410_nand_set
*set
)
757 struct nand_chip
*chip
= &nmtd
->chip
;
758 void __iomem
*regs
= info
->regs
;
760 chip
->write_buf
= s3c2410_nand_write_buf
;
761 chip
->read_buf
= s3c2410_nand_read_buf
;
762 chip
->select_chip
= s3c2410_nand_select_chip
;
763 chip
->chip_delay
= 50;
765 chip
->options
= set
->options
;
766 chip
->controller
= &info
->controller
;
768 switch (info
->cpu_type
) {
770 chip
->IO_ADDR_W
= regs
+ S3C2410_NFDATA
;
771 info
->sel_reg
= regs
+ S3C2410_NFCONF
;
772 info
->sel_bit
= S3C2410_NFCONF_nFCE
;
773 chip
->cmd_ctrl
= s3c2410_nand_hwcontrol
;
774 chip
->dev_ready
= s3c2410_nand_devready
;
778 chip
->IO_ADDR_W
= regs
+ S3C2440_NFDATA
;
779 info
->sel_reg
= regs
+ S3C2440_NFCONT
;
780 info
->sel_bit
= S3C2440_NFCONT_nFCE
;
781 chip
->cmd_ctrl
= s3c2440_nand_hwcontrol
;
782 chip
->dev_ready
= s3c2440_nand_devready
;
783 chip
->read_buf
= s3c2440_nand_read_buf
;
784 chip
->write_buf
= s3c2440_nand_write_buf
;
788 chip
->IO_ADDR_W
= regs
+ S3C2440_NFDATA
;
789 info
->sel_reg
= regs
+ S3C2440_NFCONT
;
790 info
->sel_bit
= S3C2412_NFCONT_nFCE0
;
791 chip
->cmd_ctrl
= s3c2440_nand_hwcontrol
;
792 chip
->dev_ready
= s3c2412_nand_devready
;
794 if (readl(regs
+ S3C2410_NFCONF
) & S3C2412_NFCONF_NANDBOOT
)
795 dev_info(info
->device
, "System booted from NAND\n");
800 chip
->IO_ADDR_R
= chip
->IO_ADDR_W
;
803 nmtd
->mtd
.priv
= chip
;
804 nmtd
->mtd
.owner
= THIS_MODULE
;
807 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
808 chip
->ecc
.calculate
= s3c2410_nand_calculate_ecc
;
809 chip
->ecc
.correct
= s3c2410_nand_correct_data
;
810 chip
->ecc
.mode
= NAND_ECC_HW
;
811 chip
->ecc
.strength
= 1;
813 switch (info
->cpu_type
) {
815 chip
->ecc
.hwctl
= s3c2410_nand_enable_hwecc
;
816 chip
->ecc
.calculate
= s3c2410_nand_calculate_ecc
;
820 chip
->ecc
.hwctl
= s3c2412_nand_enable_hwecc
;
821 chip
->ecc
.calculate
= s3c2412_nand_calculate_ecc
;
825 chip
->ecc
.hwctl
= s3c2440_nand_enable_hwecc
;
826 chip
->ecc
.calculate
= s3c2440_nand_calculate_ecc
;
830 chip
->ecc
.mode
= NAND_ECC_SOFT
;
833 if (set
->ecc_layout
!= NULL
)
834 chip
->ecc
.layout
= set
->ecc_layout
;
836 if (set
->disable_ecc
)
837 chip
->ecc
.mode
= NAND_ECC_NONE
;
839 switch (chip
->ecc
.mode
) {
841 dev_info(info
->device
, "NAND ECC disabled\n");
844 dev_info(info
->device
, "NAND soft ECC\n");
847 dev_info(info
->device
, "NAND hardware ECC\n");
850 dev_info(info
->device
, "NAND ECC UNKNOWN\n");
854 /* If you use u-boot BBT creation code, specifying this flag will
855 * let the kernel fish out the BBT from the NAND, and also skip the
856 * full NAND scan that can take 1/2s or so. Little things... */
857 if (set
->flash_bbt
) {
858 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
859 chip
->options
|= NAND_SKIP_BBTSCAN
;
864 * s3c2410_nand_update_chip - post probe update
865 * @info: The controller instance.
866 * @nmtd: The driver version of the MTD instance.
868 * This routine is called after the chip probe has successfully completed
869 * and the relevant per-chip information updated. This call ensure that
870 * we update the internal state accordingly.
872 * The internal state is currently limited to the ECC state information.
874 static void s3c2410_nand_update_chip(struct s3c2410_nand_info
*info
,
875 struct s3c2410_nand_mtd
*nmtd
)
877 struct nand_chip
*chip
= &nmtd
->chip
;
879 dev_dbg(info
->device
, "chip %p => page shift %d\n",
880 chip
, chip
->page_shift
);
882 if (chip
->ecc
.mode
!= NAND_ECC_HW
)
885 /* change the behaviour depending on whether we are using
886 * the large or small page nand device */
888 if (chip
->page_shift
> 10) {
889 chip
->ecc
.size
= 256;
892 chip
->ecc
.size
= 512;
894 chip
->ecc
.layout
= &nand_hw_eccoob
;
898 /* s3c24xx_nand_probe
900 * called by device layer when it finds a device matching
901 * one our driver can handled. This code checks to see if
902 * it can allocate all necessary resources then calls the
903 * nand layer to look for devices
905 static int s3c24xx_nand_probe(struct platform_device
*pdev
)
907 struct s3c2410_platform_nand
*plat
= to_nand_plat(pdev
);
908 enum s3c_cpu_type cpu_type
;
909 struct s3c2410_nand_info
*info
;
910 struct s3c2410_nand_mtd
*nmtd
;
911 struct s3c2410_nand_set
*sets
;
912 struct resource
*res
;
918 cpu_type
= platform_get_device_id(pdev
)->driver_data
;
920 pr_debug("s3c2410_nand_probe(%p)\n", pdev
);
922 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
924 dev_err(&pdev
->dev
, "no memory for flash info\n");
929 platform_set_drvdata(pdev
, info
);
931 spin_lock_init(&info
->controller
.lock
);
932 init_waitqueue_head(&info
->controller
.wq
);
934 /* get the clock source and enable it */
936 info
->clk
= devm_clk_get(&pdev
->dev
, "nand");
937 if (IS_ERR(info
->clk
)) {
938 dev_err(&pdev
->dev
, "failed to get clock\n");
943 s3c2410_nand_clk_set_state(info
, CLOCK_ENABLE
);
945 /* allocate and map the resource */
947 /* currently we assume we have the one resource */
948 res
= pdev
->resource
;
949 size
= resource_size(res
);
951 info
->device
= &pdev
->dev
;
952 info
->platform
= plat
;
953 info
->cpu_type
= cpu_type
;
955 info
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
956 if (info
->regs
== NULL
) {
957 dev_err(&pdev
->dev
, "cannot reserve register region\n");
962 dev_dbg(&pdev
->dev
, "mapped registers at %p\n", info
->regs
);
964 /* initialise the hardware */
966 err
= s3c2410_nand_inithw(info
);
970 sets
= (plat
!= NULL
) ? plat
->sets
: NULL
;
971 nr_sets
= (plat
!= NULL
) ? plat
->nr_sets
: 1;
973 info
->mtd_count
= nr_sets
;
975 /* allocate our information */
977 size
= nr_sets
* sizeof(*info
->mtds
);
978 info
->mtds
= devm_kzalloc(&pdev
->dev
, size
, GFP_KERNEL
);
979 if (info
->mtds
== NULL
) {
980 dev_err(&pdev
->dev
, "failed to allocate mtd storage\n");
985 /* initialise all possible chips */
989 for (setno
= 0; setno
< nr_sets
; setno
++, nmtd
++) {
990 pr_debug("initialising set %d (%p, info %p)\n",
993 s3c2410_nand_init_chip(info
, nmtd
, sets
);
995 nmtd
->scan_res
= nand_scan_ident(&nmtd
->mtd
,
996 (sets
) ? sets
->nr_chips
: 1,
999 if (nmtd
->scan_res
== 0) {
1000 s3c2410_nand_update_chip(info
, nmtd
);
1001 nand_scan_tail(&nmtd
->mtd
);
1002 s3c2410_nand_add_partition(info
, nmtd
, sets
);
1009 err
= s3c2410_nand_cpufreq_register(info
);
1011 dev_err(&pdev
->dev
, "failed to init cpufreq support\n");
1015 if (allow_clk_suspend(info
)) {
1016 dev_info(&pdev
->dev
, "clock idle support enabled\n");
1017 s3c2410_nand_clk_set_state(info
, CLOCK_SUSPEND
);
1020 pr_debug("initialised ok\n");
1024 s3c24xx_nand_remove(pdev
);
1034 static int s3c24xx_nand_suspend(struct platform_device
*dev
, pm_message_t pm
)
1036 struct s3c2410_nand_info
*info
= platform_get_drvdata(dev
);
1039 info
->save_sel
= readl(info
->sel_reg
);
1041 /* For the moment, we must ensure nFCE is high during
1042 * the time we are suspended. This really should be
1043 * handled by suspending the MTDs we are using, but
1044 * that is currently not the case. */
1046 writel(info
->save_sel
| info
->sel_bit
, info
->sel_reg
);
1048 s3c2410_nand_clk_set_state(info
, CLOCK_DISABLE
);
1054 static int s3c24xx_nand_resume(struct platform_device
*dev
)
1056 struct s3c2410_nand_info
*info
= platform_get_drvdata(dev
);
1060 s3c2410_nand_clk_set_state(info
, CLOCK_ENABLE
);
1061 s3c2410_nand_inithw(info
);
1063 /* Restore the state of the nFCE line. */
1065 sel
= readl(info
->sel_reg
);
1066 sel
&= ~info
->sel_bit
;
1067 sel
|= info
->save_sel
& info
->sel_bit
;
1068 writel(sel
, info
->sel_reg
);
1070 s3c2410_nand_clk_set_state(info
, CLOCK_SUSPEND
);
1077 #define s3c24xx_nand_suspend NULL
1078 #define s3c24xx_nand_resume NULL
1081 /* driver device registration */
1083 static struct platform_device_id s3c24xx_driver_ids
[] = {
1085 .name
= "s3c2410-nand",
1086 .driver_data
= TYPE_S3C2410
,
1088 .name
= "s3c2440-nand",
1089 .driver_data
= TYPE_S3C2440
,
1091 .name
= "s3c2412-nand",
1092 .driver_data
= TYPE_S3C2412
,
1094 .name
= "s3c6400-nand",
1095 .driver_data
= TYPE_S3C2412
, /* compatible with 2412 */
1100 MODULE_DEVICE_TABLE(platform
, s3c24xx_driver_ids
);
1102 static struct platform_driver s3c24xx_nand_driver
= {
1103 .probe
= s3c24xx_nand_probe
,
1104 .remove
= s3c24xx_nand_remove
,
1105 .suspend
= s3c24xx_nand_suspend
,
1106 .resume
= s3c24xx_nand_resume
,
1107 .id_table
= s3c24xx_driver_ids
,
1109 .name
= "s3c24xx-nand",
1110 .owner
= THIS_MODULE
,
1114 module_platform_driver(s3c24xx_nand_driver
);
1116 MODULE_LICENSE("GPL");
1117 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1118 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");