2 * SuperH FLCTL nand controller
4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/nand.h>
36 #include <linux/mtd/partitions.h>
37 #include <linux/mtd/sh_flctl.h>
39 static struct nand_ecclayout flctl_4secc_oob_16
= {
41 .eccpos
= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
47 static struct nand_ecclayout flctl_4secc_oob_64
= {
50 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
51 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
52 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
53 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 },
55 {.offset
= 2, .length
= 4},
56 {.offset
= 16, .length
= 6},
57 {.offset
= 32, .length
= 6},
58 {.offset
= 48, .length
= 6} },
61 static uint8_t scan_ff_pattern
[] = { 0xff, 0xff };
63 static struct nand_bbt_descr flctl_4secc_smallpage
= {
64 .options
= NAND_BBT_SCAN2NDPAGE
,
67 .pattern
= scan_ff_pattern
,
70 static struct nand_bbt_descr flctl_4secc_largepage
= {
71 .options
= NAND_BBT_SCAN2NDPAGE
,
74 .pattern
= scan_ff_pattern
,
77 static void empty_fifo(struct sh_flctl
*flctl
)
79 writel(flctl
->flintdmacr_base
| AC1CLR
| AC0CLR
, FLINTDMACR(flctl
));
80 writel(flctl
->flintdmacr_base
, FLINTDMACR(flctl
));
83 static void start_translation(struct sh_flctl
*flctl
)
85 writeb(TRSTRT
, FLTRCR(flctl
));
88 static void timeout_error(struct sh_flctl
*flctl
, const char *str
)
90 dev_err(&flctl
->pdev
->dev
, "Timeout occurred in %s\n", str
);
93 static void wait_completion(struct sh_flctl
*flctl
)
95 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
98 if (readb(FLTRCR(flctl
)) & TREND
) {
99 writeb(0x0, FLTRCR(flctl
));
105 timeout_error(flctl
, __func__
);
106 writeb(0x0, FLTRCR(flctl
));
109 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
)
111 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
115 addr
= page_addr
; /* ERASE1 */
116 } else if (page_addr
!= -1) {
117 /* SEQIN, READ0, etc.. */
118 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
120 if (flctl
->page_size
) {
121 addr
= column
& 0x0FFF;
122 addr
|= (page_addr
& 0xff) << 16;
123 addr
|= ((page_addr
>> 8) & 0xff) << 24;
125 if (flctl
->rw_ADRCNT
== ADRCNT2_E
) {
127 addr2
= (page_addr
>> 16) & 0xff;
128 writel(addr2
, FLADR2(flctl
));
132 addr
|= (page_addr
& 0xff) << 8;
133 addr
|= ((page_addr
>> 8) & 0xff) << 16;
134 addr
|= ((page_addr
>> 16) & 0xff) << 24;
137 writel(addr
, FLADR(flctl
));
140 static void wait_rfifo_ready(struct sh_flctl
*flctl
)
142 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
147 val
= readl(FLDTCNTR(flctl
)) >> 16;
152 timeout_error(flctl
, __func__
);
155 static void wait_wfifo_ready(struct sh_flctl
*flctl
)
157 uint32_t len
, timeout
= LOOP_TIMEOUT_MAX
;
161 len
= (readl(FLDTCNTR(flctl
)) >> 16) & 0xFF;
166 timeout_error(flctl
, __func__
);
169 static enum flctl_ecc_res_t wait_recfifo_ready
170 (struct sh_flctl
*flctl
, int sector_number
)
172 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
173 void __iomem
*ecc_reg
[4];
175 int state
= FL_SUCCESS
;
179 * First this loops checks in FLDTCNTR if we are ready to read out the
180 * oob data. This is the case if either all went fine without errors or
181 * if the bottom part of the loop corrected the errors or marked them as
182 * uncorrectable and the controller is given time to push the data into
186 /* check if all is ok and we can read out the OOB */
187 size
= readl(FLDTCNTR(flctl
)) >> 24;
188 if ((size
& 0xFF) == 4)
191 /* check if a correction code has been calculated */
192 if (!(readl(FL4ECCCR(flctl
)) & _4ECCEND
)) {
194 * either we wait for the fifo to be filled or a
195 * correction pattern is being generated
201 /* check for an uncorrectable error */
202 if (readl(FL4ECCCR(flctl
)) & _4ECCFA
) {
203 /* check if we face a non-empty page */
204 for (i
= 0; i
< 512; i
++) {
205 if (flctl
->done_buff
[i
] != 0xff) {
206 state
= FL_ERROR
; /* can't correct */
211 if (state
== FL_SUCCESS
)
212 dev_dbg(&flctl
->pdev
->dev
,
213 "reading empty sector %d, ecc error ignored\n",
216 writel(0, FL4ECCCR(flctl
));
220 /* start error correction */
221 ecc_reg
[0] = FL4ECCRESULT0(flctl
);
222 ecc_reg
[1] = FL4ECCRESULT1(flctl
);
223 ecc_reg
[2] = FL4ECCRESULT2(flctl
);
224 ecc_reg
[3] = FL4ECCRESULT3(flctl
);
226 for (i
= 0; i
< 3; i
++) {
230 data
= readl(ecc_reg
[i
]);
232 if (flctl
->page_size
)
233 index
= (512 * sector_number
) +
238 org
= flctl
->done_buff
[index
];
239 flctl
->done_buff
[index
] = org
^ (data
& 0xFF);
241 state
= FL_REPAIRABLE
;
242 writel(0, FL4ECCCR(flctl
));
245 timeout_error(flctl
, __func__
);
246 return FL_TIMEOUT
; /* timeout */
249 static void wait_wecfifo_ready(struct sh_flctl
*flctl
)
251 uint32_t timeout
= LOOP_TIMEOUT_MAX
;
256 len
= (readl(FLDTCNTR(flctl
)) >> 24) & 0xFF;
261 timeout_error(flctl
, __func__
);
264 static void read_datareg(struct sh_flctl
*flctl
, int offset
)
267 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
269 wait_completion(flctl
);
271 data
= readl(FLDATAR(flctl
));
272 *buf
= le32_to_cpu(data
);
275 static void read_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
278 unsigned long *buf
= (unsigned long *)&flctl
->done_buff
[offset
];
280 len_4align
= (rlen
+ 3) / 4;
282 for (i
= 0; i
< len_4align
; i
++) {
283 wait_rfifo_ready(flctl
);
284 buf
[i
] = readl(FLDTFIFO(flctl
));
285 buf
[i
] = be32_to_cpu(buf
[i
]);
289 static enum flctl_ecc_res_t read_ecfiforeg
290 (struct sh_flctl
*flctl
, uint8_t *buff
, int sector
)
293 enum flctl_ecc_res_t res
;
294 unsigned long *ecc_buf
= (unsigned long *)buff
;
296 res
= wait_recfifo_ready(flctl
, sector
);
298 if (res
!= FL_ERROR
) {
299 for (i
= 0; i
< 4; i
++) {
300 ecc_buf
[i
] = readl(FLECFIFO(flctl
));
301 ecc_buf
[i
] = be32_to_cpu(ecc_buf
[i
]);
308 static void write_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
311 unsigned long *data
= (unsigned long *)&flctl
->done_buff
[offset
];
312 void *fifo_addr
= (void *)FLDTFIFO(flctl
);
314 len_4align
= (rlen
+ 3) / 4;
315 for (i
= 0; i
< len_4align
; i
++) {
316 wait_wfifo_ready(flctl
);
317 writel(cpu_to_be32(data
[i
]), fifo_addr
);
321 static void write_ec_fiforeg(struct sh_flctl
*flctl
, int rlen
, int offset
)
324 unsigned long *data
= (unsigned long *)&flctl
->done_buff
[offset
];
326 len_4align
= (rlen
+ 3) / 4;
327 for (i
= 0; i
< len_4align
; i
++) {
328 wait_wecfifo_ready(flctl
);
329 writel(cpu_to_be32(data
[i
]), FLECFIFO(flctl
));
333 static void set_cmd_regs(struct mtd_info
*mtd
, uint32_t cmd
, uint32_t flcmcdr_val
)
335 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
336 uint32_t flcmncr_val
= flctl
->flcmncr_base
& ~SEL_16BIT
;
337 uint32_t flcmdcr_val
, addr_len_bytes
= 0;
339 /* Set SNAND bit if page size is 2048byte */
340 if (flctl
->page_size
)
341 flcmncr_val
|= SNAND_E
;
343 flcmncr_val
&= ~SNAND_E
;
345 /* default FLCMDCR val */
346 flcmdcr_val
= DOCMD1_E
| DOADR_E
;
348 /* Set for FLCMDCR */
350 case NAND_CMD_ERASE1
:
351 addr_len_bytes
= flctl
->erase_ADRCNT
;
352 flcmdcr_val
|= DOCMD2_E
;
355 case NAND_CMD_READOOB
:
356 case NAND_CMD_RNDOUT
:
357 addr_len_bytes
= flctl
->rw_ADRCNT
;
358 flcmdcr_val
|= CDSRC_E
;
359 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
360 flcmncr_val
|= SEL_16BIT
;
363 /* This case is that cmd is READ0 or READ1 or READ00 */
364 flcmdcr_val
&= ~DOADR_E
; /* ONLY execute 1st cmd */
366 case NAND_CMD_PAGEPROG
:
367 addr_len_bytes
= flctl
->rw_ADRCNT
;
368 flcmdcr_val
|= DOCMD2_E
| CDSRC_E
| SELRW
;
369 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
370 flcmncr_val
|= SEL_16BIT
;
372 case NAND_CMD_READID
:
373 flcmncr_val
&= ~SNAND_E
;
374 flcmdcr_val
|= CDSRC_E
;
375 addr_len_bytes
= ADRCNT_1
;
377 case NAND_CMD_STATUS
:
379 flcmncr_val
&= ~SNAND_E
;
380 flcmdcr_val
&= ~(DOADR_E
| DOSR_E
);
386 /* Set address bytes parameter */
387 flcmdcr_val
|= addr_len_bytes
;
389 /* Now actually write */
390 writel(flcmncr_val
, FLCMNCR(flctl
));
391 writel(flcmdcr_val
, FLCMDCR(flctl
));
392 writel(flcmcdr_val
, FLCMCDR(flctl
));
395 static int flctl_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
396 uint8_t *buf
, int oob_required
, int page
)
398 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
400 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
404 static int flctl_write_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
405 const uint8_t *buf
, int oob_required
)
407 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
408 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
412 static void execmd_read_page_sector(struct mtd_info
*mtd
, int page_addr
)
414 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
415 int sector
, page_sectors
;
416 enum flctl_ecc_res_t ecc_result
;
418 page_sectors
= flctl
->page_size
? 4 : 1;
420 set_cmd_regs(mtd
, NAND_CMD_READ0
,
421 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
423 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
| _4ECCCORRECT
,
425 writel(readl(FLCMDCR(flctl
)) | page_sectors
, FLCMDCR(flctl
));
426 writel(page_addr
<< 2, FLADR(flctl
));
429 start_translation(flctl
);
431 for (sector
= 0; sector
< page_sectors
; sector
++) {
432 read_fiforeg(flctl
, 512, 512 * sector
);
434 ecc_result
= read_ecfiforeg(flctl
,
435 &flctl
->done_buff
[mtd
->writesize
+ 16 * sector
],
438 switch (ecc_result
) {
440 dev_info(&flctl
->pdev
->dev
,
441 "applied ecc on page 0x%x", page_addr
);
442 flctl
->mtd
.ecc_stats
.corrected
++;
445 dev_warn(&flctl
->pdev
->dev
,
446 "page 0x%x contains corrupted data\n",
448 flctl
->mtd
.ecc_stats
.failed
++;
455 wait_completion(flctl
);
457 writel(readl(FLCMNCR(flctl
)) & ~(ACM_SACCES_MODE
| _4ECCCORRECT
),
461 static void execmd_read_oob(struct mtd_info
*mtd
, int page_addr
)
463 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
464 int page_sectors
= flctl
->page_size
? 4 : 1;
467 set_cmd_regs(mtd
, NAND_CMD_READ0
,
468 (NAND_CMD_READSTART
<< 8) | NAND_CMD_READ0
);
472 for (i
= 0; i
< page_sectors
; i
++) {
473 set_addr(mtd
, (512 + 16) * i
+ 512 , page_addr
);
474 writel(16, FLDTCNTR(flctl
));
476 start_translation(flctl
);
477 read_fiforeg(flctl
, 16, 16 * i
);
478 wait_completion(flctl
);
482 static void execmd_write_page_sector(struct mtd_info
*mtd
)
484 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
485 int page_addr
= flctl
->seqin_page_addr
;
486 int sector
, page_sectors
;
488 page_sectors
= flctl
->page_size
? 4 : 1;
490 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
491 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
494 writel(readl(FLCMNCR(flctl
)) | ACM_SACCES_MODE
, FLCMNCR(flctl
));
495 writel(readl(FLCMDCR(flctl
)) | page_sectors
, FLCMDCR(flctl
));
496 writel(page_addr
<< 2, FLADR(flctl
));
497 start_translation(flctl
);
499 for (sector
= 0; sector
< page_sectors
; sector
++) {
500 write_fiforeg(flctl
, 512, 512 * sector
);
501 write_ec_fiforeg(flctl
, 16, mtd
->writesize
+ 16 * sector
);
504 wait_completion(flctl
);
505 writel(readl(FLCMNCR(flctl
)) & ~ACM_SACCES_MODE
, FLCMNCR(flctl
));
508 static void execmd_write_oob(struct mtd_info
*mtd
)
510 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
511 int page_addr
= flctl
->seqin_page_addr
;
512 int sector
, page_sectors
;
514 page_sectors
= flctl
->page_size
? 4 : 1;
516 set_cmd_regs(mtd
, NAND_CMD_PAGEPROG
,
517 (NAND_CMD_PAGEPROG
<< 8) | NAND_CMD_SEQIN
);
519 for (sector
= 0; sector
< page_sectors
; sector
++) {
521 set_addr(mtd
, sector
* 528 + 512, page_addr
);
522 writel(16, FLDTCNTR(flctl
)); /* set read size */
524 start_translation(flctl
);
525 write_fiforeg(flctl
, 16, 16 * sector
);
526 wait_completion(flctl
);
530 static void flctl_cmdfunc(struct mtd_info
*mtd
, unsigned int command
,
531 int column
, int page_addr
)
533 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
534 uint32_t read_cmd
= 0;
536 pm_runtime_get_sync(&flctl
->pdev
->dev
);
538 flctl
->read_bytes
= 0;
539 if (command
!= NAND_CMD_PAGEPROG
)
546 /* read page with hwecc */
547 execmd_read_page_sector(mtd
, page_addr
);
550 if (flctl
->page_size
)
551 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
554 set_cmd_regs(mtd
, command
, command
);
556 set_addr(mtd
, 0, page_addr
);
558 flctl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
;
559 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
561 flctl
->index
+= column
;
562 goto read_normal_exit
;
564 case NAND_CMD_READOOB
:
566 /* read page with hwecc */
567 execmd_read_oob(mtd
, page_addr
);
571 if (flctl
->page_size
) {
572 set_cmd_regs(mtd
, command
, (NAND_CMD_READSTART
<< 8)
574 set_addr(mtd
, mtd
->writesize
, page_addr
);
576 set_cmd_regs(mtd
, command
, command
);
577 set_addr(mtd
, 0, page_addr
);
579 flctl
->read_bytes
= mtd
->oobsize
;
580 goto read_normal_exit
;
582 case NAND_CMD_RNDOUT
:
586 if (flctl
->page_size
)
587 set_cmd_regs(mtd
, command
, (NAND_CMD_RNDOUTSTART
<< 8)
590 set_cmd_regs(mtd
, command
, command
);
592 set_addr(mtd
, column
, 0);
594 flctl
->read_bytes
= mtd
->writesize
+ mtd
->oobsize
- column
;
595 goto read_normal_exit
;
597 case NAND_CMD_READID
:
598 set_cmd_regs(mtd
, command
, command
);
600 /* READID is always performed using an 8-bit bus */
601 if (flctl
->chip
.options
& NAND_BUSWIDTH_16
)
603 set_addr(mtd
, column
, 0);
605 flctl
->read_bytes
= 8;
606 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
608 start_translation(flctl
);
609 read_fiforeg(flctl
, flctl
->read_bytes
, 0);
610 wait_completion(flctl
);
613 case NAND_CMD_ERASE1
:
614 flctl
->erase1_page_addr
= page_addr
;
617 case NAND_CMD_ERASE2
:
618 set_cmd_regs(mtd
, NAND_CMD_ERASE1
,
619 (command
<< 8) | NAND_CMD_ERASE1
);
620 set_addr(mtd
, -1, flctl
->erase1_page_addr
);
621 start_translation(flctl
);
622 wait_completion(flctl
);
626 if (!flctl
->page_size
) {
627 /* output read command */
628 if (column
>= mtd
->writesize
) {
629 column
-= mtd
->writesize
;
630 read_cmd
= NAND_CMD_READOOB
;
631 } else if (column
< 256) {
632 read_cmd
= NAND_CMD_READ0
;
635 read_cmd
= NAND_CMD_READ1
;
638 flctl
->seqin_column
= column
;
639 flctl
->seqin_page_addr
= page_addr
;
640 flctl
->seqin_read_cmd
= read_cmd
;
643 case NAND_CMD_PAGEPROG
:
645 if (!flctl
->page_size
) {
646 set_cmd_regs(mtd
, NAND_CMD_SEQIN
,
647 flctl
->seqin_read_cmd
);
648 set_addr(mtd
, -1, -1);
649 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
650 start_translation(flctl
);
651 wait_completion(flctl
);
654 /* write page with hwecc */
655 if (flctl
->seqin_column
== mtd
->writesize
)
656 execmd_write_oob(mtd
);
657 else if (!flctl
->seqin_column
)
658 execmd_write_page_sector(mtd
);
660 printk(KERN_ERR
"Invalid address !?\n");
663 set_cmd_regs(mtd
, command
, (command
<< 8) | NAND_CMD_SEQIN
);
664 set_addr(mtd
, flctl
->seqin_column
, flctl
->seqin_page_addr
);
665 writel(flctl
->index
, FLDTCNTR(flctl
)); /* set write size */
666 start_translation(flctl
);
667 write_fiforeg(flctl
, flctl
->index
, 0);
668 wait_completion(flctl
);
671 case NAND_CMD_STATUS
:
672 set_cmd_regs(mtd
, command
, command
);
673 set_addr(mtd
, -1, -1);
675 flctl
->read_bytes
= 1;
676 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
677 start_translation(flctl
);
678 read_datareg(flctl
, 0); /* read and end */
682 set_cmd_regs(mtd
, command
, command
);
683 set_addr(mtd
, -1, -1);
685 writel(0, FLDTCNTR(flctl
)); /* set 0 size */
686 start_translation(flctl
);
687 wait_completion(flctl
);
696 writel(flctl
->read_bytes
, FLDTCNTR(flctl
)); /* set read size */
698 start_translation(flctl
);
699 read_fiforeg(flctl
, flctl
->read_bytes
, 0);
700 wait_completion(flctl
);
702 pm_runtime_put_sync(&flctl
->pdev
->dev
);
706 static void flctl_select_chip(struct mtd_info
*mtd
, int chipnr
)
708 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
713 flctl
->flcmncr_base
&= ~CE0_ENABLE
;
715 pm_runtime_get_sync(&flctl
->pdev
->dev
);
716 writel(flctl
->flcmncr_base
, FLCMNCR(flctl
));
718 if (flctl
->qos_request
) {
719 dev_pm_qos_remove_request(&flctl
->pm_qos
);
720 flctl
->qos_request
= 0;
723 pm_runtime_put_sync(&flctl
->pdev
->dev
);
726 flctl
->flcmncr_base
|= CE0_ENABLE
;
728 if (!flctl
->qos_request
) {
729 ret
= dev_pm_qos_add_request(&flctl
->pdev
->dev
,
734 dev_err(&flctl
->pdev
->dev
,
735 "PM QoS request failed: %d\n", ret
);
736 flctl
->qos_request
= 1;
740 pm_runtime_get_sync(&flctl
->pdev
->dev
);
741 writel(HOLDEN
, FLHOLDCR(flctl
));
742 pm_runtime_put_sync(&flctl
->pdev
->dev
);
750 static void flctl_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
752 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
753 int index
= flctl
->index
;
755 memcpy(&flctl
->done_buff
[index
], buf
, len
);
759 static uint8_t flctl_read_byte(struct mtd_info
*mtd
)
761 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
762 int index
= flctl
->index
;
765 data
= flctl
->done_buff
[index
];
770 static uint16_t flctl_read_word(struct mtd_info
*mtd
)
772 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
773 int index
= flctl
->index
;
775 uint16_t *buf
= (uint16_t *)&flctl
->done_buff
[index
];
782 static void flctl_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
784 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
785 int index
= flctl
->index
;
787 memcpy(buf
, &flctl
->done_buff
[index
], len
);
791 static int flctl_chip_init_tail(struct mtd_info
*mtd
)
793 struct sh_flctl
*flctl
= mtd_to_flctl(mtd
);
794 struct nand_chip
*chip
= &flctl
->chip
;
796 if (mtd
->writesize
== 512) {
797 flctl
->page_size
= 0;
798 if (chip
->chipsize
> (32 << 20)) {
800 flctl
->rw_ADRCNT
= ADRCNT_4
;
801 flctl
->erase_ADRCNT
= ADRCNT_3
;
802 } else if (chip
->chipsize
> (2 << 16)) {
804 flctl
->rw_ADRCNT
= ADRCNT_3
;
805 flctl
->erase_ADRCNT
= ADRCNT_2
;
807 flctl
->rw_ADRCNT
= ADRCNT_2
;
808 flctl
->erase_ADRCNT
= ADRCNT_1
;
811 flctl
->page_size
= 1;
812 if (chip
->chipsize
> (128 << 20)) {
814 flctl
->rw_ADRCNT
= ADRCNT2_E
;
815 flctl
->erase_ADRCNT
= ADRCNT_3
;
816 } else if (chip
->chipsize
> (8 << 16)) {
818 flctl
->rw_ADRCNT
= ADRCNT_4
;
819 flctl
->erase_ADRCNT
= ADRCNT_2
;
821 flctl
->rw_ADRCNT
= ADRCNT_3
;
822 flctl
->erase_ADRCNT
= ADRCNT_1
;
827 if (mtd
->writesize
== 512) {
828 chip
->ecc
.layout
= &flctl_4secc_oob_16
;
829 chip
->badblock_pattern
= &flctl_4secc_smallpage
;
831 chip
->ecc
.layout
= &flctl_4secc_oob_64
;
832 chip
->badblock_pattern
= &flctl_4secc_largepage
;
835 chip
->ecc
.size
= 512;
836 chip
->ecc
.bytes
= 10;
837 chip
->ecc
.strength
= 4;
838 chip
->ecc
.read_page
= flctl_read_page_hwecc
;
839 chip
->ecc
.write_page
= flctl_write_page_hwecc
;
840 chip
->ecc
.mode
= NAND_ECC_HW
;
842 /* 4 symbols ECC enabled */
843 flctl
->flcmncr_base
|= _4ECCEN
;
845 chip
->ecc
.mode
= NAND_ECC_SOFT
;
851 static irqreturn_t
flctl_handle_flste(int irq
, void *dev_id
)
853 struct sh_flctl
*flctl
= dev_id
;
855 dev_err(&flctl
->pdev
->dev
, "flste irq: %x\n", readl(FLINTDMACR(flctl
)));
856 writel(flctl
->flintdmacr_base
, FLINTDMACR(flctl
));
861 static int __devinit
flctl_probe(struct platform_device
*pdev
)
863 struct resource
*res
;
864 struct sh_flctl
*flctl
;
865 struct mtd_info
*flctl_mtd
;
866 struct nand_chip
*nand
;
867 struct sh_flctl_platform_data
*pdata
;
871 pdata
= pdev
->dev
.platform_data
;
873 dev_err(&pdev
->dev
, "no platform data defined\n");
877 flctl
= kzalloc(sizeof(struct sh_flctl
), GFP_KERNEL
);
879 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
883 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
885 dev_err(&pdev
->dev
, "failed to get I/O memory\n");
889 flctl
->reg
= ioremap(res
->start
, resource_size(res
));
890 if (flctl
->reg
== NULL
) {
891 dev_err(&pdev
->dev
, "failed to remap I/O memory\n");
895 irq
= platform_get_irq(pdev
, 0);
897 dev_err(&pdev
->dev
, "failed to get flste irq data\n");
901 ret
= request_irq(irq
, flctl_handle_flste
, IRQF_SHARED
, "flste", flctl
);
903 dev_err(&pdev
->dev
, "request interrupt failed.\n");
907 platform_set_drvdata(pdev
, flctl
);
908 flctl_mtd
= &flctl
->mtd
;
910 flctl_mtd
->priv
= nand
;
912 flctl
->hwecc
= pdata
->has_hwecc
;
913 flctl
->holden
= pdata
->use_holden
;
914 flctl
->flcmncr_base
= pdata
->flcmncr_val
;
915 flctl
->flintdmacr_base
= flctl
->hwecc
? (STERINTE
| ECERB
) : STERINTE
;
917 /* Set address of hardware control function */
918 /* 20 us command delay time */
919 nand
->chip_delay
= 20;
921 nand
->read_byte
= flctl_read_byte
;
922 nand
->write_buf
= flctl_write_buf
;
923 nand
->read_buf
= flctl_read_buf
;
924 nand
->select_chip
= flctl_select_chip
;
925 nand
->cmdfunc
= flctl_cmdfunc
;
927 if (pdata
->flcmncr_val
& SEL_16BIT
) {
928 nand
->options
|= NAND_BUSWIDTH_16
;
929 nand
->read_word
= flctl_read_word
;
932 pm_runtime_enable(&pdev
->dev
);
933 pm_runtime_resume(&pdev
->dev
);
935 ret
= nand_scan_ident(flctl_mtd
, 1, NULL
);
939 ret
= flctl_chip_init_tail(flctl_mtd
);
943 ret
= nand_scan_tail(flctl_mtd
);
947 mtd_device_register(flctl_mtd
, pdata
->parts
, pdata
->nr_parts
);
952 pm_runtime_disable(&pdev
->dev
);
953 free_irq(irq
, flctl
);
961 static int __devexit
flctl_remove(struct platform_device
*pdev
)
963 struct sh_flctl
*flctl
= platform_get_drvdata(pdev
);
965 nand_release(&flctl
->mtd
);
966 pm_runtime_disable(&pdev
->dev
);
967 free_irq(platform_get_irq(pdev
, 0), flctl
);
974 static struct platform_driver flctl_driver
= {
975 .remove
= flctl_remove
,
978 .owner
= THIS_MODULE
,
982 static int __init
flctl_nand_init(void)
984 return platform_driver_probe(&flctl_driver
, flctl_probe
);
987 static void __exit
flctl_nand_cleanup(void)
989 platform_driver_unregister(&flctl_driver
);
992 module_init(flctl_nand_init
);
993 module_exit(flctl_nand_cleanup
);
995 MODULE_LICENSE("GPL");
996 MODULE_AUTHOR("Yoshihiro Shimoda");
997 MODULE_DESCRIPTION("SuperH FLCTL driver");
998 MODULE_ALIAS("platform:sh_flctl");