2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
5 * https://github.com/yuq/sunxi-nfc-mtd
6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
8 * https://github.com/hno/Allwinner-Info
9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/platform_device.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mtd.h>
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/nand.h>
36 #include <linux/mtd/partitions.h>
37 #include <linux/clk.h>
38 #include <linux/delay.h>
39 #include <linux/dmaengine.h>
40 #include <linux/gpio.h>
41 #include <linux/interrupt.h>
44 #define NFC_REG_CTL 0x0000
45 #define NFC_REG_ST 0x0004
46 #define NFC_REG_INT 0x0008
47 #define NFC_REG_TIMING_CTL 0x000C
48 #define NFC_REG_TIMING_CFG 0x0010
49 #define NFC_REG_ADDR_LOW 0x0014
50 #define NFC_REG_ADDR_HIGH 0x0018
51 #define NFC_REG_SECTOR_NUM 0x001C
52 #define NFC_REG_CNT 0x0020
53 #define NFC_REG_CMD 0x0024
54 #define NFC_REG_RCMD_SET 0x0028
55 #define NFC_REG_WCMD_SET 0x002C
56 #define NFC_REG_IO_DATA 0x0030
57 #define NFC_REG_ECC_CTL 0x0034
58 #define NFC_REG_ECC_ST 0x0038
59 #define NFC_REG_DEBUG 0x003C
60 #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3)
61 #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
62 #define NFC_REG_SPARE_AREA 0x00A0
63 #define NFC_RAM0_BASE 0x0400
64 #define NFC_RAM1_BASE 0x0800
66 /* define bit use in NFC_CTL */
68 #define NFC_RESET BIT(1)
69 #define NFC_BUS_WIDTH_MSK BIT(2)
70 #define NFC_BUS_WIDTH_8 (0 << 2)
71 #define NFC_BUS_WIDTH_16 (1 << 2)
72 #define NFC_RB_SEL_MSK BIT(3)
73 #define NFC_RB_SEL(x) ((x) << 3)
74 #define NFC_CE_SEL_MSK GENMASK(26, 24)
75 #define NFC_CE_SEL(x) ((x) << 24)
76 #define NFC_CE_CTL BIT(6)
77 #define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
78 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
79 #define NFC_SAM BIT(12)
80 #define NFC_RAM_METHOD BIT(14)
81 #define NFC_DEBUG_CTL BIT(31)
83 /* define bit use in NFC_ST */
84 #define NFC_RB_B2R BIT(0)
85 #define NFC_CMD_INT_FLAG BIT(1)
86 #define NFC_DMA_INT_FLAG BIT(2)
87 #define NFC_CMD_FIFO_STATUS BIT(3)
88 #define NFC_STA BIT(4)
89 #define NFC_NATCH_INT_FLAG BIT(5)
90 #define NFC_RB_STATE(x) BIT(x + 8)
92 /* define bit use in NFC_INT */
93 #define NFC_B2R_INT_ENABLE BIT(0)
94 #define NFC_CMD_INT_ENABLE BIT(1)
95 #define NFC_DMA_INT_ENABLE BIT(2)
96 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
97 NFC_CMD_INT_ENABLE | \
100 /* define bit use in NFC_TIMING_CTL */
101 #define NFC_TIMING_CTL_EDO BIT(8)
103 /* define NFC_TIMING_CFG register layout */
104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
105 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
106 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
107 (((tCAD) & 0x7) << 8))
109 /* define bit use in NFC_CMD */
110 #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
111 #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
112 #define NFC_CMD(x) (x)
113 #define NFC_ADR_NUM_MSK GENMASK(18, 16)
114 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
115 #define NFC_SEND_ADR BIT(19)
116 #define NFC_ACCESS_DIR BIT(20)
117 #define NFC_DATA_TRANS BIT(21)
118 #define NFC_SEND_CMD1 BIT(22)
119 #define NFC_WAIT_FLAG BIT(23)
120 #define NFC_SEND_CMD2 BIT(24)
121 #define NFC_SEQ BIT(25)
122 #define NFC_DATA_SWAP_METHOD BIT(26)
123 #define NFC_ROW_AUTO_INC BIT(27)
124 #define NFC_SEND_CMD3 BIT(28)
125 #define NFC_SEND_CMD4 BIT(29)
126 #define NFC_CMD_TYPE_MSK GENMASK(31, 30)
127 #define NFC_NORMAL_OP (0 << 30)
128 #define NFC_ECC_OP (1 << 30)
129 #define NFC_PAGE_OP (2 << 30)
131 /* define bit use in NFC_RCMD_SET */
132 #define NFC_READ_CMD_MSK GENMASK(7, 0)
133 #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
134 #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
136 /* define bit use in NFC_WCMD_SET */
137 #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
138 #define NFC_RND_WRITE_CMD_MSK GENMASK(15, 8)
139 #define NFC_READ_CMD0_MSK GENMASK(23, 16)
140 #define NFC_READ_CMD1_MSK GENMASK(31, 24)
142 /* define bit use in NFC_ECC_CTL */
143 #define NFC_ECC_EN BIT(0)
144 #define NFC_ECC_PIPELINE BIT(3)
145 #define NFC_ECC_EXCEPTION BIT(4)
146 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5)
147 #define NFC_RANDOM_EN BIT(9)
148 #define NFC_RANDOM_DIRECTION BIT(10)
149 #define NFC_ECC_MODE_MSK GENMASK(15, 12)
150 #define NFC_ECC_MODE(x) ((x) << 12)
151 #define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
152 #define NFC_RANDOM_SEED(x) ((x) << 16)
154 /* define bit use in NFC_ECC_ST */
155 #define NFC_ECC_ERR(x) BIT(x)
156 #define NFC_ECC_PAT_FOUND(x) BIT(x + 16)
157 #define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff)
159 #define NFC_DEFAULT_TIMEOUT_MS 1000
161 #define NFC_SRAM_SIZE 1024
166 * Ready/Busy detection type: describes the Ready/Busy detection modes
168 * @RB_NONE: no external detection available, rely on STATUS command
169 * and software timeouts
170 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
171 * pin of the NAND flash chip must be connected to one of the
172 * native NAND R/B pins (those which can be muxed to the NAND
174 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
175 * pin of the NAND flash chip must be connected to a GPIO capable
178 enum sunxi_nand_rb_type
{
185 * Ready/Busy structure: stores information related to Ready/Busy detection
187 * @type: the Ready/Busy detection mode
188 * @info: information related to the R/B detection mode. Either a gpio
189 * id or a native R/B id (those supported by the NAND controller).
191 struct sunxi_nand_rb
{
192 enum sunxi_nand_rb_type type
;
200 * Chip Select structure: stores information related to NAND Chip Select
202 * @cs: the NAND CS id used to communicate with a NAND Chip
203 * @rb: the Ready/Busy description
205 struct sunxi_nand_chip_sel
{
207 struct sunxi_nand_rb rb
;
211 * sunxi HW ECC infos: stores information related to HW ECC support
213 * @mode: the sunxi ECC mode field deduced from ECC requirements
214 * @layout: the OOB layout depending on the ECC requirements and the
217 struct sunxi_nand_hw_ecc
{
219 struct nand_ecclayout layout
;
223 * NAND chip structure: stores NAND chip device related information
225 * @node: used to store NAND chips into a list
226 * @nand: base NAND chip structure
227 * @mtd: base MTD structure
228 * @clk_rate: clk_rate required for this NAND chip
229 * @timing_cfg TIMING_CFG register value for this NAND chip
230 * @selected: current active CS
231 * @nsels: number of CS lines required by the NAND chip
232 * @sels: array of CS lines descriptions
234 struct sunxi_nand_chip
{
235 struct list_head node
;
236 struct nand_chip nand
;
237 unsigned long clk_rate
;
242 struct sunxi_nand_chip_sel sels
[0];
245 static inline struct sunxi_nand_chip
*to_sunxi_nand(struct nand_chip
*nand
)
247 return container_of(nand
, struct sunxi_nand_chip
, nand
);
251 * NAND Controller structure: stores sunxi NAND controller information
253 * @controller: base controller structure
254 * @dev: parent device (used to print error messages)
255 * @regs: NAND controller registers
256 * @ahb_clk: NAND Controller AHB clock
257 * @mod_clk: NAND Controller mod clock
258 * @assigned_cs: bitmask describing already assigned CS lines
259 * @clk_rate: NAND controller current clock rate
260 * @chips: a list containing all the NAND chips attached to
261 * this NAND controller
262 * @complete: a completion object used to wait for NAND
266 struct nand_hw_control controller
;
271 unsigned long assigned_cs
;
272 unsigned long clk_rate
;
273 struct list_head chips
;
274 struct completion complete
;
277 static inline struct sunxi_nfc
*to_sunxi_nfc(struct nand_hw_control
*ctrl
)
279 return container_of(ctrl
, struct sunxi_nfc
, controller
);
282 static irqreturn_t
sunxi_nfc_interrupt(int irq
, void *dev_id
)
284 struct sunxi_nfc
*nfc
= dev_id
;
285 u32 st
= readl(nfc
->regs
+ NFC_REG_ST
);
286 u32 ien
= readl(nfc
->regs
+ NFC_REG_INT
);
291 if ((ien
& st
) == ien
)
292 complete(&nfc
->complete
);
294 writel(st
& NFC_INT_MASK
, nfc
->regs
+ NFC_REG_ST
);
295 writel(~st
& ien
& NFC_INT_MASK
, nfc
->regs
+ NFC_REG_INT
);
300 static int sunxi_nfc_wait_int(struct sunxi_nfc
*nfc
, u32 flags
,
301 unsigned int timeout_ms
)
303 init_completion(&nfc
->complete
);
305 writel(flags
, nfc
->regs
+ NFC_REG_INT
);
308 timeout_ms
= NFC_DEFAULT_TIMEOUT_MS
;
310 if (!wait_for_completion_timeout(&nfc
->complete
,
311 msecs_to_jiffies(timeout_ms
))) {
312 dev_err(nfc
->dev
, "wait interrupt timedout\n");
319 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc
*nfc
)
321 unsigned long timeout
= jiffies
+
322 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS
);
325 if (!(readl(nfc
->regs
+ NFC_REG_ST
) & NFC_CMD_FIFO_STATUS
))
327 } while (time_before(jiffies
, timeout
));
329 dev_err(nfc
->dev
, "wait for empty cmd FIFO timedout\n");
333 static int sunxi_nfc_rst(struct sunxi_nfc
*nfc
)
335 unsigned long timeout
= jiffies
+
336 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS
);
338 writel(0, nfc
->regs
+ NFC_REG_ECC_CTL
);
339 writel(NFC_RESET
, nfc
->regs
+ NFC_REG_CTL
);
342 if (!(readl(nfc
->regs
+ NFC_REG_CTL
) & NFC_RESET
))
344 } while (time_before(jiffies
, timeout
));
346 dev_err(nfc
->dev
, "wait for NAND controller reset timedout\n");
350 static int sunxi_nfc_dev_ready(struct mtd_info
*mtd
)
352 struct nand_chip
*nand
= mtd_to_nand(mtd
);
353 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
354 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
355 struct sunxi_nand_rb
*rb
;
356 unsigned long timeo
= (sunxi_nand
->nand
.state
== FL_ERASING
? 400 : 20);
359 if (sunxi_nand
->selected
< 0)
362 rb
= &sunxi_nand
->sels
[sunxi_nand
->selected
].rb
;
366 ret
= !!(readl(nfc
->regs
+ NFC_REG_ST
) &
367 NFC_RB_STATE(rb
->info
.nativeid
));
371 sunxi_nfc_wait_int(nfc
, NFC_RB_B2R
, timeo
);
372 ret
= !!(readl(nfc
->regs
+ NFC_REG_ST
) &
373 NFC_RB_STATE(rb
->info
.nativeid
));
376 ret
= gpio_get_value(rb
->info
.gpio
);
381 dev_err(nfc
->dev
, "cannot check R/B NAND status!\n");
388 static void sunxi_nfc_select_chip(struct mtd_info
*mtd
, int chip
)
390 struct nand_chip
*nand
= mtd_to_nand(mtd
);
391 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
392 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
393 struct sunxi_nand_chip_sel
*sel
;
396 if (chip
> 0 && chip
>= sunxi_nand
->nsels
)
399 if (chip
== sunxi_nand
->selected
)
402 ctl
= readl(nfc
->regs
+ NFC_REG_CTL
) &
403 ~(NFC_PAGE_SHIFT_MSK
| NFC_CE_SEL_MSK
| NFC_RB_SEL_MSK
| NFC_EN
);
406 sel
= &sunxi_nand
->sels
[chip
];
408 ctl
|= NFC_CE_SEL(sel
->cs
) | NFC_EN
|
409 NFC_PAGE_SHIFT(nand
->page_shift
- 10);
410 if (sel
->rb
.type
== RB_NONE
) {
411 nand
->dev_ready
= NULL
;
413 nand
->dev_ready
= sunxi_nfc_dev_ready
;
414 if (sel
->rb
.type
== RB_NATIVE
)
415 ctl
|= NFC_RB_SEL(sel
->rb
.info
.nativeid
);
418 writel(mtd
->writesize
, nfc
->regs
+ NFC_REG_SPARE_AREA
);
420 if (nfc
->clk_rate
!= sunxi_nand
->clk_rate
) {
421 clk_set_rate(nfc
->mod_clk
, sunxi_nand
->clk_rate
);
422 nfc
->clk_rate
= sunxi_nand
->clk_rate
;
426 writel(sunxi_nand
->timing_ctl
, nfc
->regs
+ NFC_REG_TIMING_CTL
);
427 writel(sunxi_nand
->timing_cfg
, nfc
->regs
+ NFC_REG_TIMING_CFG
);
428 writel(ctl
, nfc
->regs
+ NFC_REG_CTL
);
430 sunxi_nand
->selected
= chip
;
433 static void sunxi_nfc_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
435 struct nand_chip
*nand
= mtd_to_nand(mtd
);
436 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
437 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
444 cnt
= min(len
- offs
, NFC_SRAM_SIZE
);
446 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
450 writel(cnt
, nfc
->regs
+ NFC_REG_CNT
);
451 tmp
= NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
;
452 writel(tmp
, nfc
->regs
+ NFC_REG_CMD
);
454 ret
= sunxi_nfc_wait_int(nfc
, NFC_CMD_INT_FLAG
, 0);
459 memcpy_fromio(buf
+ offs
, nfc
->regs
+ NFC_RAM0_BASE
,
465 static void sunxi_nfc_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
,
468 struct nand_chip
*nand
= mtd_to_nand(mtd
);
469 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
470 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
477 cnt
= min(len
- offs
, NFC_SRAM_SIZE
);
479 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
483 writel(cnt
, nfc
->regs
+ NFC_REG_CNT
);
484 memcpy_toio(nfc
->regs
+ NFC_RAM0_BASE
, buf
+ offs
, cnt
);
485 tmp
= NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
|
487 writel(tmp
, nfc
->regs
+ NFC_REG_CMD
);
489 ret
= sunxi_nfc_wait_int(nfc
, NFC_CMD_INT_FLAG
, 0);
497 static uint8_t sunxi_nfc_read_byte(struct mtd_info
*mtd
)
501 sunxi_nfc_read_buf(mtd
, &ret
, 1);
506 static void sunxi_nfc_cmd_ctrl(struct mtd_info
*mtd
, int dat
,
509 struct nand_chip
*nand
= mtd_to_nand(mtd
);
510 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
511 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
515 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
519 if (ctrl
& NAND_CTRL_CHANGE
) {
520 tmp
= readl(nfc
->regs
+ NFC_REG_CTL
);
525 writel(tmp
, nfc
->regs
+ NFC_REG_CTL
);
528 if (dat
== NAND_CMD_NONE
)
531 if (ctrl
& NAND_CLE
) {
532 writel(NFC_SEND_CMD1
| dat
, nfc
->regs
+ NFC_REG_CMD
);
534 writel(dat
, nfc
->regs
+ NFC_REG_ADDR_LOW
);
535 writel(NFC_SEND_ADR
, nfc
->regs
+ NFC_REG_CMD
);
538 sunxi_nfc_wait_int(nfc
, NFC_CMD_INT_FLAG
, 0);
541 static void sunxi_nfc_hw_ecc_enable(struct mtd_info
*mtd
)
543 struct nand_chip
*nand
= mtd_to_nand(mtd
);
544 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
545 struct sunxi_nand_hw_ecc
*data
= nand
->ecc
.priv
;
548 ecc_ctl
= readl(nfc
->regs
+ NFC_REG_ECC_CTL
);
549 ecc_ctl
&= ~(NFC_ECC_MODE_MSK
| NFC_ECC_PIPELINE
|
550 NFC_ECC_BLOCK_SIZE_MSK
);
551 ecc_ctl
|= NFC_ECC_EN
| NFC_ECC_MODE(data
->mode
) | NFC_ECC_EXCEPTION
;
553 writel(ecc_ctl
, nfc
->regs
+ NFC_REG_ECC_CTL
);
556 static void sunxi_nfc_hw_ecc_disable(struct mtd_info
*mtd
)
558 struct nand_chip
*nand
= mtd_to_nand(mtd
);
559 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
561 writel(readl(nfc
->regs
+ NFC_REG_ECC_CTL
) & ~NFC_ECC_EN
,
562 nfc
->regs
+ NFC_REG_ECC_CTL
);
565 static inline void sunxi_nfc_user_data_to_buf(u32 user_data
, u8
*buf
)
568 buf
[1] = user_data
>> 8;
569 buf
[2] = user_data
>> 16;
570 buf
[3] = user_data
>> 24;
573 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info
*mtd
,
574 u8
*data
, int data_off
,
575 u8
*oob
, int oob_off
,
577 unsigned int *max_bitflips
)
579 struct nand_chip
*nand
= mtd_to_nand(mtd
);
580 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
581 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
585 if (*cur_off
!= data_off
)
586 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, data_off
, -1);
588 sunxi_nfc_read_buf(mtd
, NULL
, ecc
->size
);
590 if (data_off
+ ecc
->size
!= oob_off
)
591 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, oob_off
, -1);
593 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
597 writel(NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
| NFC_ECC_OP
,
598 nfc
->regs
+ NFC_REG_CMD
);
600 ret
= sunxi_nfc_wait_int(nfc
, NFC_CMD_INT_FLAG
, 0);
604 status
= readl(nfc
->regs
+ NFC_REG_ECC_ST
);
605 ret
= NFC_ECC_ERR_CNT(0, readl(nfc
->regs
+ NFC_REG_ECC_ERR_CNT(0)));
607 memcpy_fromio(data
, nfc
->regs
+ NFC_RAM0_BASE
, ecc
->size
);
609 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, oob_off
, -1);
610 sunxi_nfc_read_buf(mtd
, oob
, ecc
->bytes
+ 4);
612 if (status
& NFC_ECC_ERR(0)) {
613 ret
= nand_check_erased_ecc_chunk(data
, ecc
->size
,
615 NULL
, 0, ecc
->strength
);
618 * The engine protects 4 bytes of OOB data per chunk.
619 * Retrieve the corrected OOB bytes.
621 sunxi_nfc_user_data_to_buf(readl(nfc
->regs
+ NFC_REG_USER_DATA(0)),
626 mtd
->ecc_stats
.failed
++;
628 mtd
->ecc_stats
.corrected
+= ret
;
629 *max_bitflips
= max_t(unsigned int, *max_bitflips
, ret
);
632 *cur_off
= oob_off
+ ecc
->bytes
+ 4;
637 static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info
*mtd
,
638 u8
*oob
, int *cur_off
)
640 struct nand_chip
*nand
= mtd_to_nand(mtd
);
641 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
642 int offset
= ((ecc
->bytes
+ 4) * ecc
->steps
);
643 int len
= mtd
->oobsize
- offset
;
648 if (*cur_off
!= offset
)
649 nand
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
650 offset
+ mtd
->writesize
, -1);
652 sunxi_nfc_read_buf(mtd
, oob
+ offset
, len
);
654 *cur_off
= mtd
->oobsize
+ mtd
->writesize
;
657 static inline u32
sunxi_nfc_buf_to_user_data(const u8
*buf
)
659 return buf
[0] | (buf
[1] << 8) | (buf
[2] << 16) | (buf
[3] << 24);
662 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info
*mtd
,
663 const u8
*data
, int data_off
,
664 const u8
*oob
, int oob_off
,
667 struct nand_chip
*nand
= mtd_to_nand(mtd
);
668 struct sunxi_nfc
*nfc
= to_sunxi_nfc(nand
->controller
);
669 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
672 if (data_off
!= *cur_off
)
673 nand
->cmdfunc(mtd
, NAND_CMD_RNDIN
, data_off
, -1);
675 sunxi_nfc_write_buf(mtd
, data
, ecc
->size
);
677 /* Fill OOB data in */
678 writel(sunxi_nfc_buf_to_user_data(oob
),
679 nfc
->regs
+ NFC_REG_USER_DATA(0));
681 if (data_off
+ ecc
->size
!= oob_off
)
682 nand
->cmdfunc(mtd
, NAND_CMD_RNDIN
, oob_off
, -1);
684 ret
= sunxi_nfc_wait_cmd_fifo_empty(nfc
);
688 writel(NFC_DATA_TRANS
| NFC_DATA_SWAP_METHOD
|
689 NFC_ACCESS_DIR
| NFC_ECC_OP
,
690 nfc
->regs
+ NFC_REG_CMD
);
692 ret
= sunxi_nfc_wait_int(nfc
, NFC_CMD_INT_FLAG
, 0);
696 *cur_off
= oob_off
+ ecc
->bytes
+ 4;
701 static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info
*mtd
,
702 u8
*oob
, int *cur_off
)
704 struct nand_chip
*nand
= mtd_to_nand(mtd
);
705 struct nand_ecc_ctrl
*ecc
= &nand
->ecc
;
706 int offset
= ((ecc
->bytes
+ 4) * ecc
->steps
);
707 int len
= mtd
->oobsize
- offset
;
712 if (*cur_off
!= offset
)
713 nand
->cmdfunc(mtd
, NAND_CMD_RNDIN
,
714 offset
+ mtd
->writesize
, -1);
716 sunxi_nfc_write_buf(mtd
, oob
+ offset
, len
);
718 *cur_off
= mtd
->oobsize
+ mtd
->writesize
;
721 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info
*mtd
,
722 struct nand_chip
*chip
, uint8_t *buf
,
723 int oob_required
, int page
)
725 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
726 unsigned int max_bitflips
= 0;
727 int ret
, i
, cur_off
= 0;
729 sunxi_nfc_hw_ecc_enable(mtd
);
731 for (i
= 0; i
< ecc
->steps
; i
++) {
732 int data_off
= i
* ecc
->size
;
733 int oob_off
= i
* (ecc
->bytes
+ 4);
734 u8
*data
= buf
+ data_off
;
735 u8
*oob
= chip
->oob_poi
+ oob_off
;
737 ret
= sunxi_nfc_hw_ecc_read_chunk(mtd
, data
, data_off
, oob
,
738 oob_off
+ mtd
->writesize
,
739 &cur_off
, &max_bitflips
);
745 sunxi_nfc_hw_ecc_read_extra_oob(mtd
, chip
->oob_poi
, &cur_off
);
747 sunxi_nfc_hw_ecc_disable(mtd
);
752 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info
*mtd
,
753 struct nand_chip
*chip
,
754 const uint8_t *buf
, int oob_required
,
757 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
758 int ret
, i
, cur_off
= 0;
760 sunxi_nfc_hw_ecc_enable(mtd
);
762 for (i
= 0; i
< ecc
->steps
; i
++) {
763 int data_off
= i
* ecc
->size
;
764 int oob_off
= i
* (ecc
->bytes
+ 4);
765 const u8
*data
= buf
+ data_off
;
766 const u8
*oob
= chip
->oob_poi
+ oob_off
;
768 ret
= sunxi_nfc_hw_ecc_write_chunk(mtd
, data
, data_off
, oob
,
769 oob_off
+ mtd
->writesize
,
776 sunxi_nfc_hw_ecc_write_extra_oob(mtd
, chip
->oob_poi
, &cur_off
);
778 sunxi_nfc_hw_ecc_disable(mtd
);
783 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info
*mtd
,
784 struct nand_chip
*chip
,
785 uint8_t *buf
, int oob_required
,
788 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
789 unsigned int max_bitflips
= 0;
790 int ret
, i
, cur_off
= 0;
792 sunxi_nfc_hw_ecc_enable(mtd
);
794 for (i
= 0; i
< ecc
->steps
; i
++) {
795 int data_off
= i
* (ecc
->size
+ ecc
->bytes
+ 4);
796 int oob_off
= data_off
+ ecc
->size
;
797 u8
*data
= buf
+ (i
* ecc
->size
);
798 u8
*oob
= chip
->oob_poi
+ (i
* (ecc
->bytes
+ 4));
800 ret
= sunxi_nfc_hw_ecc_read_chunk(mtd
, data
, data_off
, oob
,
808 sunxi_nfc_hw_ecc_read_extra_oob(mtd
, chip
->oob_poi
, &cur_off
);
810 sunxi_nfc_hw_ecc_disable(mtd
);
815 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info
*mtd
,
816 struct nand_chip
*chip
,
818 int oob_required
, int page
)
820 struct nand_ecc_ctrl
*ecc
= &chip
->ecc
;
821 int ret
, i
, cur_off
= 0;
823 sunxi_nfc_hw_ecc_enable(mtd
);
825 for (i
= 0; i
< ecc
->steps
; i
++) {
826 int data_off
= i
* (ecc
->size
+ ecc
->bytes
+ 4);
827 int oob_off
= data_off
+ ecc
->size
;
828 const u8
*data
= buf
+ (i
* ecc
->size
);
829 const u8
*oob
= chip
->oob_poi
+ (i
* (ecc
->bytes
+ 4));
831 ret
= sunxi_nfc_hw_ecc_write_chunk(mtd
, data
, data_off
,
832 oob
, oob_off
, &cur_off
);
838 sunxi_nfc_hw_ecc_write_extra_oob(mtd
, chip
->oob_poi
, &cur_off
);
840 sunxi_nfc_hw_ecc_disable(mtd
);
845 static const s32 tWB_lut
[] = {6, 12, 16, 20};
846 static const s32 tRHW_lut
[] = {4, 8, 12, 20};
848 static int _sunxi_nand_lookup_timing(const s32
*lut
, int lut_size
, u32 duration
,
851 u32 clk_cycles
= DIV_ROUND_UP(duration
, clk_period
);
854 for (i
= 0; i
< lut_size
; i
++) {
855 if (clk_cycles
<= lut
[i
])
863 #define sunxi_nand_lookup_timing(l, p, c) \
864 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
866 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip
*chip
,
867 const struct nand_sdr_timings
*timings
)
869 struct sunxi_nfc
*nfc
= to_sunxi_nfc(chip
->nand
.controller
);
870 u32 min_clk_period
= 0;
871 s32 tWB
, tADL
, tWHR
, tRHW
, tCAD
;
874 if (timings
->tCLS_min
> min_clk_period
)
875 min_clk_period
= timings
->tCLS_min
;
878 if (timings
->tCLH_min
> min_clk_period
)
879 min_clk_period
= timings
->tCLH_min
;
882 if (timings
->tCS_min
> min_clk_period
)
883 min_clk_period
= timings
->tCS_min
;
886 if (timings
->tCH_min
> min_clk_period
)
887 min_clk_period
= timings
->tCH_min
;
890 if (timings
->tWP_min
> min_clk_period
)
891 min_clk_period
= timings
->tWP_min
;
894 if (timings
->tWH_min
> min_clk_period
)
895 min_clk_period
= timings
->tWH_min
;
898 if (timings
->tALS_min
> min_clk_period
)
899 min_clk_period
= timings
->tALS_min
;
902 if (timings
->tDS_min
> min_clk_period
)
903 min_clk_period
= timings
->tDS_min
;
906 if (timings
->tDH_min
> min_clk_period
)
907 min_clk_period
= timings
->tDH_min
;
910 if (timings
->tRR_min
> (min_clk_period
* 3))
911 min_clk_period
= DIV_ROUND_UP(timings
->tRR_min
, 3);
914 if (timings
->tALH_min
> min_clk_period
)
915 min_clk_period
= timings
->tALH_min
;
918 if (timings
->tRP_min
> min_clk_period
)
919 min_clk_period
= timings
->tRP_min
;
922 if (timings
->tREH_min
> min_clk_period
)
923 min_clk_period
= timings
->tREH_min
;
926 if (timings
->tRC_min
> (min_clk_period
* 2))
927 min_clk_period
= DIV_ROUND_UP(timings
->tRC_min
, 2);
930 if (timings
->tWC_min
> (min_clk_period
* 2))
931 min_clk_period
= DIV_ROUND_UP(timings
->tWC_min
, 2);
933 /* T16 - T19 + tCAD */
934 tWB
= sunxi_nand_lookup_timing(tWB_lut
, timings
->tWB_max
,
937 dev_err(nfc
->dev
, "unsupported tWB\n");
941 tADL
= DIV_ROUND_UP(timings
->tADL_min
, min_clk_period
) >> 3;
943 dev_err(nfc
->dev
, "unsupported tADL\n");
947 tWHR
= DIV_ROUND_UP(timings
->tWHR_min
, min_clk_period
) >> 3;
949 dev_err(nfc
->dev
, "unsupported tWHR\n");
953 tRHW
= sunxi_nand_lookup_timing(tRHW_lut
, timings
->tRHW_min
,
956 dev_err(nfc
->dev
, "unsupported tRHW\n");
961 * TODO: according to ONFI specs this value only applies for DDR NAND,
962 * but Allwinner seems to set this to 0x7. Mimic them for now.
966 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
967 chip
->timing_cfg
= NFC_TIMING_CFG(tWB
, tADL
, tWHR
, tRHW
, tCAD
);
970 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
971 * output cycle timings shall be used if the host drives tRC less than
974 chip
->timing_ctl
= (timings
->tRC_min
< 30000) ? NFC_TIMING_CTL_EDO
: 0;
976 /* Convert min_clk_period from picoseconds to nanoseconds */
977 min_clk_period
= DIV_ROUND_UP(min_clk_period
, 1000);
980 * Convert min_clk_period into a clk frequency, then get the
981 * appropriate rate for the NAND controller IP given this formula
982 * (specified in the datasheet):
983 * nand clk_rate = 2 * min_clk_rate
985 chip
->clk_rate
= (2 * NSEC_PER_SEC
) / min_clk_period
;
990 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip
*chip
,
991 struct device_node
*np
)
993 struct mtd_info
*mtd
= nand_to_mtd(&chip
->nand
);
994 const struct nand_sdr_timings
*timings
;
998 mode
= onfi_get_async_timing_mode(&chip
->nand
);
999 if (mode
== ONFI_TIMING_MODE_UNKNOWN
) {
1000 mode
= chip
->nand
.onfi_timing_mode_default
;
1002 uint8_t feature
[ONFI_SUBFEATURE_PARAM_LEN
] = {};
1005 mode
= fls(mode
) - 1;
1010 for (i
= 0; i
< chip
->nsels
; i
++) {
1011 chip
->nand
.select_chip(mtd
, i
);
1012 ret
= chip
->nand
.onfi_set_features(mtd
, &chip
->nand
,
1013 ONFI_FEATURE_ADDR_TIMING_MODE
,
1015 chip
->nand
.select_chip(mtd
, -1);
1021 timings
= onfi_async_timing_mode_to_sdr_timings(mode
);
1022 if (IS_ERR(timings
))
1023 return PTR_ERR(timings
);
1025 return sunxi_nand_chip_set_timings(chip
, timings
);
1028 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info
*mtd
,
1029 struct nand_ecc_ctrl
*ecc
,
1030 struct device_node
*np
)
1032 static const u8 strengths
[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1033 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1034 struct sunxi_nand_chip
*sunxi_nand
= to_sunxi_nand(nand
);
1035 struct sunxi_nfc
*nfc
= to_sunxi_nfc(sunxi_nand
->nand
.controller
);
1036 struct sunxi_nand_hw_ecc
*data
;
1037 struct nand_ecclayout
*layout
;
1042 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1046 /* Add ECC info retrieval from DT */
1047 for (i
= 0; i
< ARRAY_SIZE(strengths
); i
++) {
1048 if (ecc
->strength
<= strengths
[i
])
1052 if (i
>= ARRAY_SIZE(strengths
)) {
1053 dev_err(nfc
->dev
, "unsupported strength\n");
1060 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1061 ecc
->bytes
= DIV_ROUND_UP(ecc
->strength
* fls(8 * 1024), 8);
1063 /* HW ECC always work with even numbers of ECC bytes */
1064 ecc
->bytes
= ALIGN(ecc
->bytes
, 2);
1066 layout
= &data
->layout
;
1067 nsectors
= mtd
->writesize
/ ecc
->size
;
1069 if (mtd
->oobsize
< ((ecc
->bytes
+ 4) * nsectors
)) {
1074 layout
->eccbytes
= (ecc
->bytes
* nsectors
);
1076 ecc
->layout
= layout
;
1087 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl
*ecc
)
1092 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info
*mtd
,
1093 struct nand_ecc_ctrl
*ecc
,
1094 struct device_node
*np
)
1096 struct nand_ecclayout
*layout
;
1101 ret
= sunxi_nand_hw_common_ecc_ctrl_init(mtd
, ecc
, np
);
1105 ecc
->read_page
= sunxi_nfc_hw_ecc_read_page
;
1106 ecc
->write_page
= sunxi_nfc_hw_ecc_write_page
;
1107 layout
= ecc
->layout
;
1108 nsectors
= mtd
->writesize
/ ecc
->size
;
1110 for (i
= 0; i
< nsectors
; i
++) {
1112 layout
->oobfree
[i
].offset
=
1113 layout
->oobfree
[i
- 1].offset
+
1114 layout
->oobfree
[i
- 1].length
+
1116 layout
->oobfree
[i
].length
= 4;
1119 * The first 2 bytes are used for BB markers, hence we
1120 * only have 2 bytes available in the first user data
1123 layout
->oobfree
[i
].length
= 2;
1124 layout
->oobfree
[i
].offset
= 2;
1127 for (j
= 0; j
< ecc
->bytes
; j
++)
1128 layout
->eccpos
[(ecc
->bytes
* i
) + j
] =
1129 layout
->oobfree
[i
].offset
+
1130 layout
->oobfree
[i
].length
+ j
;
1133 if (mtd
->oobsize
> (ecc
->bytes
+ 4) * nsectors
) {
1134 layout
->oobfree
[nsectors
].offset
=
1135 layout
->oobfree
[nsectors
- 1].offset
+
1136 layout
->oobfree
[nsectors
- 1].length
+
1138 layout
->oobfree
[nsectors
].length
= mtd
->oobsize
-
1139 ((ecc
->bytes
+ 4) * nsectors
);
1145 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info
*mtd
,
1146 struct nand_ecc_ctrl
*ecc
,
1147 struct device_node
*np
)
1149 struct nand_ecclayout
*layout
;
1154 ret
= sunxi_nand_hw_common_ecc_ctrl_init(mtd
, ecc
, np
);
1159 ecc
->read_page
= sunxi_nfc_hw_syndrome_ecc_read_page
;
1160 ecc
->write_page
= sunxi_nfc_hw_syndrome_ecc_write_page
;
1162 layout
= ecc
->layout
;
1163 nsectors
= mtd
->writesize
/ ecc
->size
;
1165 for (i
= 0; i
< (ecc
->bytes
* nsectors
); i
++)
1166 layout
->eccpos
[i
] = i
;
1168 layout
->oobfree
[0].length
= mtd
->oobsize
- i
;
1169 layout
->oobfree
[0].offset
= i
;
1174 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl
*ecc
)
1176 switch (ecc
->mode
) {
1178 case NAND_ECC_HW_SYNDROME
:
1179 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc
);
1188 static int sunxi_nand_ecc_init(struct mtd_info
*mtd
, struct nand_ecc_ctrl
*ecc
,
1189 struct device_node
*np
)
1191 struct nand_chip
*nand
= mtd_to_nand(mtd
);
1195 ecc
->size
= nand
->ecc_step_ds
;
1196 ecc
->strength
= nand
->ecc_strength_ds
;
1199 if (!ecc
->size
|| !ecc
->strength
)
1202 switch (ecc
->mode
) {
1203 case NAND_ECC_SOFT_BCH
:
1206 ret
= sunxi_nand_hw_ecc_ctrl_init(mtd
, ecc
, np
);
1210 case NAND_ECC_HW_SYNDROME
:
1211 ret
= sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd
, ecc
, np
);
1216 ecc
->layout
= kzalloc(sizeof(*ecc
->layout
), GFP_KERNEL
);
1219 ecc
->layout
->oobfree
[0].length
= mtd
->oobsize
;
1229 static int sunxi_nand_chip_init(struct device
*dev
, struct sunxi_nfc
*nfc
,
1230 struct device_node
*np
)
1232 const struct nand_sdr_timings
*timings
;
1233 struct sunxi_nand_chip
*chip
;
1234 struct mtd_info
*mtd
;
1235 struct nand_chip
*nand
;
1241 if (!of_get_property(np
, "reg", &nsels
))
1244 nsels
/= sizeof(u32
);
1246 dev_err(dev
, "invalid reg property size\n");
1250 chip
= devm_kzalloc(dev
,
1252 (nsels
* sizeof(struct sunxi_nand_chip_sel
)),
1255 dev_err(dev
, "could not allocate chip\n");
1259 chip
->nsels
= nsels
;
1260 chip
->selected
= -1;
1262 for (i
= 0; i
< nsels
; i
++) {
1263 ret
= of_property_read_u32_index(np
, "reg", i
, &tmp
);
1265 dev_err(dev
, "could not retrieve reg property: %d\n",
1270 if (tmp
> NFC_MAX_CS
) {
1272 "invalid reg value: %u (max CS = 7)\n",
1277 if (test_and_set_bit(tmp
, &nfc
->assigned_cs
)) {
1278 dev_err(dev
, "CS %d already assigned\n", tmp
);
1282 chip
->sels
[i
].cs
= tmp
;
1284 if (!of_property_read_u32_index(np
, "allwinner,rb", i
, &tmp
) &&
1286 chip
->sels
[i
].rb
.type
= RB_NATIVE
;
1287 chip
->sels
[i
].rb
.info
.nativeid
= tmp
;
1289 ret
= of_get_named_gpio(np
, "rb-gpios", i
);
1292 chip
->sels
[i
].rb
.type
= RB_GPIO
;
1293 chip
->sels
[i
].rb
.info
.gpio
= tmp
;
1294 ret
= devm_gpio_request(dev
, tmp
, "nand-rb");
1298 ret
= gpio_direction_input(tmp
);
1302 chip
->sels
[i
].rb
.type
= RB_NONE
;
1307 timings
= onfi_async_timing_mode_to_sdr_timings(0);
1308 if (IS_ERR(timings
)) {
1309 ret
= PTR_ERR(timings
);
1311 "could not retrieve timings for ONFI mode 0: %d\n",
1316 ret
= sunxi_nand_chip_set_timings(chip
, timings
);
1318 dev_err(dev
, "could not configure chip timings: %d\n", ret
);
1323 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1324 nand
->chip_delay
= 200;
1325 nand
->controller
= &nfc
->controller
;
1327 * Set the ECC mode to the default value in case nothing is specified
1330 nand
->ecc
.mode
= NAND_ECC_HW
;
1331 nand_set_flash_node(nand
, np
);
1332 nand
->select_chip
= sunxi_nfc_select_chip
;
1333 nand
->cmd_ctrl
= sunxi_nfc_cmd_ctrl
;
1334 nand
->read_buf
= sunxi_nfc_read_buf
;
1335 nand
->write_buf
= sunxi_nfc_write_buf
;
1336 nand
->read_byte
= sunxi_nfc_read_byte
;
1338 mtd
= nand_to_mtd(nand
);
1339 mtd
->dev
.parent
= dev
;
1341 ret
= nand_scan_ident(mtd
, nsels
, NULL
);
1345 if (nand
->bbt_options
& NAND_BBT_USE_FLASH
)
1346 nand
->bbt_options
|= NAND_BBT_NO_OOB
;
1348 ret
= sunxi_nand_chip_init_timings(chip
, np
);
1350 dev_err(dev
, "could not configure chip timings: %d\n", ret
);
1354 ret
= sunxi_nand_ecc_init(mtd
, &nand
->ecc
, np
);
1356 dev_err(dev
, "ECC init failed: %d\n", ret
);
1360 ret
= nand_scan_tail(mtd
);
1362 dev_err(dev
, "nand_scan_tail failed: %d\n", ret
);
1366 ret
= mtd_device_register(mtd
, NULL
, 0);
1368 dev_err(dev
, "failed to register mtd device: %d\n", ret
);
1373 list_add_tail(&chip
->node
, &nfc
->chips
);
1378 static int sunxi_nand_chips_init(struct device
*dev
, struct sunxi_nfc
*nfc
)
1380 struct device_node
*np
= dev
->of_node
;
1381 struct device_node
*nand_np
;
1382 int nchips
= of_get_child_count(np
);
1386 dev_err(dev
, "too many NAND chips: %d (max = 8)\n", nchips
);
1390 for_each_child_of_node(np
, nand_np
) {
1391 ret
= sunxi_nand_chip_init(dev
, nfc
, nand_np
);
1393 of_node_put(nand_np
);
1401 static void sunxi_nand_chips_cleanup(struct sunxi_nfc
*nfc
)
1403 struct sunxi_nand_chip
*chip
;
1405 while (!list_empty(&nfc
->chips
)) {
1406 chip
= list_first_entry(&nfc
->chips
, struct sunxi_nand_chip
,
1408 nand_release(nand_to_mtd(&chip
->nand
));
1409 sunxi_nand_ecc_cleanup(&chip
->nand
.ecc
);
1410 list_del(&chip
->node
);
1414 static int sunxi_nfc_probe(struct platform_device
*pdev
)
1416 struct device
*dev
= &pdev
->dev
;
1418 struct sunxi_nfc
*nfc
;
1422 nfc
= devm_kzalloc(dev
, sizeof(*nfc
), GFP_KERNEL
);
1427 spin_lock_init(&nfc
->controller
.lock
);
1428 init_waitqueue_head(&nfc
->controller
.wq
);
1429 INIT_LIST_HEAD(&nfc
->chips
);
1431 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1432 nfc
->regs
= devm_ioremap_resource(dev
, r
);
1433 if (IS_ERR(nfc
->regs
))
1434 return PTR_ERR(nfc
->regs
);
1436 irq
= platform_get_irq(pdev
, 0);
1438 dev_err(dev
, "failed to retrieve irq\n");
1442 nfc
->ahb_clk
= devm_clk_get(dev
, "ahb");
1443 if (IS_ERR(nfc
->ahb_clk
)) {
1444 dev_err(dev
, "failed to retrieve ahb clk\n");
1445 return PTR_ERR(nfc
->ahb_clk
);
1448 ret
= clk_prepare_enable(nfc
->ahb_clk
);
1452 nfc
->mod_clk
= devm_clk_get(dev
, "mod");
1453 if (IS_ERR(nfc
->mod_clk
)) {
1454 dev_err(dev
, "failed to retrieve mod clk\n");
1455 ret
= PTR_ERR(nfc
->mod_clk
);
1456 goto out_ahb_clk_unprepare
;
1459 ret
= clk_prepare_enable(nfc
->mod_clk
);
1461 goto out_ahb_clk_unprepare
;
1463 ret
= sunxi_nfc_rst(nfc
);
1465 goto out_mod_clk_unprepare
;
1467 writel(0, nfc
->regs
+ NFC_REG_INT
);
1468 ret
= devm_request_irq(dev
, irq
, sunxi_nfc_interrupt
,
1469 0, "sunxi-nand", nfc
);
1471 goto out_mod_clk_unprepare
;
1473 platform_set_drvdata(pdev
, nfc
);
1475 ret
= sunxi_nand_chips_init(dev
, nfc
);
1477 dev_err(dev
, "failed to init nand chips\n");
1478 goto out_mod_clk_unprepare
;
1483 out_mod_clk_unprepare
:
1484 clk_disable_unprepare(nfc
->mod_clk
);
1485 out_ahb_clk_unprepare
:
1486 clk_disable_unprepare(nfc
->ahb_clk
);
1491 static int sunxi_nfc_remove(struct platform_device
*pdev
)
1493 struct sunxi_nfc
*nfc
= platform_get_drvdata(pdev
);
1495 sunxi_nand_chips_cleanup(nfc
);
1500 static const struct of_device_id sunxi_nfc_ids
[] = {
1501 { .compatible
= "allwinner,sun4i-a10-nand" },
1504 MODULE_DEVICE_TABLE(of
, sunxi_nfc_ids
);
1506 static struct platform_driver sunxi_nfc_driver
= {
1508 .name
= "sunxi_nand",
1509 .of_match_table
= sunxi_nfc_ids
,
1511 .probe
= sunxi_nfc_probe
,
1512 .remove
= sunxi_nfc_remove
,
1514 module_platform_driver(sunxi_nfc_driver
);
1516 MODULE_LICENSE("GPL v2");
1517 MODULE_AUTHOR("Boris BREZILLON");
1518 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1519 MODULE_ALIAS("platform:sunxi_nand");