1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
49 #define DRV_NAME "8139cp"
50 #define DRV_VERSION "1.3"
51 #define DRV_RELDATE "Mar 22, 2004"
54 #include <linux/module.h>
55 #include <linux/moduleparam.h>
56 #include <linux/kernel.h>
57 #include <linux/compiler.h>
58 #include <linux/netdevice.h>
59 #include <linux/etherdevice.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/delay.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/if_vlan.h>
67 #include <linux/crc32.h>
70 #include <linux/tcp.h>
71 #include <linux/udp.h>
72 #include <linux/cache.h>
75 #include <asm/uaccess.h>
77 /* VLAN tagging feature enable/disable */
78 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79 #define CP_VLAN_TAG_USED 1
80 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
81 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
83 #define CP_VLAN_TAG_USED 0
84 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
88 /* These identify the driver base version and may not be removed. */
89 static char version
[] =
90 KERN_INFO DRV_NAME
": 10/100 PCI Ethernet driver v" DRV_VERSION
" (" DRV_RELDATE
")\n";
92 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
94 MODULE_VERSION(DRV_VERSION
);
95 MODULE_LICENSE("GPL");
97 static int debug
= -1;
98 module_param(debug
, int, 0);
99 MODULE_PARM_DESC (debug
, "8139cp: bitmapped message enable number");
101 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103 static int multicast_filter_limit
= 32;
104 module_param(multicast_filter_limit
, int, 0);
105 MODULE_PARM_DESC (multicast_filter_limit
, "8139cp: maximum number of filtered multicast addresses");
107 #define PFX DRV_NAME ": "
109 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
112 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114 #define CP_REGS_SIZE (0xff + 1)
115 #define CP_REGS_VER 1 /* version 1 */
116 #define CP_RX_RING_SIZE 64
117 #define CP_TX_RING_SIZE 64
118 #define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
122 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124 #define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
129 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
130 #define CP_INTERNAL_PHY 32
132 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
133 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
134 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
135 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
136 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138 /* Time in jiffies before concluding the transmitter is hung. */
139 #define TX_TIMEOUT (6*HZ)
141 /* hardware minimum and maximum for a single frame's data payload */
142 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
143 #define CP_MAX_MTU 4096
146 /* NIC register offsets */
147 MAC0
= 0x00, /* Ethernet hardware address. */
148 MAR0
= 0x08, /* Multicast filter. */
149 StatsAddr
= 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
150 TxRingAddr
= 0x20, /* 64-bit start addr of Tx ring */
151 HiTxRingAddr
= 0x28, /* 64-bit start addr of high priority Tx ring */
152 Cmd
= 0x37, /* Command register */
153 IntrMask
= 0x3C, /* Interrupt mask */
154 IntrStatus
= 0x3E, /* Interrupt status */
155 TxConfig
= 0x40, /* Tx configuration */
156 ChipVersion
= 0x43, /* 8-bit chip version, inside TxConfig */
157 RxConfig
= 0x44, /* Rx configuration */
158 RxMissed
= 0x4C, /* 24 bits valid, write clears */
159 Cfg9346
= 0x50, /* EEPROM select/control; Cfg reg [un]lock */
160 Config1
= 0x52, /* Config1 */
161 Config3
= 0x59, /* Config3 */
162 Config4
= 0x5A, /* Config4 */
163 MultiIntr
= 0x5C, /* Multiple interrupt select */
164 BasicModeCtrl
= 0x62, /* MII BMCR */
165 BasicModeStatus
= 0x64, /* MII BMSR */
166 NWayAdvert
= 0x66, /* MII ADVERTISE */
167 NWayLPAR
= 0x68, /* MII LPA */
168 NWayExpansion
= 0x6A, /* MII Expansion */
169 Config5
= 0xD8, /* Config5 */
170 TxPoll
= 0xD9, /* Tell chip to check Tx descriptors for work */
171 RxMaxSize
= 0xDA, /* Max size of an Rx packet (8169 only) */
172 CpCmd
= 0xE0, /* C+ Command register (C+ mode only) */
173 IntrMitigate
= 0xE2, /* rx/tx interrupt mitigation control */
174 RxRingAddr
= 0xE4, /* 64-bit start addr of Rx ring */
175 TxThresh
= 0xEC, /* Early Tx threshold */
176 OldRxBufAddr
= 0x30, /* DMA address of Rx ring buffer (C mode) */
177 OldTSD0
= 0x10, /* DMA address of first Tx desc (C mode) */
179 /* Tx and Rx status descriptors */
180 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
181 RingEnd
= (1 << 30), /* End of descriptor ring */
182 FirstFrag
= (1 << 29), /* First segment of a packet */
183 LastFrag
= (1 << 28), /* Final segment of a packet */
184 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
185 MSSShift
= 16, /* MSS value position */
186 MSSMask
= 0xfff, /* MSS value: 11 bits */
187 TxError
= (1 << 23), /* Tx error summary */
188 RxError
= (1 << 20), /* Rx error summary */
189 IPCS
= (1 << 18), /* Calculate IP checksum */
190 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
191 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
192 TxVlanTag
= (1 << 17), /* Add VLAN tag */
193 RxVlanTagged
= (1 << 16), /* Rx VLAN tag available */
194 IPFail
= (1 << 15), /* IP checksum failed */
195 UDPFail
= (1 << 14), /* UDP/IP checksum failed */
196 TCPFail
= (1 << 13), /* TCP/IP checksum failed */
197 NormalTxPoll
= (1 << 6), /* One or more normal Tx packets to send */
198 PID1
= (1 << 17), /* 2 protocol id bits: 0==non-IP, */
199 PID0
= (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
203 TxFIFOUnder
= (1 << 25), /* Tx FIFO underrun */
204 TxOWC
= (1 << 22), /* Tx Out-of-window collision */
205 TxLinkFail
= (1 << 21), /* Link failed during Tx of packet */
206 TxMaxCol
= (1 << 20), /* Tx aborted due to excessive collisions */
207 TxColCntShift
= 16, /* Shift, to get 4-bit Tx collision cnt */
208 TxColCntMask
= 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
209 RxErrFrame
= (1 << 27), /* Rx frame alignment error */
210 RxMcast
= (1 << 26), /* Rx multicast packet rcv'd */
211 RxErrCRC
= (1 << 18), /* Rx CRC error */
212 RxErrRunt
= (1 << 19), /* Rx error, packet < 64 bytes */
213 RxErrLong
= (1 << 21), /* Rx error, packet > 4096 bytes */
214 RxErrFIFO
= (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216 /* StatsAddr register */
217 DumpStats
= (1 << 3), /* Begin stats dump */
219 /* RxConfig register */
220 RxCfgFIFOShift
= 13, /* Shift, to get Rx FIFO thresh value */
221 RxCfgDMAShift
= 8, /* Shift, to get Rx Max DMA value */
222 AcceptErr
= 0x20, /* Accept packets with CRC errors */
223 AcceptRunt
= 0x10, /* Accept runt (<64 bytes) packets */
224 AcceptBroadcast
= 0x08, /* Accept broadcast packets */
225 AcceptMulticast
= 0x04, /* Accept multicast packets */
226 AcceptMyPhys
= 0x02, /* Accept pkts with our MAC as dest */
227 AcceptAllPhys
= 0x01, /* Accept all pkts w/ physical dest */
229 /* IntrMask / IntrStatus registers */
230 PciErr
= (1 << 15), /* System error on the PCI bus */
231 TimerIntr
= (1 << 14), /* Asserted when TCTR reaches TimerInt value */
232 LenChg
= (1 << 13), /* Cable length change */
233 SWInt
= (1 << 8), /* Software-requested interrupt */
234 TxEmpty
= (1 << 7), /* No Tx descriptors available */
235 RxFIFOOvr
= (1 << 6), /* Rx FIFO Overflow */
236 LinkChg
= (1 << 5), /* Packet underrun, or link change */
237 RxEmpty
= (1 << 4), /* No Rx descriptors available */
238 TxErr
= (1 << 3), /* Tx error */
239 TxOK
= (1 << 2), /* Tx packet sent */
240 RxErr
= (1 << 1), /* Rx error */
241 RxOK
= (1 << 0), /* Rx packet received */
242 IntrResvd
= (1 << 10), /* reserved, according to RealTek engineers,
243 but hardware likes to raise it */
245 IntrAll
= PciErr
| TimerIntr
| LenChg
| SWInt
| TxEmpty
|
246 RxFIFOOvr
| LinkChg
| RxEmpty
| TxErr
| TxOK
|
247 RxErr
| RxOK
| IntrResvd
,
249 /* C mode command register */
250 CmdReset
= (1 << 4), /* Enable to reset; self-clearing */
251 RxOn
= (1 << 3), /* Rx mode enable */
252 TxOn
= (1 << 2), /* Tx mode enable */
254 /* C+ mode command register */
255 RxVlanOn
= (1 << 6), /* Rx VLAN de-tagging enable */
256 RxChkSum
= (1 << 5), /* Rx checksum offload enable */
257 PCIDAC
= (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
258 PCIMulRW
= (1 << 3), /* Enable PCI read/write multiple */
259 CpRxOn
= (1 << 1), /* Rx mode enable */
260 CpTxOn
= (1 << 0), /* Tx mode enable */
262 /* Cfg9436 EEPROM control register */
263 Cfg9346_Lock
= 0x00, /* Lock ConfigX/MII register access */
264 Cfg9346_Unlock
= 0xC0, /* Unlock ConfigX/MII register access */
266 /* TxConfig register */
267 IFG
= (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
268 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
270 /* Early Tx Threshold register */
271 TxThreshMask
= 0x3f, /* Mask bits 5-0 */
272 TxThreshMax
= 2048, /* Max early Tx threshold */
274 /* Config1 register */
275 DriverLoaded
= (1 << 5), /* Software marker, driver is loaded */
276 LWACT
= (1 << 4), /* LWAKE active mode */
277 PMEnable
= (1 << 0), /* Enable various PM features of chip */
279 /* Config3 register */
280 PARMEnable
= (1 << 6), /* Enable auto-loading of PHY parms */
281 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
282 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
284 /* Config4 register */
285 LWPTN
= (1 << 1), /* LWAKE Pattern */
286 LWPME
= (1 << 4), /* LANWAKE vs PMEB */
288 /* Config5 register */
289 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
290 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
291 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
292 LANWake
= (1 << 1), /* Enable LANWake signal */
293 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
295 cp_norx_intr_mask
= PciErr
| LinkChg
| TxOK
| TxErr
| TxEmpty
,
296 cp_rx_intr_mask
= RxOK
| RxErr
| RxEmpty
| RxFIFOOvr
,
297 cp_intr_mask
= cp_rx_intr_mask
| cp_norx_intr_mask
,
300 static const unsigned int cp_rx_config
=
301 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) |
302 (RX_DMA_BURST
<< RxCfgDMAShift
);
310 struct cp_dma_stats
{
324 } __attribute__((packed
));
326 struct cp_extra_stats
{
327 unsigned long rx_frags
;
332 struct net_device
*dev
;
336 struct napi_struct napi
;
338 struct pci_dev
*pdev
;
342 struct cp_extra_stats cp_stats
;
344 unsigned rx_head ____cacheline_aligned
;
346 struct cp_desc
*rx_ring
;
347 struct sk_buff
*rx_skb
[CP_RX_RING_SIZE
];
349 unsigned tx_head ____cacheline_aligned
;
351 struct cp_desc
*tx_ring
;
352 struct sk_buff
*tx_skb
[CP_TX_RING_SIZE
];
355 unsigned wol_enabled
: 1; /* Is Wake-on-LAN enabled? */
358 struct vlan_group
*vlgrp
;
362 struct mii_if_info mii_if
;
365 #define cpr8(reg) readb(cp->regs + (reg))
366 #define cpr16(reg) readw(cp->regs + (reg))
367 #define cpr32(reg) readl(cp->regs + (reg))
368 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
369 #define cpw16(reg,val) writew((val), cp->regs + (reg))
370 #define cpw32(reg,val) writel((val), cp->regs + (reg))
371 #define cpw8_f(reg,val) do { \
372 writeb((val), cp->regs + (reg)); \
373 readb(cp->regs + (reg)); \
375 #define cpw16_f(reg,val) do { \
376 writew((val), cp->regs + (reg)); \
377 readw(cp->regs + (reg)); \
379 #define cpw32_f(reg,val) do { \
380 writel((val), cp->regs + (reg)); \
381 readl(cp->regs + (reg)); \
385 static void __cp_set_rx_mode (struct net_device
*dev
);
386 static void cp_tx (struct cp_private
*cp
);
387 static void cp_clean_rings (struct cp_private
*cp
);
388 #ifdef CONFIG_NET_POLL_CONTROLLER
389 static void cp_poll_controller(struct net_device
*dev
);
391 static int cp_get_eeprom_len(struct net_device
*dev
);
392 static int cp_get_eeprom(struct net_device
*dev
,
393 struct ethtool_eeprom
*eeprom
, u8
*data
);
394 static int cp_set_eeprom(struct net_device
*dev
,
395 struct ethtool_eeprom
*eeprom
, u8
*data
);
397 static struct pci_device_id cp_pci_tbl
[] = {
398 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, PCI_DEVICE_ID_REALTEK_8139
), },
399 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH
, PCI_DEVICE_ID_TTTECH_MC322
), },
402 MODULE_DEVICE_TABLE(pci
, cp_pci_tbl
);
405 const char str
[ETH_GSTRING_LEN
];
406 } ethtool_stats_keys
[] = {
425 static void cp_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
427 struct cp_private
*cp
= netdev_priv(dev
);
430 spin_lock_irqsave(&cp
->lock
, flags
);
433 cp
->cpcmd
|= RxVlanOn
;
435 cp
->cpcmd
&= ~RxVlanOn
;
437 cpw16(CpCmd
, cp
->cpcmd
);
438 spin_unlock_irqrestore(&cp
->lock
, flags
);
440 #endif /* CP_VLAN_TAG_USED */
442 static inline void cp_set_rxbufsize (struct cp_private
*cp
)
444 unsigned int mtu
= cp
->dev
->mtu
;
446 if (mtu
> ETH_DATA_LEN
)
447 /* MTU + ethernet header + FCS + optional VLAN tag */
448 cp
->rx_buf_sz
= mtu
+ ETH_HLEN
+ 8;
450 cp
->rx_buf_sz
= PKT_BUF_SZ
;
453 static inline void cp_rx_skb (struct cp_private
*cp
, struct sk_buff
*skb
,
454 struct cp_desc
*desc
)
456 skb
->protocol
= eth_type_trans (skb
, cp
->dev
);
458 cp
->dev
->stats
.rx_packets
++;
459 cp
->dev
->stats
.rx_bytes
+= skb
->len
;
462 if (cp
->vlgrp
&& (desc
->opts2
& cpu_to_le32(RxVlanTagged
))) {
463 vlan_hwaccel_receive_skb(skb
, cp
->vlgrp
,
464 swab16(le32_to_cpu(desc
->opts2
) & 0xffff));
467 netif_receive_skb(skb
);
470 static void cp_rx_err_acct (struct cp_private
*cp
, unsigned rx_tail
,
473 if (netif_msg_rx_err (cp
))
475 "%s: rx err, slot %d status 0x%x len %d\n",
476 cp
->dev
->name
, rx_tail
, status
, len
);
477 cp
->dev
->stats
.rx_errors
++;
478 if (status
& RxErrFrame
)
479 cp
->dev
->stats
.rx_frame_errors
++;
480 if (status
& RxErrCRC
)
481 cp
->dev
->stats
.rx_crc_errors
++;
482 if ((status
& RxErrRunt
) || (status
& RxErrLong
))
483 cp
->dev
->stats
.rx_length_errors
++;
484 if ((status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
))
485 cp
->dev
->stats
.rx_length_errors
++;
486 if (status
& RxErrFIFO
)
487 cp
->dev
->stats
.rx_fifo_errors
++;
490 static inline unsigned int cp_rx_csum_ok (u32 status
)
492 unsigned int protocol
= (status
>> 16) & 0x3;
494 if (likely((protocol
== RxProtoTCP
) && (!(status
& TCPFail
))))
496 else if ((protocol
== RxProtoUDP
) && (!(status
& UDPFail
)))
498 else if ((protocol
== RxProtoIP
) && (!(status
& IPFail
)))
503 static int cp_rx_poll(struct napi_struct
*napi
, int budget
)
505 struct cp_private
*cp
= container_of(napi
, struct cp_private
, napi
);
506 struct net_device
*dev
= cp
->dev
;
507 unsigned int rx_tail
= cp
->rx_tail
;
512 cpw16(IntrStatus
, cp_rx_intr_mask
);
517 struct sk_buff
*skb
, *new_skb
;
518 struct cp_desc
*desc
;
521 skb
= cp
->rx_skb
[rx_tail
];
524 desc
= &cp
->rx_ring
[rx_tail
];
525 status
= le32_to_cpu(desc
->opts1
);
526 if (status
& DescOwn
)
529 len
= (status
& 0x1fff) - 4;
530 mapping
= le64_to_cpu(desc
->addr
);
532 if ((status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
)) {
533 /* we don't support incoming fragmented frames.
534 * instead, we attempt to ensure that the
535 * pre-allocated RX skbs are properly sized such
536 * that RX fragments are never encountered
538 cp_rx_err_acct(cp
, rx_tail
, status
, len
);
539 dev
->stats
.rx_dropped
++;
540 cp
->cp_stats
.rx_frags
++;
544 if (status
& (RxError
| RxErrFIFO
)) {
545 cp_rx_err_acct(cp
, rx_tail
, status
, len
);
549 if (netif_msg_rx_status(cp
))
550 printk(KERN_DEBUG
"%s: rx slot %d status 0x%x len %d\n",
551 dev
->name
, rx_tail
, status
, len
);
553 buflen
= cp
->rx_buf_sz
+ NET_IP_ALIGN
;
554 new_skb
= netdev_alloc_skb(dev
, buflen
);
556 dev
->stats
.rx_dropped
++;
560 skb_reserve(new_skb
, NET_IP_ALIGN
);
562 dma_unmap_single(&cp
->pdev
->dev
, mapping
,
563 buflen
, PCI_DMA_FROMDEVICE
);
565 /* Handle checksum offloading for incoming packets. */
566 if (cp_rx_csum_ok(status
))
567 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
569 skb
->ip_summed
= CHECKSUM_NONE
;
573 mapping
= dma_map_single(&cp
->pdev
->dev
, new_skb
->data
, buflen
,
575 cp
->rx_skb
[rx_tail
] = new_skb
;
577 cp_rx_skb(cp
, skb
, desc
);
581 cp
->rx_ring
[rx_tail
].opts2
= 0;
582 cp
->rx_ring
[rx_tail
].addr
= cpu_to_le64(mapping
);
583 if (rx_tail
== (CP_RX_RING_SIZE
- 1))
584 desc
->opts1
= cpu_to_le32(DescOwn
| RingEnd
|
587 desc
->opts1
= cpu_to_le32(DescOwn
| cp
->rx_buf_sz
);
588 rx_tail
= NEXT_RX(rx_tail
);
594 cp
->rx_tail
= rx_tail
;
596 /* if we did not reach work limit, then we're done with
597 * this round of polling
602 if (cpr16(IntrStatus
) & cp_rx_intr_mask
)
605 spin_lock_irqsave(&cp
->lock
, flags
);
606 cpw16_f(IntrMask
, cp_intr_mask
);
607 __netif_rx_complete(dev
, napi
);
608 spin_unlock_irqrestore(&cp
->lock
, flags
);
614 static irqreturn_t
cp_interrupt (int irq
, void *dev_instance
)
616 struct net_device
*dev
= dev_instance
;
617 struct cp_private
*cp
;
620 if (unlikely(dev
== NULL
))
622 cp
= netdev_priv(dev
);
624 status
= cpr16(IntrStatus
);
625 if (!status
|| (status
== 0xFFFF))
628 if (netif_msg_intr(cp
))
629 printk(KERN_DEBUG
"%s: intr, status %04x cmd %02x cpcmd %04x\n",
630 dev
->name
, status
, cpr8(Cmd
), cpr16(CpCmd
));
632 cpw16(IntrStatus
, status
& ~cp_rx_intr_mask
);
634 spin_lock(&cp
->lock
);
636 /* close possible race's with dev_close */
637 if (unlikely(!netif_running(dev
))) {
639 spin_unlock(&cp
->lock
);
643 if (status
& (RxOK
| RxErr
| RxEmpty
| RxFIFOOvr
))
644 if (netif_rx_schedule_prep(dev
, &cp
->napi
)) {
645 cpw16_f(IntrMask
, cp_norx_intr_mask
);
646 __netif_rx_schedule(dev
, &cp
->napi
);
649 if (status
& (TxOK
| TxErr
| TxEmpty
| SWInt
))
651 if (status
& LinkChg
)
652 mii_check_media(&cp
->mii_if
, netif_msg_link(cp
), false);
654 spin_unlock(&cp
->lock
);
656 if (status
& PciErr
) {
659 pci_read_config_word(cp
->pdev
, PCI_STATUS
, &pci_status
);
660 pci_write_config_word(cp
->pdev
, PCI_STATUS
, pci_status
);
661 printk(KERN_ERR
"%s: PCI bus error, status=%04x, PCI status=%04x\n",
662 dev
->name
, status
, pci_status
);
664 /* TODO: reset hardware */
670 #ifdef CONFIG_NET_POLL_CONTROLLER
672 * Polling receive - used by netconsole and other diagnostic tools
673 * to allow network i/o with interrupts disabled.
675 static void cp_poll_controller(struct net_device
*dev
)
677 disable_irq(dev
->irq
);
678 cp_interrupt(dev
->irq
, dev
);
679 enable_irq(dev
->irq
);
683 static void cp_tx (struct cp_private
*cp
)
685 unsigned tx_head
= cp
->tx_head
;
686 unsigned tx_tail
= cp
->tx_tail
;
688 while (tx_tail
!= tx_head
) {
689 struct cp_desc
*txd
= cp
->tx_ring
+ tx_tail
;
694 status
= le32_to_cpu(txd
->opts1
);
695 if (status
& DescOwn
)
698 skb
= cp
->tx_skb
[tx_tail
];
701 dma_unmap_single(&cp
->pdev
->dev
, le64_to_cpu(txd
->addr
),
702 le32_to_cpu(txd
->opts1
) & 0xffff,
705 if (status
& LastFrag
) {
706 if (status
& (TxError
| TxFIFOUnder
)) {
707 if (netif_msg_tx_err(cp
))
708 printk(KERN_DEBUG
"%s: tx err, status 0x%x\n",
709 cp
->dev
->name
, status
);
710 cp
->dev
->stats
.tx_errors
++;
712 cp
->dev
->stats
.tx_window_errors
++;
713 if (status
& TxMaxCol
)
714 cp
->dev
->stats
.tx_aborted_errors
++;
715 if (status
& TxLinkFail
)
716 cp
->dev
->stats
.tx_carrier_errors
++;
717 if (status
& TxFIFOUnder
)
718 cp
->dev
->stats
.tx_fifo_errors
++;
720 cp
->dev
->stats
.collisions
+=
721 ((status
>> TxColCntShift
) & TxColCntMask
);
722 cp
->dev
->stats
.tx_packets
++;
723 cp
->dev
->stats
.tx_bytes
+= skb
->len
;
724 if (netif_msg_tx_done(cp
))
725 printk(KERN_DEBUG
"%s: tx done, slot %d\n", cp
->dev
->name
, tx_tail
);
727 dev_kfree_skb_irq(skb
);
730 cp
->tx_skb
[tx_tail
] = NULL
;
732 tx_tail
= NEXT_TX(tx_tail
);
735 cp
->tx_tail
= tx_tail
;
737 if (TX_BUFFS_AVAIL(cp
) > (MAX_SKB_FRAGS
+ 1))
738 netif_wake_queue(cp
->dev
);
741 static int cp_start_xmit (struct sk_buff
*skb
, struct net_device
*dev
)
743 struct cp_private
*cp
= netdev_priv(dev
);
746 unsigned long intr_flags
;
752 spin_lock_irqsave(&cp
->lock
, intr_flags
);
754 /* This is a hard error, log it. */
755 if (TX_BUFFS_AVAIL(cp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
756 netif_stop_queue(dev
);
757 spin_unlock_irqrestore(&cp
->lock
, intr_flags
);
758 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
764 if (cp
->vlgrp
&& vlan_tx_tag_present(skb
))
765 vlan_tag
= TxVlanTag
| swab16(vlan_tx_tag_get(skb
));
769 eor
= (entry
== (CP_TX_RING_SIZE
- 1)) ? RingEnd
: 0;
770 if (dev
->features
& NETIF_F_TSO
)
771 mss
= skb_shinfo(skb
)->gso_size
;
773 if (skb_shinfo(skb
)->nr_frags
== 0) {
774 struct cp_desc
*txd
= &cp
->tx_ring
[entry
];
779 mapping
= dma_map_single(&cp
->pdev
->dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
780 CP_VLAN_TX_TAG(txd
, vlan_tag
);
781 txd
->addr
= cpu_to_le64(mapping
);
784 flags
= eor
| len
| DescOwn
| FirstFrag
| LastFrag
;
787 flags
|= LargeSend
| ((mss
& MSSMask
) << MSSShift
);
788 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
789 const struct iphdr
*ip
= ip_hdr(skb
);
790 if (ip
->protocol
== IPPROTO_TCP
)
791 flags
|= IPCS
| TCPCS
;
792 else if (ip
->protocol
== IPPROTO_UDP
)
793 flags
|= IPCS
| UDPCS
;
795 WARN_ON(1); /* we need a WARN() */
798 txd
->opts1
= cpu_to_le32(flags
);
801 cp
->tx_skb
[entry
] = skb
;
802 entry
= NEXT_TX(entry
);
805 u32 first_len
, first_eor
;
806 dma_addr_t first_mapping
;
807 int frag
, first_entry
= entry
;
808 const struct iphdr
*ip
= ip_hdr(skb
);
810 /* We must give this initial chunk to the device last.
811 * Otherwise we could race with the device.
814 first_len
= skb_headlen(skb
);
815 first_mapping
= dma_map_single(&cp
->pdev
->dev
, skb
->data
,
816 first_len
, PCI_DMA_TODEVICE
);
817 cp
->tx_skb
[entry
] = skb
;
818 entry
= NEXT_TX(entry
);
820 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
821 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
826 len
= this_frag
->size
;
827 mapping
= dma_map_single(&cp
->pdev
->dev
,
828 ((void *) page_address(this_frag
->page
) +
829 this_frag
->page_offset
),
830 len
, PCI_DMA_TODEVICE
);
831 eor
= (entry
== (CP_TX_RING_SIZE
- 1)) ? RingEnd
: 0;
833 ctrl
= eor
| len
| DescOwn
;
837 ((mss
& MSSMask
) << MSSShift
);
838 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
839 if (ip
->protocol
== IPPROTO_TCP
)
840 ctrl
|= IPCS
| TCPCS
;
841 else if (ip
->protocol
== IPPROTO_UDP
)
842 ctrl
|= IPCS
| UDPCS
;
847 if (frag
== skb_shinfo(skb
)->nr_frags
- 1)
850 txd
= &cp
->tx_ring
[entry
];
851 CP_VLAN_TX_TAG(txd
, vlan_tag
);
852 txd
->addr
= cpu_to_le64(mapping
);
855 txd
->opts1
= cpu_to_le32(ctrl
);
858 cp
->tx_skb
[entry
] = skb
;
859 entry
= NEXT_TX(entry
);
862 txd
= &cp
->tx_ring
[first_entry
];
863 CP_VLAN_TX_TAG(txd
, vlan_tag
);
864 txd
->addr
= cpu_to_le64(first_mapping
);
867 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
868 if (ip
->protocol
== IPPROTO_TCP
)
869 txd
->opts1
= cpu_to_le32(first_eor
| first_len
|
870 FirstFrag
| DescOwn
|
872 else if (ip
->protocol
== IPPROTO_UDP
)
873 txd
->opts1
= cpu_to_le32(first_eor
| first_len
|
874 FirstFrag
| DescOwn
|
879 txd
->opts1
= cpu_to_le32(first_eor
| first_len
|
880 FirstFrag
| DescOwn
);
884 if (netif_msg_tx_queued(cp
))
885 printk(KERN_DEBUG
"%s: tx queued, slot %d, skblen %d\n",
886 dev
->name
, entry
, skb
->len
);
887 if (TX_BUFFS_AVAIL(cp
) <= (MAX_SKB_FRAGS
+ 1))
888 netif_stop_queue(dev
);
890 spin_unlock_irqrestore(&cp
->lock
, intr_flags
);
892 cpw8(TxPoll
, NormalTxPoll
);
893 dev
->trans_start
= jiffies
;
898 /* Set or clear the multicast filter for this adaptor.
899 This routine is not state sensitive and need not be SMP locked. */
901 static void __cp_set_rx_mode (struct net_device
*dev
)
903 struct cp_private
*cp
= netdev_priv(dev
);
904 u32 mc_filter
[2]; /* Multicast hash filter */
908 /* Note: do not reorder, GCC is clever about common statements. */
909 if (dev
->flags
& IFF_PROMISC
) {
910 /* Unconditionally log net taps. */
912 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
914 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
915 } else if ((dev
->mc_count
> multicast_filter_limit
)
916 || (dev
->flags
& IFF_ALLMULTI
)) {
917 /* Too many to filter perfectly -- accept all multicasts. */
918 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
919 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
921 struct dev_mc_list
*mclist
;
922 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
923 mc_filter
[1] = mc_filter
[0] = 0;
924 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
925 i
++, mclist
= mclist
->next
) {
926 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
928 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
929 rx_mode
|= AcceptMulticast
;
933 /* We can safely update without stopping the chip. */
934 tmp
= cp_rx_config
| rx_mode
;
935 if (cp
->rx_config
!= tmp
) {
936 cpw32_f (RxConfig
, tmp
);
939 cpw32_f (MAR0
+ 0, mc_filter
[0]);
940 cpw32_f (MAR0
+ 4, mc_filter
[1]);
943 static void cp_set_rx_mode (struct net_device
*dev
)
946 struct cp_private
*cp
= netdev_priv(dev
);
948 spin_lock_irqsave (&cp
->lock
, flags
);
949 __cp_set_rx_mode(dev
);
950 spin_unlock_irqrestore (&cp
->lock
, flags
);
953 static void __cp_get_stats(struct cp_private
*cp
)
955 /* only lower 24 bits valid; write any value to clear */
956 cp
->dev
->stats
.rx_missed_errors
+= (cpr32 (RxMissed
) & 0xffffff);
960 static struct net_device_stats
*cp_get_stats(struct net_device
*dev
)
962 struct cp_private
*cp
= netdev_priv(dev
);
965 /* The chip only need report frame silently dropped. */
966 spin_lock_irqsave(&cp
->lock
, flags
);
967 if (netif_running(dev
) && netif_device_present(dev
))
969 spin_unlock_irqrestore(&cp
->lock
, flags
);
974 static void cp_stop_hw (struct cp_private
*cp
)
976 cpw16(IntrStatus
, ~(cpr16(IntrStatus
)));
977 cpw16_f(IntrMask
, 0);
980 cpw16_f(IntrStatus
, ~(cpr16(IntrStatus
)));
983 cp
->tx_head
= cp
->tx_tail
= 0;
986 static void cp_reset_hw (struct cp_private
*cp
)
988 unsigned work
= 1000;
993 if (!(cpr8(Cmd
) & CmdReset
))
996 schedule_timeout_uninterruptible(10);
999 printk(KERN_ERR
"%s: hardware reset timeout\n", cp
->dev
->name
);
1002 static inline void cp_start_hw (struct cp_private
*cp
)
1004 cpw16(CpCmd
, cp
->cpcmd
);
1005 cpw8(Cmd
, RxOn
| TxOn
);
1008 static void cp_init_hw (struct cp_private
*cp
)
1010 struct net_device
*dev
= cp
->dev
;
1011 dma_addr_t ring_dma
;
1015 cpw8_f (Cfg9346
, Cfg9346_Unlock
);
1017 /* Restore our idea of the MAC address. */
1018 cpw32_f (MAC0
+ 0, le32_to_cpu (*(__le32
*) (dev
->dev_addr
+ 0)));
1019 cpw32_f (MAC0
+ 4, le32_to_cpu (*(__le32
*) (dev
->dev_addr
+ 4)));
1022 cpw8(TxThresh
, 0x06); /* XXX convert magic num to a constant */
1024 __cp_set_rx_mode(dev
);
1025 cpw32_f (TxConfig
, IFG
| (TX_DMA_BURST
<< TxDMAShift
));
1027 cpw8(Config1
, cpr8(Config1
) | DriverLoaded
| PMEnable
);
1028 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1029 cpw8(Config3
, PARMEnable
);
1030 cp
->wol_enabled
= 0;
1032 cpw8(Config5
, cpr8(Config5
) & PMEStatus
);
1034 cpw32_f(HiTxRingAddr
, 0);
1035 cpw32_f(HiTxRingAddr
+ 4, 0);
1037 ring_dma
= cp
->ring_dma
;
1038 cpw32_f(RxRingAddr
, ring_dma
& 0xffffffff);
1039 cpw32_f(RxRingAddr
+ 4, (ring_dma
>> 16) >> 16);
1041 ring_dma
+= sizeof(struct cp_desc
) * CP_RX_RING_SIZE
;
1042 cpw32_f(TxRingAddr
, ring_dma
& 0xffffffff);
1043 cpw32_f(TxRingAddr
+ 4, (ring_dma
>> 16) >> 16);
1045 cpw16(MultiIntr
, 0);
1047 cpw16_f(IntrMask
, cp_intr_mask
);
1049 cpw8_f(Cfg9346
, Cfg9346_Lock
);
1052 static int cp_refill_rx(struct cp_private
*cp
)
1054 struct net_device
*dev
= cp
->dev
;
1057 for (i
= 0; i
< CP_RX_RING_SIZE
; i
++) {
1058 struct sk_buff
*skb
;
1061 skb
= netdev_alloc_skb(dev
, cp
->rx_buf_sz
+ NET_IP_ALIGN
);
1065 skb_reserve(skb
, NET_IP_ALIGN
);
1067 mapping
= dma_map_single(&cp
->pdev
->dev
, skb
->data
,
1068 cp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1069 cp
->rx_skb
[i
] = skb
;
1071 cp
->rx_ring
[i
].opts2
= 0;
1072 cp
->rx_ring
[i
].addr
= cpu_to_le64(mapping
);
1073 if (i
== (CP_RX_RING_SIZE
- 1))
1074 cp
->rx_ring
[i
].opts1
=
1075 cpu_to_le32(DescOwn
| RingEnd
| cp
->rx_buf_sz
);
1077 cp
->rx_ring
[i
].opts1
=
1078 cpu_to_le32(DescOwn
| cp
->rx_buf_sz
);
1088 static void cp_init_rings_index (struct cp_private
*cp
)
1091 cp
->tx_head
= cp
->tx_tail
= 0;
1094 static int cp_init_rings (struct cp_private
*cp
)
1096 memset(cp
->tx_ring
, 0, sizeof(struct cp_desc
) * CP_TX_RING_SIZE
);
1097 cp
->tx_ring
[CP_TX_RING_SIZE
- 1].opts1
= cpu_to_le32(RingEnd
);
1099 cp_init_rings_index(cp
);
1101 return cp_refill_rx (cp
);
1104 static int cp_alloc_rings (struct cp_private
*cp
)
1108 mem
= dma_alloc_coherent(&cp
->pdev
->dev
, CP_RING_BYTES
,
1109 &cp
->ring_dma
, GFP_KERNEL
);
1114 cp
->tx_ring
= &cp
->rx_ring
[CP_RX_RING_SIZE
];
1116 return cp_init_rings(cp
);
1119 static void cp_clean_rings (struct cp_private
*cp
)
1121 struct cp_desc
*desc
;
1124 for (i
= 0; i
< CP_RX_RING_SIZE
; i
++) {
1125 if (cp
->rx_skb
[i
]) {
1126 desc
= cp
->rx_ring
+ i
;
1127 dma_unmap_single(&cp
->pdev
->dev
,le64_to_cpu(desc
->addr
),
1128 cp
->rx_buf_sz
, PCI_DMA_FROMDEVICE
);
1129 dev_kfree_skb(cp
->rx_skb
[i
]);
1133 for (i
= 0; i
< CP_TX_RING_SIZE
; i
++) {
1134 if (cp
->tx_skb
[i
]) {
1135 struct sk_buff
*skb
= cp
->tx_skb
[i
];
1137 desc
= cp
->tx_ring
+ i
;
1138 dma_unmap_single(&cp
->pdev
->dev
,le64_to_cpu(desc
->addr
),
1139 le32_to_cpu(desc
->opts1
) & 0xffff,
1141 if (le32_to_cpu(desc
->opts1
) & LastFrag
)
1143 cp
->dev
->stats
.tx_dropped
++;
1147 memset(cp
->rx_ring
, 0, sizeof(struct cp_desc
) * CP_RX_RING_SIZE
);
1148 memset(cp
->tx_ring
, 0, sizeof(struct cp_desc
) * CP_TX_RING_SIZE
);
1150 memset(cp
->rx_skb
, 0, sizeof(struct sk_buff
*) * CP_RX_RING_SIZE
);
1151 memset(cp
->tx_skb
, 0, sizeof(struct sk_buff
*) * CP_TX_RING_SIZE
);
1154 static void cp_free_rings (struct cp_private
*cp
)
1157 dma_free_coherent(&cp
->pdev
->dev
, CP_RING_BYTES
, cp
->rx_ring
,
1163 static int cp_open (struct net_device
*dev
)
1165 struct cp_private
*cp
= netdev_priv(dev
);
1168 if (netif_msg_ifup(cp
))
1169 printk(KERN_DEBUG
"%s: enabling interface\n", dev
->name
);
1171 rc
= cp_alloc_rings(cp
);
1175 napi_enable(&cp
->napi
);
1179 rc
= request_irq(dev
->irq
, cp_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
1183 netif_carrier_off(dev
);
1184 mii_check_media(&cp
->mii_if
, netif_msg_link(cp
), true);
1185 netif_start_queue(dev
);
1190 napi_disable(&cp
->napi
);
1196 static int cp_close (struct net_device
*dev
)
1198 struct cp_private
*cp
= netdev_priv(dev
);
1199 unsigned long flags
;
1201 napi_disable(&cp
->napi
);
1203 if (netif_msg_ifdown(cp
))
1204 printk(KERN_DEBUG
"%s: disabling interface\n", dev
->name
);
1206 spin_lock_irqsave(&cp
->lock
, flags
);
1208 netif_stop_queue(dev
);
1209 netif_carrier_off(dev
);
1213 spin_unlock_irqrestore(&cp
->lock
, flags
);
1215 free_irq(dev
->irq
, dev
);
1221 static void cp_tx_timeout(struct net_device
*dev
)
1223 struct cp_private
*cp
= netdev_priv(dev
);
1224 unsigned long flags
;
1227 printk(KERN_WARNING
"%s: Transmit timeout, status %2x %4x %4x %4x\n",
1228 dev
->name
, cpr8(Cmd
), cpr16(CpCmd
),
1229 cpr16(IntrStatus
), cpr16(IntrMask
));
1231 spin_lock_irqsave(&cp
->lock
, flags
);
1235 rc
= cp_init_rings(cp
);
1238 netif_wake_queue(dev
);
1240 spin_unlock_irqrestore(&cp
->lock
, flags
);
1246 static int cp_change_mtu(struct net_device
*dev
, int new_mtu
)
1248 struct cp_private
*cp
= netdev_priv(dev
);
1250 unsigned long flags
;
1252 /* check for invalid MTU, according to hardware limits */
1253 if (new_mtu
< CP_MIN_MTU
|| new_mtu
> CP_MAX_MTU
)
1256 /* if network interface not up, no need for complexity */
1257 if (!netif_running(dev
)) {
1259 cp_set_rxbufsize(cp
); /* set new rx buf size */
1263 spin_lock_irqsave(&cp
->lock
, flags
);
1265 cp_stop_hw(cp
); /* stop h/w and free rings */
1269 cp_set_rxbufsize(cp
); /* set new rx buf size */
1271 rc
= cp_init_rings(cp
); /* realloc and restart h/w */
1274 spin_unlock_irqrestore(&cp
->lock
, flags
);
1280 static const char mii_2_8139_map
[8] = {
1291 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1293 struct cp_private
*cp
= netdev_priv(dev
);
1295 return location
< 8 && mii_2_8139_map
[location
] ?
1296 readw(cp
->regs
+ mii_2_8139_map
[location
]) : 0;
1300 static void mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1303 struct cp_private
*cp
= netdev_priv(dev
);
1305 if (location
== 0) {
1306 cpw8(Cfg9346
, Cfg9346_Unlock
);
1307 cpw16(BasicModeCtrl
, value
);
1308 cpw8(Cfg9346
, Cfg9346_Lock
);
1309 } else if (location
< 8 && mii_2_8139_map
[location
])
1310 cpw16(mii_2_8139_map
[location
], value
);
1313 /* Set the ethtool Wake-on-LAN settings */
1314 static int netdev_set_wol (struct cp_private
*cp
,
1315 const struct ethtool_wolinfo
*wol
)
1319 options
= cpr8 (Config3
) & ~(LinkUp
| MagicPacket
);
1320 /* If WOL is being disabled, no need for complexity */
1322 if (wol
->wolopts
& WAKE_PHY
) options
|= LinkUp
;
1323 if (wol
->wolopts
& WAKE_MAGIC
) options
|= MagicPacket
;
1326 cpw8 (Cfg9346
, Cfg9346_Unlock
);
1327 cpw8 (Config3
, options
);
1328 cpw8 (Cfg9346
, Cfg9346_Lock
);
1330 options
= 0; /* Paranoia setting */
1331 options
= cpr8 (Config5
) & ~(UWF
| MWF
| BWF
);
1332 /* If WOL is being disabled, no need for complexity */
1334 if (wol
->wolopts
& WAKE_UCAST
) options
|= UWF
;
1335 if (wol
->wolopts
& WAKE_BCAST
) options
|= BWF
;
1336 if (wol
->wolopts
& WAKE_MCAST
) options
|= MWF
;
1339 cpw8 (Config5
, options
);
1341 cp
->wol_enabled
= (wol
->wolopts
) ? 1 : 0;
1346 /* Get the ethtool Wake-on-LAN settings */
1347 static void netdev_get_wol (struct cp_private
*cp
,
1348 struct ethtool_wolinfo
*wol
)
1352 wol
->wolopts
= 0; /* Start from scratch */
1353 wol
->supported
= WAKE_PHY
| WAKE_BCAST
| WAKE_MAGIC
|
1354 WAKE_MCAST
| WAKE_UCAST
;
1355 /* We don't need to go on if WOL is disabled */
1356 if (!cp
->wol_enabled
) return;
1358 options
= cpr8 (Config3
);
1359 if (options
& LinkUp
) wol
->wolopts
|= WAKE_PHY
;
1360 if (options
& MagicPacket
) wol
->wolopts
|= WAKE_MAGIC
;
1362 options
= 0; /* Paranoia setting */
1363 options
= cpr8 (Config5
);
1364 if (options
& UWF
) wol
->wolopts
|= WAKE_UCAST
;
1365 if (options
& BWF
) wol
->wolopts
|= WAKE_BCAST
;
1366 if (options
& MWF
) wol
->wolopts
|= WAKE_MCAST
;
1369 static void cp_get_drvinfo (struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1371 struct cp_private
*cp
= netdev_priv(dev
);
1373 strcpy (info
->driver
, DRV_NAME
);
1374 strcpy (info
->version
, DRV_VERSION
);
1375 strcpy (info
->bus_info
, pci_name(cp
->pdev
));
1378 static int cp_get_regs_len(struct net_device
*dev
)
1380 return CP_REGS_SIZE
;
1383 static int cp_get_sset_count (struct net_device
*dev
, int sset
)
1387 return CP_NUM_STATS
;
1393 static int cp_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1395 struct cp_private
*cp
= netdev_priv(dev
);
1397 unsigned long flags
;
1399 spin_lock_irqsave(&cp
->lock
, flags
);
1400 rc
= mii_ethtool_gset(&cp
->mii_if
, cmd
);
1401 spin_unlock_irqrestore(&cp
->lock
, flags
);
1406 static int cp_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1408 struct cp_private
*cp
= netdev_priv(dev
);
1410 unsigned long flags
;
1412 spin_lock_irqsave(&cp
->lock
, flags
);
1413 rc
= mii_ethtool_sset(&cp
->mii_if
, cmd
);
1414 spin_unlock_irqrestore(&cp
->lock
, flags
);
1419 static int cp_nway_reset(struct net_device
*dev
)
1421 struct cp_private
*cp
= netdev_priv(dev
);
1422 return mii_nway_restart(&cp
->mii_if
);
1425 static u32
cp_get_msglevel(struct net_device
*dev
)
1427 struct cp_private
*cp
= netdev_priv(dev
);
1428 return cp
->msg_enable
;
1431 static void cp_set_msglevel(struct net_device
*dev
, u32 value
)
1433 struct cp_private
*cp
= netdev_priv(dev
);
1434 cp
->msg_enable
= value
;
1437 static u32
cp_get_rx_csum(struct net_device
*dev
)
1439 struct cp_private
*cp
= netdev_priv(dev
);
1440 return (cpr16(CpCmd
) & RxChkSum
) ? 1 : 0;
1443 static int cp_set_rx_csum(struct net_device
*dev
, u32 data
)
1445 struct cp_private
*cp
= netdev_priv(dev
);
1446 u16 cmd
= cp
->cpcmd
, newcmd
;
1453 newcmd
&= ~RxChkSum
;
1455 if (newcmd
!= cmd
) {
1456 unsigned long flags
;
1458 spin_lock_irqsave(&cp
->lock
, flags
);
1460 cpw16_f(CpCmd
, newcmd
);
1461 spin_unlock_irqrestore(&cp
->lock
, flags
);
1467 static void cp_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1470 struct cp_private
*cp
= netdev_priv(dev
);
1471 unsigned long flags
;
1473 if (regs
->len
< CP_REGS_SIZE
)
1474 return /* -EINVAL */;
1476 regs
->version
= CP_REGS_VER
;
1478 spin_lock_irqsave(&cp
->lock
, flags
);
1479 memcpy_fromio(p
, cp
->regs
, CP_REGS_SIZE
);
1480 spin_unlock_irqrestore(&cp
->lock
, flags
);
1483 static void cp_get_wol (struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1485 struct cp_private
*cp
= netdev_priv(dev
);
1486 unsigned long flags
;
1488 spin_lock_irqsave (&cp
->lock
, flags
);
1489 netdev_get_wol (cp
, wol
);
1490 spin_unlock_irqrestore (&cp
->lock
, flags
);
1493 static int cp_set_wol (struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1495 struct cp_private
*cp
= netdev_priv(dev
);
1496 unsigned long flags
;
1499 spin_lock_irqsave (&cp
->lock
, flags
);
1500 rc
= netdev_set_wol (cp
, wol
);
1501 spin_unlock_irqrestore (&cp
->lock
, flags
);
1506 static void cp_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
1508 switch (stringset
) {
1510 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
1518 static void cp_get_ethtool_stats (struct net_device
*dev
,
1519 struct ethtool_stats
*estats
, u64
*tmp_stats
)
1521 struct cp_private
*cp
= netdev_priv(dev
);
1522 struct cp_dma_stats
*nic_stats
;
1526 nic_stats
= dma_alloc_coherent(&cp
->pdev
->dev
, sizeof(*nic_stats
),
1531 /* begin NIC statistics dump */
1532 cpw32(StatsAddr
+ 4, (u64
)dma
>> 32);
1533 cpw32(StatsAddr
, ((u64
)dma
& DMA_32BIT_MASK
) | DumpStats
);
1536 for (i
= 0; i
< 1000; i
++) {
1537 if ((cpr32(StatsAddr
) & DumpStats
) == 0)
1541 cpw32(StatsAddr
, 0);
1542 cpw32(StatsAddr
+ 4, 0);
1546 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->tx_ok
);
1547 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->rx_ok
);
1548 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->tx_err
);
1549 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->rx_err
);
1550 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->rx_fifo
);
1551 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->frame_align
);
1552 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->tx_ok_1col
);
1553 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->tx_ok_mcol
);
1554 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->rx_ok_phys
);
1555 tmp_stats
[i
++] = le64_to_cpu(nic_stats
->rx_ok_bcast
);
1556 tmp_stats
[i
++] = le32_to_cpu(nic_stats
->rx_ok_mcast
);
1557 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->tx_abort
);
1558 tmp_stats
[i
++] = le16_to_cpu(nic_stats
->tx_underrun
);
1559 tmp_stats
[i
++] = cp
->cp_stats
.rx_frags
;
1560 BUG_ON(i
!= CP_NUM_STATS
);
1562 dma_free_coherent(&cp
->pdev
->dev
, sizeof(*nic_stats
), nic_stats
, dma
);
1565 static const struct ethtool_ops cp_ethtool_ops
= {
1566 .get_drvinfo
= cp_get_drvinfo
,
1567 .get_regs_len
= cp_get_regs_len
,
1568 .get_sset_count
= cp_get_sset_count
,
1569 .get_settings
= cp_get_settings
,
1570 .set_settings
= cp_set_settings
,
1571 .nway_reset
= cp_nway_reset
,
1572 .get_link
= ethtool_op_get_link
,
1573 .get_msglevel
= cp_get_msglevel
,
1574 .set_msglevel
= cp_set_msglevel
,
1575 .get_rx_csum
= cp_get_rx_csum
,
1576 .set_rx_csum
= cp_set_rx_csum
,
1577 .set_tx_csum
= ethtool_op_set_tx_csum
, /* local! */
1578 .set_sg
= ethtool_op_set_sg
,
1579 .set_tso
= ethtool_op_set_tso
,
1580 .get_regs
= cp_get_regs
,
1581 .get_wol
= cp_get_wol
,
1582 .set_wol
= cp_set_wol
,
1583 .get_strings
= cp_get_strings
,
1584 .get_ethtool_stats
= cp_get_ethtool_stats
,
1585 .get_eeprom_len
= cp_get_eeprom_len
,
1586 .get_eeprom
= cp_get_eeprom
,
1587 .set_eeprom
= cp_set_eeprom
,
1590 static int cp_ioctl (struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1592 struct cp_private
*cp
= netdev_priv(dev
);
1594 unsigned long flags
;
1596 if (!netif_running(dev
))
1599 spin_lock_irqsave(&cp
->lock
, flags
);
1600 rc
= generic_mii_ioctl(&cp
->mii_if
, if_mii(rq
), cmd
, NULL
);
1601 spin_unlock_irqrestore(&cp
->lock
, flags
);
1605 /* Serial EEPROM section. */
1607 /* EEPROM_Ctrl bits. */
1608 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1609 #define EE_CS 0x08 /* EEPROM chip select. */
1610 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1611 #define EE_WRITE_0 0x00
1612 #define EE_WRITE_1 0x02
1613 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1614 #define EE_ENB (0x80 | EE_CS)
1616 /* Delay between EEPROM clock transitions.
1617 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1620 #define eeprom_delay() readl(ee_addr)
1622 /* The EEPROM commands include the alway-set leading bit. */
1623 #define EE_EXTEND_CMD (4)
1624 #define EE_WRITE_CMD (5)
1625 #define EE_READ_CMD (6)
1626 #define EE_ERASE_CMD (7)
1628 #define EE_EWDS_ADDR (0)
1629 #define EE_WRAL_ADDR (1)
1630 #define EE_ERAL_ADDR (2)
1631 #define EE_EWEN_ADDR (3)
1633 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1635 static void eeprom_cmd_start(void __iomem
*ee_addr
)
1637 writeb (EE_ENB
& ~EE_CS
, ee_addr
);
1638 writeb (EE_ENB
, ee_addr
);
1642 static void eeprom_cmd(void __iomem
*ee_addr
, int cmd
, int cmd_len
)
1646 /* Shift the command bits out. */
1647 for (i
= cmd_len
- 1; i
>= 0; i
--) {
1648 int dataval
= (cmd
& (1 << i
)) ? EE_DATA_WRITE
: 0;
1649 writeb (EE_ENB
| dataval
, ee_addr
);
1651 writeb (EE_ENB
| dataval
| EE_SHIFT_CLK
, ee_addr
);
1654 writeb (EE_ENB
, ee_addr
);
1658 static void eeprom_cmd_end(void __iomem
*ee_addr
)
1660 writeb (~EE_CS
, ee_addr
);
1664 static void eeprom_extend_cmd(void __iomem
*ee_addr
, int extend_cmd
,
1667 int cmd
= (EE_EXTEND_CMD
<< addr_len
) | (extend_cmd
<< (addr_len
- 2));
1669 eeprom_cmd_start(ee_addr
);
1670 eeprom_cmd(ee_addr
, cmd
, 3 + addr_len
);
1671 eeprom_cmd_end(ee_addr
);
1674 static u16
read_eeprom (void __iomem
*ioaddr
, int location
, int addr_len
)
1678 void __iomem
*ee_addr
= ioaddr
+ Cfg9346
;
1679 int read_cmd
= location
| (EE_READ_CMD
<< addr_len
);
1681 eeprom_cmd_start(ee_addr
);
1682 eeprom_cmd(ee_addr
, read_cmd
, 3 + addr_len
);
1684 for (i
= 16; i
> 0; i
--) {
1685 writeb (EE_ENB
| EE_SHIFT_CLK
, ee_addr
);
1688 (retval
<< 1) | ((readb (ee_addr
) & EE_DATA_READ
) ? 1 :
1690 writeb (EE_ENB
, ee_addr
);
1694 eeprom_cmd_end(ee_addr
);
1699 static void write_eeprom(void __iomem
*ioaddr
, int location
, u16 val
,
1703 void __iomem
*ee_addr
= ioaddr
+ Cfg9346
;
1704 int write_cmd
= location
| (EE_WRITE_CMD
<< addr_len
);
1706 eeprom_extend_cmd(ee_addr
, EE_EWEN_ADDR
, addr_len
);
1708 eeprom_cmd_start(ee_addr
);
1709 eeprom_cmd(ee_addr
, write_cmd
, 3 + addr_len
);
1710 eeprom_cmd(ee_addr
, val
, 16);
1711 eeprom_cmd_end(ee_addr
);
1713 eeprom_cmd_start(ee_addr
);
1714 for (i
= 0; i
< 20000; i
++)
1715 if (readb(ee_addr
) & EE_DATA_READ
)
1717 eeprom_cmd_end(ee_addr
);
1719 eeprom_extend_cmd(ee_addr
, EE_EWDS_ADDR
, addr_len
);
1722 static int cp_get_eeprom_len(struct net_device
*dev
)
1724 struct cp_private
*cp
= netdev_priv(dev
);
1727 spin_lock_irq(&cp
->lock
);
1728 size
= read_eeprom(cp
->regs
, 0, 8) == 0x8129 ? 256 : 128;
1729 spin_unlock_irq(&cp
->lock
);
1734 static int cp_get_eeprom(struct net_device
*dev
,
1735 struct ethtool_eeprom
*eeprom
, u8
*data
)
1737 struct cp_private
*cp
= netdev_priv(dev
);
1738 unsigned int addr_len
;
1740 u32 offset
= eeprom
->offset
>> 1;
1741 u32 len
= eeprom
->len
;
1744 eeprom
->magic
= CP_EEPROM_MAGIC
;
1746 spin_lock_irq(&cp
->lock
);
1748 addr_len
= read_eeprom(cp
->regs
, 0, 8) == 0x8129 ? 8 : 6;
1750 if (eeprom
->offset
& 1) {
1751 val
= read_eeprom(cp
->regs
, offset
, addr_len
);
1752 data
[i
++] = (u8
)(val
>> 8);
1756 while (i
< len
- 1) {
1757 val
= read_eeprom(cp
->regs
, offset
, addr_len
);
1758 data
[i
++] = (u8
)val
;
1759 data
[i
++] = (u8
)(val
>> 8);
1764 val
= read_eeprom(cp
->regs
, offset
, addr_len
);
1768 spin_unlock_irq(&cp
->lock
);
1772 static int cp_set_eeprom(struct net_device
*dev
,
1773 struct ethtool_eeprom
*eeprom
, u8
*data
)
1775 struct cp_private
*cp
= netdev_priv(dev
);
1776 unsigned int addr_len
;
1778 u32 offset
= eeprom
->offset
>> 1;
1779 u32 len
= eeprom
->len
;
1782 if (eeprom
->magic
!= CP_EEPROM_MAGIC
)
1785 spin_lock_irq(&cp
->lock
);
1787 addr_len
= read_eeprom(cp
->regs
, 0, 8) == 0x8129 ? 8 : 6;
1789 if (eeprom
->offset
& 1) {
1790 val
= read_eeprom(cp
->regs
, offset
, addr_len
) & 0xff;
1791 val
|= (u16
)data
[i
++] << 8;
1792 write_eeprom(cp
->regs
, offset
, val
, addr_len
);
1796 while (i
< len
- 1) {
1797 val
= (u16
)data
[i
++];
1798 val
|= (u16
)data
[i
++] << 8;
1799 write_eeprom(cp
->regs
, offset
, val
, addr_len
);
1804 val
= read_eeprom(cp
->regs
, offset
, addr_len
) & 0xff00;
1805 val
|= (u16
)data
[i
];
1806 write_eeprom(cp
->regs
, offset
, val
, addr_len
);
1809 spin_unlock_irq(&cp
->lock
);
1813 /* Put the board into D3cold state and wait for WakeUp signal */
1814 static void cp_set_d3_state (struct cp_private
*cp
)
1816 pci_enable_wake (cp
->pdev
, 0, 1); /* Enable PME# generation */
1817 pci_set_power_state (cp
->pdev
, PCI_D3hot
);
1820 static const struct net_device_ops cp_netdev_ops
= {
1821 .ndo_open
= cp_open
,
1822 .ndo_stop
= cp_close
,
1823 .ndo_validate_addr
= eth_validate_addr
,
1824 .ndo_set_multicast_list
= cp_set_rx_mode
,
1825 .ndo_get_stats
= cp_get_stats
,
1826 .ndo_do_ioctl
= cp_ioctl
,
1827 .ndo_start_xmit
= cp_start_xmit
,
1828 .ndo_tx_timeout
= cp_tx_timeout
,
1829 #if CP_VLAN_TAG_USED
1830 .ndo_vlan_rx_register
= cp_vlan_rx_register
,
1833 .ndo_change_mtu
= cp_change_mtu
,
1835 #ifdef CONFIG_NET_POLL_CONTROLLER
1836 .ndo_poll_controller
= cp_poll_controller
,
1840 static int cp_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1842 struct net_device
*dev
;
1843 struct cp_private
*cp
;
1846 resource_size_t pciaddr
;
1847 unsigned int addr_len
, i
, pci_using_dac
;
1850 static int version_printed
;
1851 if (version_printed
++ == 0)
1852 printk("%s", version
);
1855 if (pdev
->vendor
== PCI_VENDOR_ID_REALTEK
&&
1856 pdev
->device
== PCI_DEVICE_ID_REALTEK_8139
&& pdev
->revision
< 0x20) {
1857 dev_info(&pdev
->dev
,
1858 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1859 pdev
->vendor
, pdev
->device
, pdev
->revision
);
1863 dev
= alloc_etherdev(sizeof(struct cp_private
));
1866 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1868 cp
= netdev_priv(dev
);
1871 cp
->msg_enable
= (debug
< 0 ? CP_DEF_MSG_ENABLE
: debug
);
1872 spin_lock_init (&cp
->lock
);
1873 cp
->mii_if
.dev
= dev
;
1874 cp
->mii_if
.mdio_read
= mdio_read
;
1875 cp
->mii_if
.mdio_write
= mdio_write
;
1876 cp
->mii_if
.phy_id
= CP_INTERNAL_PHY
;
1877 cp
->mii_if
.phy_id_mask
= 0x1f;
1878 cp
->mii_if
.reg_num_mask
= 0x1f;
1879 cp_set_rxbufsize(cp
);
1881 rc
= pci_enable_device(pdev
);
1885 rc
= pci_set_mwi(pdev
);
1887 goto err_out_disable
;
1889 rc
= pci_request_regions(pdev
, DRV_NAME
);
1893 pciaddr
= pci_resource_start(pdev
, 1);
1896 dev_err(&pdev
->dev
, "no MMIO resource\n");
1899 if (pci_resource_len(pdev
, 1) < CP_REGS_SIZE
) {
1901 dev_err(&pdev
->dev
, "MMIO resource (%llx) too small\n",
1902 (unsigned long long)pci_resource_len(pdev
, 1));
1906 /* Configure DMA attributes. */
1907 if ((sizeof(dma_addr_t
) > 4) &&
1908 !pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
) &&
1909 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1914 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1917 "No usable DMA configuration, aborting.\n");
1920 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1923 "No usable consistent DMA configuration, "
1929 cp
->cpcmd
= (pci_using_dac
? PCIDAC
: 0) |
1930 PCIMulRW
| RxChkSum
| CpRxOn
| CpTxOn
;
1932 regs
= ioremap(pciaddr
, CP_REGS_SIZE
);
1935 dev_err(&pdev
->dev
, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1936 (unsigned long long)pci_resource_len(pdev
, 1),
1937 (unsigned long long)pciaddr
);
1940 dev
->base_addr
= (unsigned long) regs
;
1945 /* read MAC address from EEPROM */
1946 addr_len
= read_eeprom (regs
, 0, 8) == 0x8129 ? 8 : 6;
1947 for (i
= 0; i
< 3; i
++)
1948 ((__le16
*) (dev
->dev_addr
))[i
] =
1949 cpu_to_le16(read_eeprom (regs
, i
+ 7, addr_len
));
1950 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1952 dev
->netdev_ops
= &cp_netdev_ops
;
1953 netif_napi_add(dev
, &cp
->napi
, cp_rx_poll
, 16);
1954 dev
->ethtool_ops
= &cp_ethtool_ops
;
1955 dev
->watchdog_timeo
= TX_TIMEOUT
;
1957 #if CP_VLAN_TAG_USED
1958 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1962 dev
->features
|= NETIF_F_HIGHDMA
;
1964 #if 0 /* disabled by default until verified */
1965 dev
->features
|= NETIF_F_TSO
;
1968 dev
->irq
= pdev
->irq
;
1970 rc
= register_netdev(dev
);
1974 printk (KERN_INFO
"%s: RTL-8139C+ at 0x%lx, "
1981 pci_set_drvdata(pdev
, dev
);
1983 /* enable busmastering and memory-write-invalidate */
1984 pci_set_master(pdev
);
1986 if (cp
->wol_enabled
)
1987 cp_set_d3_state (cp
);
1994 pci_release_regions(pdev
);
1996 pci_clear_mwi(pdev
);
1998 pci_disable_device(pdev
);
2004 static void cp_remove_one (struct pci_dev
*pdev
)
2006 struct net_device
*dev
= pci_get_drvdata(pdev
);
2007 struct cp_private
*cp
= netdev_priv(dev
);
2009 unregister_netdev(dev
);
2011 if (cp
->wol_enabled
)
2012 pci_set_power_state (pdev
, PCI_D0
);
2013 pci_release_regions(pdev
);
2014 pci_clear_mwi(pdev
);
2015 pci_disable_device(pdev
);
2016 pci_set_drvdata(pdev
, NULL
);
2021 static int cp_suspend (struct pci_dev
*pdev
, pm_message_t state
)
2023 struct net_device
*dev
= pci_get_drvdata(pdev
);
2024 struct cp_private
*cp
= netdev_priv(dev
);
2025 unsigned long flags
;
2027 if (!netif_running(dev
))
2030 netif_device_detach (dev
);
2031 netif_stop_queue (dev
);
2033 spin_lock_irqsave (&cp
->lock
, flags
);
2035 /* Disable Rx and Tx */
2036 cpw16 (IntrMask
, 0);
2037 cpw8 (Cmd
, cpr8 (Cmd
) & (~RxOn
| ~TxOn
));
2039 spin_unlock_irqrestore (&cp
->lock
, flags
);
2041 pci_save_state(pdev
);
2042 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), cp
->wol_enabled
);
2043 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2048 static int cp_resume (struct pci_dev
*pdev
)
2050 struct net_device
*dev
= pci_get_drvdata (pdev
);
2051 struct cp_private
*cp
= netdev_priv(dev
);
2052 unsigned long flags
;
2054 if (!netif_running(dev
))
2057 netif_device_attach (dev
);
2059 pci_set_power_state(pdev
, PCI_D0
);
2060 pci_restore_state(pdev
);
2061 pci_enable_wake(pdev
, PCI_D0
, 0);
2063 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2064 cp_init_rings_index (cp
);
2066 netif_start_queue (dev
);
2068 spin_lock_irqsave (&cp
->lock
, flags
);
2070 mii_check_media(&cp
->mii_if
, netif_msg_link(cp
), false);
2072 spin_unlock_irqrestore (&cp
->lock
, flags
);
2076 #endif /* CONFIG_PM */
2078 static struct pci_driver cp_driver
= {
2080 .id_table
= cp_pci_tbl
,
2081 .probe
= cp_init_one
,
2082 .remove
= cp_remove_one
,
2084 .resume
= cp_resume
,
2085 .suspend
= cp_suspend
,
2089 static int __init
cp_init (void)
2092 printk("%s", version
);
2094 return pci_register_driver(&cp_driver
);
2097 static void __exit
cp_exit (void)
2099 pci_unregister_driver (&cp_driver
);
2102 module_init(cp_init
);
2103 module_exit(cp_exit
);