1 /* Generic NS8390 register definitions. */
2 /* This file is part of Donald Becker's 8390 drivers, and is distributed
3 under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
4 Some of these names and comments originated from the Crynwr
5 packet drivers, which are distributed under the GPL. */
10 #include <linux/if_ether.h>
11 #include <linux/ioport.h>
12 #include <linux/skbuff.h>
14 #define TX_PAGES 12 /* Two Tx slots */
16 #define ETHER_ADDR_LEN 6
18 /* The 8390 specific per-packet-header format. */
19 struct e8390_pkt_hdr
{
20 unsigned char status
; /* status */
21 unsigned char next
; /* pointer to next packet. */
22 unsigned short count
; /* header + packet length in bytes */
31 #ifdef CONFIG_NET_POLL_CONTROLLER
32 extern void ei_poll(struct net_device
*dev
);
33 extern void eip_poll(struct net_device
*dev
);
36 /* Without I/O delay - non ISA or later chips */
37 extern void NS8390_init(struct net_device
*dev
, int startp
);
38 extern int ei_open(struct net_device
*dev
);
39 extern int ei_close(struct net_device
*dev
);
40 extern irqreturn_t
ei_interrupt(int irq
, void *dev_id
);
41 extern struct net_device
*__alloc_ei_netdev(int size
);
42 static inline struct net_device
*alloc_ei_netdev(void)
44 return __alloc_ei_netdev(0);
47 /* With I/O delay form */
48 extern void NS8390p_init(struct net_device
*dev
, int startp
);
49 extern int eip_open(struct net_device
*dev
);
50 extern int eip_close(struct net_device
*dev
);
51 extern irqreturn_t
eip_interrupt(int irq
, void *dev_id
);
52 extern struct net_device
*__alloc_eip_netdev(int size
);
53 static inline struct net_device
*alloc_eip_netdev(void)
55 return __alloc_eip_netdev(0);
58 /* You have one of these per-board */
61 void (*reset_8390
)(struct net_device
*);
62 void (*get_8390_hdr
)(struct net_device
*, struct e8390_pkt_hdr
*, int);
63 void (*block_output
)(struct net_device
*, int, const unsigned char *, int);
64 void (*block_input
)(struct net_device
*, int, struct sk_buff
*, int);
65 unsigned long rmem_start
;
66 unsigned long rmem_end
;
68 unsigned char mcfilter
[8];
70 unsigned word16
:1; /* We have the 16-bit (vs 8-bit) version of the card. */
71 unsigned bigendian
:1; /* 16-bit big endian mode. Do NOT */
72 /* set this on random 8390 clones! */
73 unsigned txing
:1; /* Transmit Active */
74 unsigned irqlock
:1; /* 8390's intrs disabled when '1'. */
75 unsigned dmaing
:1; /* Remote DMA Active */
76 unsigned char tx_start_page
, rx_start_page
, stop_page
;
77 unsigned char current_page
; /* Read pointer in buffer */
78 unsigned char interface_num
; /* Net port (AUI, 10bT.) to use. */
79 unsigned char txqueue
; /* Tx Packet buffer queue length. */
80 short tx1
, tx2
; /* Packet lengths for ping-pong tx. */
81 short lasttx
; /* Alpha version consistency check. */
82 unsigned char reg0
; /* Register '0' in a WD8013 */
83 unsigned char reg5
; /* Register '5' in a WD8013 */
84 unsigned char saved_irq
; /* Original dev->irq value. */
85 u32
*reg_offset
; /* Register mapping table */
86 spinlock_t page_lock
; /* Page register locks */
87 unsigned long priv
; /* Private field to store bus IDs etc. */
88 #ifdef AX88796_PLATFORM
89 unsigned char rxcr_base
; /* default value for RXCR */
93 /* The maximum number of 8390 interrupt service routines called per IRQ. */
94 #define MAX_SERVICE 12
96 /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
97 #define TX_TIMEOUT (20*HZ/100)
99 #define ei_status (*(struct ei_device *)netdev_priv(dev))
101 /* Some generic ethernet register configurations. */
102 #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
103 #define E8390_RX_IRQ_MASK 0x5
105 #ifdef AX88796_PLATFORM
106 #define E8390_RXCONFIG (ei_status.rxcr_base | 0x04)
107 #define E8390_RXOFF (ei_status.rxcr_base | 0x20)
109 #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
110 #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
113 #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
114 #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
117 /* Register accessed at EN_CMD, the 8390 base addr. */
118 #define E8390_STOP 0x01 /* Stop and reset the chip */
119 #define E8390_START 0x02 /* Start the chip, clear reset */
120 #define E8390_TRANS 0x04 /* Transmit a frame */
121 #define E8390_RREAD 0x08 /* Remote read */
122 #define E8390_RWRITE 0x10 /* Remote write */
123 #define E8390_NODMA 0x20 /* Remote DMA */
124 #define E8390_PAGE0 0x00 /* Select page chip registers */
125 #define E8390_PAGE1 0x40 /* using the two high-order bits */
126 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
129 * Only generate indirect loads given a machine that needs them.
130 * - removed AMIGA_PCMCIA from this list, handled as ISA io now
131 * - the _p for generates no delay by default 8390p.c overrides this.
135 #define ei_inb(_p) inb(_p)
136 #define ei_outb(_v,_p) outb(_v,_p)
137 #define ei_inb_p(_p) inb(_p)
138 #define ei_outb_p(_v,_p) outb(_v,_p)
142 #define EI_SHIFT(x) (x)
145 #define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
146 /* Page 0 register offsets. */
147 #define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
148 #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
149 #define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
150 #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
151 #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
152 #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
153 #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
154 #define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
155 #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
156 #define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
157 #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
158 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
159 #define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
160 #define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
161 #define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
162 #define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
163 #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
164 #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
165 #define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
166 #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
167 #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
168 #define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
169 #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
170 #define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
171 #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
172 #define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
174 /* Bits in EN0_ISR - Interrupt status register */
175 #define ENISR_RX 0x01 /* Receiver, no error */
176 #define ENISR_TX 0x02 /* Transmitter, no error */
177 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
178 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
179 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
180 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
181 #define ENISR_RDC 0x40 /* remote dma complete */
182 #define ENISR_RESET 0x80 /* Reset completed */
183 #define ENISR_ALL 0x3f /* Interrupts we will enable */
185 /* Bits in EN0_DCFG - Data config register */
186 #define ENDCFG_WTS 0x01 /* word transfer mode selection */
187 #define ENDCFG_BOS 0x02 /* byte order selection */
189 /* Page 1 register offsets. */
190 #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
191 #define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
192 #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
193 #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
194 #define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
196 /* Bits in received packet status byte and EN0_RSR*/
197 #define ENRSR_RXOK 0x01 /* Received a good packet */
198 #define ENRSR_CRC 0x02 /* CRC error */
199 #define ENRSR_FAE 0x04 /* frame alignment error */
200 #define ENRSR_FO 0x08 /* FIFO overrun */
201 #define ENRSR_MPA 0x10 /* missed pkt */
202 #define ENRSR_PHY 0x20 /* physical/multicast address */
203 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
204 #define ENRSR_DEF 0x80 /* deferring */
206 /* Transmitted packet status, EN0_TSR. */
207 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
208 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
209 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
210 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
211 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
212 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
213 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
214 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
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