projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / atl1e / atl1e_main.c
1 /*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include "atl1e.h"
23
24 #define DRV_VERSION "1.0.0.7-NAPI"
25
26 char atl1e_driver_name[] = "ATL1E";
27 char atl1e_driver_version[] = DRV_VERSION;
28 #define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
29 /*
30 * atl1e_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38 static DEFINE_PCI_DEVICE_TABLE(atl1e_pci_tbl) = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
40 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, 0x1066)},
41 /* required last entry */
42 { 0 }
43 };
44 MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
45
46 MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
47 MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
48 MODULE_LICENSE("GPL");
49 MODULE_VERSION(DRV_VERSION);
50
51 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
52
53 static const u16
54 atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
55 {
56 {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
57 {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
58 {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
59 {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
60 };
61
62 static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
63 {
64 REG_RXF0_BASE_ADDR_HI,
65 REG_RXF1_BASE_ADDR_HI,
66 REG_RXF2_BASE_ADDR_HI,
67 REG_RXF3_BASE_ADDR_HI
68 };
69
70 static const u16
71 atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
72 {
73 {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
74 {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
75 {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
76 {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
77 };
78
79 static const u16
80 atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
81 {
82 {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
83 {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
84 {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
85 {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
86 };
87
88 static const u16 atl1e_pay_load_size[] = {
89 128, 256, 512, 1024, 2048, 4096,
90 };
91
92 /*
93 * atl1e_irq_enable - Enable default interrupt generation settings
94 * @adapter: board private structure
95 */
96 static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
97 {
98 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
99 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
100 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
101 AT_WRITE_FLUSH(&adapter->hw);
102 }
103 }
104
105 /*
106 * atl1e_irq_disable - Mask off interrupt generation on the NIC
107 * @adapter: board private structure
108 */
109 static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
110 {
111 atomic_inc(&adapter->irq_sem);
112 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
113 AT_WRITE_FLUSH(&adapter->hw);
114 synchronize_irq(adapter->pdev->irq);
115 }
116
117 /*
118 * atl1e_irq_reset - reset interrupt confiure on the NIC
119 * @adapter: board private structure
120 */
121 static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
122 {
123 atomic_set(&adapter->irq_sem, 0);
124 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
125 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
126 AT_WRITE_FLUSH(&adapter->hw);
127 }
128
129 /*
130 * atl1e_phy_config - Timer Call-back
131 * @data: pointer to netdev cast into an unsigned long
132 */
133 static void atl1e_phy_config(unsigned long data)
134 {
135 struct atl1e_adapter *adapter = (struct atl1e_adapter *) data;
136 struct atl1e_hw *hw = &adapter->hw;
137 unsigned long flags;
138
139 spin_lock_irqsave(&adapter->mdio_lock, flags);
140 atl1e_restart_autoneg(hw);
141 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
142 }
143
144 void atl1e_reinit_locked(struct atl1e_adapter *adapter)
145 {
146
147 WARN_ON(in_interrupt());
148 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
149 msleep(1);
150 atl1e_down(adapter);
151 atl1e_up(adapter);
152 clear_bit(__AT_RESETTING, &adapter->flags);
153 }
154
155 static void atl1e_reset_task(struct work_struct *work)
156 {
157 struct atl1e_adapter *adapter;
158 adapter = container_of(work, struct atl1e_adapter, reset_task);
159
160 atl1e_reinit_locked(adapter);
161 }
162
163 static int atl1e_check_link(struct atl1e_adapter *adapter)
164 {
165 struct atl1e_hw *hw = &adapter->hw;
166 struct net_device *netdev = adapter->netdev;
167 int err = 0;
168 u16 speed, duplex, phy_data;
169
170 /* MII_BMSR must read twice */
171 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
173 if ((phy_data & BMSR_LSTATUS) == 0) {
174 /* link down */
175 if (netif_carrier_ok(netdev)) { /* old link state: Up */
176 u32 value;
177 /* disable rx */
178 value = AT_READ_REG(hw, REG_MAC_CTRL);
179 value &= ~MAC_CTRL_RX_EN;
180 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
181 adapter->link_speed = SPEED_0;
182 netif_carrier_off(netdev);
183 netif_stop_queue(netdev);
184 }
185 } else {
186 /* Link Up */
187 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
188 if (unlikely(err))
189 return err;
190
191 /* link result is our setting */
192 if (adapter->link_speed != speed ||
193 adapter->link_duplex != duplex) {
194 adapter->link_speed = speed;
195 adapter->link_duplex = duplex;
196 atl1e_setup_mac_ctrl(adapter);
197 netdev_info(netdev,
198 "NIC Link is Up <%d Mbps %s Duplex>\n",
199 adapter->link_speed,
200 adapter->link_duplex == FULL_DUPLEX ?
201 "Full" : "Half");
202 }
203
204 if (!netif_carrier_ok(netdev)) {
205 /* Link down -> Up */
206 netif_carrier_on(netdev);
207 netif_wake_queue(netdev);
208 }
209 }
210 return 0;
211 }
212
213 /*
214 * atl1e_link_chg_task - deal with link change event Out of interrupt context
215 * @netdev: network interface device structure
216 */
217 static void atl1e_link_chg_task(struct work_struct *work)
218 {
219 struct atl1e_adapter *adapter;
220 unsigned long flags;
221
222 adapter = container_of(work, struct atl1e_adapter, link_chg_task);
223 spin_lock_irqsave(&adapter->mdio_lock, flags);
224 atl1e_check_link(adapter);
225 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
226 }
227
228 static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
229 {
230 struct net_device *netdev = adapter->netdev;
231 u16 phy_data = 0;
232 u16 link_up = 0;
233
234 spin_lock(&adapter->mdio_lock);
235 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
236 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
237 spin_unlock(&adapter->mdio_lock);
238 link_up = phy_data & BMSR_LSTATUS;
239 /* notify upper layer link down ASAP */
240 if (!link_up) {
241 if (netif_carrier_ok(netdev)) {
242 /* old link state: Up */
243 netdev_info(netdev, "NIC Link is Down\n");
244 adapter->link_speed = SPEED_0;
245 netif_stop_queue(netdev);
246 }
247 }
248 schedule_work(&adapter->link_chg_task);
249 }
250
251 static void atl1e_del_timer(struct atl1e_adapter *adapter)
252 {
253 del_timer_sync(&adapter->phy_config_timer);
254 }
255
256 static void atl1e_cancel_work(struct atl1e_adapter *adapter)
257 {
258 cancel_work_sync(&adapter->reset_task);
259 cancel_work_sync(&adapter->link_chg_task);
260 }
261
262 /*
263 * atl1e_tx_timeout - Respond to a Tx Hang
264 * @netdev: network interface device structure
265 */
266 static void atl1e_tx_timeout(struct net_device *netdev)
267 {
268 struct atl1e_adapter *adapter = netdev_priv(netdev);
269
270 /* Do the reset outside of interrupt context */
271 schedule_work(&adapter->reset_task);
272 }
273
274 /*
275 * atl1e_set_multi - Multicast and Promiscuous mode set
276 * @netdev: network interface device structure
277 *
278 * The set_multi entry point is called whenever the multicast address
279 * list or the network interface flags are updated. This routine is
280 * responsible for configuring the hardware for proper multicast,
281 * promiscuous mode, and all-multi behavior.
282 */
283 static void atl1e_set_multi(struct net_device *netdev)
284 {
285 struct atl1e_adapter *adapter = netdev_priv(netdev);
286 struct atl1e_hw *hw = &adapter->hw;
287 struct netdev_hw_addr *ha;
288 u32 mac_ctrl_data = 0;
289 u32 hash_value;
290
291 /* Check for Promiscuous and All Multicast modes */
292 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
293
294 if (netdev->flags & IFF_PROMISC) {
295 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
296 } else if (netdev->flags & IFF_ALLMULTI) {
297 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
298 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
299 } else {
300 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
301 }
302
303 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
304
305 /* clear the old settings from the multicast hash table */
306 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
307 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
308
309 /* comoute mc addresses' hash value ,and put it into hash table */
310 netdev_for_each_mc_addr(ha, netdev) {
311 hash_value = atl1e_hash_mc_addr(hw, ha->addr);
312 atl1e_hash_set(hw, hash_value);
313 }
314 }
315
316 static void atl1e_vlan_rx_register(struct net_device *netdev,
317 struct vlan_group *grp)
318 {
319 struct atl1e_adapter *adapter = netdev_priv(netdev);
320 u32 mac_ctrl_data = 0;
321
322 netdev_dbg(adapter->netdev, "%s\n", __func__);
323
324 atl1e_irq_disable(adapter);
325
326 adapter->vlgrp = grp;
327 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
328
329 if (grp) {
330 /* enable VLAN tag insert/strip */
331 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
332 } else {
333 /* disable VLAN tag insert/strip */
334 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
335 }
336
337 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
338 atl1e_irq_enable(adapter);
339 }
340
341 static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
342 {
343 netdev_dbg(adapter->netdev, "%s\n", __func__);
344 atl1e_vlan_rx_register(adapter->netdev, adapter->vlgrp);
345 }
346 /*
347 * atl1e_set_mac - Change the Ethernet Address of the NIC
348 * @netdev: network interface device structure
349 * @p: pointer to an address structure
350 *
351 * Returns 0 on success, negative on failure
352 */
353 static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
354 {
355 struct atl1e_adapter *adapter = netdev_priv(netdev);
356 struct sockaddr *addr = p;
357
358 if (!is_valid_ether_addr(addr->sa_data))
359 return -EADDRNOTAVAIL;
360
361 if (netif_running(netdev))
362 return -EBUSY;
363
364 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
365 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
366
367 atl1e_hw_set_mac_addr(&adapter->hw);
368
369 return 0;
370 }
371
372 /*
373 * atl1e_change_mtu - Change the Maximum Transfer Unit
374 * @netdev: network interface device structure
375 * @new_mtu: new value for maximum frame size
376 *
377 * Returns 0 on success, negative on failure
378 */
379 static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
380 {
381 struct atl1e_adapter *adapter = netdev_priv(netdev);
382 int old_mtu = netdev->mtu;
383 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
384
385 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
386 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
387 netdev_warn(adapter->netdev, "invalid MTU setting\n");
388 return -EINVAL;
389 }
390 /* set MTU */
391 if (old_mtu != new_mtu && netif_running(netdev)) {
392 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
393 msleep(1);
394 netdev->mtu = new_mtu;
395 adapter->hw.max_frame_size = new_mtu;
396 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
397 atl1e_down(adapter);
398 atl1e_up(adapter);
399 clear_bit(__AT_RESETTING, &adapter->flags);
400 }
401 return 0;
402 }
403
404 /*
405 * caller should hold mdio_lock
406 */
407 static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
408 {
409 struct atl1e_adapter *adapter = netdev_priv(netdev);
410 u16 result;
411
412 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
413 return result;
414 }
415
416 static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
417 int reg_num, int val)
418 {
419 struct atl1e_adapter *adapter = netdev_priv(netdev);
420
421 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
422 }
423
424 /*
425 * atl1e_mii_ioctl -
426 * @netdev:
427 * @ifreq:
428 * @cmd:
429 */
430 static int atl1e_mii_ioctl(struct net_device *netdev,
431 struct ifreq *ifr, int cmd)
432 {
433 struct atl1e_adapter *adapter = netdev_priv(netdev);
434 struct mii_ioctl_data *data = if_mii(ifr);
435 unsigned long flags;
436 int retval = 0;
437
438 if (!netif_running(netdev))
439 return -EINVAL;
440
441 spin_lock_irqsave(&adapter->mdio_lock, flags);
442 switch (cmd) {
443 case SIOCGMIIPHY:
444 data->phy_id = 0;
445 break;
446
447 case SIOCGMIIREG:
448 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
449 &data->val_out)) {
450 retval = -EIO;
451 goto out;
452 }
453 break;
454
455 case SIOCSMIIREG:
456 if (data->reg_num & ~(0x1F)) {
457 retval = -EFAULT;
458 goto out;
459 }
460
461 netdev_dbg(adapter->netdev, "<atl1e_mii_ioctl> write %x %x\n",
462 data->reg_num, data->val_in);
463 if (atl1e_write_phy_reg(&adapter->hw,
464 data->reg_num, data->val_in)) {
465 retval = -EIO;
466 goto out;
467 }
468 break;
469
470 default:
471 retval = -EOPNOTSUPP;
472 break;
473 }
474 out:
475 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
476 return retval;
477
478 }
479
480 /*
481 * atl1e_ioctl -
482 * @netdev:
483 * @ifreq:
484 * @cmd:
485 */
486 static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
487 {
488 switch (cmd) {
489 case SIOCGMIIPHY:
490 case SIOCGMIIREG:
491 case SIOCSMIIREG:
492 return atl1e_mii_ioctl(netdev, ifr, cmd);
493 default:
494 return -EOPNOTSUPP;
495 }
496 }
497
498 static void atl1e_setup_pcicmd(struct pci_dev *pdev)
499 {
500 u16 cmd;
501
502 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
503 cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
504 cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
505 pci_write_config_word(pdev, PCI_COMMAND, cmd);
506
507 /*
508 * some motherboards BIOS(PXE/EFI) driver may set PME
509 * while they transfer control to OS (Windows/Linux)
510 * so we should clear this bit before NIC work normally
511 */
512 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
513 msleep(1);
514 }
515
516 /*
517 * atl1e_alloc_queues - Allocate memory for all rings
518 * @adapter: board private structure to initialize
519 *
520 */
521 static int __devinit atl1e_alloc_queues(struct atl1e_adapter *adapter)
522 {
523 return 0;
524 }
525
526 /*
527 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
528 * @adapter: board private structure to initialize
529 *
530 * atl1e_sw_init initializes the Adapter private data structure.
531 * Fields are initialized based on PCI device information and
532 * OS network device settings (MTU size).
533 */
534 static int __devinit atl1e_sw_init(struct atl1e_adapter *adapter)
535 {
536 struct atl1e_hw *hw = &adapter->hw;
537 struct pci_dev *pdev = adapter->pdev;
538 u32 phy_status_data = 0;
539
540 adapter->wol = 0;
541 adapter->link_speed = SPEED_0; /* hardware init */
542 adapter->link_duplex = FULL_DUPLEX;
543 adapter->num_rx_queues = 1;
544
545 /* PCI config space info */
546 hw->vendor_id = pdev->vendor;
547 hw->device_id = pdev->device;
548 hw->subsystem_vendor_id = pdev->subsystem_vendor;
549 hw->subsystem_id = pdev->subsystem_device;
550
551 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
552 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
553
554 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
555 /* nic type */
556 if (hw->revision_id >= 0xF0) {
557 hw->nic_type = athr_l2e_revB;
558 } else {
559 if (phy_status_data & PHY_STATUS_100M)
560 hw->nic_type = athr_l1e;
561 else
562 hw->nic_type = athr_l2e_revA;
563 }
564
565 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
566
567 if (phy_status_data & PHY_STATUS_EMI_CA)
568 hw->emi_ca = true;
569 else
570 hw->emi_ca = false;
571
572 hw->phy_configured = false;
573 hw->preamble_len = 7;
574 hw->max_frame_size = adapter->netdev->mtu;
575 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
576 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
577
578 hw->rrs_type = atl1e_rrs_disable;
579 hw->indirect_tab = 0;
580 hw->base_cpu = 0;
581
582 /* need confirm */
583
584 hw->ict = 50000; /* 100ms */
585 hw->smb_timer = 200000; /* 200ms */
586 hw->tpd_burst = 5;
587 hw->rrd_thresh = 1;
588 hw->tpd_thresh = adapter->tx_ring.count / 2;
589 hw->rx_count_down = 4; /* 2us resolution */
590 hw->tx_count_down = hw->imt * 4 / 3;
591 hw->dmar_block = atl1e_dma_req_1024;
592 hw->dmaw_block = atl1e_dma_req_1024;
593 hw->dmar_dly_cnt = 15;
594 hw->dmaw_dly_cnt = 4;
595
596 if (atl1e_alloc_queues(adapter)) {
597 netdev_err(adapter->netdev, "Unable to allocate memory for queues\n");
598 return -ENOMEM;
599 }
600
601 atomic_set(&adapter->irq_sem, 1);
602 spin_lock_init(&adapter->mdio_lock);
603 spin_lock_init(&adapter->tx_lock);
604
605 set_bit(__AT_DOWN, &adapter->flags);
606
607 return 0;
608 }
609
610 /*
611 * atl1e_clean_tx_ring - Free Tx-skb
612 * @adapter: board private structure
613 */
614 static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
615 {
616 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
617 &adapter->tx_ring;
618 struct atl1e_tx_buffer *tx_buffer = NULL;
619 struct pci_dev *pdev = adapter->pdev;
620 u16 index, ring_count;
621
622 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
623 return;
624
625 ring_count = tx_ring->count;
626 /* first unmmap dma */
627 for (index = 0; index < ring_count; index++) {
628 tx_buffer = &tx_ring->tx_buffer[index];
629 if (tx_buffer->dma) {
630 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
631 pci_unmap_single(pdev, tx_buffer->dma,
632 tx_buffer->length, PCI_DMA_TODEVICE);
633 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
634 pci_unmap_page(pdev, tx_buffer->dma,
635 tx_buffer->length, PCI_DMA_TODEVICE);
636 tx_buffer->dma = 0;
637 }
638 }
639 /* second free skb */
640 for (index = 0; index < ring_count; index++) {
641 tx_buffer = &tx_ring->tx_buffer[index];
642 if (tx_buffer->skb) {
643 dev_kfree_skb_any(tx_buffer->skb);
644 tx_buffer->skb = NULL;
645 }
646 }
647 /* Zero out Tx-buffers */
648 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
649 ring_count);
650 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
651 ring_count);
652 }
653
654 /*
655 * atl1e_clean_rx_ring - Free rx-reservation skbs
656 * @adapter: board private structure
657 */
658 static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
659 {
660 struct atl1e_rx_ring *rx_ring =
661 (struct atl1e_rx_ring *)&adapter->rx_ring;
662 struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
663 u16 i, j;
664
665
666 if (adapter->ring_vir_addr == NULL)
667 return;
668 /* Zero out the descriptor ring */
669 for (i = 0; i < adapter->num_rx_queues; i++) {
670 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
671 if (rx_page_desc[i].rx_page[j].addr != NULL) {
672 memset(rx_page_desc[i].rx_page[j].addr, 0,
673 rx_ring->real_page_size);
674 }
675 }
676 }
677 }
678
679 static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
680 {
681 *ring_size = ((u32)(adapter->tx_ring.count *
682 sizeof(struct atl1e_tpd_desc) + 7
683 /* tx ring, qword align */
684 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
685 adapter->num_rx_queues + 31
686 /* rx ring, 32 bytes align */
687 + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
688 sizeof(u32) + 3));
689 /* tx, rx cmd, dword align */
690 }
691
692 static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
693 {
694 struct atl1e_tx_ring *tx_ring = NULL;
695 struct atl1e_rx_ring *rx_ring = NULL;
696
697 tx_ring = &adapter->tx_ring;
698 rx_ring = &adapter->rx_ring;
699
700 rx_ring->real_page_size = adapter->rx_ring.page_size
701 + adapter->hw.max_frame_size
702 + ETH_HLEN + VLAN_HLEN
703 + ETH_FCS_LEN;
704 rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
705 atl1e_cal_ring_size(adapter, &adapter->ring_size);
706
707 adapter->ring_vir_addr = NULL;
708 adapter->rx_ring.desc = NULL;
709 rwlock_init(&adapter->tx_ring.tx_lock);
710
711 return;
712 }
713
714 /*
715 * Read / Write Ptr Initialize:
716 */
717 static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
718 {
719 struct atl1e_tx_ring *tx_ring = NULL;
720 struct atl1e_rx_ring *rx_ring = NULL;
721 struct atl1e_rx_page_desc *rx_page_desc = NULL;
722 int i, j;
723
724 tx_ring = &adapter->tx_ring;
725 rx_ring = &adapter->rx_ring;
726 rx_page_desc = rx_ring->rx_page_desc;
727
728 tx_ring->next_to_use = 0;
729 atomic_set(&tx_ring->next_to_clean, 0);
730
731 for (i = 0; i < adapter->num_rx_queues; i++) {
732 rx_page_desc[i].rx_using = 0;
733 rx_page_desc[i].rx_nxseq = 0;
734 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
735 *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
736 rx_page_desc[i].rx_page[j].read_offset = 0;
737 }
738 }
739 }
740
741 /*
742 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
743 * @adapter: board private structure
744 *
745 * Free all transmit software resources
746 */
747 static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
748 {
749 struct pci_dev *pdev = adapter->pdev;
750
751 atl1e_clean_tx_ring(adapter);
752 atl1e_clean_rx_ring(adapter);
753
754 if (adapter->ring_vir_addr) {
755 pci_free_consistent(pdev, adapter->ring_size,
756 adapter->ring_vir_addr, adapter->ring_dma);
757 adapter->ring_vir_addr = NULL;
758 }
759
760 if (adapter->tx_ring.tx_buffer) {
761 kfree(adapter->tx_ring.tx_buffer);
762 adapter->tx_ring.tx_buffer = NULL;
763 }
764 }
765
766 /*
767 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
768 * @adapter: board private structure
769 *
770 * Return 0 on success, negative on failure
771 */
772 static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
773 {
774 struct pci_dev *pdev = adapter->pdev;
775 struct atl1e_tx_ring *tx_ring;
776 struct atl1e_rx_ring *rx_ring;
777 struct atl1e_rx_page_desc *rx_page_desc;
778 int size, i, j;
779 u32 offset = 0;
780 int err = 0;
781
782 if (adapter->ring_vir_addr != NULL)
783 return 0; /* alloced already */
784
785 tx_ring = &adapter->tx_ring;
786 rx_ring = &adapter->rx_ring;
787
788 /* real ring DMA buffer */
789
790 size = adapter->ring_size;
791 adapter->ring_vir_addr = pci_alloc_consistent(pdev,
792 adapter->ring_size, &adapter->ring_dma);
793
794 if (adapter->ring_vir_addr == NULL) {
795 netdev_err(adapter->netdev,
796 "pci_alloc_consistent failed, size = D%d\n", size);
797 return -ENOMEM;
798 }
799
800 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
801
802 rx_page_desc = rx_ring->rx_page_desc;
803
804 /* Init TPD Ring */
805 tx_ring->dma = roundup(adapter->ring_dma, 8);
806 offset = tx_ring->dma - adapter->ring_dma;
807 tx_ring->desc = (struct atl1e_tpd_desc *)
808 (adapter->ring_vir_addr + offset);
809 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
810 tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
811 if (tx_ring->tx_buffer == NULL) {
812 netdev_err(adapter->netdev, "kzalloc failed, size = D%d\n",
813 size);
814 err = -ENOMEM;
815 goto failed;
816 }
817
818 /* Init RXF-Pages */
819 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
820 offset = roundup(offset, 32);
821
822 for (i = 0; i < adapter->num_rx_queues; i++) {
823 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
824 rx_page_desc[i].rx_page[j].dma =
825 adapter->ring_dma + offset;
826 rx_page_desc[i].rx_page[j].addr =
827 adapter->ring_vir_addr + offset;
828 offset += rx_ring->real_page_size;
829 }
830 }
831
832 /* Init CMB dma address */
833 tx_ring->cmb_dma = adapter->ring_dma + offset;
834 tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset);
835 offset += sizeof(u32);
836
837 for (i = 0; i < adapter->num_rx_queues; i++) {
838 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
839 rx_page_desc[i].rx_page[j].write_offset_dma =
840 adapter->ring_dma + offset;
841 rx_page_desc[i].rx_page[j].write_offset_addr =
842 adapter->ring_vir_addr + offset;
843 offset += sizeof(u32);
844 }
845 }
846
847 if (unlikely(offset > adapter->ring_size)) {
848 netdev_err(adapter->netdev, "offset(%d) > ring size(%d) !!\n",
849 offset, adapter->ring_size);
850 err = -1;
851 goto failed;
852 }
853
854 return 0;
855 failed:
856 if (adapter->ring_vir_addr != NULL) {
857 pci_free_consistent(pdev, adapter->ring_size,
858 adapter->ring_vir_addr, adapter->ring_dma);
859 adapter->ring_vir_addr = NULL;
860 }
861 return err;
862 }
863
864 static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
865 {
866
867 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
868 struct atl1e_rx_ring *rx_ring =
869 (struct atl1e_rx_ring *)&adapter->rx_ring;
870 struct atl1e_tx_ring *tx_ring =
871 (struct atl1e_tx_ring *)&adapter->tx_ring;
872 struct atl1e_rx_page_desc *rx_page_desc = NULL;
873 int i, j;
874
875 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
876 (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
877 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
878 (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
879 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
880 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
881 (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
882
883 rx_page_desc = rx_ring->rx_page_desc;
884 /* RXF Page Physical address / Page Length */
885 for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
886 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
887 (u32)((adapter->ring_dma &
888 AT_DMA_HI_ADDR_MASK) >> 32));
889 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
890 u32 page_phy_addr;
891 u32 offset_phy_addr;
892
893 page_phy_addr = rx_page_desc[i].rx_page[j].dma;
894 offset_phy_addr =
895 rx_page_desc[i].rx_page[j].write_offset_dma;
896
897 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
898 page_phy_addr & AT_DMA_LO_ADDR_MASK);
899 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
900 offset_phy_addr & AT_DMA_LO_ADDR_MASK);
901 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
902 }
903 }
904 /* Page Length */
905 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
906 /* Load all of base address above */
907 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
908
909 return;
910 }
911
912 static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
913 {
914 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
915 u32 dev_ctrl_data = 0;
916 u32 max_pay_load = 0;
917 u32 jumbo_thresh = 0;
918 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
919
920 /* configure TXQ param */
921 if (hw->nic_type != athr_l2e_revB) {
922 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
923 if (hw->max_frame_size <= 1500) {
924 jumbo_thresh = hw->max_frame_size + extra_size;
925 } else if (hw->max_frame_size < 6*1024) {
926 jumbo_thresh =
927 (hw->max_frame_size + extra_size) * 2 / 3;
928 } else {
929 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
930 }
931 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
932 }
933
934 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
935
936 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
937 DEVICE_CTRL_MAX_PAYLOAD_MASK;
938
939 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
940
941 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
942 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
943 hw->dmar_block = min(max_pay_load, hw->dmar_block);
944
945 if (hw->nic_type != athr_l2e_revB)
946 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
947 atl1e_pay_load_size[hw->dmar_block]);
948 /* enable TXQ */
949 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
950 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
951 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
952 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
953 return;
954 }
955
956 static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
957 {
958 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
959 u32 rxf_len = 0;
960 u32 rxf_low = 0;
961 u32 rxf_high = 0;
962 u32 rxf_thresh_data = 0;
963 u32 rxq_ctrl_data = 0;
964
965 if (hw->nic_type != athr_l2e_revB) {
966 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
967 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
968 RXQ_JMBOSZ_TH_SHIFT |
969 (1 & RXQ_JMBO_LKAH_MASK) <<
970 RXQ_JMBO_LKAH_SHIFT));
971
972 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
973 rxf_high = rxf_len * 4 / 5;
974 rxf_low = rxf_len / 5;
975 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
976 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
977 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
978 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
979
980 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
981 }
982
983 /* RRS */
984 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
985 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
986
987 if (hw->rrs_type & atl1e_rrs_ipv4)
988 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
989
990 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
991 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
992
993 if (hw->rrs_type & atl1e_rrs_ipv6)
994 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
995
996 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
997 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
998
999 if (hw->rrs_type != atl1e_rrs_disable)
1000 rxq_ctrl_data |=
1001 (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
1002
1003 rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
1004 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1005
1006 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1007 return;
1008 }
1009
1010 static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
1011 {
1012 struct atl1e_hw *hw = &adapter->hw;
1013 u32 dma_ctrl_data = 0;
1014
1015 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
1016 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1017 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1018 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1019 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1020 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
1021 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1022 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1023 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1024 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1025
1026 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1027 return;
1028 }
1029
1030 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
1031 {
1032 u32 value;
1033 struct atl1e_hw *hw = &adapter->hw;
1034 struct net_device *netdev = adapter->netdev;
1035
1036 /* Config MAC CTRL Register */
1037 value = MAC_CTRL_TX_EN |
1038 MAC_CTRL_RX_EN ;
1039
1040 if (FULL_DUPLEX == adapter->link_duplex)
1041 value |= MAC_CTRL_DUPLX;
1042
1043 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
1044 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1045 MAC_CTRL_SPEED_SHIFT);
1046 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1047
1048 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1049 value |= (((u32)adapter->hw.preamble_len &
1050 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1051
1052 if (adapter->vlgrp)
1053 value |= MAC_CTRL_RMV_VLAN;
1054
1055 value |= MAC_CTRL_BC_EN;
1056 if (netdev->flags & IFF_PROMISC)
1057 value |= MAC_CTRL_PROMIS_EN;
1058 if (netdev->flags & IFF_ALLMULTI)
1059 value |= MAC_CTRL_MC_ALL_EN;
1060
1061 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1062 }
1063
1064 /*
1065 * atl1e_configure - Configure Transmit&Receive Unit after Reset
1066 * @adapter: board private structure
1067 *
1068 * Configure the Tx /Rx unit of the MAC after a reset.
1069 */
1070 static int atl1e_configure(struct atl1e_adapter *adapter)
1071 {
1072 struct atl1e_hw *hw = &adapter->hw;
1073
1074 u32 intr_status_data = 0;
1075
1076 /* clear interrupt status */
1077 AT_WRITE_REG(hw, REG_ISR, ~0);
1078
1079 /* 1. set MAC Address */
1080 atl1e_hw_set_mac_addr(hw);
1081
1082 /* 2. Init the Multicast HASH table done by set_muti */
1083
1084 /* 3. Clear any WOL status */
1085 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1086
1087 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
1088 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
1089 * High 32bits memory */
1090 atl1e_configure_des_ring(adapter);
1091
1092 /* 5. set Interrupt Moderator Timer */
1093 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1094 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1095 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1096 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
1097
1098 /* 6. rx/tx threshold to trig interrupt */
1099 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1100 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1101 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1102 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1103
1104 /* 7. set Interrupt Clear Timer */
1105 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1106
1107 /* 8. set MTU */
1108 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1109 VLAN_HLEN + ETH_FCS_LEN);
1110
1111 /* 9. config TXQ early tx threshold */
1112 atl1e_configure_tx(adapter);
1113
1114 /* 10. config RXQ */
1115 atl1e_configure_rx(adapter);
1116
1117 /* 11. config DMA Engine */
1118 atl1e_configure_dma(adapter);
1119
1120 /* 12. smb timer to trig interrupt */
1121 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1122
1123 intr_status_data = AT_READ_REG(hw, REG_ISR);
1124 if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
1125 netdev_err(adapter->netdev,
1126 "atl1e_configure failed, PCIE phy link down\n");
1127 return -1;
1128 }
1129
1130 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1131 return 0;
1132 }
1133
1134 /*
1135 * atl1e_get_stats - Get System Network Statistics
1136 * @netdev: network interface device structure
1137 *
1138 * Returns the address of the device statistics structure.
1139 * The statistics are actually updated from the timer callback.
1140 */
1141 static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
1142 {
1143 struct atl1e_adapter *adapter = netdev_priv(netdev);
1144 struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
1145 struct net_device_stats *net_stats = &netdev->stats;
1146
1147 net_stats->rx_packets = hw_stats->rx_ok;
1148 net_stats->tx_packets = hw_stats->tx_ok;
1149 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1150 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1151 net_stats->multicast = hw_stats->rx_mcast;
1152 net_stats->collisions = hw_stats->tx_1_col +
1153 hw_stats->tx_2_col * 2 +
1154 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1155
1156 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1157 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1158 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1159 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1160 net_stats->rx_length_errors = hw_stats->rx_len_err;
1161 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1162 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1163 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1164
1165 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1166
1167 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1168 hw_stats->tx_underrun + hw_stats->tx_trunc;
1169 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1170 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1171 net_stats->tx_window_errors = hw_stats->tx_late_col;
1172
1173 return net_stats;
1174 }
1175
1176 static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
1177 {
1178 u16 hw_reg_addr = 0;
1179 unsigned long *stats_item = NULL;
1180
1181 /* update rx status */
1182 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1183 stats_item = &adapter->hw_stats.rx_ok;
1184 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1185 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1186 stats_item++;
1187 hw_reg_addr += 4;
1188 }
1189 /* update tx status */
1190 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1191 stats_item = &adapter->hw_stats.tx_ok;
1192 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1193 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1194 stats_item++;
1195 hw_reg_addr += 4;
1196 }
1197 }
1198
1199 static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
1200 {
1201 u16 phy_data;
1202
1203 spin_lock(&adapter->mdio_lock);
1204 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1205 spin_unlock(&adapter->mdio_lock);
1206 }
1207
1208 static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
1209 {
1210 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
1211 &adapter->tx_ring;
1212 struct atl1e_tx_buffer *tx_buffer = NULL;
1213 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1214 u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1215
1216 while (next_to_clean != hw_next_to_clean) {
1217 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
1218 if (tx_buffer->dma) {
1219 if (tx_buffer->flags & ATL1E_TX_PCIMAP_SINGLE)
1220 pci_unmap_single(adapter->pdev, tx_buffer->dma,
1221 tx_buffer->length, PCI_DMA_TODEVICE);
1222 else if (tx_buffer->flags & ATL1E_TX_PCIMAP_PAGE)
1223 pci_unmap_page(adapter->pdev, tx_buffer->dma,
1224 tx_buffer->length, PCI_DMA_TODEVICE);
1225 tx_buffer->dma = 0;
1226 }
1227
1228 if (tx_buffer->skb) {
1229 dev_kfree_skb_irq(tx_buffer->skb);
1230 tx_buffer->skb = NULL;
1231 }
1232
1233 if (++next_to_clean == tx_ring->count)
1234 next_to_clean = 0;
1235 }
1236
1237 atomic_set(&tx_ring->next_to_clean, next_to_clean);
1238
1239 if (netif_queue_stopped(adapter->netdev) &&
1240 netif_carrier_ok(adapter->netdev)) {
1241 netif_wake_queue(adapter->netdev);
1242 }
1243
1244 return true;
1245 }
1246
1247 /*
1248 * atl1e_intr - Interrupt Handler
1249 * @irq: interrupt number
1250 * @data: pointer to a network interface device structure
1251 * @pt_regs: CPU registers structure
1252 */
1253 static irqreturn_t atl1e_intr(int irq, void *data)
1254 {
1255 struct net_device *netdev = data;
1256 struct atl1e_adapter *adapter = netdev_priv(netdev);
1257 struct atl1e_hw *hw = &adapter->hw;
1258 int max_ints = AT_MAX_INT_WORK;
1259 int handled = IRQ_NONE;
1260 u32 status;
1261
1262 do {
1263 status = AT_READ_REG(hw, REG_ISR);
1264 if ((status & IMR_NORMAL_MASK) == 0 ||
1265 (status & ISR_DIS_INT) != 0) {
1266 if (max_ints != AT_MAX_INT_WORK)
1267 handled = IRQ_HANDLED;
1268 break;
1269 }
1270 /* link event */
1271 if (status & ISR_GPHY)
1272 atl1e_clear_phy_int(adapter);
1273 /* Ack ISR */
1274 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1275
1276 handled = IRQ_HANDLED;
1277 /* check if PCIE PHY Link down */
1278 if (status & ISR_PHY_LINKDOWN) {
1279 netdev_err(adapter->netdev,
1280 "pcie phy linkdown %x\n", status);
1281 if (netif_running(adapter->netdev)) {
1282 /* reset MAC */
1283 atl1e_irq_reset(adapter);
1284 schedule_work(&adapter->reset_task);
1285 break;
1286 }
1287 }
1288
1289 /* check if DMA read/write error */
1290 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1291 netdev_err(adapter->netdev,
1292 "PCIE DMA RW error (status = 0x%x)\n",
1293 status);
1294 atl1e_irq_reset(adapter);
1295 schedule_work(&adapter->reset_task);
1296 break;
1297 }
1298
1299 if (status & ISR_SMB)
1300 atl1e_update_hw_stats(adapter);
1301
1302 /* link event */
1303 if (status & (ISR_GPHY | ISR_MANUAL)) {
1304 netdev->stats.tx_carrier_errors++;
1305 atl1e_link_chg_event(adapter);
1306 break;
1307 }
1308
1309 /* transmit event */
1310 if (status & ISR_TX_EVENT)
1311 atl1e_clean_tx_irq(adapter);
1312
1313 if (status & ISR_RX_EVENT) {
1314 /*
1315 * disable rx interrupts, without
1316 * the synchronize_irq bit
1317 */
1318 AT_WRITE_REG(hw, REG_IMR,
1319 IMR_NORMAL_MASK & ~ISR_RX_EVENT);
1320 AT_WRITE_FLUSH(hw);
1321 if (likely(napi_schedule_prep(
1322 &adapter->napi)))
1323 __napi_schedule(&adapter->napi);
1324 }
1325 } while (--max_ints > 0);
1326 /* re-enable Interrupt*/
1327 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1328
1329 return handled;
1330 }
1331
1332 static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
1333 struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
1334 {
1335 u8 *packet = (u8 *)(prrs + 1);
1336 struct iphdr *iph;
1337 u16 head_len = ETH_HLEN;
1338 u16 pkt_flags;
1339 u16 err_flags;
1340
1341 skb->ip_summed = CHECKSUM_NONE;
1342 pkt_flags = prrs->pkt_flag;
1343 err_flags = prrs->err_flag;
1344 if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
1345 ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
1346 if (pkt_flags & RRS_IS_IPV4) {
1347 if (pkt_flags & RRS_IS_802_3)
1348 head_len += 8;
1349 iph = (struct iphdr *) (packet + head_len);
1350 if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
1351 goto hw_xsum;
1352 }
1353 if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
1354 skb->ip_summed = CHECKSUM_UNNECESSARY;
1355 return;
1356 }
1357 }
1358
1359 hw_xsum :
1360 return;
1361 }
1362
1363 static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
1364 u8 que)
1365 {
1366 struct atl1e_rx_page_desc *rx_page_desc =
1367 (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
1368 u8 rx_using = rx_page_desc[que].rx_using;
1369
1370 return (struct atl1e_rx_page *)&(rx_page_desc[que].rx_page[rx_using]);
1371 }
1372
1373 static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
1374 int *work_done, int work_to_do)
1375 {
1376 struct net_device *netdev = adapter->netdev;
1377 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
1378 &adapter->rx_ring;
1379 struct atl1e_rx_page_desc *rx_page_desc =
1380 (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
1381 struct sk_buff *skb = NULL;
1382 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
1383 u32 packet_size, write_offset;
1384 struct atl1e_recv_ret_status *prrs;
1385
1386 write_offset = *(rx_page->write_offset_addr);
1387 if (likely(rx_page->read_offset < write_offset)) {
1388 do {
1389 if (*work_done >= work_to_do)
1390 break;
1391 (*work_done)++;
1392 /* get new packet's rrs */
1393 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
1394 rx_page->read_offset);
1395 /* check sequence number */
1396 if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
1397 netdev_err(netdev,
1398 "rx sequence number error (rx=%d) (expect=%d)\n",
1399 prrs->seq_num,
1400 rx_page_desc[que].rx_nxseq);
1401 rx_page_desc[que].rx_nxseq++;
1402 /* just for debug use */
1403 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1404 (((u32)prrs->seq_num) << 16) |
1405 rx_page_desc[que].rx_nxseq);
1406 goto fatal_err;
1407 }
1408 rx_page_desc[que].rx_nxseq++;
1409
1410 /* error packet */
1411 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
1412 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
1413 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
1414 RRS_ERR_TRUNC)) {
1415 /* hardware error, discard this packet*/
1416 netdev_err(netdev,
1417 "rx packet desc error %x\n",
1418 *((u32 *)prrs + 1));
1419 goto skip_pkt;
1420 }
1421 }
1422
1423 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1424 RRS_PKT_SIZE_MASK) - 4; /* CRC */
1425 skb = netdev_alloc_skb_ip_align(netdev, packet_size);
1426 if (skb == NULL) {
1427 netdev_warn(netdev,
1428 "Memory squeeze, deferring packet\n");
1429 goto skip_pkt;
1430 }
1431 memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
1432 skb_put(skb, packet_size);
1433 skb->protocol = eth_type_trans(skb, netdev);
1434 atl1e_rx_checksum(adapter, skb, prrs);
1435
1436 if (unlikely(adapter->vlgrp &&
1437 (prrs->pkt_flag & RRS_IS_VLAN_TAG))) {
1438 u16 vlan_tag = (prrs->vtag >> 4) |
1439 ((prrs->vtag & 7) << 13) |
1440 ((prrs->vtag & 8) << 9);
1441 netdev_dbg(netdev,
1442 "RXD VLAN TAG<RRD>=0x%04x\n",
1443 prrs->vtag);
1444 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
1445 vlan_tag);
1446 } else {
1447 netif_receive_skb(skb);
1448 }
1449
1450 skip_pkt:
1451 /* skip current packet whether it's ok or not. */
1452 rx_page->read_offset +=
1453 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1454 RRS_PKT_SIZE_MASK) +
1455 sizeof(struct atl1e_recv_ret_status) + 31) &
1456 0xFFFFFFE0);
1457
1458 if (rx_page->read_offset >= rx_ring->page_size) {
1459 /* mark this page clean */
1460 u16 reg_addr;
1461 u8 rx_using;
1462
1463 rx_page->read_offset =
1464 *(rx_page->write_offset_addr) = 0;
1465 rx_using = rx_page_desc[que].rx_using;
1466 reg_addr =
1467 atl1e_rx_page_vld_regs[que][rx_using];
1468 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1469 rx_page_desc[que].rx_using ^= 1;
1470 rx_page = atl1e_get_rx_page(adapter, que);
1471 }
1472 write_offset = *(rx_page->write_offset_addr);
1473 } while (rx_page->read_offset < write_offset);
1474 }
1475
1476 return;
1477
1478 fatal_err:
1479 if (!test_bit(__AT_DOWN, &adapter->flags))
1480 schedule_work(&adapter->reset_task);
1481 }
1482
1483 /*
1484 * atl1e_clean - NAPI Rx polling callback
1485 * @adapter: board private structure
1486 */
1487 static int atl1e_clean(struct napi_struct *napi, int budget)
1488 {
1489 struct atl1e_adapter *adapter =
1490 container_of(napi, struct atl1e_adapter, napi);
1491 u32 imr_data;
1492 int work_done = 0;
1493
1494 /* Keep link state information with original netdev */
1495 if (!netif_carrier_ok(adapter->netdev))
1496 goto quit_polling;
1497
1498 atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
1499
1500 /* If no Tx and not enough Rx work done, exit the polling mode */
1501 if (work_done < budget) {
1502 quit_polling:
1503 napi_complete(napi);
1504 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1505 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1506 /* test debug */
1507 if (test_bit(__AT_DOWN, &adapter->flags)) {
1508 atomic_dec(&adapter->irq_sem);
1509 netdev_err(adapter->netdev,
1510 "atl1e_clean is called when AT_DOWN\n");
1511 }
1512 /* reenable RX intr */
1513 /*atl1e_irq_enable(adapter); */
1514
1515 }
1516 return work_done;
1517 }
1518
1519 #ifdef CONFIG_NET_POLL_CONTROLLER
1520
1521 /*
1522 * Polling 'interrupt' - used by things like netconsole to send skbs
1523 * without having to re-enable interrupts. It's not called while
1524 * the interrupt routine is executing.
1525 */
1526 static void atl1e_netpoll(struct net_device *netdev)
1527 {
1528 struct atl1e_adapter *adapter = netdev_priv(netdev);
1529
1530 disable_irq(adapter->pdev->irq);
1531 atl1e_intr(adapter->pdev->irq, netdev);
1532 enable_irq(adapter->pdev->irq);
1533 }
1534 #endif
1535
1536 static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
1537 {
1538 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1539 u16 next_to_use = 0;
1540 u16 next_to_clean = 0;
1541
1542 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1543 next_to_use = tx_ring->next_to_use;
1544
1545 return (u16)(next_to_clean > next_to_use) ?
1546 (next_to_clean - next_to_use - 1) :
1547 (tx_ring->count + next_to_clean - next_to_use - 1);
1548 }
1549
1550 /*
1551 * get next usable tpd
1552 * Note: should call atl1e_tdp_avail to make sure
1553 * there is enough tpd to use
1554 */
1555 static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
1556 {
1557 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1558 u16 next_to_use = 0;
1559
1560 next_to_use = tx_ring->next_to_use;
1561 if (++tx_ring->next_to_use == tx_ring->count)
1562 tx_ring->next_to_use = 0;
1563
1564 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
1565 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
1566 }
1567
1568 static struct atl1e_tx_buffer *
1569 atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
1570 {
1571 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1572
1573 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
1574 }
1575
1576 /* Calculate the transmit packet descript needed*/
1577 static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
1578 {
1579 int i = 0;
1580 u16 tpd_req = 1;
1581 u16 fg_size = 0;
1582 u16 proto_hdr_len = 0;
1583
1584 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1585 fg_size = skb_shinfo(skb)->frags[i].size;
1586 tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
1587 }
1588
1589 if (skb_is_gso(skb)) {
1590 if (skb->protocol == htons(ETH_P_IP) ||
1591 (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
1592 proto_hdr_len = skb_transport_offset(skb) +
1593 tcp_hdrlen(skb);
1594 if (proto_hdr_len < skb_headlen(skb)) {
1595 tpd_req += ((skb_headlen(skb) - proto_hdr_len +
1596 MAX_TX_BUF_LEN - 1) >>
1597 MAX_TX_BUF_SHIFT);
1598 }
1599 }
1600
1601 }
1602 return tpd_req;
1603 }
1604
1605 static int atl1e_tso_csum(struct atl1e_adapter *adapter,
1606 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1607 {
1608 u8 hdr_len;
1609 u32 real_len;
1610 unsigned short offload_type;
1611 int err;
1612
1613 if (skb_is_gso(skb)) {
1614 if (skb_header_cloned(skb)) {
1615 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1616 if (unlikely(err))
1617 return -1;
1618 }
1619 offload_type = skb_shinfo(skb)->gso_type;
1620
1621 if (offload_type & SKB_GSO_TCPV4) {
1622 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1623 + ntohs(ip_hdr(skb)->tot_len));
1624
1625 if (real_len < skb->len)
1626 pskb_trim(skb, real_len);
1627
1628 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1629 if (unlikely(skb->len == hdr_len)) {
1630 /* only xsum need */
1631 netdev_warn(adapter->netdev,
1632 "IPV4 tso with zero data??\n");
1633 goto check_sum;
1634 } else {
1635 ip_hdr(skb)->check = 0;
1636 ip_hdr(skb)->tot_len = 0;
1637 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1638 ip_hdr(skb)->saddr,
1639 ip_hdr(skb)->daddr,
1640 0, IPPROTO_TCP, 0);
1641 tpd->word3 |= (ip_hdr(skb)->ihl &
1642 TDP_V4_IPHL_MASK) <<
1643 TPD_V4_IPHL_SHIFT;
1644 tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
1645 TPD_TCPHDRLEN_MASK) <<
1646 TPD_TCPHDRLEN_SHIFT;
1647 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1648 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1649 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1650 }
1651 return 0;
1652 }
1653 }
1654
1655 check_sum:
1656 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1657 u8 css, cso;
1658
1659 cso = skb_transport_offset(skb);
1660 if (unlikely(cso & 0x1)) {
1661 netdev_err(adapter->netdev,
1662 "payload offset should not ant event number\n");
1663 return -1;
1664 } else {
1665 css = cso + skb->csum_offset;
1666 tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
1667 TPD_PLOADOFFSET_SHIFT;
1668 tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
1669 TPD_CCSUMOFFSET_SHIFT;
1670 tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
1671 }
1672 }
1673
1674 return 0;
1675 }
1676
1677 static void atl1e_tx_map(struct atl1e_adapter *adapter,
1678 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1679 {
1680 struct atl1e_tpd_desc *use_tpd = NULL;
1681 struct atl1e_tx_buffer *tx_buffer = NULL;
1682 u16 buf_len = skb_headlen(skb);
1683 u16 map_len = 0;
1684 u16 mapped_len = 0;
1685 u16 hdr_len = 0;
1686 u16 nr_frags;
1687 u16 f;
1688 int segment;
1689
1690 nr_frags = skb_shinfo(skb)->nr_frags;
1691 segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
1692 if (segment) {
1693 /* TSO */
1694 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1695 use_tpd = tpd;
1696
1697 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1698 tx_buffer->length = map_len;
1699 tx_buffer->dma = pci_map_single(adapter->pdev,
1700 skb->data, hdr_len, PCI_DMA_TODEVICE);
1701 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1702 mapped_len += map_len;
1703 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1704 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1705 ((cpu_to_le32(tx_buffer->length) &
1706 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1707 }
1708
1709 while (mapped_len < buf_len) {
1710 /* mapped_len == 0, means we should use the first tpd,
1711 which is given by caller */
1712 if (mapped_len == 0) {
1713 use_tpd = tpd;
1714 } else {
1715 use_tpd = atl1e_get_tpd(adapter);
1716 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1717 }
1718 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1719 tx_buffer->skb = NULL;
1720
1721 tx_buffer->length = map_len =
1722 ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
1723 MAX_TX_BUF_LEN : (buf_len - mapped_len);
1724 tx_buffer->dma =
1725 pci_map_single(adapter->pdev, skb->data + mapped_len,
1726 map_len, PCI_DMA_TODEVICE);
1727 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_SINGLE);
1728 mapped_len += map_len;
1729 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1730 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1731 ((cpu_to_le32(tx_buffer->length) &
1732 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1733 }
1734
1735 for (f = 0; f < nr_frags; f++) {
1736 struct skb_frag_struct *frag;
1737 u16 i;
1738 u16 seg_num;
1739
1740 frag = &skb_shinfo(skb)->frags[f];
1741 buf_len = frag->size;
1742
1743 seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1744 for (i = 0; i < seg_num; i++) {
1745 use_tpd = atl1e_get_tpd(adapter);
1746 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1747
1748 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1749 BUG_ON(tx_buffer->skb);
1750
1751 tx_buffer->skb = NULL;
1752 tx_buffer->length =
1753 (buf_len > MAX_TX_BUF_LEN) ?
1754 MAX_TX_BUF_LEN : buf_len;
1755 buf_len -= tx_buffer->length;
1756
1757 tx_buffer->dma =
1758 pci_map_page(adapter->pdev, frag->page,
1759 frag->page_offset +
1760 (i * MAX_TX_BUF_LEN),
1761 tx_buffer->length,
1762 PCI_DMA_TODEVICE);
1763 ATL1E_SET_PCIMAP_TYPE(tx_buffer, ATL1E_TX_PCIMAP_PAGE);
1764 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1765 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1766 ((cpu_to_le32(tx_buffer->length) &
1767 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1768 }
1769 }
1770
1771 if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
1772 /* note this one is a tcp header */
1773 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
1774 /* The last tpd */
1775
1776 use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
1777 /* The last buffer info contain the skb address,
1778 so it will be free after unmap */
1779 tx_buffer->skb = skb;
1780 }
1781
1782 static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
1783 struct atl1e_tpd_desc *tpd)
1784 {
1785 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1786 /* Force memory writes to complete before letting h/w
1787 * know there are new descriptors to fetch. (Only
1788 * applicable for weak-ordered memory model archs,
1789 * such as IA-64). */
1790 wmb();
1791 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1792 }
1793
1794 static netdev_tx_t atl1e_xmit_frame(struct sk_buff *skb,
1795 struct net_device *netdev)
1796 {
1797 struct atl1e_adapter *adapter = netdev_priv(netdev);
1798 unsigned long flags;
1799 u16 tpd_req = 1;
1800 struct atl1e_tpd_desc *tpd;
1801
1802 if (test_bit(__AT_DOWN, &adapter->flags)) {
1803 dev_kfree_skb_any(skb);
1804 return NETDEV_TX_OK;
1805 }
1806
1807 if (unlikely(skb->len <= 0)) {
1808 dev_kfree_skb_any(skb);
1809 return NETDEV_TX_OK;
1810 }
1811 tpd_req = atl1e_cal_tdp_req(skb);
1812 if (!spin_trylock_irqsave(&adapter->tx_lock, flags))
1813 return NETDEV_TX_LOCKED;
1814
1815 if (atl1e_tpd_avail(adapter) < tpd_req) {
1816 /* no enough descriptor, just stop queue */
1817 netif_stop_queue(netdev);
1818 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1819 return NETDEV_TX_BUSY;
1820 }
1821
1822 tpd = atl1e_get_tpd(adapter);
1823
1824 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1825 u16 vlan_tag = vlan_tx_tag_get(skb);
1826 u16 atl1e_vlan_tag;
1827
1828 tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
1829 AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
1830 tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
1831 TPD_VLAN_SHIFT;
1832 }
1833
1834 if (skb->protocol == htons(ETH_P_8021Q))
1835 tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
1836
1837 if (skb_network_offset(skb) != ETH_HLEN)
1838 tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
1839
1840 /* do TSO and check sum */
1841 if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
1842 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1843 dev_kfree_skb_any(skb);
1844 return NETDEV_TX_OK;
1845 }
1846
1847 atl1e_tx_map(adapter, skb, tpd);
1848 atl1e_tx_queue(adapter, tpd_req, tpd);
1849
1850 netdev->trans_start = jiffies; /* NETIF_F_LLTX driver :( */
1851 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1852 return NETDEV_TX_OK;
1853 }
1854
1855 static void atl1e_free_irq(struct atl1e_adapter *adapter)
1856 {
1857 struct net_device *netdev = adapter->netdev;
1858
1859 free_irq(adapter->pdev->irq, netdev);
1860
1861 if (adapter->have_msi)
1862 pci_disable_msi(adapter->pdev);
1863 }
1864
1865 static int atl1e_request_irq(struct atl1e_adapter *adapter)
1866 {
1867 struct pci_dev *pdev = adapter->pdev;
1868 struct net_device *netdev = adapter->netdev;
1869 int flags = 0;
1870 int err = 0;
1871
1872 adapter->have_msi = true;
1873 err = pci_enable_msi(adapter->pdev);
1874 if (err) {
1875 netdev_dbg(adapter->netdev,
1876 "Unable to allocate MSI interrupt Error: %d\n", err);
1877 adapter->have_msi = false;
1878 } else
1879 netdev->irq = pdev->irq;
1880
1881
1882 if (!adapter->have_msi)
1883 flags |= IRQF_SHARED;
1884 err = request_irq(adapter->pdev->irq, atl1e_intr, flags,
1885 netdev->name, netdev);
1886 if (err) {
1887 netdev_dbg(adapter->netdev,
1888 "Unable to allocate interrupt Error: %d\n", err);
1889 if (adapter->have_msi)
1890 pci_disable_msi(adapter->pdev);
1891 return err;
1892 }
1893 netdev_dbg(adapter->netdev, "atl1e_request_irq OK\n");
1894 return err;
1895 }
1896
1897 int atl1e_up(struct atl1e_adapter *adapter)
1898 {
1899 struct net_device *netdev = adapter->netdev;
1900 int err = 0;
1901 u32 val;
1902
1903 /* hardware has been reset, we need to reload some things */
1904 err = atl1e_init_hw(&adapter->hw);
1905 if (err) {
1906 err = -EIO;
1907 return err;
1908 }
1909 atl1e_init_ring_ptrs(adapter);
1910 atl1e_set_multi(netdev);
1911 atl1e_restore_vlan(adapter);
1912
1913 if (atl1e_configure(adapter)) {
1914 err = -EIO;
1915 goto err_up;
1916 }
1917
1918 clear_bit(__AT_DOWN, &adapter->flags);
1919 napi_enable(&adapter->napi);
1920 atl1e_irq_enable(adapter);
1921 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1922 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1923 val | MASTER_CTRL_MANUAL_INT);
1924
1925 err_up:
1926 return err;
1927 }
1928
1929 void atl1e_down(struct atl1e_adapter *adapter)
1930 {
1931 struct net_device *netdev = adapter->netdev;
1932
1933 /* signal that we're down so the interrupt handler does not
1934 * reschedule our watchdog timer */
1935 set_bit(__AT_DOWN, &adapter->flags);
1936
1937 #ifdef NETIF_F_LLTX
1938 netif_stop_queue(netdev);
1939 #else
1940 netif_tx_disable(netdev);
1941 #endif
1942
1943 /* reset MAC to disable all RX/TX */
1944 atl1e_reset_hw(&adapter->hw);
1945 msleep(1);
1946
1947 napi_disable(&adapter->napi);
1948 atl1e_del_timer(adapter);
1949 atl1e_irq_disable(adapter);
1950
1951 netif_carrier_off(netdev);
1952 adapter->link_speed = SPEED_0;
1953 adapter->link_duplex = -1;
1954 atl1e_clean_tx_ring(adapter);
1955 atl1e_clean_rx_ring(adapter);
1956 }
1957
1958 /*
1959 * atl1e_open - Called when a network interface is made active
1960 * @netdev: network interface device structure
1961 *
1962 * Returns 0 on success, negative value on failure
1963 *
1964 * The open entry point is called when a network interface is made
1965 * active by the system (IFF_UP). At this point all resources needed
1966 * for transmit and receive operations are allocated, the interrupt
1967 * handler is registered with the OS, the watchdog timer is started,
1968 * and the stack is notified that the interface is ready.
1969 */
1970 static int atl1e_open(struct net_device *netdev)
1971 {
1972 struct atl1e_adapter *adapter = netdev_priv(netdev);
1973 int err;
1974
1975 /* disallow open during test */
1976 if (test_bit(__AT_TESTING, &adapter->flags))
1977 return -EBUSY;
1978
1979 /* allocate rx/tx dma buffer & descriptors */
1980 atl1e_init_ring_resources(adapter);
1981 err = atl1e_setup_ring_resources(adapter);
1982 if (unlikely(err))
1983 return err;
1984
1985 err = atl1e_request_irq(adapter);
1986 if (unlikely(err))
1987 goto err_req_irq;
1988
1989 err = atl1e_up(adapter);
1990 if (unlikely(err))
1991 goto err_up;
1992
1993 return 0;
1994
1995 err_up:
1996 atl1e_free_irq(adapter);
1997 err_req_irq:
1998 atl1e_free_ring_resources(adapter);
1999 atl1e_reset_hw(&adapter->hw);
2000
2001 return err;
2002 }
2003
2004 /*
2005 * atl1e_close - Disables a network interface
2006 * @netdev: network interface device structure
2007 *
2008 * Returns 0, this is not allowed to fail
2009 *
2010 * The close entry point is called when an interface is de-activated
2011 * by the OS. The hardware is still under the drivers control, but
2012 * needs to be disabled. A global MAC reset is issued to stop the
2013 * hardware, and all transmit and receive resources are freed.
2014 */
2015 static int atl1e_close(struct net_device *netdev)
2016 {
2017 struct atl1e_adapter *adapter = netdev_priv(netdev);
2018
2019 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2020 atl1e_down(adapter);
2021 atl1e_free_irq(adapter);
2022 atl1e_free_ring_resources(adapter);
2023
2024 return 0;
2025 }
2026
2027 static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
2028 {
2029 struct net_device *netdev = pci_get_drvdata(pdev);
2030 struct atl1e_adapter *adapter = netdev_priv(netdev);
2031 struct atl1e_hw *hw = &adapter->hw;
2032 u32 ctrl = 0;
2033 u32 mac_ctrl_data = 0;
2034 u32 wol_ctrl_data = 0;
2035 u16 mii_advertise_data = 0;
2036 u16 mii_bmsr_data = 0;
2037 u16 mii_intr_status_data = 0;
2038 u32 wufc = adapter->wol;
2039 u32 i;
2040 #ifdef CONFIG_PM
2041 int retval = 0;
2042 #endif
2043
2044 if (netif_running(netdev)) {
2045 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2046 atl1e_down(adapter);
2047 }
2048 netif_device_detach(netdev);
2049
2050 #ifdef CONFIG_PM
2051 retval = pci_save_state(pdev);
2052 if (retval)
2053 return retval;
2054 #endif
2055
2056 if (wufc) {
2057 /* get link status */
2058 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2059 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2060
2061 mii_advertise_data = MII_AR_10T_HD_CAPS;
2062
2063 if ((atl1e_write_phy_reg(hw, MII_AT001_CR, 0) != 0) ||
2064 (atl1e_write_phy_reg(hw,
2065 MII_ADVERTISE, mii_advertise_data) != 0) ||
2066 (atl1e_phy_commit(hw)) != 0) {
2067 netdev_dbg(adapter->netdev, "set phy register failed\n");
2068 goto wol_dis;
2069 }
2070
2071 hw->phy_configured = false; /* re-init PHY when resume */
2072
2073 /* turn on magic packet wol */
2074 if (wufc & AT_WUFC_MAG)
2075 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2076
2077 if (wufc & AT_WUFC_LNKC) {
2078 /* if orignal link status is link, just wait for retrive link */
2079 if (mii_bmsr_data & BMSR_LSTATUS) {
2080 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2081 msleep(100);
2082 atl1e_read_phy_reg(hw, MII_BMSR,
2083 (u16 *)&mii_bmsr_data);
2084 if (mii_bmsr_data & BMSR_LSTATUS)
2085 break;
2086 }
2087
2088 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2089 netdev_dbg(adapter->netdev,
2090 "Link may change when suspend\n");
2091 }
2092 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2093 /* only link up can wake up */
2094 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2095 netdev_dbg(adapter->netdev,
2096 "read write phy register failed\n");
2097 goto wol_dis;
2098 }
2099 }
2100 /* clear phy interrupt */
2101 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2102 /* Config MAC Ctrl register */
2103 mac_ctrl_data = MAC_CTRL_RX_EN;
2104 /* set to 10/100M halt duplex */
2105 mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
2106 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2107 MAC_CTRL_PRMLEN_MASK) <<
2108 MAC_CTRL_PRMLEN_SHIFT);
2109
2110 if (adapter->vlgrp)
2111 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2112
2113 /* magic packet maybe Broadcast&multicast&Unicast frame */
2114 if (wufc & AT_WUFC_MAG)
2115 mac_ctrl_data |= MAC_CTRL_BC_EN;
2116
2117 netdev_dbg(adapter->netdev, "suspend MAC=0x%x\n",
2118 mac_ctrl_data);
2119
2120 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2121 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2122 /* pcie patch */
2123 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2124 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2125 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2126 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2127 goto suspend_exit;
2128 }
2129 wol_dis:
2130
2131 /* WOL disabled */
2132 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2133
2134 /* pcie patch */
2135 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2136 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2137 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2138
2139 atl1e_force_ps(hw);
2140 hw->phy_configured = false; /* re-init PHY when resume */
2141
2142 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2143
2144 suspend_exit:
2145
2146 if (netif_running(netdev))
2147 atl1e_free_irq(adapter);
2148
2149 pci_disable_device(pdev);
2150
2151 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2152
2153 return 0;
2154 }
2155
2156 #ifdef CONFIG_PM
2157 static int atl1e_resume(struct pci_dev *pdev)
2158 {
2159 struct net_device *netdev = pci_get_drvdata(pdev);
2160 struct atl1e_adapter *adapter = netdev_priv(netdev);
2161 u32 err;
2162
2163 pci_set_power_state(pdev, PCI_D0);
2164 pci_restore_state(pdev);
2165
2166 err = pci_enable_device(pdev);
2167 if (err) {
2168 netdev_err(adapter->netdev,
2169 "Cannot enable PCI device from suspend\n");
2170 return err;
2171 }
2172
2173 pci_set_master(pdev);
2174
2175 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2176
2177 pci_enable_wake(pdev, PCI_D3hot, 0);
2178 pci_enable_wake(pdev, PCI_D3cold, 0);
2179
2180 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2181
2182 if (netif_running(netdev)) {
2183 err = atl1e_request_irq(adapter);
2184 if (err)
2185 return err;
2186 }
2187
2188 atl1e_reset_hw(&adapter->hw);
2189
2190 if (netif_running(netdev))
2191 atl1e_up(adapter);
2192
2193 netif_device_attach(netdev);
2194
2195 return 0;
2196 }
2197 #endif
2198
2199 static void atl1e_shutdown(struct pci_dev *pdev)
2200 {
2201 atl1e_suspend(pdev, PMSG_SUSPEND);
2202 }
2203
2204 static const struct net_device_ops atl1e_netdev_ops = {
2205 .ndo_open = atl1e_open,
2206 .ndo_stop = atl1e_close,
2207 .ndo_start_xmit = atl1e_xmit_frame,
2208 .ndo_get_stats = atl1e_get_stats,
2209 .ndo_set_multicast_list = atl1e_set_multi,
2210 .ndo_validate_addr = eth_validate_addr,
2211 .ndo_set_mac_address = atl1e_set_mac_addr,
2212 .ndo_change_mtu = atl1e_change_mtu,
2213 .ndo_do_ioctl = atl1e_ioctl,
2214 .ndo_tx_timeout = atl1e_tx_timeout,
2215 .ndo_vlan_rx_register = atl1e_vlan_rx_register,
2216 #ifdef CONFIG_NET_POLL_CONTROLLER
2217 .ndo_poll_controller = atl1e_netpoll,
2218 #endif
2219
2220 };
2221
2222 static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2223 {
2224 SET_NETDEV_DEV(netdev, &pdev->dev);
2225 pci_set_drvdata(pdev, netdev);
2226
2227 netdev->irq = pdev->irq;
2228 netdev->netdev_ops = &atl1e_netdev_ops;
2229
2230 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2231 atl1e_set_ethtool_ops(netdev);
2232
2233 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM |
2234 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2235 netdev->features |= NETIF_F_LLTX;
2236 netdev->features |= NETIF_F_TSO;
2237
2238 return 0;
2239 }
2240
2241 /*
2242 * atl1e_probe - Device Initialization Routine
2243 * @pdev: PCI device information struct
2244 * @ent: entry in atl1e_pci_tbl
2245 *
2246 * Returns 0 on success, negative on failure
2247 *
2248 * atl1e_probe initializes an adapter identified by a pci_dev structure.
2249 * The OS initialization, configuring of the adapter private structure,
2250 * and a hardware reset occur.
2251 */
2252 static int __devinit atl1e_probe(struct pci_dev *pdev,
2253 const struct pci_device_id *ent)
2254 {
2255 struct net_device *netdev;
2256 struct atl1e_adapter *adapter = NULL;
2257 static int cards_found;
2258
2259 int err = 0;
2260
2261 err = pci_enable_device(pdev);
2262 if (err) {
2263 dev_err(&pdev->dev, "cannot enable PCI device\n");
2264 return err;
2265 }
2266
2267 /*
2268 * The atl1e chip can DMA to 64-bit addresses, but it uses a single
2269 * shared register for the high 32 bits, so only a single, aligned,
2270 * 4 GB physical address range can be used at a time.
2271 *
2272 * Supporting 64-bit DMA on this hardware is more trouble than it's
2273 * worth. It is far easier to limit to 32-bit DMA than update
2274 * various kernel subsystems to support the mechanics required by a
2275 * fixed-high-32-bit system.
2276 */
2277 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2278 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
2279 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2280 goto err_dma;
2281 }
2282
2283 err = pci_request_regions(pdev, atl1e_driver_name);
2284 if (err) {
2285 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2286 goto err_pci_reg;
2287 }
2288
2289 pci_set_master(pdev);
2290
2291 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
2292 if (netdev == NULL) {
2293 err = -ENOMEM;
2294 dev_err(&pdev->dev, "etherdev alloc failed\n");
2295 goto err_alloc_etherdev;
2296 }
2297
2298 err = atl1e_init_netdev(netdev, pdev);
2299 if (err) {
2300 netdev_err(netdev, "init netdevice failed\n");
2301 goto err_init_netdev;
2302 }
2303 adapter = netdev_priv(netdev);
2304 adapter->bd_number = cards_found;
2305 adapter->netdev = netdev;
2306 adapter->pdev = pdev;
2307 adapter->hw.adapter = adapter;
2308 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2309 if (!adapter->hw.hw_addr) {
2310 err = -EIO;
2311 netdev_err(netdev, "cannot map device registers\n");
2312 goto err_ioremap;
2313 }
2314 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2315
2316 /* init mii data */
2317 adapter->mii.dev = netdev;
2318 adapter->mii.mdio_read = atl1e_mdio_read;
2319 adapter->mii.mdio_write = atl1e_mdio_write;
2320 adapter->mii.phy_id_mask = 0x1f;
2321 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2322
2323 netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
2324
2325 init_timer(&adapter->phy_config_timer);
2326 adapter->phy_config_timer.function = &atl1e_phy_config;
2327 adapter->phy_config_timer.data = (unsigned long) adapter;
2328
2329 /* get user settings */
2330 atl1e_check_options(adapter);
2331 /*
2332 * Mark all PCI regions associated with PCI device
2333 * pdev as being reserved by owner atl1e_driver_name
2334 * Enables bus-mastering on the device and calls
2335 * pcibios_set_master to do the needed arch specific settings
2336 */
2337 atl1e_setup_pcicmd(pdev);
2338 /* setup the private structure */
2339 err = atl1e_sw_init(adapter);
2340 if (err) {
2341 netdev_err(netdev, "net device private data init failed\n");
2342 goto err_sw_init;
2343 }
2344
2345 /* Init GPHY as early as possible due to power saving issue */
2346 atl1e_phy_init(&adapter->hw);
2347 /* reset the controller to
2348 * put the device in a known good starting state */
2349 err = atl1e_reset_hw(&adapter->hw);
2350 if (err) {
2351 err = -EIO;
2352 goto err_reset;
2353 }
2354
2355 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2356 err = -EIO;
2357 netdev_err(netdev, "get mac address failed\n");
2358 goto err_eeprom;
2359 }
2360
2361 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2362 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2363 netdev_dbg(netdev, "mac address : %pM\n", adapter->hw.mac_addr);
2364
2365 INIT_WORK(&adapter->reset_task, atl1e_reset_task);
2366 INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
2367 err = register_netdev(netdev);
2368 if (err) {
2369 netdev_err(netdev, "register netdevice failed\n");
2370 goto err_register;
2371 }
2372
2373 /* assume we have no link for now */
2374 netif_stop_queue(netdev);
2375 netif_carrier_off(netdev);
2376
2377 cards_found++;
2378
2379 return 0;
2380
2381 err_reset:
2382 err_register:
2383 err_sw_init:
2384 err_eeprom:
2385 iounmap(adapter->hw.hw_addr);
2386 err_init_netdev:
2387 err_ioremap:
2388 free_netdev(netdev);
2389 err_alloc_etherdev:
2390 pci_release_regions(pdev);
2391 err_pci_reg:
2392 err_dma:
2393 pci_disable_device(pdev);
2394 return err;
2395 }
2396
2397 /*
2398 * atl1e_remove - Device Removal Routine
2399 * @pdev: PCI device information struct
2400 *
2401 * atl1e_remove is called by the PCI subsystem to alert the driver
2402 * that it should release a PCI device. The could be caused by a
2403 * Hot-Plug event, or because the driver is going to be removed from
2404 * memory.
2405 */
2406 static void __devexit atl1e_remove(struct pci_dev *pdev)
2407 {
2408 struct net_device *netdev = pci_get_drvdata(pdev);
2409 struct atl1e_adapter *adapter = netdev_priv(netdev);
2410
2411 /*
2412 * flush_scheduled work may reschedule our watchdog task, so
2413 * explicitly disable watchdog tasks from being rescheduled
2414 */
2415 set_bit(__AT_DOWN, &adapter->flags);
2416
2417 atl1e_del_timer(adapter);
2418 atl1e_cancel_work(adapter);
2419
2420 unregister_netdev(netdev);
2421 atl1e_free_ring_resources(adapter);
2422 atl1e_force_ps(&adapter->hw);
2423 iounmap(adapter->hw.hw_addr);
2424 pci_release_regions(pdev);
2425 free_netdev(netdev);
2426 pci_disable_device(pdev);
2427 }
2428
2429 /*
2430 * atl1e_io_error_detected - called when PCI error is detected
2431 * @pdev: Pointer to PCI device
2432 * @state: The current pci connection state
2433 *
2434 * This function is called after a PCI bus error affecting
2435 * this device has been detected.
2436 */
2437 static pci_ers_result_t
2438 atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2439 {
2440 struct net_device *netdev = pci_get_drvdata(pdev);
2441 struct atl1e_adapter *adapter = netdev_priv(netdev);
2442
2443 netif_device_detach(netdev);
2444
2445 if (state == pci_channel_io_perm_failure)
2446 return PCI_ERS_RESULT_DISCONNECT;
2447
2448 if (netif_running(netdev))
2449 atl1e_down(adapter);
2450
2451 pci_disable_device(pdev);
2452
2453 /* Request a slot slot reset. */
2454 return PCI_ERS_RESULT_NEED_RESET;
2455 }
2456
2457 /*
2458 * atl1e_io_slot_reset - called after the pci bus has been reset.
2459 * @pdev: Pointer to PCI device
2460 *
2461 * Restart the card from scratch, as if from a cold-boot. Implementation
2462 * resembles the first-half of the e1000_resume routine.
2463 */
2464 static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
2465 {
2466 struct net_device *netdev = pci_get_drvdata(pdev);
2467 struct atl1e_adapter *adapter = netdev_priv(netdev);
2468
2469 if (pci_enable_device(pdev)) {
2470 netdev_err(adapter->netdev,
2471 "Cannot re-enable PCI device after reset\n");
2472 return PCI_ERS_RESULT_DISCONNECT;
2473 }
2474 pci_set_master(pdev);
2475
2476 pci_enable_wake(pdev, PCI_D3hot, 0);
2477 pci_enable_wake(pdev, PCI_D3cold, 0);
2478
2479 atl1e_reset_hw(&adapter->hw);
2480
2481 return PCI_ERS_RESULT_RECOVERED;
2482 }
2483
2484 /*
2485 * atl1e_io_resume - called when traffic can start flowing again.
2486 * @pdev: Pointer to PCI device
2487 *
2488 * This callback is called when the error recovery driver tells us that
2489 * its OK to resume normal operation. Implementation resembles the
2490 * second-half of the atl1e_resume routine.
2491 */
2492 static void atl1e_io_resume(struct pci_dev *pdev)
2493 {
2494 struct net_device *netdev = pci_get_drvdata(pdev);
2495 struct atl1e_adapter *adapter = netdev_priv(netdev);
2496
2497 if (netif_running(netdev)) {
2498 if (atl1e_up(adapter)) {
2499 netdev_err(adapter->netdev,
2500 "can't bring device back up after reset\n");
2501 return;
2502 }
2503 }
2504
2505 netif_device_attach(netdev);
2506 }
2507
2508 static struct pci_error_handlers atl1e_err_handler = {
2509 .error_detected = atl1e_io_error_detected,
2510 .slot_reset = atl1e_io_slot_reset,
2511 .resume = atl1e_io_resume,
2512 };
2513
2514 static struct pci_driver atl1e_driver = {
2515 .name = atl1e_driver_name,
2516 .id_table = atl1e_pci_tbl,
2517 .probe = atl1e_probe,
2518 .remove = __devexit_p(atl1e_remove),
2519 /* Power Managment Hooks */
2520 #ifdef CONFIG_PM
2521 .suspend = atl1e_suspend,
2522 .resume = atl1e_resume,
2523 #endif
2524 .shutdown = atl1e_shutdown,
2525 .err_handler = &atl1e_err_handler
2526 };
2527
2528 /*
2529 * atl1e_init_module - Driver Registration Routine
2530 *
2531 * atl1e_init_module is the first routine called when the driver is
2532 * loaded. All it does is register with the PCI subsystem.
2533 */
2534 static int __init atl1e_init_module(void)
2535 {
2536 return pci_register_driver(&atl1e_driver);
2537 }
2538
2539 /*
2540 * atl1e_exit_module - Driver Exit Cleanup Routine
2541 *
2542 * atl1e_exit_module is called just before the driver is removed
2543 * from memory.
2544 */
2545 static void __exit atl1e_exit_module(void)
2546 {
2547 pci_unregister_driver(&atl1e_driver);
2548 }
2549
2550 module_init(atl1e_init_module);
2551 module_exit(atl1e_exit_module);
Linux kernel - Deliverables
This page took 0.086135 seconds and 5 git commands to generate.