2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 #include <linux/pci.h>
22 #include <linux/etherdevice.h>
23 #include <linux/version.h>
24 #include <linux/delay.h>
28 #include <linux/if_vlan.h>
29 #include <linux/workqueue.h>
30 #include <linux/interrupt.h>
31 #include <linux/firmware.h>
32 #include <linux/slab.h>
36 #define DRV_VER "2.103.175u"
37 #define DRV_NAME "be2net"
38 #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
39 #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
40 #define OC_NAME "Emulex OneConnect 10Gbps NIC"
41 #define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
42 #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
44 #define BE_VENDOR_ID 0x19a2
45 #define BE_DEVICE_ID1 0x211
46 #define BE_DEVICE_ID2 0x221
47 #define OC_DEVICE_ID1 0x700
48 #define OC_DEVICE_ID2 0x710
50 static inline char *nic_name(struct pci_dev
*pdev
)
52 switch (pdev
->device
) {
64 /* Number of bytes of an RX frame that are copied to skb->data */
66 #define BE_MAX_JUMBO_FRAME_SIZE 9018
67 #define BE_MIN_MTU 256
69 #define BE_NUM_VLANS_SUPPORTED 64
71 #define BE_MAX_TX_FRAG_COUNT 30
73 #define EVNT_Q_LEN 1024
75 #define TX_CQ_LEN 1024
76 #define RX_Q_LEN 1024 /* Does not support any other value */
77 #define RX_CQ_LEN 1024
78 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
79 #define MCC_CQ_LEN 256
81 #define MAX_RSS_QS 4 /* BE limit is 4 queues/port */
82 #define BE_MAX_MSIX_VECTORS (MAX_RSS_QS + 1 + 1)/* RSS qs + 1 def Rx + Tx */
83 #define BE_NAPI_WEIGHT 64
84 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
85 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
97 struct be_queue_info
{
98 struct be_dma_mem dma_mem
;
100 u16 entry_size
; /* Size of an element in the queue */
104 atomic_t used
; /* Number of valid elements in the queue */
107 static inline u32
MODULO(u16 val
, u16 limit
)
109 BUG_ON(limit
& (limit
- 1));
110 return val
& (limit
- 1);
113 static inline void index_adv(u16
*index
, u16 val
, u16 limit
)
115 *index
= MODULO((*index
+ val
), limit
);
118 static inline void index_inc(u16
*index
, u16 limit
)
120 *index
= MODULO((*index
+ 1), limit
);
123 static inline void *queue_head_node(struct be_queue_info
*q
)
125 return q
->dma_mem
.va
+ q
->head
* q
->entry_size
;
128 static inline void *queue_tail_node(struct be_queue_info
*q
)
130 return q
->dma_mem
.va
+ q
->tail
* q
->entry_size
;
133 static inline void queue_head_inc(struct be_queue_info
*q
)
135 index_inc(&q
->head
, q
->len
);
138 static inline void queue_tail_inc(struct be_queue_info
*q
)
140 index_inc(&q
->tail
, q
->len
);
144 struct be_queue_info q
;
147 /* Adaptive interrupt coalescing (AIC) info */
149 u16 min_eqd
; /* in usecs */
150 u16 max_eqd
; /* in usecs */
151 u16 cur_eqd
; /* in usecs */
153 struct napi_struct napi
;
157 struct be_queue_info q
;
158 struct be_queue_info cq
;
163 u32 be_tx_reqs
; /* number of TX requests initiated */
164 u32 be_tx_stops
; /* number of times TX Q was stopped */
165 u32 be_tx_wrbs
; /* number of tx WRBs used */
166 u32 be_tx_events
; /* number of tx completion events */
167 u32 be_tx_compl
; /* number of tx completion entries processed */
170 u64 be_tx_bytes_prev
;
176 struct be_queue_info q
;
177 struct be_queue_info cq
;
178 /* Remember the skbs that were transmitted */
179 struct sk_buff
*sent_skb_list
[TX_Q_LEN
];
182 /* Struct to remember the pages posted for rx frags */
183 struct be_rx_page_info
{
185 DEFINE_DMA_UNMAP_ADDR(bus
);
191 u32 rx_post_fail
;/* number of ethrx buffer alloc failures */
192 u32 rx_polls
; /* number of times NAPI called poll function */
193 u32 rx_events
; /* number of ucast rx completion events */
194 u32 rx_compl
; /* number of rx completion entries processed */
201 u32 rxcp_err
; /* Num rx completion entries w/ err set. */
202 ulong rx_fps_jiffies
; /* jiffies at last FPS calc */
205 u32 rx_fps
; /* Rx frags per second */
209 struct be_adapter
*adapter
;
210 struct be_queue_info q
;
211 struct be_queue_info cq
;
212 struct be_rx_page_info page_info_tbl
[RX_Q_LEN
];
213 struct be_eq_obj rx_eq
;
214 struct be_rx_stats stats
;
216 bool rx_post_starved
; /* Zero rx frags have been posted to BE */
217 u32 cache_line_barrier
[16];
221 unsigned char vf_mac_addr
[ETH_ALEN
];
228 #define BE_INVALID_PMAC_ID 0xffffffff
230 struct pci_dev
*pdev
;
231 struct net_device
*netdev
;
234 u8 __iomem
*db
; /* Door Bell */
235 u8 __iomem
*pcicfg
; /* PCI config space */
237 spinlock_t mbox_lock
; /* For serializing mbox cmds to BE card */
238 struct be_dma_mem mbox_mem
;
239 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
240 * is stored for freeing purpose */
241 struct be_dma_mem mbox_mem_alloced
;
243 struct be_mcc_obj mcc_obj
;
244 spinlock_t mcc_lock
; /* For serializing mcc cmds to BE card */
245 spinlock_t mcc_cq_lock
;
247 struct msix_entry msix_entries
[BE_MAX_MSIX_VECTORS
];
252 struct be_eq_obj tx_eq
;
253 struct be_tx_obj tx_obj
;
254 struct be_tx_stats tx_stats
;
256 u32 cache_line_break
[8];
259 struct be_rx_obj rx_obj
[MAX_RSS_QS
+ 1]; /* one default non-rss Q */
261 u32 big_page_size
; /* Compounded page size shared by rx wrbs */
263 struct vlan_group
*vlan_grp
;
265 u16 max_vlans
; /* Number of vlans supported */
266 u8 vlan_tag
[VLAN_N_VID
];
267 u8 vlan_prio_bmap
; /* Available Priority BitMap */
268 u16 recommended_prio
; /* Recommended Priority */
269 struct be_dma_mem mc_cmd_mem
;
271 struct be_dma_mem stats_cmd
;
272 /* Work queue used to perform periodic tasks like getting statistics */
273 struct delayed_work work
;
275 /* Ethtool knobs and info */
276 bool rx_csum
; /* BE card must perform rx-checksumming */
277 char fw_ver
[FW_VER_LEN
];
278 u32 if_handle
; /* Used to configure filtering */
279 u32 pmac_id
; /* MAC addr handle used by BE card */
288 u32 rx_fc
; /* Rx flow control */
289 u32 tx_fc
; /* Tx flow control */
291 bool stats_ioctl_sent
;
296 u8 generation
; /* BladeEngine ASIC generation */
298 struct completion flash_compl
;
301 struct be_vf_cfg vf_cfg
[BE_MAX_VF
];
306 #define be_physfn(adapter) (!adapter->is_virtfn)
308 /* BladeEngine Generation numbers */
312 extern const struct ethtool_ops be_ethtool_ops
;
314 #define tx_stats(adapter) (&adapter->tx_stats)
315 #define rx_stats(rxo) (&rxo->stats)
317 #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
319 #define for_all_rx_queues(adapter, rxo, i) \
320 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
323 /* Just skip the first default non-rss queue */
324 #define for_all_rss_queues(adapter, rxo, i) \
325 for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\
328 #define PAGE_SHIFT_4K 12
329 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
331 /* Returns number of pages spanned by the data starting at the given addr */
332 #define PAGES_4K_SPANNED(_address, size) \
333 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
334 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
336 /* Byte offset into the page corresponding to given address */
337 #define OFFSET_IN_PAGE(addr) \
338 ((size_t)(addr) & (PAGE_SIZE_4K-1))
340 /* Returns bit offset within a DWORD of a bitfield */
341 #define AMAP_BIT_OFFSET(_struct, field) \
342 (((size_t)&(((_struct *)0)->field))%32)
344 /* Returns the bit mask of the field that is NOT shifted into location. */
345 static inline u32
amap_mask(u32 bitsize
)
347 return (bitsize
== 32 ? 0xFFFFFFFF : (1 << bitsize
) - 1);
351 amap_set(void *ptr
, u32 dw_offset
, u32 mask
, u32 offset
, u32 value
)
353 u32
*dw
= (u32
*) ptr
+ dw_offset
;
354 *dw
&= ~(mask
<< offset
);
355 *dw
|= (mask
& value
) << offset
;
358 #define AMAP_SET_BITS(_struct, field, ptr, val) \
360 offsetof(_struct, field)/32, \
361 amap_mask(sizeof(((_struct *)0)->field)), \
362 AMAP_BIT_OFFSET(_struct, field), \
365 static inline u32
amap_get(void *ptr
, u32 dw_offset
, u32 mask
, u32 offset
)
367 u32
*dw
= (u32
*) ptr
;
368 return mask
& (*(dw
+ dw_offset
) >> offset
);
371 #define AMAP_GET_BITS(_struct, field, ptr) \
373 offsetof(_struct, field)/32, \
374 amap_mask(sizeof(((_struct *)0)->field)), \
375 AMAP_BIT_OFFSET(_struct, field))
377 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
378 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
379 static inline void swap_dws(void *wrb
, int len
)
385 *dw
= cpu_to_le32(*dw
);
389 #endif /* __BIG_ENDIAN */
392 static inline u8
is_tcp_pkt(struct sk_buff
*skb
)
396 if (ip_hdr(skb
)->version
== 4)
397 val
= (ip_hdr(skb
)->protocol
== IPPROTO_TCP
);
398 else if (ip_hdr(skb
)->version
== 6)
399 val
= (ipv6_hdr(skb
)->nexthdr
== NEXTHDR_TCP
);
404 static inline u8
is_udp_pkt(struct sk_buff
*skb
)
408 if (ip_hdr(skb
)->version
== 4)
409 val
= (ip_hdr(skb
)->protocol
== IPPROTO_UDP
);
410 else if (ip_hdr(skb
)->version
== 6)
411 val
= (ipv6_hdr(skb
)->nexthdr
== NEXTHDR_UDP
);
416 static inline void be_check_sriov_fn_type(struct be_adapter
*adapter
)
420 pci_write_config_byte(adapter
->pdev
, 0xFE, 0xAA);
421 pci_read_config_byte(adapter
->pdev
, 0xFE, &data
);
422 adapter
->is_virtfn
= (data
!= 0xAA);
425 static inline void be_vf_eth_addr_generate(struct be_adapter
*adapter
, u8
*mac
)
429 addr
= jhash(adapter
->netdev
->dev_addr
, ETH_ALEN
, 0);
431 mac
[5] = (u8
)(addr
& 0xFF);
432 mac
[4] = (u8
)((addr
>> 8) & 0xFF);
433 mac
[3] = (u8
)((addr
>> 16) & 0xFF);
439 extern void be_cq_notify(struct be_adapter
*adapter
, u16 qid
, bool arm
,
441 extern void be_link_status_update(struct be_adapter
*adapter
, bool link_up
);
442 extern void netdev_stats_update(struct be_adapter
*adapter
);
443 extern int be_load_fw(struct be_adapter
*adapter
, u8
*func
);