2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
28 #define MPU_MAILBOX_DB_OFFSET 0x160
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
32 #define MPU_EP_CONTROL 0
34 /********** MPU semphore ******************/
35 #define MPU_EP_SEMAPHORE_OFFSET 0xac
36 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
37 #define EP_SEMAPHORE_POST_ERR_MASK 0x1
38 #define EP_SEMAPHORE_POST_ERR_SHIFT 31
39 /* MPU semphore POST stage values */
40 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
41 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
42 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
43 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
45 /********* Memory BAR register ************/
46 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
47 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
48 * Disable" may still globally block interrupts in addition to individual
49 * interrupt masks; a mechanism for the device driver to block all interrupts
50 * atomically without having to arbitrate for the PCI Interrupt Disable bit
53 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
55 /********* Power management (WOL) **********/
56 #define PCICFG_PM_CONTROL_OFFSET 0x44
57 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
59 /********* Online Control Registers *******/
60 #define PCICFG_ONLINE0 0xB0
61 #define PCICFG_ONLINE1 0xB4
63 /********* UE Status and Mask Registers ***/
64 #define PCICFG_UE_STATUS_LOW 0xA0
65 #define PCICFG_UE_STATUS_HIGH 0xA4
66 #define PCICFG_UE_STATUS_LOW_MASK 0xA8
67 #define PCICFG_UE_STATUS_HI_MASK 0xAC
69 /********* ISR0 Register offset **********/
70 #define CEV_ISR0_OFFSET 0xC18
71 #define CEV_ISR_SIZE 4
73 /********* Event Q door bell *************/
74 #define DB_EQ_OFFSET DB_CQ_OFFSET
75 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
76 /* Clear the interrupt for this eq */
77 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
79 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
80 /* Number of event entries processed */
81 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
83 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
85 /********* Compl Q door bell *************/
86 #define DB_CQ_OFFSET 0x120
87 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
88 /* Number of event entries processed */
89 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
91 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
93 /********** TX ULP door bell *************/
94 #define DB_TXULP1_OFFSET 0x60
95 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
96 /* Number of tx entries posted */
97 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
98 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
100 /********** RQ(erx) door bell ************/
101 #define DB_RQ_OFFSET 0x100
102 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
103 /* Number of rx frags posted */
104 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
106 /********** MCC door bell ************/
107 #define DB_MCCQ_OFFSET 0x140
108 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
109 /* Number of entries posted */
110 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
112 /********** SRIOV VF PCICFG OFFSET ********/
113 #define SRIOV_VF_PCICFG_OFFSET (4096)
115 /* Flashrom related descriptors */
116 #define IMAGE_TYPE_FIRMWARE 160
117 #define IMAGE_TYPE_BOOTCODE 224
118 #define IMAGE_TYPE_OPTIONROM 32
120 #define NUM_FLASHDIR_ENTRIES 32
122 #define IMG_TYPE_ISCSI_ACTIVE 0
123 #define IMG_TYPE_REDBOOT 1
124 #define IMG_TYPE_BIOS 2
125 #define IMG_TYPE_PXE_BIOS 3
126 #define IMG_TYPE_FCOE_BIOS 8
127 #define IMG_TYPE_ISCSI_BACKUP 9
128 #define IMG_TYPE_FCOE_FW_ACTIVE 10
129 #define IMG_TYPE_FCOE_FW_BACKUP 11
130 #define IMG_TYPE_NCSI_FW 13
132 #define FLASHROM_OPER_FLASH 1
133 #define FLASHROM_OPER_SAVE 2
134 #define FLASHROM_OPER_REPORT 4
136 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image sz */
137 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM img sz */
138 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
139 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max fw image size */
140 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM img sz */
141 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
142 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) /* Max NSCI image sz */
144 #define FLASH_NCSI_MAGIC (0x16032009)
145 #define FLASH_NCSI_DISABLED (0)
146 #define FLASH_NCSI_ENABLED (1)
148 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
150 /* Offsets for components on Flash. */
151 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
152 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
153 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
154 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
155 #define FLASH_iSCSI_BIOS_START_g2 (7340032)
156 #define FLASH_PXE_BIOS_START_g2 (7864320)
157 #define FLASH_FCoE_BIOS_START_g2 (524288)
158 #define FLASH_REDBOOT_START_g2 (0)
160 #define FLASH_NCSI_START_g3 (15990784)
161 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
162 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
163 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
164 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
165 #define FLASH_iSCSI_BIOS_START_g3 (12582912)
166 #define FLASH_PXE_BIOS_START_g3 (13107200)
167 #define FLASH_FCoE_BIOS_START_g3 (13631488)
168 #define FLASH_REDBOOT_START_g3 (262144)
174 * BE descriptors: host memory data structures whose formats
175 * are hardwired in BE silicon.
177 /* Event Queue Descriptor */
178 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
179 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
180 #define EQ_ENTRY_RES_ID_SHIFT 16
186 /* TX Queue Descriptor */
187 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
189 u32 frag_pa_hi
; /* dword 0 */
190 u32 frag_pa_lo
; /* dword 1 */
191 u32 rsvd0
; /* dword 2 */
192 u32 frag_len
; /* dword 3: bits 0 - 15 */
195 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
196 * actual structure is defined as a byte : used to calculate
197 * offset/shift/mask of each field */
198 struct amap_eth_hdr_wrb
{
199 u8 rsvd0
[32]; /* dword 0 */
200 u8 rsvd1
[32]; /* dword 1 */
201 u8 complete
; /* dword 2 */
215 u8 len
[16]; /* dword 3 */
219 struct be_eth_hdr_wrb
{
223 /* TX Compl Queue Descriptor */
225 /* Pseudo amap definition for eth_tx_compl in which each bit of the
226 * actual structure is defined as a byte: used to calculate
227 * offset/shift/mask of each field */
228 struct amap_eth_tx_compl
{
229 u8 wrb_index
[16]; /* dword 0 */
230 u8 ct
[2]; /* dword 0 */
231 u8 port
[2]; /* dword 0 */
232 u8 rsvd0
[8]; /* dword 0 */
233 u8 status
[4]; /* dword 0 */
234 u8 user_bytes
[16]; /* dword 1 */
235 u8 nwh_bytes
[8]; /* dword 1 */
236 u8 lso
; /* dword 1 */
237 u8 cast_enc
[2]; /* dword 1 */
238 u8 rsvd1
[5]; /* dword 1 */
239 u8 rsvd2
[32]; /* dword 2 */
240 u8 pkts
[16]; /* dword 3 */
241 u8 ringid
[11]; /* dword 3 */
242 u8 hash_val
[4]; /* dword 3 */
243 u8 valid
; /* dword 3 */
246 struct be_eth_tx_compl
{
250 /* RX Queue Descriptor */
256 /* RX Compl Queue Descriptor */
258 /* Pseudo amap definition for eth_rx_compl in which each bit of the
259 * actual structure is defined as a byte: used to calculate
260 * offset/shift/mask of each field */
261 struct amap_eth_rx_compl
{
262 u8 vlan_tag
[16]; /* dword 0 */
263 u8 pktsize
[14]; /* dword 0 */
264 u8 port
; /* dword 0 */
265 u8 ip_opt
; /* dword 0 */
266 u8 err
; /* dword 1 */
267 u8 rsshp
; /* dword 1 */
268 u8 ipf
; /* dword 1 */
269 u8 tcpf
; /* dword 1 */
270 u8 udpf
; /* dword 1 */
271 u8 ipcksm
; /* dword 1 */
272 u8 l4_cksm
; /* dword 1 */
273 u8 ip_version
; /* dword 1 */
274 u8 macdst
[6]; /* dword 1 */
275 u8 vtp
; /* dword 1 */
276 u8 rsvd0
; /* dword 1 */
277 u8 fragndx
[10]; /* dword 1 */
278 u8 ct
[2]; /* dword 1 */
280 u8 numfrags
[3]; /* dword 1 */
281 u8 rss_flush
; /* dword 2 */
282 u8 cast_enc
[2]; /* dword 2 */
283 u8 vtm
; /* dword 2 */
284 u8 rss_bank
; /* dword 2 */
285 u8 rsvd1
[23]; /* dword 2 */
286 u8 lro_pkt
; /* dword 2 */
287 u8 rsvd2
[2]; /* dword 2 */
288 u8 valid
; /* dword 2 */
289 u8 rsshash
[32]; /* dword 3 */
292 struct be_eth_rx_compl
{
296 struct controller_id
{
304 unsigned long offset
;
314 u8 image_version
[32];
316 struct flash_file_hdr_g2
{
320 struct controller_id cont_id
;
328 struct flash_file_hdr_g3
{
339 struct flash_section_hdr
{
345 u32 active_entry_mask
;
346 u32 valid_entry_mask
;
347 u32 org_content_mask
;
355 struct flash_section_entry
{
367 struct flash_section_info
{
369 struct flash_section_hdr fsec_hdr
;
370 struct flash_section_entry fsec_entry
[32];