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bnx2: use device model DMA API
[deliverable/linux.git] / drivers / net / bnx2.c
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33 #include <linux/delay.h>
34 #include <asm/byteorder.h>
35 #include <asm/page.h>
36 #include <linux/time.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
39 #include <linux/if_vlan.h>
40 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
41 #define BCM_VLAN 1
42 #endif
43 #include <net/ip.h>
44 #include <net/tcp.h>
45 #include <net/checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/prefetch.h>
49 #include <linux/cache.h>
50 #include <linux/firmware.h>
51 #include <linux/log2.h>
52
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54 #define BCM_CNIC 1
55 #include "cnic_if.h"
56 #endif
57 #include "bnx2.h"
58 #include "bnx2_fw.h"
59
60 #define DRV_MODULE_NAME "bnx2"
61 #define DRV_MODULE_VERSION "2.0.16"
62 #define DRV_MODULE_RELDATE "July 2, 2010"
63 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
64 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
65 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
66 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
67 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
68
69 #define RUN_AT(x) (jiffies + (x))
70
71 /* Time in jiffies before concluding the transmitter is hung. */
72 #define TX_TIMEOUT (5*HZ)
73
74 static char version[] __devinitdata =
75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
78 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
79 MODULE_LICENSE("GPL");
80 MODULE_VERSION(DRV_MODULE_VERSION);
81 MODULE_FIRMWARE(FW_MIPS_FILE_06);
82 MODULE_FIRMWARE(FW_RV2P_FILE_06);
83 MODULE_FIRMWARE(FW_MIPS_FILE_09);
84 MODULE_FIRMWARE(FW_RV2P_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
86
87 static int disable_msi = 0;
88
89 module_param(disable_msi, int, 0);
90 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92 typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
98 BCM5708,
99 BCM5708S,
100 BCM5709,
101 BCM5709S,
102 BCM5716,
103 BCM5716S,
104 } board_t;
105
106 /* indexed by board_t, above */
107 static struct {
108 char *name;
109 } board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
121 };
122
123 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
146 { 0, }
147 };
148
149 static const struct flash_spec flash_table[] =
150 {
151 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
153 /* Slow EEPROM */
154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
236 };
237
238 static const struct flash_spec flash_5709 = {
239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245 };
246
247 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
249 static void bnx2_init_napi(struct bnx2 *bp);
250 static void bnx2_del_napi(struct bnx2 *bp);
251
252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
253 {
254 u32 diff;
255
256 smp_mb();
257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
261 diff = txr->tx_prod - txr->tx_cons;
262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
267 return (bp->tx_ring_size - diff);
268 }
269
270 static u32
271 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272 {
273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
280 }
281
282 static void
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284 {
285 spin_lock_bh(&bp->indirect_lock);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
288 spin_unlock_bh(&bp->indirect_lock);
289 }
290
291 static void
292 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293 {
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295 }
296
297 static u32
298 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299 {
300 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
301 }
302
303 static void
304 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305 {
306 offset += cid_addr;
307 spin_lock_bh(&bp->indirect_lock);
308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
324 spin_unlock_bh(&bp->indirect_lock);
325 }
326
327 #ifdef BCM_CNIC
328 static int
329 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330 {
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348 }
349
350 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351 {
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375 }
376
377 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379 {
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
389 bp->cnic_data = data;
390 rcu_assign_pointer(bp->cnic_ops, ops);
391
392 cp->num_irq = 0;
393 cp->drv_state = CNIC_DRV_STATE_REGD;
394
395 bnx2_setup_cnic_irq_info(bp);
396
397 return 0;
398 }
399
400 static int bnx2_unregister_cnic(struct net_device *dev)
401 {
402 struct bnx2 *bp = netdev_priv(dev);
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
405
406 mutex_lock(&bp->cnic_lock);
407 cp->drv_state = 0;
408 bnapi->cnic_present = 0;
409 rcu_assign_pointer(bp->cnic_ops, NULL);
410 mutex_unlock(&bp->cnic_lock);
411 synchronize_rcu();
412 return 0;
413 }
414
415 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
416 {
417 struct bnx2 *bp = netdev_priv(dev);
418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
419
420 cp->drv_owner = THIS_MODULE;
421 cp->chip_id = bp->chip_id;
422 cp->pdev = bp->pdev;
423 cp->io_base = bp->regview;
424 cp->drv_ctl = bnx2_drv_ctl;
425 cp->drv_register_cnic = bnx2_register_cnic;
426 cp->drv_unregister_cnic = bnx2_unregister_cnic;
427
428 return cp;
429 }
430 EXPORT_SYMBOL(bnx2_cnic_probe);
431
432 static void
433 bnx2_cnic_stop(struct bnx2 *bp)
434 {
435 struct cnic_ops *c_ops;
436 struct cnic_ctl_info info;
437
438 mutex_lock(&bp->cnic_lock);
439 c_ops = bp->cnic_ops;
440 if (c_ops) {
441 info.cmd = CNIC_CTL_STOP_CMD;
442 c_ops->cnic_ctl(bp->cnic_data, &info);
443 }
444 mutex_unlock(&bp->cnic_lock);
445 }
446
447 static void
448 bnx2_cnic_start(struct bnx2 *bp)
449 {
450 struct cnic_ops *c_ops;
451 struct cnic_ctl_info info;
452
453 mutex_lock(&bp->cnic_lock);
454 c_ops = bp->cnic_ops;
455 if (c_ops) {
456 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
457 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
458
459 bnapi->cnic_tag = bnapi->last_status_idx;
460 }
461 info.cmd = CNIC_CTL_START_CMD;
462 c_ops->cnic_ctl(bp->cnic_data, &info);
463 }
464 mutex_unlock(&bp->cnic_lock);
465 }
466
467 #else
468
469 static void
470 bnx2_cnic_stop(struct bnx2 *bp)
471 {
472 }
473
474 static void
475 bnx2_cnic_start(struct bnx2 *bp)
476 {
477 }
478
479 #endif
480
481 static int
482 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
483 {
484 u32 val1;
485 int i, ret;
486
487 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
488 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
489 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
490
491 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
492 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
493
494 udelay(40);
495 }
496
497 val1 = (bp->phy_addr << 21) | (reg << 16) |
498 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
499 BNX2_EMAC_MDIO_COMM_START_BUSY;
500 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
501
502 for (i = 0; i < 50; i++) {
503 udelay(10);
504
505 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
506 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
507 udelay(5);
508
509 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
510 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
511
512 break;
513 }
514 }
515
516 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
517 *val = 0x0;
518 ret = -EBUSY;
519 }
520 else {
521 *val = val1;
522 ret = 0;
523 }
524
525 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
526 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
527 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
528
529 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
530 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
531
532 udelay(40);
533 }
534
535 return ret;
536 }
537
538 static int
539 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
540 {
541 u32 val1;
542 int i, ret;
543
544 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
545 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
546 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
547
548 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
549 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
550
551 udelay(40);
552 }
553
554 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
555 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
556 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
557 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
558
559 for (i = 0; i < 50; i++) {
560 udelay(10);
561
562 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
563 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
564 udelay(5);
565 break;
566 }
567 }
568
569 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
570 ret = -EBUSY;
571 else
572 ret = 0;
573
574 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
575 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
576 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
577
578 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
579 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
580
581 udelay(40);
582 }
583
584 return ret;
585 }
586
587 static void
588 bnx2_disable_int(struct bnx2 *bp)
589 {
590 int i;
591 struct bnx2_napi *bnapi;
592
593 for (i = 0; i < bp->irq_nvecs; i++) {
594 bnapi = &bp->bnx2_napi[i];
595 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
596 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
597 }
598 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
599 }
600
601 static void
602 bnx2_enable_int(struct bnx2 *bp)
603 {
604 int i;
605 struct bnx2_napi *bnapi;
606
607 for (i = 0; i < bp->irq_nvecs; i++) {
608 bnapi = &bp->bnx2_napi[i];
609
610 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
611 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
612 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
613 bnapi->last_status_idx);
614
615 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
617 bnapi->last_status_idx);
618 }
619 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
620 }
621
622 static void
623 bnx2_disable_int_sync(struct bnx2 *bp)
624 {
625 int i;
626
627 atomic_inc(&bp->intr_sem);
628 if (!netif_running(bp->dev))
629 return;
630
631 bnx2_disable_int(bp);
632 for (i = 0; i < bp->irq_nvecs; i++)
633 synchronize_irq(bp->irq_tbl[i].vector);
634 }
635
636 static void
637 bnx2_napi_disable(struct bnx2 *bp)
638 {
639 int i;
640
641 for (i = 0; i < bp->irq_nvecs; i++)
642 napi_disable(&bp->bnx2_napi[i].napi);
643 }
644
645 static void
646 bnx2_napi_enable(struct bnx2 *bp)
647 {
648 int i;
649
650 for (i = 0; i < bp->irq_nvecs; i++)
651 napi_enable(&bp->bnx2_napi[i].napi);
652 }
653
654 static void
655 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
656 {
657 if (stop_cnic)
658 bnx2_cnic_stop(bp);
659 if (netif_running(bp->dev)) {
660 bnx2_napi_disable(bp);
661 netif_tx_disable(bp->dev);
662 }
663 bnx2_disable_int_sync(bp);
664 netif_carrier_off(bp->dev); /* prevent tx timeout */
665 }
666
667 static void
668 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
669 {
670 if (atomic_dec_and_test(&bp->intr_sem)) {
671 if (netif_running(bp->dev)) {
672 netif_tx_wake_all_queues(bp->dev);
673 spin_lock_bh(&bp->phy_lock);
674 if (bp->link_up)
675 netif_carrier_on(bp->dev);
676 spin_unlock_bh(&bp->phy_lock);
677 bnx2_napi_enable(bp);
678 bnx2_enable_int(bp);
679 if (start_cnic)
680 bnx2_cnic_start(bp);
681 }
682 }
683 }
684
685 static void
686 bnx2_free_tx_mem(struct bnx2 *bp)
687 {
688 int i;
689
690 for (i = 0; i < bp->num_tx_rings; i++) {
691 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
692 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
693
694 if (txr->tx_desc_ring) {
695 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
696 txr->tx_desc_ring,
697 txr->tx_desc_mapping);
698 txr->tx_desc_ring = NULL;
699 }
700 kfree(txr->tx_buf_ring);
701 txr->tx_buf_ring = NULL;
702 }
703 }
704
705 static void
706 bnx2_free_rx_mem(struct bnx2 *bp)
707 {
708 int i;
709
710 for (i = 0; i < bp->num_rx_rings; i++) {
711 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
712 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
713 int j;
714
715 for (j = 0; j < bp->rx_max_ring; j++) {
716 if (rxr->rx_desc_ring[j])
717 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
718 rxr->rx_desc_ring[j],
719 rxr->rx_desc_mapping[j]);
720 rxr->rx_desc_ring[j] = NULL;
721 }
722 vfree(rxr->rx_buf_ring);
723 rxr->rx_buf_ring = NULL;
724
725 for (j = 0; j < bp->rx_max_pg_ring; j++) {
726 if (rxr->rx_pg_desc_ring[j])
727 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
728 rxr->rx_pg_desc_ring[j],
729 rxr->rx_pg_desc_mapping[j]);
730 rxr->rx_pg_desc_ring[j] = NULL;
731 }
732 vfree(rxr->rx_pg_ring);
733 rxr->rx_pg_ring = NULL;
734 }
735 }
736
737 static int
738 bnx2_alloc_tx_mem(struct bnx2 *bp)
739 {
740 int i;
741
742 for (i = 0; i < bp->num_tx_rings; i++) {
743 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
744 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
745
746 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
747 if (txr->tx_buf_ring == NULL)
748 return -ENOMEM;
749
750 txr->tx_desc_ring =
751 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
752 &txr->tx_desc_mapping, GFP_KERNEL);
753 if (txr->tx_desc_ring == NULL)
754 return -ENOMEM;
755 }
756 return 0;
757 }
758
759 static int
760 bnx2_alloc_rx_mem(struct bnx2 *bp)
761 {
762 int i;
763
764 for (i = 0; i < bp->num_rx_rings; i++) {
765 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
766 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
767 int j;
768
769 rxr->rx_buf_ring =
770 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
771 if (rxr->rx_buf_ring == NULL)
772 return -ENOMEM;
773
774 memset(rxr->rx_buf_ring, 0,
775 SW_RXBD_RING_SIZE * bp->rx_max_ring);
776
777 for (j = 0; j < bp->rx_max_ring; j++) {
778 rxr->rx_desc_ring[j] =
779 dma_alloc_coherent(&bp->pdev->dev,
780 RXBD_RING_SIZE,
781 &rxr->rx_desc_mapping[j],
782 GFP_KERNEL);
783 if (rxr->rx_desc_ring[j] == NULL)
784 return -ENOMEM;
785
786 }
787
788 if (bp->rx_pg_ring_size) {
789 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
790 bp->rx_max_pg_ring);
791 if (rxr->rx_pg_ring == NULL)
792 return -ENOMEM;
793
794 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
795 bp->rx_max_pg_ring);
796 }
797
798 for (j = 0; j < bp->rx_max_pg_ring; j++) {
799 rxr->rx_pg_desc_ring[j] =
800 dma_alloc_coherent(&bp->pdev->dev,
801 RXBD_RING_SIZE,
802 &rxr->rx_pg_desc_mapping[j],
803 GFP_KERNEL);
804 if (rxr->rx_pg_desc_ring[j] == NULL)
805 return -ENOMEM;
806
807 }
808 }
809 return 0;
810 }
811
812 static void
813 bnx2_free_mem(struct bnx2 *bp)
814 {
815 int i;
816 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
817
818 bnx2_free_tx_mem(bp);
819 bnx2_free_rx_mem(bp);
820
821 for (i = 0; i < bp->ctx_pages; i++) {
822 if (bp->ctx_blk[i]) {
823 dma_free_coherent(&bp->pdev->dev, BCM_PAGE_SIZE,
824 bp->ctx_blk[i],
825 bp->ctx_blk_mapping[i]);
826 bp->ctx_blk[i] = NULL;
827 }
828 }
829 if (bnapi->status_blk.msi) {
830 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
831 bnapi->status_blk.msi,
832 bp->status_blk_mapping);
833 bnapi->status_blk.msi = NULL;
834 bp->stats_blk = NULL;
835 }
836 }
837
838 static int
839 bnx2_alloc_mem(struct bnx2 *bp)
840 {
841 int i, status_blk_size, err;
842 struct bnx2_napi *bnapi;
843 void *status_blk;
844
845 /* Combine status and statistics blocks into one allocation. */
846 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
847 if (bp->flags & BNX2_FLAG_MSIX_CAP)
848 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
849 BNX2_SBLK_MSIX_ALIGN_SIZE);
850 bp->status_stats_size = status_blk_size +
851 sizeof(struct statistics_block);
852
853 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
854 &bp->status_blk_mapping, GFP_KERNEL);
855 if (status_blk == NULL)
856 goto alloc_mem_err;
857
858 memset(status_blk, 0, bp->status_stats_size);
859
860 bnapi = &bp->bnx2_napi[0];
861 bnapi->status_blk.msi = status_blk;
862 bnapi->hw_tx_cons_ptr =
863 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
864 bnapi->hw_rx_cons_ptr =
865 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
866 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
867 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
868 struct status_block_msix *sblk;
869
870 bnapi = &bp->bnx2_napi[i];
871
872 sblk = (void *) (status_blk +
873 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
874 bnapi->status_blk.msix = sblk;
875 bnapi->hw_tx_cons_ptr =
876 &sblk->status_tx_quick_consumer_index;
877 bnapi->hw_rx_cons_ptr =
878 &sblk->status_rx_quick_consumer_index;
879 bnapi->int_num = i << 24;
880 }
881 }
882
883 bp->stats_blk = status_blk + status_blk_size;
884
885 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
886
887 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
888 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
889 if (bp->ctx_pages == 0)
890 bp->ctx_pages = 1;
891 for (i = 0; i < bp->ctx_pages; i++) {
892 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
893 BCM_PAGE_SIZE,
894 &bp->ctx_blk_mapping[i],
895 GFP_KERNEL);
896 if (bp->ctx_blk[i] == NULL)
897 goto alloc_mem_err;
898 }
899 }
900
901 err = bnx2_alloc_rx_mem(bp);
902 if (err)
903 goto alloc_mem_err;
904
905 err = bnx2_alloc_tx_mem(bp);
906 if (err)
907 goto alloc_mem_err;
908
909 return 0;
910
911 alloc_mem_err:
912 bnx2_free_mem(bp);
913 return -ENOMEM;
914 }
915
916 static void
917 bnx2_report_fw_link(struct bnx2 *bp)
918 {
919 u32 fw_link_status = 0;
920
921 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
922 return;
923
924 if (bp->link_up) {
925 u32 bmsr;
926
927 switch (bp->line_speed) {
928 case SPEED_10:
929 if (bp->duplex == DUPLEX_HALF)
930 fw_link_status = BNX2_LINK_STATUS_10HALF;
931 else
932 fw_link_status = BNX2_LINK_STATUS_10FULL;
933 break;
934 case SPEED_100:
935 if (bp->duplex == DUPLEX_HALF)
936 fw_link_status = BNX2_LINK_STATUS_100HALF;
937 else
938 fw_link_status = BNX2_LINK_STATUS_100FULL;
939 break;
940 case SPEED_1000:
941 if (bp->duplex == DUPLEX_HALF)
942 fw_link_status = BNX2_LINK_STATUS_1000HALF;
943 else
944 fw_link_status = BNX2_LINK_STATUS_1000FULL;
945 break;
946 case SPEED_2500:
947 if (bp->duplex == DUPLEX_HALF)
948 fw_link_status = BNX2_LINK_STATUS_2500HALF;
949 else
950 fw_link_status = BNX2_LINK_STATUS_2500FULL;
951 break;
952 }
953
954 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
955
956 if (bp->autoneg) {
957 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
958
959 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
960 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
961
962 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
963 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
964 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
965 else
966 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
967 }
968 }
969 else
970 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
971
972 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
973 }
974
975 static char *
976 bnx2_xceiver_str(struct bnx2 *bp)
977 {
978 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
979 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
980 "Copper"));
981 }
982
983 static void
984 bnx2_report_link(struct bnx2 *bp)
985 {
986 if (bp->link_up) {
987 netif_carrier_on(bp->dev);
988 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
989 bnx2_xceiver_str(bp),
990 bp->line_speed,
991 bp->duplex == DUPLEX_FULL ? "full" : "half");
992
993 if (bp->flow_ctrl) {
994 if (bp->flow_ctrl & FLOW_CTRL_RX) {
995 pr_cont(", receive ");
996 if (bp->flow_ctrl & FLOW_CTRL_TX)
997 pr_cont("& transmit ");
998 }
999 else {
1000 pr_cont(", transmit ");
1001 }
1002 pr_cont("flow control ON");
1003 }
1004 pr_cont("\n");
1005 } else {
1006 netif_carrier_off(bp->dev);
1007 netdev_err(bp->dev, "NIC %s Link is Down\n",
1008 bnx2_xceiver_str(bp));
1009 }
1010
1011 bnx2_report_fw_link(bp);
1012 }
1013
1014 static void
1015 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1016 {
1017 u32 local_adv, remote_adv;
1018
1019 bp->flow_ctrl = 0;
1020 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1021 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1022
1023 if (bp->duplex == DUPLEX_FULL) {
1024 bp->flow_ctrl = bp->req_flow_ctrl;
1025 }
1026 return;
1027 }
1028
1029 if (bp->duplex != DUPLEX_FULL) {
1030 return;
1031 }
1032
1033 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1034 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1035 u32 val;
1036
1037 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1038 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1039 bp->flow_ctrl |= FLOW_CTRL_TX;
1040 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1041 bp->flow_ctrl |= FLOW_CTRL_RX;
1042 return;
1043 }
1044
1045 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1046 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1047
1048 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1049 u32 new_local_adv = 0;
1050 u32 new_remote_adv = 0;
1051
1052 if (local_adv & ADVERTISE_1000XPAUSE)
1053 new_local_adv |= ADVERTISE_PAUSE_CAP;
1054 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1055 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1056 if (remote_adv & ADVERTISE_1000XPAUSE)
1057 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1058 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1059 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1060
1061 local_adv = new_local_adv;
1062 remote_adv = new_remote_adv;
1063 }
1064
1065 /* See Table 28B-3 of 802.3ab-1999 spec. */
1066 if (local_adv & ADVERTISE_PAUSE_CAP) {
1067 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1068 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1069 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1070 }
1071 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1072 bp->flow_ctrl = FLOW_CTRL_RX;
1073 }
1074 }
1075 else {
1076 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1077 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1078 }
1079 }
1080 }
1081 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1082 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1083 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1084
1085 bp->flow_ctrl = FLOW_CTRL_TX;
1086 }
1087 }
1088 }
1089
1090 static int
1091 bnx2_5709s_linkup(struct bnx2 *bp)
1092 {
1093 u32 val, speed;
1094
1095 bp->link_up = 1;
1096
1097 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1098 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1099 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1100
1101 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1102 bp->line_speed = bp->req_line_speed;
1103 bp->duplex = bp->req_duplex;
1104 return 0;
1105 }
1106 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1107 switch (speed) {
1108 case MII_BNX2_GP_TOP_AN_SPEED_10:
1109 bp->line_speed = SPEED_10;
1110 break;
1111 case MII_BNX2_GP_TOP_AN_SPEED_100:
1112 bp->line_speed = SPEED_100;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1115 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1116 bp->line_speed = SPEED_1000;
1117 break;
1118 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1119 bp->line_speed = SPEED_2500;
1120 break;
1121 }
1122 if (val & MII_BNX2_GP_TOP_AN_FD)
1123 bp->duplex = DUPLEX_FULL;
1124 else
1125 bp->duplex = DUPLEX_HALF;
1126 return 0;
1127 }
1128
1129 static int
1130 bnx2_5708s_linkup(struct bnx2 *bp)
1131 {
1132 u32 val;
1133
1134 bp->link_up = 1;
1135 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1136 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1137 case BCM5708S_1000X_STAT1_SPEED_10:
1138 bp->line_speed = SPEED_10;
1139 break;
1140 case BCM5708S_1000X_STAT1_SPEED_100:
1141 bp->line_speed = SPEED_100;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_1G:
1144 bp->line_speed = SPEED_1000;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_2G5:
1147 bp->line_speed = SPEED_2500;
1148 break;
1149 }
1150 if (val & BCM5708S_1000X_STAT1_FD)
1151 bp->duplex = DUPLEX_FULL;
1152 else
1153 bp->duplex = DUPLEX_HALF;
1154
1155 return 0;
1156 }
1157
1158 static int
1159 bnx2_5706s_linkup(struct bnx2 *bp)
1160 {
1161 u32 bmcr, local_adv, remote_adv, common;
1162
1163 bp->link_up = 1;
1164 bp->line_speed = SPEED_1000;
1165
1166 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1167 if (bmcr & BMCR_FULLDPLX) {
1168 bp->duplex = DUPLEX_FULL;
1169 }
1170 else {
1171 bp->duplex = DUPLEX_HALF;
1172 }
1173
1174 if (!(bmcr & BMCR_ANENABLE)) {
1175 return 0;
1176 }
1177
1178 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1179 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1180
1181 common = local_adv & remote_adv;
1182 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1183
1184 if (common & ADVERTISE_1000XFULL) {
1185 bp->duplex = DUPLEX_FULL;
1186 }
1187 else {
1188 bp->duplex = DUPLEX_HALF;
1189 }
1190 }
1191
1192 return 0;
1193 }
1194
1195 static int
1196 bnx2_copper_linkup(struct bnx2 *bp)
1197 {
1198 u32 bmcr;
1199
1200 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1201 if (bmcr & BMCR_ANENABLE) {
1202 u32 local_adv, remote_adv, common;
1203
1204 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1205 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1206
1207 common = local_adv & (remote_adv >> 2);
1208 if (common & ADVERTISE_1000FULL) {
1209 bp->line_speed = SPEED_1000;
1210 bp->duplex = DUPLEX_FULL;
1211 }
1212 else if (common & ADVERTISE_1000HALF) {
1213 bp->line_speed = SPEED_1000;
1214 bp->duplex = DUPLEX_HALF;
1215 }
1216 else {
1217 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1218 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1219
1220 common = local_adv & remote_adv;
1221 if (common & ADVERTISE_100FULL) {
1222 bp->line_speed = SPEED_100;
1223 bp->duplex = DUPLEX_FULL;
1224 }
1225 else if (common & ADVERTISE_100HALF) {
1226 bp->line_speed = SPEED_100;
1227 bp->duplex = DUPLEX_HALF;
1228 }
1229 else if (common & ADVERTISE_10FULL) {
1230 bp->line_speed = SPEED_10;
1231 bp->duplex = DUPLEX_FULL;
1232 }
1233 else if (common & ADVERTISE_10HALF) {
1234 bp->line_speed = SPEED_10;
1235 bp->duplex = DUPLEX_HALF;
1236 }
1237 else {
1238 bp->line_speed = 0;
1239 bp->link_up = 0;
1240 }
1241 }
1242 }
1243 else {
1244 if (bmcr & BMCR_SPEED100) {
1245 bp->line_speed = SPEED_100;
1246 }
1247 else {
1248 bp->line_speed = SPEED_10;
1249 }
1250 if (bmcr & BMCR_FULLDPLX) {
1251 bp->duplex = DUPLEX_FULL;
1252 }
1253 else {
1254 bp->duplex = DUPLEX_HALF;
1255 }
1256 }
1257
1258 return 0;
1259 }
1260
1261 static void
1262 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1263 {
1264 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1265
1266 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1267 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1268 val |= 0x02 << 8;
1269
1270 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1271 u32 lo_water, hi_water;
1272
1273 if (bp->flow_ctrl & FLOW_CTRL_TX)
1274 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1275 else
1276 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1277 if (lo_water >= bp->rx_ring_size)
1278 lo_water = 0;
1279
1280 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
1281
1282 if (hi_water <= lo_water)
1283 lo_water = 0;
1284
1285 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1286 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1287
1288 if (hi_water > 0xf)
1289 hi_water = 0xf;
1290 else if (hi_water == 0)
1291 lo_water = 0;
1292 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1293 }
1294 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1295 }
1296
1297 static void
1298 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1299 {
1300 int i;
1301 u32 cid;
1302
1303 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1304 if (i == 1)
1305 cid = RX_RSS_CID;
1306 bnx2_init_rx_context(bp, cid);
1307 }
1308 }
1309
1310 static void
1311 bnx2_set_mac_link(struct bnx2 *bp)
1312 {
1313 u32 val;
1314
1315 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1316 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1317 (bp->duplex == DUPLEX_HALF)) {
1318 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1319 }
1320
1321 /* Configure the EMAC mode register. */
1322 val = REG_RD(bp, BNX2_EMAC_MODE);
1323
1324 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1325 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1326 BNX2_EMAC_MODE_25G_MODE);
1327
1328 if (bp->link_up) {
1329 switch (bp->line_speed) {
1330 case SPEED_10:
1331 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1332 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1333 break;
1334 }
1335 /* fall through */
1336 case SPEED_100:
1337 val |= BNX2_EMAC_MODE_PORT_MII;
1338 break;
1339 case SPEED_2500:
1340 val |= BNX2_EMAC_MODE_25G_MODE;
1341 /* fall through */
1342 case SPEED_1000:
1343 val |= BNX2_EMAC_MODE_PORT_GMII;
1344 break;
1345 }
1346 }
1347 else {
1348 val |= BNX2_EMAC_MODE_PORT_GMII;
1349 }
1350
1351 /* Set the MAC to operate in the appropriate duplex mode. */
1352 if (bp->duplex == DUPLEX_HALF)
1353 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1354 REG_WR(bp, BNX2_EMAC_MODE, val);
1355
1356 /* Enable/disable rx PAUSE. */
1357 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1358
1359 if (bp->flow_ctrl & FLOW_CTRL_RX)
1360 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1361 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1362
1363 /* Enable/disable tx PAUSE. */
1364 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1365 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1366
1367 if (bp->flow_ctrl & FLOW_CTRL_TX)
1368 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1369 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1370
1371 /* Acknowledge the interrupt. */
1372 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1373
1374 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1375 bnx2_init_all_rx_contexts(bp);
1376 }
1377
1378 static void
1379 bnx2_enable_bmsr1(struct bnx2 *bp)
1380 {
1381 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1382 (CHIP_NUM(bp) == CHIP_NUM_5709))
1383 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1384 MII_BNX2_BLK_ADDR_GP_STATUS);
1385 }
1386
1387 static void
1388 bnx2_disable_bmsr1(struct bnx2 *bp)
1389 {
1390 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1391 (CHIP_NUM(bp) == CHIP_NUM_5709))
1392 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1393 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1394 }
1395
1396 static int
1397 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1398 {
1399 u32 up1;
1400 int ret = 1;
1401
1402 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1403 return 0;
1404
1405 if (bp->autoneg & AUTONEG_SPEED)
1406 bp->advertising |= ADVERTISED_2500baseX_Full;
1407
1408 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1409 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1410
1411 bnx2_read_phy(bp, bp->mii_up1, &up1);
1412 if (!(up1 & BCM5708S_UP1_2G5)) {
1413 up1 |= BCM5708S_UP1_2G5;
1414 bnx2_write_phy(bp, bp->mii_up1, up1);
1415 ret = 0;
1416 }
1417
1418 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1419 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1420 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1421
1422 return ret;
1423 }
1424
1425 static int
1426 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1427 {
1428 u32 up1;
1429 int ret = 0;
1430
1431 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1432 return 0;
1433
1434 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1435 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1436
1437 bnx2_read_phy(bp, bp->mii_up1, &up1);
1438 if (up1 & BCM5708S_UP1_2G5) {
1439 up1 &= ~BCM5708S_UP1_2G5;
1440 bnx2_write_phy(bp, bp->mii_up1, up1);
1441 ret = 1;
1442 }
1443
1444 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1445 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1446 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1447
1448 return ret;
1449 }
1450
1451 static void
1452 bnx2_enable_forced_2g5(struct bnx2 *bp)
1453 {
1454 u32 uninitialized_var(bmcr);
1455 int err;
1456
1457 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1458 return;
1459
1460 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1461 u32 val;
1462
1463 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1464 MII_BNX2_BLK_ADDR_SERDES_DIG);
1465 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1466 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1467 val |= MII_BNX2_SD_MISC1_FORCE |
1468 MII_BNX2_SD_MISC1_FORCE_2_5G;
1469 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1470 }
1471
1472 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1473 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1474 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1475
1476 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1477 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1478 if (!err)
1479 bmcr |= BCM5708S_BMCR_FORCE_2500;
1480 } else {
1481 return;
1482 }
1483
1484 if (err)
1485 return;
1486
1487 if (bp->autoneg & AUTONEG_SPEED) {
1488 bmcr &= ~BMCR_ANENABLE;
1489 if (bp->req_duplex == DUPLEX_FULL)
1490 bmcr |= BMCR_FULLDPLX;
1491 }
1492 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1493 }
1494
1495 static void
1496 bnx2_disable_forced_2g5(struct bnx2 *bp)
1497 {
1498 u32 uninitialized_var(bmcr);
1499 int err;
1500
1501 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1502 return;
1503
1504 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1505 u32 val;
1506
1507 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1508 MII_BNX2_BLK_ADDR_SERDES_DIG);
1509 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1510 val &= ~MII_BNX2_SD_MISC1_FORCE;
1511 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1512 }
1513
1514 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1515 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1516 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1517
1518 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1519 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1520 if (!err)
1521 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1522 } else {
1523 return;
1524 }
1525
1526 if (err)
1527 return;
1528
1529 if (bp->autoneg & AUTONEG_SPEED)
1530 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1531 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1532 }
1533
1534 static void
1535 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1536 {
1537 u32 val;
1538
1539 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1540 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1541 if (start)
1542 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1543 else
1544 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1545 }
1546
1547 static int
1548 bnx2_set_link(struct bnx2 *bp)
1549 {
1550 u32 bmsr;
1551 u8 link_up;
1552
1553 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1554 bp->link_up = 1;
1555 return 0;
1556 }
1557
1558 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1559 return 0;
1560
1561 link_up = bp->link_up;
1562
1563 bnx2_enable_bmsr1(bp);
1564 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1565 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1566 bnx2_disable_bmsr1(bp);
1567
1568 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1569 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1570 u32 val, an_dbg;
1571
1572 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1573 bnx2_5706s_force_link_dn(bp, 0);
1574 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1575 }
1576 val = REG_RD(bp, BNX2_EMAC_STATUS);
1577
1578 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1579 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1580 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1581
1582 if ((val & BNX2_EMAC_STATUS_LINK) &&
1583 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1584 bmsr |= BMSR_LSTATUS;
1585 else
1586 bmsr &= ~BMSR_LSTATUS;
1587 }
1588
1589 if (bmsr & BMSR_LSTATUS) {
1590 bp->link_up = 1;
1591
1592 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1593 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1594 bnx2_5706s_linkup(bp);
1595 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1596 bnx2_5708s_linkup(bp);
1597 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1598 bnx2_5709s_linkup(bp);
1599 }
1600 else {
1601 bnx2_copper_linkup(bp);
1602 }
1603 bnx2_resolve_flow_ctrl(bp);
1604 }
1605 else {
1606 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1607 (bp->autoneg & AUTONEG_SPEED))
1608 bnx2_disable_forced_2g5(bp);
1609
1610 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1611 u32 bmcr;
1612
1613 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1614 bmcr |= BMCR_ANENABLE;
1615 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1616
1617 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1618 }
1619 bp->link_up = 0;
1620 }
1621
1622 if (bp->link_up != link_up) {
1623 bnx2_report_link(bp);
1624 }
1625
1626 bnx2_set_mac_link(bp);
1627
1628 return 0;
1629 }
1630
1631 static int
1632 bnx2_reset_phy(struct bnx2 *bp)
1633 {
1634 int i;
1635 u32 reg;
1636
1637 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1638
1639 #define PHY_RESET_MAX_WAIT 100
1640 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1641 udelay(10);
1642
1643 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1644 if (!(reg & BMCR_RESET)) {
1645 udelay(20);
1646 break;
1647 }
1648 }
1649 if (i == PHY_RESET_MAX_WAIT) {
1650 return -EBUSY;
1651 }
1652 return 0;
1653 }
1654
1655 static u32
1656 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1657 {
1658 u32 adv = 0;
1659
1660 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1661 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1662
1663 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1664 adv = ADVERTISE_1000XPAUSE;
1665 }
1666 else {
1667 adv = ADVERTISE_PAUSE_CAP;
1668 }
1669 }
1670 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1671 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1672 adv = ADVERTISE_1000XPSE_ASYM;
1673 }
1674 else {
1675 adv = ADVERTISE_PAUSE_ASYM;
1676 }
1677 }
1678 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1679 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1680 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1681 }
1682 else {
1683 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1684 }
1685 }
1686 return adv;
1687 }
1688
1689 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1690
1691 static int
1692 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1693 __releases(&bp->phy_lock)
1694 __acquires(&bp->phy_lock)
1695 {
1696 u32 speed_arg = 0, pause_adv;
1697
1698 pause_adv = bnx2_phy_get_pause_adv(bp);
1699
1700 if (bp->autoneg & AUTONEG_SPEED) {
1701 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1702 if (bp->advertising & ADVERTISED_10baseT_Half)
1703 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1704 if (bp->advertising & ADVERTISED_10baseT_Full)
1705 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1706 if (bp->advertising & ADVERTISED_100baseT_Half)
1707 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1708 if (bp->advertising & ADVERTISED_100baseT_Full)
1709 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1710 if (bp->advertising & ADVERTISED_1000baseT_Full)
1711 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1712 if (bp->advertising & ADVERTISED_2500baseX_Full)
1713 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1714 } else {
1715 if (bp->req_line_speed == SPEED_2500)
1716 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1717 else if (bp->req_line_speed == SPEED_1000)
1718 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1719 else if (bp->req_line_speed == SPEED_100) {
1720 if (bp->req_duplex == DUPLEX_FULL)
1721 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1722 else
1723 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1724 } else if (bp->req_line_speed == SPEED_10) {
1725 if (bp->req_duplex == DUPLEX_FULL)
1726 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1727 else
1728 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1729 }
1730 }
1731
1732 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1733 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1734 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1735 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1736
1737 if (port == PORT_TP)
1738 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1739 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1740
1741 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1742
1743 spin_unlock_bh(&bp->phy_lock);
1744 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1745 spin_lock_bh(&bp->phy_lock);
1746
1747 return 0;
1748 }
1749
1750 static int
1751 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1752 __releases(&bp->phy_lock)
1753 __acquires(&bp->phy_lock)
1754 {
1755 u32 adv, bmcr;
1756 u32 new_adv = 0;
1757
1758 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1759 return (bnx2_setup_remote_phy(bp, port));
1760
1761 if (!(bp->autoneg & AUTONEG_SPEED)) {
1762 u32 new_bmcr;
1763 int force_link_down = 0;
1764
1765 if (bp->req_line_speed == SPEED_2500) {
1766 if (!bnx2_test_and_enable_2g5(bp))
1767 force_link_down = 1;
1768 } else if (bp->req_line_speed == SPEED_1000) {
1769 if (bnx2_test_and_disable_2g5(bp))
1770 force_link_down = 1;
1771 }
1772 bnx2_read_phy(bp, bp->mii_adv, &adv);
1773 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1774
1775 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1776 new_bmcr = bmcr & ~BMCR_ANENABLE;
1777 new_bmcr |= BMCR_SPEED1000;
1778
1779 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1780 if (bp->req_line_speed == SPEED_2500)
1781 bnx2_enable_forced_2g5(bp);
1782 else if (bp->req_line_speed == SPEED_1000) {
1783 bnx2_disable_forced_2g5(bp);
1784 new_bmcr &= ~0x2000;
1785 }
1786
1787 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1788 if (bp->req_line_speed == SPEED_2500)
1789 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1790 else
1791 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1792 }
1793
1794 if (bp->req_duplex == DUPLEX_FULL) {
1795 adv |= ADVERTISE_1000XFULL;
1796 new_bmcr |= BMCR_FULLDPLX;
1797 }
1798 else {
1799 adv |= ADVERTISE_1000XHALF;
1800 new_bmcr &= ~BMCR_FULLDPLX;
1801 }
1802 if ((new_bmcr != bmcr) || (force_link_down)) {
1803 /* Force a link down visible on the other side */
1804 if (bp->link_up) {
1805 bnx2_write_phy(bp, bp->mii_adv, adv &
1806 ~(ADVERTISE_1000XFULL |
1807 ADVERTISE_1000XHALF));
1808 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1809 BMCR_ANRESTART | BMCR_ANENABLE);
1810
1811 bp->link_up = 0;
1812 netif_carrier_off(bp->dev);
1813 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1814 bnx2_report_link(bp);
1815 }
1816 bnx2_write_phy(bp, bp->mii_adv, adv);
1817 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1818 } else {
1819 bnx2_resolve_flow_ctrl(bp);
1820 bnx2_set_mac_link(bp);
1821 }
1822 return 0;
1823 }
1824
1825 bnx2_test_and_enable_2g5(bp);
1826
1827 if (bp->advertising & ADVERTISED_1000baseT_Full)
1828 new_adv |= ADVERTISE_1000XFULL;
1829
1830 new_adv |= bnx2_phy_get_pause_adv(bp);
1831
1832 bnx2_read_phy(bp, bp->mii_adv, &adv);
1833 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1834
1835 bp->serdes_an_pending = 0;
1836 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1837 /* Force a link down visible on the other side */
1838 if (bp->link_up) {
1839 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1840 spin_unlock_bh(&bp->phy_lock);
1841 msleep(20);
1842 spin_lock_bh(&bp->phy_lock);
1843 }
1844
1845 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1846 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1847 BMCR_ANENABLE);
1848 /* Speed up link-up time when the link partner
1849 * does not autonegotiate which is very common
1850 * in blade servers. Some blade servers use
1851 * IPMI for kerboard input and it's important
1852 * to minimize link disruptions. Autoneg. involves
1853 * exchanging base pages plus 3 next pages and
1854 * normally completes in about 120 msec.
1855 */
1856 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1857 bp->serdes_an_pending = 1;
1858 mod_timer(&bp->timer, jiffies + bp->current_interval);
1859 } else {
1860 bnx2_resolve_flow_ctrl(bp);
1861 bnx2_set_mac_link(bp);
1862 }
1863
1864 return 0;
1865 }
1866
1867 #define ETHTOOL_ALL_FIBRE_SPEED \
1868 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1869 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1870 (ADVERTISED_1000baseT_Full)
1871
1872 #define ETHTOOL_ALL_COPPER_SPEED \
1873 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1874 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1875 ADVERTISED_1000baseT_Full)
1876
1877 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1878 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1879
1880 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1881
1882 static void
1883 bnx2_set_default_remote_link(struct bnx2 *bp)
1884 {
1885 u32 link;
1886
1887 if (bp->phy_port == PORT_TP)
1888 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1889 else
1890 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1891
1892 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1893 bp->req_line_speed = 0;
1894 bp->autoneg |= AUTONEG_SPEED;
1895 bp->advertising = ADVERTISED_Autoneg;
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1897 bp->advertising |= ADVERTISED_10baseT_Half;
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1899 bp->advertising |= ADVERTISED_10baseT_Full;
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1901 bp->advertising |= ADVERTISED_100baseT_Half;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1903 bp->advertising |= ADVERTISED_100baseT_Full;
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1905 bp->advertising |= ADVERTISED_1000baseT_Full;
1906 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1907 bp->advertising |= ADVERTISED_2500baseX_Full;
1908 } else {
1909 bp->autoneg = 0;
1910 bp->advertising = 0;
1911 bp->req_duplex = DUPLEX_FULL;
1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1913 bp->req_line_speed = SPEED_10;
1914 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1915 bp->req_duplex = DUPLEX_HALF;
1916 }
1917 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1918 bp->req_line_speed = SPEED_100;
1919 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1920 bp->req_duplex = DUPLEX_HALF;
1921 }
1922 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1923 bp->req_line_speed = SPEED_1000;
1924 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1925 bp->req_line_speed = SPEED_2500;
1926 }
1927 }
1928
1929 static void
1930 bnx2_set_default_link(struct bnx2 *bp)
1931 {
1932 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1933 bnx2_set_default_remote_link(bp);
1934 return;
1935 }
1936
1937 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1938 bp->req_line_speed = 0;
1939 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1940 u32 reg;
1941
1942 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1943
1944 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1945 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1946 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1947 bp->autoneg = 0;
1948 bp->req_line_speed = bp->line_speed = SPEED_1000;
1949 bp->req_duplex = DUPLEX_FULL;
1950 }
1951 } else
1952 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1953 }
1954
1955 static void
1956 bnx2_send_heart_beat(struct bnx2 *bp)
1957 {
1958 u32 msg;
1959 u32 addr;
1960
1961 spin_lock(&bp->indirect_lock);
1962 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1963 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1964 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1965 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1966 spin_unlock(&bp->indirect_lock);
1967 }
1968
1969 static void
1970 bnx2_remote_phy_event(struct bnx2 *bp)
1971 {
1972 u32 msg;
1973 u8 link_up = bp->link_up;
1974 u8 old_port;
1975
1976 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1977
1978 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1979 bnx2_send_heart_beat(bp);
1980
1981 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1982
1983 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1984 bp->link_up = 0;
1985 else {
1986 u32 speed;
1987
1988 bp->link_up = 1;
1989 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1990 bp->duplex = DUPLEX_FULL;
1991 switch (speed) {
1992 case BNX2_LINK_STATUS_10HALF:
1993 bp->duplex = DUPLEX_HALF;
1994 case BNX2_LINK_STATUS_10FULL:
1995 bp->line_speed = SPEED_10;
1996 break;
1997 case BNX2_LINK_STATUS_100HALF:
1998 bp->duplex = DUPLEX_HALF;
1999 case BNX2_LINK_STATUS_100BASE_T4:
2000 case BNX2_LINK_STATUS_100FULL:
2001 bp->line_speed = SPEED_100;
2002 break;
2003 case BNX2_LINK_STATUS_1000HALF:
2004 bp->duplex = DUPLEX_HALF;
2005 case BNX2_LINK_STATUS_1000FULL:
2006 bp->line_speed = SPEED_1000;
2007 break;
2008 case BNX2_LINK_STATUS_2500HALF:
2009 bp->duplex = DUPLEX_HALF;
2010 case BNX2_LINK_STATUS_2500FULL:
2011 bp->line_speed = SPEED_2500;
2012 break;
2013 default:
2014 bp->line_speed = 0;
2015 break;
2016 }
2017
2018 bp->flow_ctrl = 0;
2019 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2020 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2021 if (bp->duplex == DUPLEX_FULL)
2022 bp->flow_ctrl = bp->req_flow_ctrl;
2023 } else {
2024 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2025 bp->flow_ctrl |= FLOW_CTRL_TX;
2026 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2027 bp->flow_ctrl |= FLOW_CTRL_RX;
2028 }
2029
2030 old_port = bp->phy_port;
2031 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2032 bp->phy_port = PORT_FIBRE;
2033 else
2034 bp->phy_port = PORT_TP;
2035
2036 if (old_port != bp->phy_port)
2037 bnx2_set_default_link(bp);
2038
2039 }
2040 if (bp->link_up != link_up)
2041 bnx2_report_link(bp);
2042
2043 bnx2_set_mac_link(bp);
2044 }
2045
2046 static int
2047 bnx2_set_remote_link(struct bnx2 *bp)
2048 {
2049 u32 evt_code;
2050
2051 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2052 switch (evt_code) {
2053 case BNX2_FW_EVT_CODE_LINK_EVENT:
2054 bnx2_remote_phy_event(bp);
2055 break;
2056 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2057 default:
2058 bnx2_send_heart_beat(bp);
2059 break;
2060 }
2061 return 0;
2062 }
2063
2064 static int
2065 bnx2_setup_copper_phy(struct bnx2 *bp)
2066 __releases(&bp->phy_lock)
2067 __acquires(&bp->phy_lock)
2068 {
2069 u32 bmcr;
2070 u32 new_bmcr;
2071
2072 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2073
2074 if (bp->autoneg & AUTONEG_SPEED) {
2075 u32 adv_reg, adv1000_reg;
2076 u32 new_adv_reg = 0;
2077 u32 new_adv1000_reg = 0;
2078
2079 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2080 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2081 ADVERTISE_PAUSE_ASYM);
2082
2083 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2084 adv1000_reg &= PHY_ALL_1000_SPEED;
2085
2086 if (bp->advertising & ADVERTISED_10baseT_Half)
2087 new_adv_reg |= ADVERTISE_10HALF;
2088 if (bp->advertising & ADVERTISED_10baseT_Full)
2089 new_adv_reg |= ADVERTISE_10FULL;
2090 if (bp->advertising & ADVERTISED_100baseT_Half)
2091 new_adv_reg |= ADVERTISE_100HALF;
2092 if (bp->advertising & ADVERTISED_100baseT_Full)
2093 new_adv_reg |= ADVERTISE_100FULL;
2094 if (bp->advertising & ADVERTISED_1000baseT_Full)
2095 new_adv1000_reg |= ADVERTISE_1000FULL;
2096
2097 new_adv_reg |= ADVERTISE_CSMA;
2098
2099 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2100
2101 if ((adv1000_reg != new_adv1000_reg) ||
2102 (adv_reg != new_adv_reg) ||
2103 ((bmcr & BMCR_ANENABLE) == 0)) {
2104
2105 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2106 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2107 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2108 BMCR_ANENABLE);
2109 }
2110 else if (bp->link_up) {
2111 /* Flow ctrl may have changed from auto to forced */
2112 /* or vice-versa. */
2113
2114 bnx2_resolve_flow_ctrl(bp);
2115 bnx2_set_mac_link(bp);
2116 }
2117 return 0;
2118 }
2119
2120 new_bmcr = 0;
2121 if (bp->req_line_speed == SPEED_100) {
2122 new_bmcr |= BMCR_SPEED100;
2123 }
2124 if (bp->req_duplex == DUPLEX_FULL) {
2125 new_bmcr |= BMCR_FULLDPLX;
2126 }
2127 if (new_bmcr != bmcr) {
2128 u32 bmsr;
2129
2130 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2131 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2132
2133 if (bmsr & BMSR_LSTATUS) {
2134 /* Force link down */
2135 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2136 spin_unlock_bh(&bp->phy_lock);
2137 msleep(50);
2138 spin_lock_bh(&bp->phy_lock);
2139
2140 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2141 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2142 }
2143
2144 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2145
2146 /* Normally, the new speed is setup after the link has
2147 * gone down and up again. In some cases, link will not go
2148 * down so we need to set up the new speed here.
2149 */
2150 if (bmsr & BMSR_LSTATUS) {
2151 bp->line_speed = bp->req_line_speed;
2152 bp->duplex = bp->req_duplex;
2153 bnx2_resolve_flow_ctrl(bp);
2154 bnx2_set_mac_link(bp);
2155 }
2156 } else {
2157 bnx2_resolve_flow_ctrl(bp);
2158 bnx2_set_mac_link(bp);
2159 }
2160 return 0;
2161 }
2162
2163 static int
2164 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2165 __releases(&bp->phy_lock)
2166 __acquires(&bp->phy_lock)
2167 {
2168 if (bp->loopback == MAC_LOOPBACK)
2169 return 0;
2170
2171 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2172 return (bnx2_setup_serdes_phy(bp, port));
2173 }
2174 else {
2175 return (bnx2_setup_copper_phy(bp));
2176 }
2177 }
2178
2179 static int
2180 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2181 {
2182 u32 val;
2183
2184 bp->mii_bmcr = MII_BMCR + 0x10;
2185 bp->mii_bmsr = MII_BMSR + 0x10;
2186 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2187 bp->mii_adv = MII_ADVERTISE + 0x10;
2188 bp->mii_lpa = MII_LPA + 0x10;
2189 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2190
2191 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2192 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2193
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2195 if (reset_phy)
2196 bnx2_reset_phy(bp);
2197
2198 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2199
2200 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2201 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2202 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2203 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2204
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2206 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2207 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2208 val |= BCM5708S_UP1_2G5;
2209 else
2210 val &= ~BCM5708S_UP1_2G5;
2211 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2212
2213 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2214 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2215 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2216 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2217
2218 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2219
2220 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2221 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2222 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2223
2224 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2225
2226 return 0;
2227 }
2228
2229 static int
2230 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2231 {
2232 u32 val;
2233
2234 if (reset_phy)
2235 bnx2_reset_phy(bp);
2236
2237 bp->mii_up1 = BCM5708S_UP1;
2238
2239 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2240 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2241 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2242
2243 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2244 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2245 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2246
2247 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2248 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2249 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2250
2251 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2252 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2253 val |= BCM5708S_UP1_2G5;
2254 bnx2_write_phy(bp, BCM5708S_UP1, val);
2255 }
2256
2257 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2258 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2259 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2260 /* increase tx signal amplitude */
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2262 BCM5708S_BLK_ADDR_TX_MISC);
2263 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2264 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2265 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2266 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2267 }
2268
2269 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2270 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2271
2272 if (val) {
2273 u32 is_backplane;
2274
2275 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2276 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2277 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2278 BCM5708S_BLK_ADDR_TX_MISC);
2279 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2280 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2281 BCM5708S_BLK_ADDR_DIG);
2282 }
2283 }
2284 return 0;
2285 }
2286
2287 static int
2288 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2289 {
2290 if (reset_phy)
2291 bnx2_reset_phy(bp);
2292
2293 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2294
2295 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2296 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2297
2298 if (bp->dev->mtu > 1500) {
2299 u32 val;
2300
2301 /* Set extended packet length bit */
2302 bnx2_write_phy(bp, 0x18, 0x7);
2303 bnx2_read_phy(bp, 0x18, &val);
2304 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2305
2306 bnx2_write_phy(bp, 0x1c, 0x6c00);
2307 bnx2_read_phy(bp, 0x1c, &val);
2308 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2309 }
2310 else {
2311 u32 val;
2312
2313 bnx2_write_phy(bp, 0x18, 0x7);
2314 bnx2_read_phy(bp, 0x18, &val);
2315 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2316
2317 bnx2_write_phy(bp, 0x1c, 0x6c00);
2318 bnx2_read_phy(bp, 0x1c, &val);
2319 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2320 }
2321
2322 return 0;
2323 }
2324
2325 static int
2326 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2327 {
2328 u32 val;
2329
2330 if (reset_phy)
2331 bnx2_reset_phy(bp);
2332
2333 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2334 bnx2_write_phy(bp, 0x18, 0x0c00);
2335 bnx2_write_phy(bp, 0x17, 0x000a);
2336 bnx2_write_phy(bp, 0x15, 0x310b);
2337 bnx2_write_phy(bp, 0x17, 0x201f);
2338 bnx2_write_phy(bp, 0x15, 0x9506);
2339 bnx2_write_phy(bp, 0x17, 0x401f);
2340 bnx2_write_phy(bp, 0x15, 0x14e2);
2341 bnx2_write_phy(bp, 0x18, 0x0400);
2342 }
2343
2344 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2345 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2346 MII_BNX2_DSP_EXPAND_REG | 0x8);
2347 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2348 val &= ~(1 << 8);
2349 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2350 }
2351
2352 if (bp->dev->mtu > 1500) {
2353 /* Set extended packet length bit */
2354 bnx2_write_phy(bp, 0x18, 0x7);
2355 bnx2_read_phy(bp, 0x18, &val);
2356 bnx2_write_phy(bp, 0x18, val | 0x4000);
2357
2358 bnx2_read_phy(bp, 0x10, &val);
2359 bnx2_write_phy(bp, 0x10, val | 0x1);
2360 }
2361 else {
2362 bnx2_write_phy(bp, 0x18, 0x7);
2363 bnx2_read_phy(bp, 0x18, &val);
2364 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2365
2366 bnx2_read_phy(bp, 0x10, &val);
2367 bnx2_write_phy(bp, 0x10, val & ~0x1);
2368 }
2369
2370 /* ethernet@wirespeed */
2371 bnx2_write_phy(bp, 0x18, 0x7007);
2372 bnx2_read_phy(bp, 0x18, &val);
2373 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2374 return 0;
2375 }
2376
2377
2378 static int
2379 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2380 __releases(&bp->phy_lock)
2381 __acquires(&bp->phy_lock)
2382 {
2383 u32 val;
2384 int rc = 0;
2385
2386 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2387 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2388
2389 bp->mii_bmcr = MII_BMCR;
2390 bp->mii_bmsr = MII_BMSR;
2391 bp->mii_bmsr1 = MII_BMSR;
2392 bp->mii_adv = MII_ADVERTISE;
2393 bp->mii_lpa = MII_LPA;
2394
2395 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2396
2397 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2398 goto setup_phy;
2399
2400 bnx2_read_phy(bp, MII_PHYSID1, &val);
2401 bp->phy_id = val << 16;
2402 bnx2_read_phy(bp, MII_PHYSID2, &val);
2403 bp->phy_id |= val & 0xffff;
2404
2405 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2406 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2407 rc = bnx2_init_5706s_phy(bp, reset_phy);
2408 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2409 rc = bnx2_init_5708s_phy(bp, reset_phy);
2410 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2411 rc = bnx2_init_5709s_phy(bp, reset_phy);
2412 }
2413 else {
2414 rc = bnx2_init_copper_phy(bp, reset_phy);
2415 }
2416
2417 setup_phy:
2418 if (!rc)
2419 rc = bnx2_setup_phy(bp, bp->phy_port);
2420
2421 return rc;
2422 }
2423
2424 static int
2425 bnx2_set_mac_loopback(struct bnx2 *bp)
2426 {
2427 u32 mac_mode;
2428
2429 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2430 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2431 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2432 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2433 bp->link_up = 1;
2434 return 0;
2435 }
2436
2437 static int bnx2_test_link(struct bnx2 *);
2438
2439 static int
2440 bnx2_set_phy_loopback(struct bnx2 *bp)
2441 {
2442 u32 mac_mode;
2443 int rc, i;
2444
2445 spin_lock_bh(&bp->phy_lock);
2446 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2447 BMCR_SPEED1000);
2448 spin_unlock_bh(&bp->phy_lock);
2449 if (rc)
2450 return rc;
2451
2452 for (i = 0; i < 10; i++) {
2453 if (bnx2_test_link(bp) == 0)
2454 break;
2455 msleep(100);
2456 }
2457
2458 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2459 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2460 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2461 BNX2_EMAC_MODE_25G_MODE);
2462
2463 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2464 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2465 bp->link_up = 1;
2466 return 0;
2467 }
2468
2469 static int
2470 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2471 {
2472 int i;
2473 u32 val;
2474
2475 bp->fw_wr_seq++;
2476 msg_data |= bp->fw_wr_seq;
2477
2478 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2479
2480 if (!ack)
2481 return 0;
2482
2483 /* wait for an acknowledgement. */
2484 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2485 msleep(10);
2486
2487 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2488
2489 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2490 break;
2491 }
2492 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2493 return 0;
2494
2495 /* If we timed out, inform the firmware that this is the case. */
2496 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2497 if (!silent)
2498 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2499
2500 msg_data &= ~BNX2_DRV_MSG_CODE;
2501 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2502
2503 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2504
2505 return -EBUSY;
2506 }
2507
2508 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2509 return -EIO;
2510
2511 return 0;
2512 }
2513
2514 static int
2515 bnx2_init_5709_context(struct bnx2 *bp)
2516 {
2517 int i, ret = 0;
2518 u32 val;
2519
2520 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2521 val |= (BCM_PAGE_BITS - 8) << 16;
2522 REG_WR(bp, BNX2_CTX_COMMAND, val);
2523 for (i = 0; i < 10; i++) {
2524 val = REG_RD(bp, BNX2_CTX_COMMAND);
2525 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2526 break;
2527 udelay(2);
2528 }
2529 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2530 return -EBUSY;
2531
2532 for (i = 0; i < bp->ctx_pages; i++) {
2533 int j;
2534
2535 if (bp->ctx_blk[i])
2536 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2537 else
2538 return -ENOMEM;
2539
2540 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2541 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2542 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2543 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2544 (u64) bp->ctx_blk_mapping[i] >> 32);
2545 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2546 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2547 for (j = 0; j < 10; j++) {
2548
2549 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2550 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2551 break;
2552 udelay(5);
2553 }
2554 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2555 ret = -EBUSY;
2556 break;
2557 }
2558 }
2559 return ret;
2560 }
2561
2562 static void
2563 bnx2_init_context(struct bnx2 *bp)
2564 {
2565 u32 vcid;
2566
2567 vcid = 96;
2568 while (vcid) {
2569 u32 vcid_addr, pcid_addr, offset;
2570 int i;
2571
2572 vcid--;
2573
2574 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2575 u32 new_vcid;
2576
2577 vcid_addr = GET_PCID_ADDR(vcid);
2578 if (vcid & 0x8) {
2579 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2580 }
2581 else {
2582 new_vcid = vcid;
2583 }
2584 pcid_addr = GET_PCID_ADDR(new_vcid);
2585 }
2586 else {
2587 vcid_addr = GET_CID_ADDR(vcid);
2588 pcid_addr = vcid_addr;
2589 }
2590
2591 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2592 vcid_addr += (i << PHY_CTX_SHIFT);
2593 pcid_addr += (i << PHY_CTX_SHIFT);
2594
2595 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2596 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2597
2598 /* Zero out the context. */
2599 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2600 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2601 }
2602 }
2603 }
2604
2605 static int
2606 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2607 {
2608 u16 *good_mbuf;
2609 u32 good_mbuf_cnt;
2610 u32 val;
2611
2612 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2613 if (good_mbuf == NULL) {
2614 pr_err("Failed to allocate memory in %s\n", __func__);
2615 return -ENOMEM;
2616 }
2617
2618 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2619 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2620
2621 good_mbuf_cnt = 0;
2622
2623 /* Allocate a bunch of mbufs and save the good ones in an array. */
2624 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2625 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2626 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2627 BNX2_RBUF_COMMAND_ALLOC_REQ);
2628
2629 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2630
2631 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2632
2633 /* The addresses with Bit 9 set are bad memory blocks. */
2634 if (!(val & (1 << 9))) {
2635 good_mbuf[good_mbuf_cnt] = (u16) val;
2636 good_mbuf_cnt++;
2637 }
2638
2639 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2640 }
2641
2642 /* Free the good ones back to the mbuf pool thus discarding
2643 * all the bad ones. */
2644 while (good_mbuf_cnt) {
2645 good_mbuf_cnt--;
2646
2647 val = good_mbuf[good_mbuf_cnt];
2648 val = (val << 9) | val | 1;
2649
2650 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2651 }
2652 kfree(good_mbuf);
2653 return 0;
2654 }
2655
2656 static void
2657 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2658 {
2659 u32 val;
2660
2661 val = (mac_addr[0] << 8) | mac_addr[1];
2662
2663 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2664
2665 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2666 (mac_addr[4] << 8) | mac_addr[5];
2667
2668 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2669 }
2670
2671 static inline int
2672 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2673 {
2674 dma_addr_t mapping;
2675 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2676 struct rx_bd *rxbd =
2677 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2678 struct page *page = alloc_page(gfp);
2679
2680 if (!page)
2681 return -ENOMEM;
2682 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
2683 PCI_DMA_FROMDEVICE);
2684 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2685 __free_page(page);
2686 return -EIO;
2687 }
2688
2689 rx_pg->page = page;
2690 dma_unmap_addr_set(rx_pg, mapping, mapping);
2691 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2692 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2693 return 0;
2694 }
2695
2696 static void
2697 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2698 {
2699 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2700 struct page *page = rx_pg->page;
2701
2702 if (!page)
2703 return;
2704
2705 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2706 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2707
2708 __free_page(page);
2709 rx_pg->page = NULL;
2710 }
2711
2712 static inline int
2713 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
2714 {
2715 struct sk_buff *skb;
2716 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2717 dma_addr_t mapping;
2718 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2719 unsigned long align;
2720
2721 skb = __netdev_alloc_skb(bp->dev, bp->rx_buf_size, gfp);
2722 if (skb == NULL) {
2723 return -ENOMEM;
2724 }
2725
2726 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2727 skb_reserve(skb, BNX2_RX_ALIGN - align);
2728
2729 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_use_size,
2730 PCI_DMA_FROMDEVICE);
2731 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
2732 dev_kfree_skb(skb);
2733 return -EIO;
2734 }
2735
2736 rx_buf->skb = skb;
2737 rx_buf->desc = (struct l2_fhdr *) skb->data;
2738 dma_unmap_addr_set(rx_buf, mapping, mapping);
2739
2740 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2741 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2742
2743 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2744
2745 return 0;
2746 }
2747
2748 static int
2749 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2750 {
2751 struct status_block *sblk = bnapi->status_blk.msi;
2752 u32 new_link_state, old_link_state;
2753 int is_set = 1;
2754
2755 new_link_state = sblk->status_attn_bits & event;
2756 old_link_state = sblk->status_attn_bits_ack & event;
2757 if (new_link_state != old_link_state) {
2758 if (new_link_state)
2759 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2760 else
2761 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2762 } else
2763 is_set = 0;
2764
2765 return is_set;
2766 }
2767
2768 static void
2769 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2770 {
2771 spin_lock(&bp->phy_lock);
2772
2773 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2774 bnx2_set_link(bp);
2775 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2776 bnx2_set_remote_link(bp);
2777
2778 spin_unlock(&bp->phy_lock);
2779
2780 }
2781
2782 static inline u16
2783 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2784 {
2785 u16 cons;
2786
2787 /* Tell compiler that status block fields can change. */
2788 barrier();
2789 cons = *bnapi->hw_tx_cons_ptr;
2790 barrier();
2791 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2792 cons++;
2793 return cons;
2794 }
2795
2796 static int
2797 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2798 {
2799 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2800 u16 hw_cons, sw_cons, sw_ring_cons;
2801 int tx_pkt = 0, index;
2802 struct netdev_queue *txq;
2803
2804 index = (bnapi - bp->bnx2_napi);
2805 txq = netdev_get_tx_queue(bp->dev, index);
2806
2807 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2808 sw_cons = txr->tx_cons;
2809
2810 while (sw_cons != hw_cons) {
2811 struct sw_tx_bd *tx_buf;
2812 struct sk_buff *skb;
2813 int i, last;
2814
2815 sw_ring_cons = TX_RING_IDX(sw_cons);
2816
2817 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2818 skb = tx_buf->skb;
2819
2820 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2821 prefetch(&skb->end);
2822
2823 /* partial BD completions possible with TSO packets */
2824 if (tx_buf->is_gso) {
2825 u16 last_idx, last_ring_idx;
2826
2827 last_idx = sw_cons + tx_buf->nr_frags + 1;
2828 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2829 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2830 last_idx++;
2831 }
2832 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2833 break;
2834 }
2835 }
2836
2837 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
2838 skb_headlen(skb), PCI_DMA_TODEVICE);
2839
2840 tx_buf->skb = NULL;
2841 last = tx_buf->nr_frags;
2842
2843 for (i = 0; i < last; i++) {
2844 sw_cons = NEXT_TX_BD(sw_cons);
2845
2846 dma_unmap_page(&bp->pdev->dev,
2847 dma_unmap_addr(
2848 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2849 mapping),
2850 skb_shinfo(skb)->frags[i].size,
2851 PCI_DMA_TODEVICE);
2852 }
2853
2854 sw_cons = NEXT_TX_BD(sw_cons);
2855
2856 dev_kfree_skb(skb);
2857 tx_pkt++;
2858 if (tx_pkt == budget)
2859 break;
2860
2861 if (hw_cons == sw_cons)
2862 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2863 }
2864
2865 txr->hw_tx_cons = hw_cons;
2866 txr->tx_cons = sw_cons;
2867
2868 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2869 * before checking for netif_tx_queue_stopped(). Without the
2870 * memory barrier, there is a small possibility that bnx2_start_xmit()
2871 * will miss it and cause the queue to be stopped forever.
2872 */
2873 smp_mb();
2874
2875 if (unlikely(netif_tx_queue_stopped(txq)) &&
2876 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2877 __netif_tx_lock(txq, smp_processor_id());
2878 if ((netif_tx_queue_stopped(txq)) &&
2879 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2880 netif_tx_wake_queue(txq);
2881 __netif_tx_unlock(txq);
2882 }
2883
2884 return tx_pkt;
2885 }
2886
2887 static void
2888 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2889 struct sk_buff *skb, int count)
2890 {
2891 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2892 struct rx_bd *cons_bd, *prod_bd;
2893 int i;
2894 u16 hw_prod, prod;
2895 u16 cons = rxr->rx_pg_cons;
2896
2897 cons_rx_pg = &rxr->rx_pg_ring[cons];
2898
2899 /* The caller was unable to allocate a new page to replace the
2900 * last one in the frags array, so we need to recycle that page
2901 * and then free the skb.
2902 */
2903 if (skb) {
2904 struct page *page;
2905 struct skb_shared_info *shinfo;
2906
2907 shinfo = skb_shinfo(skb);
2908 shinfo->nr_frags--;
2909 page = shinfo->frags[shinfo->nr_frags].page;
2910 shinfo->frags[shinfo->nr_frags].page = NULL;
2911
2912 cons_rx_pg->page = page;
2913 dev_kfree_skb(skb);
2914 }
2915
2916 hw_prod = rxr->rx_pg_prod;
2917
2918 for (i = 0; i < count; i++) {
2919 prod = RX_PG_RING_IDX(hw_prod);
2920
2921 prod_rx_pg = &rxr->rx_pg_ring[prod];
2922 cons_rx_pg = &rxr->rx_pg_ring[cons];
2923 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2924 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2925
2926 if (prod != cons) {
2927 prod_rx_pg->page = cons_rx_pg->page;
2928 cons_rx_pg->page = NULL;
2929 dma_unmap_addr_set(prod_rx_pg, mapping,
2930 dma_unmap_addr(cons_rx_pg, mapping));
2931
2932 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2933 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2934
2935 }
2936 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2937 hw_prod = NEXT_RX_BD(hw_prod);
2938 }
2939 rxr->rx_pg_prod = hw_prod;
2940 rxr->rx_pg_cons = cons;
2941 }
2942
2943 static inline void
2944 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2945 struct sk_buff *skb, u16 cons, u16 prod)
2946 {
2947 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2948 struct rx_bd *cons_bd, *prod_bd;
2949
2950 cons_rx_buf = &rxr->rx_buf_ring[cons];
2951 prod_rx_buf = &rxr->rx_buf_ring[prod];
2952
2953 dma_sync_single_for_device(&bp->pdev->dev,
2954 dma_unmap_addr(cons_rx_buf, mapping),
2955 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2956
2957 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2958
2959 prod_rx_buf->skb = skb;
2960 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
2961
2962 if (cons == prod)
2963 return;
2964
2965 dma_unmap_addr_set(prod_rx_buf, mapping,
2966 dma_unmap_addr(cons_rx_buf, mapping));
2967
2968 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2969 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2970 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2971 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2972 }
2973
2974 static int
2975 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2976 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2977 u32 ring_idx)
2978 {
2979 int err;
2980 u16 prod = ring_idx & 0xffff;
2981
2982 err = bnx2_alloc_rx_skb(bp, rxr, prod, GFP_ATOMIC);
2983 if (unlikely(err)) {
2984 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2985 if (hdr_len) {
2986 unsigned int raw_len = len + 4;
2987 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2988
2989 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2990 }
2991 return err;
2992 }
2993
2994 skb_reserve(skb, BNX2_RX_OFFSET);
2995 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
2996 PCI_DMA_FROMDEVICE);
2997
2998 if (hdr_len == 0) {
2999 skb_put(skb, len);
3000 return 0;
3001 } else {
3002 unsigned int i, frag_len, frag_size, pages;
3003 struct sw_pg *rx_pg;
3004 u16 pg_cons = rxr->rx_pg_cons;
3005 u16 pg_prod = rxr->rx_pg_prod;
3006
3007 frag_size = len + 4 - hdr_len;
3008 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3009 skb_put(skb, hdr_len);
3010
3011 for (i = 0; i < pages; i++) {
3012 dma_addr_t mapping_old;
3013
3014 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3015 if (unlikely(frag_len <= 4)) {
3016 unsigned int tail = 4 - frag_len;
3017
3018 rxr->rx_pg_cons = pg_cons;
3019 rxr->rx_pg_prod = pg_prod;
3020 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3021 pages - i);
3022 skb->len -= tail;
3023 if (i == 0) {
3024 skb->tail -= tail;
3025 } else {
3026 skb_frag_t *frag =
3027 &skb_shinfo(skb)->frags[i - 1];
3028 frag->size -= tail;
3029 skb->data_len -= tail;
3030 skb->truesize -= tail;
3031 }
3032 return 0;
3033 }
3034 rx_pg = &rxr->rx_pg_ring[pg_cons];
3035
3036 /* Don't unmap yet. If we're unable to allocate a new
3037 * page, we need to recycle the page and the DMA addr.
3038 */
3039 mapping_old = dma_unmap_addr(rx_pg, mapping);
3040 if (i == pages - 1)
3041 frag_len -= 4;
3042
3043 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3044 rx_pg->page = NULL;
3045
3046 err = bnx2_alloc_rx_page(bp, rxr,
3047 RX_PG_RING_IDX(pg_prod),
3048 GFP_ATOMIC);
3049 if (unlikely(err)) {
3050 rxr->rx_pg_cons = pg_cons;
3051 rxr->rx_pg_prod = pg_prod;
3052 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3053 pages - i);
3054 return err;
3055 }
3056
3057 dma_unmap_page(&bp->pdev->dev, mapping_old,
3058 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3059
3060 frag_size -= frag_len;
3061 skb->data_len += frag_len;
3062 skb->truesize += frag_len;
3063 skb->len += frag_len;
3064
3065 pg_prod = NEXT_RX_BD(pg_prod);
3066 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3067 }
3068 rxr->rx_pg_prod = pg_prod;
3069 rxr->rx_pg_cons = pg_cons;
3070 }
3071 return 0;
3072 }
3073
3074 static inline u16
3075 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3076 {
3077 u16 cons;
3078
3079 /* Tell compiler that status block fields can change. */
3080 barrier();
3081 cons = *bnapi->hw_rx_cons_ptr;
3082 barrier();
3083 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3084 cons++;
3085 return cons;
3086 }
3087
3088 static int
3089 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3090 {
3091 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3092 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3093 struct l2_fhdr *rx_hdr;
3094 int rx_pkt = 0, pg_ring_used = 0;
3095
3096 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3097 sw_cons = rxr->rx_cons;
3098 sw_prod = rxr->rx_prod;
3099
3100 /* Memory barrier necessary as speculative reads of the rx
3101 * buffer can be ahead of the index in the status block
3102 */
3103 rmb();
3104 while (sw_cons != hw_cons) {
3105 unsigned int len, hdr_len;
3106 u32 status;
3107 struct sw_bd *rx_buf, *next_rx_buf;
3108 struct sk_buff *skb;
3109 dma_addr_t dma_addr;
3110 u16 vtag = 0;
3111 int hw_vlan __maybe_unused = 0;
3112
3113 sw_ring_cons = RX_RING_IDX(sw_cons);
3114 sw_ring_prod = RX_RING_IDX(sw_prod);
3115
3116 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3117 skb = rx_buf->skb;
3118 prefetchw(skb);
3119
3120 next_rx_buf =
3121 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3122 prefetch(next_rx_buf->desc);
3123
3124 rx_buf->skb = NULL;
3125
3126 dma_addr = dma_unmap_addr(rx_buf, mapping);
3127
3128 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
3129 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3130 PCI_DMA_FROMDEVICE);
3131
3132 rx_hdr = rx_buf->desc;
3133 len = rx_hdr->l2_fhdr_pkt_len;
3134 status = rx_hdr->l2_fhdr_status;
3135
3136 hdr_len = 0;
3137 if (status & L2_FHDR_STATUS_SPLIT) {
3138 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3139 pg_ring_used = 1;
3140 } else if (len > bp->rx_jumbo_thresh) {
3141 hdr_len = bp->rx_jumbo_thresh;
3142 pg_ring_used = 1;
3143 }
3144
3145 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3146 L2_FHDR_ERRORS_PHY_DECODE |
3147 L2_FHDR_ERRORS_ALIGNMENT |
3148 L2_FHDR_ERRORS_TOO_SHORT |
3149 L2_FHDR_ERRORS_GIANT_FRAME))) {
3150
3151 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3152 sw_ring_prod);
3153 if (pg_ring_used) {
3154 int pages;
3155
3156 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3157
3158 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3159 }
3160 goto next_rx;
3161 }
3162
3163 len -= 4;
3164
3165 if (len <= bp->rx_copy_thresh) {
3166 struct sk_buff *new_skb;
3167
3168 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3169 if (new_skb == NULL) {
3170 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3171 sw_ring_prod);
3172 goto next_rx;
3173 }
3174
3175 /* aligned copy */
3176 skb_copy_from_linear_data_offset(skb,
3177 BNX2_RX_OFFSET - 6,
3178 new_skb->data, len + 6);
3179 skb_reserve(new_skb, 6);
3180 skb_put(new_skb, len);
3181
3182 bnx2_reuse_rx_skb(bp, rxr, skb,
3183 sw_ring_cons, sw_ring_prod);
3184
3185 skb = new_skb;
3186 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3187 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3188 goto next_rx;
3189
3190 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3191 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3192 vtag = rx_hdr->l2_fhdr_vlan_tag;
3193 #ifdef BCM_VLAN
3194 if (bp->vlgrp)
3195 hw_vlan = 1;
3196 else
3197 #endif
3198 {
3199 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3200 __skb_push(skb, 4);
3201
3202 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3203 ve->h_vlan_proto = htons(ETH_P_8021Q);
3204 ve->h_vlan_TCI = htons(vtag);
3205 len += 4;
3206 }
3207 }
3208
3209 skb->protocol = eth_type_trans(skb, bp->dev);
3210
3211 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3212 (ntohs(skb->protocol) != 0x8100)) {
3213
3214 dev_kfree_skb(skb);
3215 goto next_rx;
3216
3217 }
3218
3219 skb->ip_summed = CHECKSUM_NONE;
3220 if (bp->rx_csum &&
3221 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3222 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3223
3224 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3225 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3226 skb->ip_summed = CHECKSUM_UNNECESSARY;
3227 }
3228 if ((bp->dev->features & NETIF_F_RXHASH) &&
3229 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3230 L2_FHDR_STATUS_USE_RXHASH))
3231 skb->rxhash = rx_hdr->l2_fhdr_hash;
3232
3233 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3234
3235 #ifdef BCM_VLAN
3236 if (hw_vlan)
3237 vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
3238 else
3239 #endif
3240 napi_gro_receive(&bnapi->napi, skb);
3241
3242 rx_pkt++;
3243
3244 next_rx:
3245 sw_cons = NEXT_RX_BD(sw_cons);
3246 sw_prod = NEXT_RX_BD(sw_prod);
3247
3248 if ((rx_pkt == budget))
3249 break;
3250
3251 /* Refresh hw_cons to see if there is new work */
3252 if (sw_cons == hw_cons) {
3253 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3254 rmb();
3255 }
3256 }
3257 rxr->rx_cons = sw_cons;
3258 rxr->rx_prod = sw_prod;
3259
3260 if (pg_ring_used)
3261 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3262
3263 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3264
3265 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3266
3267 mmiowb();
3268
3269 return rx_pkt;
3270
3271 }
3272
3273 /* MSI ISR - The only difference between this and the INTx ISR
3274 * is that the MSI interrupt is always serviced.
3275 */
3276 static irqreturn_t
3277 bnx2_msi(int irq, void *dev_instance)
3278 {
3279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
3281
3282 prefetch(bnapi->status_blk.msi);
3283 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3284 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3285 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3286
3287 /* Return here if interrupt is disabled. */
3288 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3289 return IRQ_HANDLED;
3290
3291 napi_schedule(&bnapi->napi);
3292
3293 return IRQ_HANDLED;
3294 }
3295
3296 static irqreturn_t
3297 bnx2_msi_1shot(int irq, void *dev_instance)
3298 {
3299 struct bnx2_napi *bnapi = dev_instance;
3300 struct bnx2 *bp = bnapi->bp;
3301
3302 prefetch(bnapi->status_blk.msi);
3303
3304 /* Return here if interrupt is disabled. */
3305 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3306 return IRQ_HANDLED;
3307
3308 napi_schedule(&bnapi->napi);
3309
3310 return IRQ_HANDLED;
3311 }
3312
3313 static irqreturn_t
3314 bnx2_interrupt(int irq, void *dev_instance)
3315 {
3316 struct bnx2_napi *bnapi = dev_instance;
3317 struct bnx2 *bp = bnapi->bp;
3318 struct status_block *sblk = bnapi->status_blk.msi;
3319
3320 /* When using INTx, it is possible for the interrupt to arrive
3321 * at the CPU before the status block posted prior to the
3322 * interrupt. Reading a register will flush the status block.
3323 * When using MSI, the MSI message will always complete after
3324 * the status block write.
3325 */
3326 if ((sblk->status_idx == bnapi->last_status_idx) &&
3327 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3328 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3329 return IRQ_NONE;
3330
3331 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3332 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3333 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3334
3335 /* Read back to deassert IRQ immediately to avoid too many
3336 * spurious interrupts.
3337 */
3338 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3339
3340 /* Return here if interrupt is shared and is disabled. */
3341 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3342 return IRQ_HANDLED;
3343
3344 if (napi_schedule_prep(&bnapi->napi)) {
3345 bnapi->last_status_idx = sblk->status_idx;
3346 __napi_schedule(&bnapi->napi);
3347 }
3348
3349 return IRQ_HANDLED;
3350 }
3351
3352 static inline int
3353 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3354 {
3355 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3356 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3357
3358 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3359 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3360 return 1;
3361 return 0;
3362 }
3363
3364 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3365 STATUS_ATTN_BITS_TIMER_ABORT)
3366
3367 static inline int
3368 bnx2_has_work(struct bnx2_napi *bnapi)
3369 {
3370 struct status_block *sblk = bnapi->status_blk.msi;
3371
3372 if (bnx2_has_fast_work(bnapi))
3373 return 1;
3374
3375 #ifdef BCM_CNIC
3376 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3377 return 1;
3378 #endif
3379
3380 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3381 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3382 return 1;
3383
3384 return 0;
3385 }
3386
3387 static void
3388 bnx2_chk_missed_msi(struct bnx2 *bp)
3389 {
3390 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3391 u32 msi_ctrl;
3392
3393 if (bnx2_has_work(bnapi)) {
3394 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3395 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3396 return;
3397
3398 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3399 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3400 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3401 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3402 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3403 }
3404 }
3405
3406 bp->idle_chk_status_idx = bnapi->last_status_idx;
3407 }
3408
3409 #ifdef BCM_CNIC
3410 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3411 {
3412 struct cnic_ops *c_ops;
3413
3414 if (!bnapi->cnic_present)
3415 return;
3416
3417 rcu_read_lock();
3418 c_ops = rcu_dereference(bp->cnic_ops);
3419 if (c_ops)
3420 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3421 bnapi->status_blk.msi);
3422 rcu_read_unlock();
3423 }
3424 #endif
3425
3426 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3427 {
3428 struct status_block *sblk = bnapi->status_blk.msi;
3429 u32 status_attn_bits = sblk->status_attn_bits;
3430 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3431
3432 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3433 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3434
3435 bnx2_phy_int(bp, bnapi);
3436
3437 /* This is needed to take care of transient status
3438 * during link changes.
3439 */
3440 REG_WR(bp, BNX2_HC_COMMAND,
3441 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3442 REG_RD(bp, BNX2_HC_COMMAND);
3443 }
3444 }
3445
3446 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3447 int work_done, int budget)
3448 {
3449 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3450 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3451
3452 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3453 bnx2_tx_int(bp, bnapi, 0);
3454
3455 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3456 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3457
3458 return work_done;
3459 }
3460
3461 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3462 {
3463 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3464 struct bnx2 *bp = bnapi->bp;
3465 int work_done = 0;
3466 struct status_block_msix *sblk = bnapi->status_blk.msix;
3467
3468 while (1) {
3469 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3470 if (unlikely(work_done >= budget))
3471 break;
3472
3473 bnapi->last_status_idx = sblk->status_idx;
3474 /* status idx must be read before checking for more work. */
3475 rmb();
3476 if (likely(!bnx2_has_fast_work(bnapi))) {
3477
3478 napi_complete(napi);
3479 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3480 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3481 bnapi->last_status_idx);
3482 break;
3483 }
3484 }
3485 return work_done;
3486 }
3487
3488 static int bnx2_poll(struct napi_struct *napi, int budget)
3489 {
3490 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3491 struct bnx2 *bp = bnapi->bp;
3492 int work_done = 0;
3493 struct status_block *sblk = bnapi->status_blk.msi;
3494
3495 while (1) {
3496 bnx2_poll_link(bp, bnapi);
3497
3498 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3499
3500 #ifdef BCM_CNIC
3501 bnx2_poll_cnic(bp, bnapi);
3502 #endif
3503
3504 /* bnapi->last_status_idx is used below to tell the hw how
3505 * much work has been processed, so we must read it before
3506 * checking for more work.
3507 */
3508 bnapi->last_status_idx = sblk->status_idx;
3509
3510 if (unlikely(work_done >= budget))
3511 break;
3512
3513 rmb();
3514 if (likely(!bnx2_has_work(bnapi))) {
3515 napi_complete(napi);
3516 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3517 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3518 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3519 bnapi->last_status_idx);
3520 break;
3521 }
3522 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3523 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3524 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3525 bnapi->last_status_idx);
3526
3527 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3528 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3529 bnapi->last_status_idx);
3530 break;
3531 }
3532 }
3533
3534 return work_done;
3535 }
3536
3537 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3538 * from set_multicast.
3539 */
3540 static void
3541 bnx2_set_rx_mode(struct net_device *dev)
3542 {
3543 struct bnx2 *bp = netdev_priv(dev);
3544 u32 rx_mode, sort_mode;
3545 struct netdev_hw_addr *ha;
3546 int i;
3547
3548 if (!netif_running(dev))
3549 return;
3550
3551 spin_lock_bh(&bp->phy_lock);
3552
3553 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3554 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3555 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3556 #ifdef BCM_VLAN
3557 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3558 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3559 #else
3560 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3561 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3562 #endif
3563 if (dev->flags & IFF_PROMISC) {
3564 /* Promiscuous mode. */
3565 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3566 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3567 BNX2_RPM_SORT_USER0_PROM_VLAN;
3568 }
3569 else if (dev->flags & IFF_ALLMULTI) {
3570 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3571 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3572 0xffffffff);
3573 }
3574 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3575 }
3576 else {
3577 /* Accept one or more multicast(s). */
3578 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3579 u32 regidx;
3580 u32 bit;
3581 u32 crc;
3582
3583 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3584
3585 netdev_for_each_mc_addr(ha, dev) {
3586 crc = ether_crc_le(ETH_ALEN, ha->addr);
3587 bit = crc & 0xff;
3588 regidx = (bit & 0xe0) >> 5;
3589 bit &= 0x1f;
3590 mc_filter[regidx] |= (1 << bit);
3591 }
3592
3593 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3594 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3595 mc_filter[i]);
3596 }
3597
3598 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3599 }
3600
3601 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3602 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3603 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3604 BNX2_RPM_SORT_USER0_PROM_VLAN;
3605 } else if (!(dev->flags & IFF_PROMISC)) {
3606 /* Add all entries into to the match filter list */
3607 i = 0;
3608 netdev_for_each_uc_addr(ha, dev) {
3609 bnx2_set_mac_addr(bp, ha->addr,
3610 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3611 sort_mode |= (1 <<
3612 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3613 i++;
3614 }
3615
3616 }
3617
3618 if (rx_mode != bp->rx_mode) {
3619 bp->rx_mode = rx_mode;
3620 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3621 }
3622
3623 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3624 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3625 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3626
3627 spin_unlock_bh(&bp->phy_lock);
3628 }
3629
3630 static int __devinit
3631 check_fw_section(const struct firmware *fw,
3632 const struct bnx2_fw_file_section *section,
3633 u32 alignment, bool non_empty)
3634 {
3635 u32 offset = be32_to_cpu(section->offset);
3636 u32 len = be32_to_cpu(section->len);
3637
3638 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3639 return -EINVAL;
3640 if ((non_empty && len == 0) || len > fw->size - offset ||
3641 len & (alignment - 1))
3642 return -EINVAL;
3643 return 0;
3644 }
3645
3646 static int __devinit
3647 check_mips_fw_entry(const struct firmware *fw,
3648 const struct bnx2_mips_fw_file_entry *entry)
3649 {
3650 if (check_fw_section(fw, &entry->text, 4, true) ||
3651 check_fw_section(fw, &entry->data, 4, false) ||
3652 check_fw_section(fw, &entry->rodata, 4, false))
3653 return -EINVAL;
3654 return 0;
3655 }
3656
3657 static int __devinit
3658 bnx2_request_firmware(struct bnx2 *bp)
3659 {
3660 const char *mips_fw_file, *rv2p_fw_file;
3661 const struct bnx2_mips_fw_file *mips_fw;
3662 const struct bnx2_rv2p_fw_file *rv2p_fw;
3663 int rc;
3664
3665 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3666 mips_fw_file = FW_MIPS_FILE_09;
3667 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3668 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3669 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3670 else
3671 rv2p_fw_file = FW_RV2P_FILE_09;
3672 } else {
3673 mips_fw_file = FW_MIPS_FILE_06;
3674 rv2p_fw_file = FW_RV2P_FILE_06;
3675 }
3676
3677 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3678 if (rc) {
3679 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3680 return rc;
3681 }
3682
3683 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3684 if (rc) {
3685 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3686 return rc;
3687 }
3688 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3689 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3690 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3691 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3692 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3693 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3694 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3695 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3696 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3697 return -EINVAL;
3698 }
3699 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3700 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3701 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3702 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3703 return -EINVAL;
3704 }
3705
3706 return 0;
3707 }
3708
3709 static u32
3710 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3711 {
3712 switch (idx) {
3713 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3714 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3715 rv2p_code |= RV2P_BD_PAGE_SIZE;
3716 break;
3717 }
3718 return rv2p_code;
3719 }
3720
3721 static int
3722 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3723 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3724 {
3725 u32 rv2p_code_len, file_offset;
3726 __be32 *rv2p_code;
3727 int i;
3728 u32 val, cmd, addr;
3729
3730 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3731 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3732
3733 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3734
3735 if (rv2p_proc == RV2P_PROC1) {
3736 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3737 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3738 } else {
3739 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3740 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3741 }
3742
3743 for (i = 0; i < rv2p_code_len; i += 8) {
3744 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3745 rv2p_code++;
3746 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3747 rv2p_code++;
3748
3749 val = (i / 8) | cmd;
3750 REG_WR(bp, addr, val);
3751 }
3752
3753 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3754 for (i = 0; i < 8; i++) {
3755 u32 loc, code;
3756
3757 loc = be32_to_cpu(fw_entry->fixup[i]);
3758 if (loc && ((loc * 4) < rv2p_code_len)) {
3759 code = be32_to_cpu(*(rv2p_code + loc - 1));
3760 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3761 code = be32_to_cpu(*(rv2p_code + loc));
3762 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3763 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3764
3765 val = (loc / 2) | cmd;
3766 REG_WR(bp, addr, val);
3767 }
3768 }
3769
3770 /* Reset the processor, un-stall is done later. */
3771 if (rv2p_proc == RV2P_PROC1) {
3772 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3773 }
3774 else {
3775 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3776 }
3777
3778 return 0;
3779 }
3780
3781 static int
3782 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3783 const struct bnx2_mips_fw_file_entry *fw_entry)
3784 {
3785 u32 addr, len, file_offset;
3786 __be32 *data;
3787 u32 offset;
3788 u32 val;
3789
3790 /* Halt the CPU. */
3791 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3792 val |= cpu_reg->mode_value_halt;
3793 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3794 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3795
3796 /* Load the Text area. */
3797 addr = be32_to_cpu(fw_entry->text.addr);
3798 len = be32_to_cpu(fw_entry->text.len);
3799 file_offset = be32_to_cpu(fw_entry->text.offset);
3800 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3801
3802 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3803 if (len) {
3804 int j;
3805
3806 for (j = 0; j < (len / 4); j++, offset += 4)
3807 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3808 }
3809
3810 /* Load the Data area. */
3811 addr = be32_to_cpu(fw_entry->data.addr);
3812 len = be32_to_cpu(fw_entry->data.len);
3813 file_offset = be32_to_cpu(fw_entry->data.offset);
3814 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3815
3816 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3817 if (len) {
3818 int j;
3819
3820 for (j = 0; j < (len / 4); j++, offset += 4)
3821 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3822 }
3823
3824 /* Load the Read-Only area. */
3825 addr = be32_to_cpu(fw_entry->rodata.addr);
3826 len = be32_to_cpu(fw_entry->rodata.len);
3827 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3828 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3829
3830 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3831 if (len) {
3832 int j;
3833
3834 for (j = 0; j < (len / 4); j++, offset += 4)
3835 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3836 }
3837
3838 /* Clear the pre-fetch instruction. */
3839 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3840
3841 val = be32_to_cpu(fw_entry->start_addr);
3842 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3843
3844 /* Start the CPU. */
3845 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3846 val &= ~cpu_reg->mode_value_halt;
3847 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3848 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3849
3850 return 0;
3851 }
3852
3853 static int
3854 bnx2_init_cpus(struct bnx2 *bp)
3855 {
3856 const struct bnx2_mips_fw_file *mips_fw =
3857 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3858 const struct bnx2_rv2p_fw_file *rv2p_fw =
3859 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3860 int rc;
3861
3862 /* Initialize the RV2P processor. */
3863 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3864 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3865
3866 /* Initialize the RX Processor. */
3867 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3868 if (rc)
3869 goto init_cpu_err;
3870
3871 /* Initialize the TX Processor. */
3872 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3873 if (rc)
3874 goto init_cpu_err;
3875
3876 /* Initialize the TX Patch-up Processor. */
3877 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3878 if (rc)
3879 goto init_cpu_err;
3880
3881 /* Initialize the Completion Processor. */
3882 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3883 if (rc)
3884 goto init_cpu_err;
3885
3886 /* Initialize the Command Processor. */
3887 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3888
3889 init_cpu_err:
3890 return rc;
3891 }
3892
3893 static int
3894 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3895 {
3896 u16 pmcsr;
3897
3898 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3899
3900 switch (state) {
3901 case PCI_D0: {
3902 u32 val;
3903
3904 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3905 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3906 PCI_PM_CTRL_PME_STATUS);
3907
3908 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3909 /* delay required during transition out of D3hot */
3910 msleep(20);
3911
3912 val = REG_RD(bp, BNX2_EMAC_MODE);
3913 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3914 val &= ~BNX2_EMAC_MODE_MPKT;
3915 REG_WR(bp, BNX2_EMAC_MODE, val);
3916
3917 val = REG_RD(bp, BNX2_RPM_CONFIG);
3918 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3919 REG_WR(bp, BNX2_RPM_CONFIG, val);
3920 break;
3921 }
3922 case PCI_D3hot: {
3923 int i;
3924 u32 val, wol_msg;
3925
3926 if (bp->wol) {
3927 u32 advertising;
3928 u8 autoneg;
3929
3930 autoneg = bp->autoneg;
3931 advertising = bp->advertising;
3932
3933 if (bp->phy_port == PORT_TP) {
3934 bp->autoneg = AUTONEG_SPEED;
3935 bp->advertising = ADVERTISED_10baseT_Half |
3936 ADVERTISED_10baseT_Full |
3937 ADVERTISED_100baseT_Half |
3938 ADVERTISED_100baseT_Full |
3939 ADVERTISED_Autoneg;
3940 }
3941
3942 spin_lock_bh(&bp->phy_lock);
3943 bnx2_setup_phy(bp, bp->phy_port);
3944 spin_unlock_bh(&bp->phy_lock);
3945
3946 bp->autoneg = autoneg;
3947 bp->advertising = advertising;
3948
3949 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3950
3951 val = REG_RD(bp, BNX2_EMAC_MODE);
3952
3953 /* Enable port mode. */
3954 val &= ~BNX2_EMAC_MODE_PORT;
3955 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3956 BNX2_EMAC_MODE_ACPI_RCVD |
3957 BNX2_EMAC_MODE_MPKT;
3958 if (bp->phy_port == PORT_TP)
3959 val |= BNX2_EMAC_MODE_PORT_MII;
3960 else {
3961 val |= BNX2_EMAC_MODE_PORT_GMII;
3962 if (bp->line_speed == SPEED_2500)
3963 val |= BNX2_EMAC_MODE_25G_MODE;
3964 }
3965
3966 REG_WR(bp, BNX2_EMAC_MODE, val);
3967
3968 /* receive all multicast */
3969 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3970 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3971 0xffffffff);
3972 }
3973 REG_WR(bp, BNX2_EMAC_RX_MODE,
3974 BNX2_EMAC_RX_MODE_SORT_MODE);
3975
3976 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3977 BNX2_RPM_SORT_USER0_MC_EN;
3978 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3979 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3980 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3981 BNX2_RPM_SORT_USER0_ENA);
3982
3983 /* Need to enable EMAC and RPM for WOL. */
3984 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3985 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3986 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3987 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3988
3989 val = REG_RD(bp, BNX2_RPM_CONFIG);
3990 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3991 REG_WR(bp, BNX2_RPM_CONFIG, val);
3992
3993 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3994 }
3995 else {
3996 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3997 }
3998
3999 if (!(bp->flags & BNX2_FLAG_NO_WOL))
4000 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
4001 1, 0);
4002
4003 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4004 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4005 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4006
4007 if (bp->wol)
4008 pmcsr |= 3;
4009 }
4010 else {
4011 pmcsr |= 3;
4012 }
4013 if (bp->wol) {
4014 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4015 }
4016 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4017 pmcsr);
4018
4019 /* No more memory access after this point until
4020 * device is brought back to D0.
4021 */
4022 udelay(50);
4023 break;
4024 }
4025 default:
4026 return -EINVAL;
4027 }
4028 return 0;
4029 }
4030
4031 static int
4032 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4033 {
4034 u32 val;
4035 int j;
4036
4037 /* Request access to the flash interface. */
4038 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4039 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4040 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4041 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4042 break;
4043
4044 udelay(5);
4045 }
4046
4047 if (j >= NVRAM_TIMEOUT_COUNT)
4048 return -EBUSY;
4049
4050 return 0;
4051 }
4052
4053 static int
4054 bnx2_release_nvram_lock(struct bnx2 *bp)
4055 {
4056 int j;
4057 u32 val;
4058
4059 /* Relinquish nvram interface. */
4060 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4061
4062 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4063 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4064 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4065 break;
4066
4067 udelay(5);
4068 }
4069
4070 if (j >= NVRAM_TIMEOUT_COUNT)
4071 return -EBUSY;
4072
4073 return 0;
4074 }
4075
4076
4077 static int
4078 bnx2_enable_nvram_write(struct bnx2 *bp)
4079 {
4080 u32 val;
4081
4082 val = REG_RD(bp, BNX2_MISC_CFG);
4083 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4084
4085 if (bp->flash_info->flags & BNX2_NV_WREN) {
4086 int j;
4087
4088 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4089 REG_WR(bp, BNX2_NVM_COMMAND,
4090 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4091
4092 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4093 udelay(5);
4094
4095 val = REG_RD(bp, BNX2_NVM_COMMAND);
4096 if (val & BNX2_NVM_COMMAND_DONE)
4097 break;
4098 }
4099
4100 if (j >= NVRAM_TIMEOUT_COUNT)
4101 return -EBUSY;
4102 }
4103 return 0;
4104 }
4105
4106 static void
4107 bnx2_disable_nvram_write(struct bnx2 *bp)
4108 {
4109 u32 val;
4110
4111 val = REG_RD(bp, BNX2_MISC_CFG);
4112 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4113 }
4114
4115
4116 static void
4117 bnx2_enable_nvram_access(struct bnx2 *bp)
4118 {
4119 u32 val;
4120
4121 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4122 /* Enable both bits, even on read. */
4123 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4124 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4125 }
4126
4127 static void
4128 bnx2_disable_nvram_access(struct bnx2 *bp)
4129 {
4130 u32 val;
4131
4132 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4133 /* Disable both bits, even after read. */
4134 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4135 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4136 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4137 }
4138
4139 static int
4140 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4141 {
4142 u32 cmd;
4143 int j;
4144
4145 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4146 /* Buffered flash, no erase needed */
4147 return 0;
4148
4149 /* Build an erase command */
4150 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4151 BNX2_NVM_COMMAND_DOIT;
4152
4153 /* Need to clear DONE bit separately. */
4154 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4155
4156 /* Address of the NVRAM to read from. */
4157 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4158
4159 /* Issue an erase command. */
4160 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4161
4162 /* Wait for completion. */
4163 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4164 u32 val;
4165
4166 udelay(5);
4167
4168 val = REG_RD(bp, BNX2_NVM_COMMAND);
4169 if (val & BNX2_NVM_COMMAND_DONE)
4170 break;
4171 }
4172
4173 if (j >= NVRAM_TIMEOUT_COUNT)
4174 return -EBUSY;
4175
4176 return 0;
4177 }
4178
4179 static int
4180 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4181 {
4182 u32 cmd;
4183 int j;
4184
4185 /* Build the command word. */
4186 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4187
4188 /* Calculate an offset of a buffered flash, not needed for 5709. */
4189 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4190 offset = ((offset / bp->flash_info->page_size) <<
4191 bp->flash_info->page_bits) +
4192 (offset % bp->flash_info->page_size);
4193 }
4194
4195 /* Need to clear DONE bit separately. */
4196 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4197
4198 /* Address of the NVRAM to read from. */
4199 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4200
4201 /* Issue a read command. */
4202 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4203
4204 /* Wait for completion. */
4205 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4206 u32 val;
4207
4208 udelay(5);
4209
4210 val = REG_RD(bp, BNX2_NVM_COMMAND);
4211 if (val & BNX2_NVM_COMMAND_DONE) {
4212 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4213 memcpy(ret_val, &v, 4);
4214 break;
4215 }
4216 }
4217 if (j >= NVRAM_TIMEOUT_COUNT)
4218 return -EBUSY;
4219
4220 return 0;
4221 }
4222
4223
4224 static int
4225 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4226 {
4227 u32 cmd;
4228 __be32 val32;
4229 int j;
4230
4231 /* Build the command word. */
4232 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4233
4234 /* Calculate an offset of a buffered flash, not needed for 5709. */
4235 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4236 offset = ((offset / bp->flash_info->page_size) <<
4237 bp->flash_info->page_bits) +
4238 (offset % bp->flash_info->page_size);
4239 }
4240
4241 /* Need to clear DONE bit separately. */
4242 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4243
4244 memcpy(&val32, val, 4);
4245
4246 /* Write the data. */
4247 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4248
4249 /* Address of the NVRAM to write to. */
4250 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4251
4252 /* Issue the write command. */
4253 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4254
4255 /* Wait for completion. */
4256 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4257 udelay(5);
4258
4259 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4260 break;
4261 }
4262 if (j >= NVRAM_TIMEOUT_COUNT)
4263 return -EBUSY;
4264
4265 return 0;
4266 }
4267
4268 static int
4269 bnx2_init_nvram(struct bnx2 *bp)
4270 {
4271 u32 val;
4272 int j, entry_count, rc = 0;
4273 const struct flash_spec *flash;
4274
4275 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4276 bp->flash_info = &flash_5709;
4277 goto get_flash_size;
4278 }
4279
4280 /* Determine the selected interface. */
4281 val = REG_RD(bp, BNX2_NVM_CFG1);
4282
4283 entry_count = ARRAY_SIZE(flash_table);
4284
4285 if (val & 0x40000000) {
4286
4287 /* Flash interface has been reconfigured */
4288 for (j = 0, flash = &flash_table[0]; j < entry_count;
4289 j++, flash++) {
4290 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4291 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4292 bp->flash_info = flash;
4293 break;
4294 }
4295 }
4296 }
4297 else {
4298 u32 mask;
4299 /* Not yet been reconfigured */
4300
4301 if (val & (1 << 23))
4302 mask = FLASH_BACKUP_STRAP_MASK;
4303 else
4304 mask = FLASH_STRAP_MASK;
4305
4306 for (j = 0, flash = &flash_table[0]; j < entry_count;
4307 j++, flash++) {
4308
4309 if ((val & mask) == (flash->strapping & mask)) {
4310 bp->flash_info = flash;
4311
4312 /* Request access to the flash interface. */
4313 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4314 return rc;
4315
4316 /* Enable access to flash interface */
4317 bnx2_enable_nvram_access(bp);
4318
4319 /* Reconfigure the flash interface */
4320 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4321 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4322 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4323 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4324
4325 /* Disable access to flash interface */
4326 bnx2_disable_nvram_access(bp);
4327 bnx2_release_nvram_lock(bp);
4328
4329 break;
4330 }
4331 }
4332 } /* if (val & 0x40000000) */
4333
4334 if (j == entry_count) {
4335 bp->flash_info = NULL;
4336 pr_alert("Unknown flash/EEPROM type\n");
4337 return -ENODEV;
4338 }
4339
4340 get_flash_size:
4341 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4342 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4343 if (val)
4344 bp->flash_size = val;
4345 else
4346 bp->flash_size = bp->flash_info->total_size;
4347
4348 return rc;
4349 }
4350
4351 static int
4352 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4353 int buf_size)
4354 {
4355 int rc = 0;
4356 u32 cmd_flags, offset32, len32, extra;
4357
4358 if (buf_size == 0)
4359 return 0;
4360
4361 /* Request access to the flash interface. */
4362 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4363 return rc;
4364
4365 /* Enable access to flash interface */
4366 bnx2_enable_nvram_access(bp);
4367
4368 len32 = buf_size;
4369 offset32 = offset;
4370 extra = 0;
4371
4372 cmd_flags = 0;
4373
4374 if (offset32 & 3) {
4375 u8 buf[4];
4376 u32 pre_len;
4377
4378 offset32 &= ~3;
4379 pre_len = 4 - (offset & 3);
4380
4381 if (pre_len >= len32) {
4382 pre_len = len32;
4383 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4384 BNX2_NVM_COMMAND_LAST;
4385 }
4386 else {
4387 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4388 }
4389
4390 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4391
4392 if (rc)
4393 return rc;
4394
4395 memcpy(ret_buf, buf + (offset & 3), pre_len);
4396
4397 offset32 += 4;
4398 ret_buf += pre_len;
4399 len32 -= pre_len;
4400 }
4401 if (len32 & 3) {
4402 extra = 4 - (len32 & 3);
4403 len32 = (len32 + 4) & ~3;
4404 }
4405
4406 if (len32 == 4) {
4407 u8 buf[4];
4408
4409 if (cmd_flags)
4410 cmd_flags = BNX2_NVM_COMMAND_LAST;
4411 else
4412 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4413 BNX2_NVM_COMMAND_LAST;
4414
4415 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4416
4417 memcpy(ret_buf, buf, 4 - extra);
4418 }
4419 else if (len32 > 0) {
4420 u8 buf[4];
4421
4422 /* Read the first word. */
4423 if (cmd_flags)
4424 cmd_flags = 0;
4425 else
4426 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4427
4428 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4429
4430 /* Advance to the next dword. */
4431 offset32 += 4;
4432 ret_buf += 4;
4433 len32 -= 4;
4434
4435 while (len32 > 4 && rc == 0) {
4436 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4437
4438 /* Advance to the next dword. */
4439 offset32 += 4;
4440 ret_buf += 4;
4441 len32 -= 4;
4442 }
4443
4444 if (rc)
4445 return rc;
4446
4447 cmd_flags = BNX2_NVM_COMMAND_LAST;
4448 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4449
4450 memcpy(ret_buf, buf, 4 - extra);
4451 }
4452
4453 /* Disable access to flash interface */
4454 bnx2_disable_nvram_access(bp);
4455
4456 bnx2_release_nvram_lock(bp);
4457
4458 return rc;
4459 }
4460
4461 static int
4462 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4463 int buf_size)
4464 {
4465 u32 written, offset32, len32;
4466 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4467 int rc = 0;
4468 int align_start, align_end;
4469
4470 buf = data_buf;
4471 offset32 = offset;
4472 len32 = buf_size;
4473 align_start = align_end = 0;
4474
4475 if ((align_start = (offset32 & 3))) {
4476 offset32 &= ~3;
4477 len32 += align_start;
4478 if (len32 < 4)
4479 len32 = 4;
4480 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4481 return rc;
4482 }
4483
4484 if (len32 & 3) {
4485 align_end = 4 - (len32 & 3);
4486 len32 += align_end;
4487 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4488 return rc;
4489 }
4490
4491 if (align_start || align_end) {
4492 align_buf = kmalloc(len32, GFP_KERNEL);
4493 if (align_buf == NULL)
4494 return -ENOMEM;
4495 if (align_start) {
4496 memcpy(align_buf, start, 4);
4497 }
4498 if (align_end) {
4499 memcpy(align_buf + len32 - 4, end, 4);
4500 }
4501 memcpy(align_buf + align_start, data_buf, buf_size);
4502 buf = align_buf;
4503 }
4504
4505 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4506 flash_buffer = kmalloc(264, GFP_KERNEL);
4507 if (flash_buffer == NULL) {
4508 rc = -ENOMEM;
4509 goto nvram_write_end;
4510 }
4511 }
4512
4513 written = 0;
4514 while ((written < len32) && (rc == 0)) {
4515 u32 page_start, page_end, data_start, data_end;
4516 u32 addr, cmd_flags;
4517 int i;
4518
4519 /* Find the page_start addr */
4520 page_start = offset32 + written;
4521 page_start -= (page_start % bp->flash_info->page_size);
4522 /* Find the page_end addr */
4523 page_end = page_start + bp->flash_info->page_size;
4524 /* Find the data_start addr */
4525 data_start = (written == 0) ? offset32 : page_start;
4526 /* Find the data_end addr */
4527 data_end = (page_end > offset32 + len32) ?
4528 (offset32 + len32) : page_end;
4529
4530 /* Request access to the flash interface. */
4531 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4532 goto nvram_write_end;
4533
4534 /* Enable access to flash interface */
4535 bnx2_enable_nvram_access(bp);
4536
4537 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4538 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4539 int j;
4540
4541 /* Read the whole page into the buffer
4542 * (non-buffer flash only) */
4543 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4544 if (j == (bp->flash_info->page_size - 4)) {
4545 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4546 }
4547 rc = bnx2_nvram_read_dword(bp,
4548 page_start + j,
4549 &flash_buffer[j],
4550 cmd_flags);
4551
4552 if (rc)
4553 goto nvram_write_end;
4554
4555 cmd_flags = 0;
4556 }
4557 }
4558
4559 /* Enable writes to flash interface (unlock write-protect) */
4560 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4561 goto nvram_write_end;
4562
4563 /* Loop to write back the buffer data from page_start to
4564 * data_start */
4565 i = 0;
4566 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4567 /* Erase the page */
4568 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4569 goto nvram_write_end;
4570
4571 /* Re-enable the write again for the actual write */
4572 bnx2_enable_nvram_write(bp);
4573
4574 for (addr = page_start; addr < data_start;
4575 addr += 4, i += 4) {
4576
4577 rc = bnx2_nvram_write_dword(bp, addr,
4578 &flash_buffer[i], cmd_flags);
4579
4580 if (rc != 0)
4581 goto nvram_write_end;
4582
4583 cmd_flags = 0;
4584 }
4585 }
4586
4587 /* Loop to write the new data from data_start to data_end */
4588 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4589 if ((addr == page_end - 4) ||
4590 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4591 (addr == data_end - 4))) {
4592
4593 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4594 }
4595 rc = bnx2_nvram_write_dword(bp, addr, buf,
4596 cmd_flags);
4597
4598 if (rc != 0)
4599 goto nvram_write_end;
4600
4601 cmd_flags = 0;
4602 buf += 4;
4603 }
4604
4605 /* Loop to write back the buffer data from data_end
4606 * to page_end */
4607 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4608 for (addr = data_end; addr < page_end;
4609 addr += 4, i += 4) {
4610
4611 if (addr == page_end-4) {
4612 cmd_flags = BNX2_NVM_COMMAND_LAST;
4613 }
4614 rc = bnx2_nvram_write_dword(bp, addr,
4615 &flash_buffer[i], cmd_flags);
4616
4617 if (rc != 0)
4618 goto nvram_write_end;
4619
4620 cmd_flags = 0;
4621 }
4622 }
4623
4624 /* Disable writes to flash interface (lock write-protect) */
4625 bnx2_disable_nvram_write(bp);
4626
4627 /* Disable access to flash interface */
4628 bnx2_disable_nvram_access(bp);
4629 bnx2_release_nvram_lock(bp);
4630
4631 /* Increment written */
4632 written += data_end - data_start;
4633 }
4634
4635 nvram_write_end:
4636 kfree(flash_buffer);
4637 kfree(align_buf);
4638 return rc;
4639 }
4640
4641 static void
4642 bnx2_init_fw_cap(struct bnx2 *bp)
4643 {
4644 u32 val, sig = 0;
4645
4646 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4647 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4648
4649 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4650 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4651
4652 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4653 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4654 return;
4655
4656 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4657 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4658 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4659 }
4660
4661 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4662 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4663 u32 link;
4664
4665 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4666
4667 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4668 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4669 bp->phy_port = PORT_FIBRE;
4670 else
4671 bp->phy_port = PORT_TP;
4672
4673 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4674 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4675 }
4676
4677 if (netif_running(bp->dev) && sig)
4678 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4679 }
4680
4681 static void
4682 bnx2_setup_msix_tbl(struct bnx2 *bp)
4683 {
4684 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4685
4686 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4687 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4688 }
4689
4690 static int
4691 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4692 {
4693 u32 val;
4694 int i, rc = 0;
4695 u8 old_port;
4696
4697 /* Wait for the current PCI transaction to complete before
4698 * issuing a reset. */
4699 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4700 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4701 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4702 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4703 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4704 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4705 udelay(5);
4706
4707 /* Wait for the firmware to tell us it is ok to issue a reset. */
4708 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4709
4710 /* Deposit a driver reset signature so the firmware knows that
4711 * this is a soft reset. */
4712 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4713 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4714
4715 /* Do a dummy read to force the chip to complete all current transaction
4716 * before we issue a reset. */
4717 val = REG_RD(bp, BNX2_MISC_ID);
4718
4719 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4720 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4721 REG_RD(bp, BNX2_MISC_COMMAND);
4722 udelay(5);
4723
4724 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4725 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4726
4727 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4728
4729 } else {
4730 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4731 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4732 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4733
4734 /* Chip reset. */
4735 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4736
4737 /* Reading back any register after chip reset will hang the
4738 * bus on 5706 A0 and A1. The msleep below provides plenty
4739 * of margin for write posting.
4740 */
4741 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4742 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4743 msleep(20);
4744
4745 /* Reset takes approximate 30 usec */
4746 for (i = 0; i < 10; i++) {
4747 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4748 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4749 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4750 break;
4751 udelay(10);
4752 }
4753
4754 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4755 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4756 pr_err("Chip reset did not complete\n");
4757 return -EBUSY;
4758 }
4759 }
4760
4761 /* Make sure byte swapping is properly configured. */
4762 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4763 if (val != 0x01020304) {
4764 pr_err("Chip not in correct endian mode\n");
4765 return -ENODEV;
4766 }
4767
4768 /* Wait for the firmware to finish its initialization. */
4769 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4770 if (rc)
4771 return rc;
4772
4773 spin_lock_bh(&bp->phy_lock);
4774 old_port = bp->phy_port;
4775 bnx2_init_fw_cap(bp);
4776 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4777 old_port != bp->phy_port)
4778 bnx2_set_default_remote_link(bp);
4779 spin_unlock_bh(&bp->phy_lock);
4780
4781 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4782 /* Adjust the voltage regular to two steps lower. The default
4783 * of this register is 0x0000000e. */
4784 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4785
4786 /* Remove bad rbuf memory from the free pool. */
4787 rc = bnx2_alloc_bad_rbuf(bp);
4788 }
4789
4790 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4791 bnx2_setup_msix_tbl(bp);
4792 /* Prevent MSIX table reads and write from timing out */
4793 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4794 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4795 }
4796
4797 return rc;
4798 }
4799
4800 static int
4801 bnx2_init_chip(struct bnx2 *bp)
4802 {
4803 u32 val, mtu;
4804 int rc, i;
4805
4806 /* Make sure the interrupt is not active. */
4807 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4808
4809 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4810 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4811 #ifdef __BIG_ENDIAN
4812 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4813 #endif
4814 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4815 DMA_READ_CHANS << 12 |
4816 DMA_WRITE_CHANS << 16;
4817
4818 val |= (0x2 << 20) | (1 << 11);
4819
4820 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4821 val |= (1 << 23);
4822
4823 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4824 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4825 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4826
4827 REG_WR(bp, BNX2_DMA_CONFIG, val);
4828
4829 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4830 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4831 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4832 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4833 }
4834
4835 if (bp->flags & BNX2_FLAG_PCIX) {
4836 u16 val16;
4837
4838 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4839 &val16);
4840 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4841 val16 & ~PCI_X_CMD_ERO);
4842 }
4843
4844 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4845 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4846 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4847 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4848
4849 /* Initialize context mapping and zero out the quick contexts. The
4850 * context block must have already been enabled. */
4851 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4852 rc = bnx2_init_5709_context(bp);
4853 if (rc)
4854 return rc;
4855 } else
4856 bnx2_init_context(bp);
4857
4858 if ((rc = bnx2_init_cpus(bp)) != 0)
4859 return rc;
4860
4861 bnx2_init_nvram(bp);
4862
4863 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4864
4865 val = REG_RD(bp, BNX2_MQ_CONFIG);
4866 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4867 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4868 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4869 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4870 if (CHIP_REV(bp) == CHIP_REV_Ax)
4871 val |= BNX2_MQ_CONFIG_HALT_DIS;
4872 }
4873
4874 REG_WR(bp, BNX2_MQ_CONFIG, val);
4875
4876 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4877 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4878 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4879
4880 val = (BCM_PAGE_BITS - 8) << 24;
4881 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4882
4883 /* Configure page size. */
4884 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4885 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4886 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4887 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4888
4889 val = bp->mac_addr[0] +
4890 (bp->mac_addr[1] << 8) +
4891 (bp->mac_addr[2] << 16) +
4892 bp->mac_addr[3] +
4893 (bp->mac_addr[4] << 8) +
4894 (bp->mac_addr[5] << 16);
4895 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4896
4897 /* Program the MTU. Also include 4 bytes for CRC32. */
4898 mtu = bp->dev->mtu;
4899 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4900 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4901 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4902 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4903
4904 if (mtu < 1500)
4905 mtu = 1500;
4906
4907 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4908 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4909 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4910
4911 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4912 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4913 bp->bnx2_napi[i].last_status_idx = 0;
4914
4915 bp->idle_chk_status_idx = 0xffff;
4916
4917 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4918
4919 /* Set up how to generate a link change interrupt. */
4920 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4921
4922 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4923 (u64) bp->status_blk_mapping & 0xffffffff);
4924 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4925
4926 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4927 (u64) bp->stats_blk_mapping & 0xffffffff);
4928 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4929 (u64) bp->stats_blk_mapping >> 32);
4930
4931 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4932 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4933
4934 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4935 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4936
4937 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4938 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4939
4940 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4941
4942 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4943
4944 REG_WR(bp, BNX2_HC_COM_TICKS,
4945 (bp->com_ticks_int << 16) | bp->com_ticks);
4946
4947 REG_WR(bp, BNX2_HC_CMD_TICKS,
4948 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4949
4950 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4951 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4952 else
4953 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4954 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4955
4956 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4957 val = BNX2_HC_CONFIG_COLLECT_STATS;
4958 else {
4959 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4960 BNX2_HC_CONFIG_COLLECT_STATS;
4961 }
4962
4963 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4964 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4965 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4966
4967 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4968 }
4969
4970 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4971 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4972
4973 REG_WR(bp, BNX2_HC_CONFIG, val);
4974
4975 for (i = 1; i < bp->irq_nvecs; i++) {
4976 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4977 BNX2_HC_SB_CONFIG_1;
4978
4979 REG_WR(bp, base,
4980 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4981 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4982 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4983
4984 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4985 (bp->tx_quick_cons_trip_int << 16) |
4986 bp->tx_quick_cons_trip);
4987
4988 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4989 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4990
4991 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4992 (bp->rx_quick_cons_trip_int << 16) |
4993 bp->rx_quick_cons_trip);
4994
4995 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4996 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4997 }
4998
4999 /* Clear internal stats counters. */
5000 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
5001
5002 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
5003
5004 /* Initialize the receive filter. */
5005 bnx2_set_rx_mode(bp->dev);
5006
5007 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5008 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5009 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5010 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5011 }
5012 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
5013 1, 0);
5014
5015 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5016 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5017
5018 udelay(20);
5019
5020 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5021
5022 return rc;
5023 }
5024
5025 static void
5026 bnx2_clear_ring_states(struct bnx2 *bp)
5027 {
5028 struct bnx2_napi *bnapi;
5029 struct bnx2_tx_ring_info *txr;
5030 struct bnx2_rx_ring_info *rxr;
5031 int i;
5032
5033 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5034 bnapi = &bp->bnx2_napi[i];
5035 txr = &bnapi->tx_ring;
5036 rxr = &bnapi->rx_ring;
5037
5038 txr->tx_cons = 0;
5039 txr->hw_tx_cons = 0;
5040 rxr->rx_prod_bseq = 0;
5041 rxr->rx_prod = 0;
5042 rxr->rx_cons = 0;
5043 rxr->rx_pg_prod = 0;
5044 rxr->rx_pg_cons = 0;
5045 }
5046 }
5047
5048 static void
5049 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5050 {
5051 u32 val, offset0, offset1, offset2, offset3;
5052 u32 cid_addr = GET_CID_ADDR(cid);
5053
5054 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5055 offset0 = BNX2_L2CTX_TYPE_XI;
5056 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5057 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5058 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5059 } else {
5060 offset0 = BNX2_L2CTX_TYPE;
5061 offset1 = BNX2_L2CTX_CMD_TYPE;
5062 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5063 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5064 }
5065 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5066 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5067
5068 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5069 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5070
5071 val = (u64) txr->tx_desc_mapping >> 32;
5072 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5073
5074 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5075 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5076 }
5077
5078 static void
5079 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5080 {
5081 struct tx_bd *txbd;
5082 u32 cid = TX_CID;
5083 struct bnx2_napi *bnapi;
5084 struct bnx2_tx_ring_info *txr;
5085
5086 bnapi = &bp->bnx2_napi[ring_num];
5087 txr = &bnapi->tx_ring;
5088
5089 if (ring_num == 0)
5090 cid = TX_CID;
5091 else
5092 cid = TX_TSS_CID + ring_num - 1;
5093
5094 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5095
5096 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5097
5098 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5099 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5100
5101 txr->tx_prod = 0;
5102 txr->tx_prod_bseq = 0;
5103
5104 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5105 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5106
5107 bnx2_init_tx_context(bp, cid, txr);
5108 }
5109
5110 static void
5111 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5112 int num_rings)
5113 {
5114 int i;
5115 struct rx_bd *rxbd;
5116
5117 for (i = 0; i < num_rings; i++) {
5118 int j;
5119
5120 rxbd = &rx_ring[i][0];
5121 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5122 rxbd->rx_bd_len = buf_size;
5123 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5124 }
5125 if (i == (num_rings - 1))
5126 j = 0;
5127 else
5128 j = i + 1;
5129 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5130 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5131 }
5132 }
5133
5134 static void
5135 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5136 {
5137 int i;
5138 u16 prod, ring_prod;
5139 u32 cid, rx_cid_addr, val;
5140 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5141 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5142
5143 if (ring_num == 0)
5144 cid = RX_CID;
5145 else
5146 cid = RX_RSS_CID + ring_num - 1;
5147
5148 rx_cid_addr = GET_CID_ADDR(cid);
5149
5150 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5151 bp->rx_buf_use_size, bp->rx_max_ring);
5152
5153 bnx2_init_rx_context(bp, cid);
5154
5155 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5156 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5157 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5158 }
5159
5160 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5161 if (bp->rx_pg_ring_size) {
5162 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5163 rxr->rx_pg_desc_mapping,
5164 PAGE_SIZE, bp->rx_max_pg_ring);
5165 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5166 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5167 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5168 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5169
5170 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5171 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5172
5173 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5174 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5175
5176 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5177 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5178 }
5179
5180 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5181 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5182
5183 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5184 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5185
5186 ring_prod = prod = rxr->rx_pg_prod;
5187 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5188 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5189 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5190 ring_num, i, bp->rx_pg_ring_size);
5191 break;
5192 }
5193 prod = NEXT_RX_BD(prod);
5194 ring_prod = RX_PG_RING_IDX(prod);
5195 }
5196 rxr->rx_pg_prod = prod;
5197
5198 ring_prod = prod = rxr->rx_prod;
5199 for (i = 0; i < bp->rx_ring_size; i++) {
5200 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
5201 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5202 ring_num, i, bp->rx_ring_size);
5203 break;
5204 }
5205 prod = NEXT_RX_BD(prod);
5206 ring_prod = RX_RING_IDX(prod);
5207 }
5208 rxr->rx_prod = prod;
5209
5210 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5211 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5212 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5213
5214 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5215 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5216
5217 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5218 }
5219
5220 static void
5221 bnx2_init_all_rings(struct bnx2 *bp)
5222 {
5223 int i;
5224 u32 val;
5225
5226 bnx2_clear_ring_states(bp);
5227
5228 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5229 for (i = 0; i < bp->num_tx_rings; i++)
5230 bnx2_init_tx_ring(bp, i);
5231
5232 if (bp->num_tx_rings > 1)
5233 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5234 (TX_TSS_CID << 7));
5235
5236 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5237 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5238
5239 for (i = 0; i < bp->num_rx_rings; i++)
5240 bnx2_init_rx_ring(bp, i);
5241
5242 if (bp->num_rx_rings > 1) {
5243 u32 tbl_32;
5244 u8 *tbl = (u8 *) &tbl_32;
5245
5246 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5247 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5248
5249 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5250 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5251 if ((i % 4) == 3)
5252 bnx2_reg_wr_ind(bp,
5253 BNX2_RXP_SCRATCH_RSS_TBL + i,
5254 cpu_to_be32(tbl_32));
5255 }
5256
5257 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5258 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5259
5260 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5261
5262 }
5263 }
5264
5265 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5266 {
5267 u32 max, num_rings = 1;
5268
5269 while (ring_size > MAX_RX_DESC_CNT) {
5270 ring_size -= MAX_RX_DESC_CNT;
5271 num_rings++;
5272 }
5273 /* round to next power of 2 */
5274 max = max_size;
5275 while ((max & num_rings) == 0)
5276 max >>= 1;
5277
5278 if (num_rings != max)
5279 max <<= 1;
5280
5281 return max;
5282 }
5283
5284 static void
5285 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5286 {
5287 u32 rx_size, rx_space, jumbo_size;
5288
5289 /* 8 for CRC and VLAN */
5290 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5291
5292 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5293 sizeof(struct skb_shared_info);
5294
5295 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5296 bp->rx_pg_ring_size = 0;
5297 bp->rx_max_pg_ring = 0;
5298 bp->rx_max_pg_ring_idx = 0;
5299 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5300 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5301
5302 jumbo_size = size * pages;
5303 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5304 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5305
5306 bp->rx_pg_ring_size = jumbo_size;
5307 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5308 MAX_RX_PG_RINGS);
5309 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5310 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5311 bp->rx_copy_thresh = 0;
5312 }
5313
5314 bp->rx_buf_use_size = rx_size;
5315 /* hw alignment */
5316 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5317 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5318 bp->rx_ring_size = size;
5319 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5320 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5321 }
5322
5323 static void
5324 bnx2_free_tx_skbs(struct bnx2 *bp)
5325 {
5326 int i;
5327
5328 for (i = 0; i < bp->num_tx_rings; i++) {
5329 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5330 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5331 int j;
5332
5333 if (txr->tx_buf_ring == NULL)
5334 continue;
5335
5336 for (j = 0; j < TX_DESC_CNT; ) {
5337 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5338 struct sk_buff *skb = tx_buf->skb;
5339 int k, last;
5340
5341 if (skb == NULL) {
5342 j++;
5343 continue;
5344 }
5345
5346 dma_unmap_single(&bp->pdev->dev,
5347 dma_unmap_addr(tx_buf, mapping),
5348 skb_headlen(skb),
5349 PCI_DMA_TODEVICE);
5350
5351 tx_buf->skb = NULL;
5352
5353 last = tx_buf->nr_frags;
5354 j++;
5355 for (k = 0; k < last; k++, j++) {
5356 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5357 dma_unmap_page(&bp->pdev->dev,
5358 dma_unmap_addr(tx_buf, mapping),
5359 skb_shinfo(skb)->frags[k].size,
5360 PCI_DMA_TODEVICE);
5361 }
5362 dev_kfree_skb(skb);
5363 }
5364 }
5365 }
5366
5367 static void
5368 bnx2_free_rx_skbs(struct bnx2 *bp)
5369 {
5370 int i;
5371
5372 for (i = 0; i < bp->num_rx_rings; i++) {
5373 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5374 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5375 int j;
5376
5377 if (rxr->rx_buf_ring == NULL)
5378 return;
5379
5380 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5381 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5382 struct sk_buff *skb = rx_buf->skb;
5383
5384 if (skb == NULL)
5385 continue;
5386
5387 dma_unmap_single(&bp->pdev->dev,
5388 dma_unmap_addr(rx_buf, mapping),
5389 bp->rx_buf_use_size,
5390 PCI_DMA_FROMDEVICE);
5391
5392 rx_buf->skb = NULL;
5393
5394 dev_kfree_skb(skb);
5395 }
5396 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5397 bnx2_free_rx_page(bp, rxr, j);
5398 }
5399 }
5400
5401 static void
5402 bnx2_free_skbs(struct bnx2 *bp)
5403 {
5404 bnx2_free_tx_skbs(bp);
5405 bnx2_free_rx_skbs(bp);
5406 }
5407
5408 static int
5409 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5410 {
5411 int rc;
5412
5413 rc = bnx2_reset_chip(bp, reset_code);
5414 bnx2_free_skbs(bp);
5415 if (rc)
5416 return rc;
5417
5418 if ((rc = bnx2_init_chip(bp)) != 0)
5419 return rc;
5420
5421 bnx2_init_all_rings(bp);
5422 return 0;
5423 }
5424
5425 static int
5426 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5427 {
5428 int rc;
5429
5430 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5431 return rc;
5432
5433 spin_lock_bh(&bp->phy_lock);
5434 bnx2_init_phy(bp, reset_phy);
5435 bnx2_set_link(bp);
5436 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5437 bnx2_remote_phy_event(bp);
5438 spin_unlock_bh(&bp->phy_lock);
5439 return 0;
5440 }
5441
5442 static int
5443 bnx2_shutdown_chip(struct bnx2 *bp)
5444 {
5445 u32 reset_code;
5446
5447 if (bp->flags & BNX2_FLAG_NO_WOL)
5448 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5449 else if (bp->wol)
5450 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5451 else
5452 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5453
5454 return bnx2_reset_chip(bp, reset_code);
5455 }
5456
5457 static int
5458 bnx2_test_registers(struct bnx2 *bp)
5459 {
5460 int ret;
5461 int i, is_5709;
5462 static const struct {
5463 u16 offset;
5464 u16 flags;
5465 #define BNX2_FL_NOT_5709 1
5466 u32 rw_mask;
5467 u32 ro_mask;
5468 } reg_tbl[] = {
5469 { 0x006c, 0, 0x00000000, 0x0000003f },
5470 { 0x0090, 0, 0xffffffff, 0x00000000 },
5471 { 0x0094, 0, 0x00000000, 0x00000000 },
5472
5473 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5474 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5475 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5476 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5477 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5478 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5479 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5480 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5481 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5482
5483 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5484 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5485 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5486 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5487 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5488 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5489
5490 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5491 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5492 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5493
5494 { 0x1000, 0, 0x00000000, 0x00000001 },
5495 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5496
5497 { 0x1408, 0, 0x01c00800, 0x00000000 },
5498 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5499 { 0x14a8, 0, 0x00000000, 0x000001ff },
5500 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5501 { 0x14b0, 0, 0x00000002, 0x00000001 },
5502 { 0x14b8, 0, 0x00000000, 0x00000000 },
5503 { 0x14c0, 0, 0x00000000, 0x00000009 },
5504 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5505 { 0x14cc, 0, 0x00000000, 0x00000001 },
5506 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5507
5508 { 0x1800, 0, 0x00000000, 0x00000001 },
5509 { 0x1804, 0, 0x00000000, 0x00000003 },
5510
5511 { 0x2800, 0, 0x00000000, 0x00000001 },
5512 { 0x2804, 0, 0x00000000, 0x00003f01 },
5513 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5514 { 0x2810, 0, 0xffff0000, 0x00000000 },
5515 { 0x2814, 0, 0xffff0000, 0x00000000 },
5516 { 0x2818, 0, 0xffff0000, 0x00000000 },
5517 { 0x281c, 0, 0xffff0000, 0x00000000 },
5518 { 0x2834, 0, 0xffffffff, 0x00000000 },
5519 { 0x2840, 0, 0x00000000, 0xffffffff },
5520 { 0x2844, 0, 0x00000000, 0xffffffff },
5521 { 0x2848, 0, 0xffffffff, 0x00000000 },
5522 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5523
5524 { 0x2c00, 0, 0x00000000, 0x00000011 },
5525 { 0x2c04, 0, 0x00000000, 0x00030007 },
5526
5527 { 0x3c00, 0, 0x00000000, 0x00000001 },
5528 { 0x3c04, 0, 0x00000000, 0x00070000 },
5529 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5530 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5531 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5532 { 0x3c14, 0, 0x00000000, 0xffffffff },
5533 { 0x3c18, 0, 0x00000000, 0xffffffff },
5534 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5535 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5536
5537 { 0x5004, 0, 0x00000000, 0x0000007f },
5538 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5539
5540 { 0x5c00, 0, 0x00000000, 0x00000001 },
5541 { 0x5c04, 0, 0x00000000, 0x0003000f },
5542 { 0x5c08, 0, 0x00000003, 0x00000000 },
5543 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5544 { 0x5c10, 0, 0x00000000, 0xffffffff },
5545 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5546 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5547 { 0x5c88, 0, 0x00000000, 0x00077373 },
5548 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5549
5550 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5551 { 0x680c, 0, 0xffffffff, 0x00000000 },
5552 { 0x6810, 0, 0xffffffff, 0x00000000 },
5553 { 0x6814, 0, 0xffffffff, 0x00000000 },
5554 { 0x6818, 0, 0xffffffff, 0x00000000 },
5555 { 0x681c, 0, 0xffffffff, 0x00000000 },
5556 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5557 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5558 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5559 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5560 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5561 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5562 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5563 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5564 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5565 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5566 { 0x684c, 0, 0xffffffff, 0x00000000 },
5567 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5568 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5569 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5570 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5571 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5572 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5573
5574 { 0xffff, 0, 0x00000000, 0x00000000 },
5575 };
5576
5577 ret = 0;
5578 is_5709 = 0;
5579 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5580 is_5709 = 1;
5581
5582 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5583 u32 offset, rw_mask, ro_mask, save_val, val;
5584 u16 flags = reg_tbl[i].flags;
5585
5586 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5587 continue;
5588
5589 offset = (u32) reg_tbl[i].offset;
5590 rw_mask = reg_tbl[i].rw_mask;
5591 ro_mask = reg_tbl[i].ro_mask;
5592
5593 save_val = readl(bp->regview + offset);
5594
5595 writel(0, bp->regview + offset);
5596
5597 val = readl(bp->regview + offset);
5598 if ((val & rw_mask) != 0) {
5599 goto reg_test_err;
5600 }
5601
5602 if ((val & ro_mask) != (save_val & ro_mask)) {
5603 goto reg_test_err;
5604 }
5605
5606 writel(0xffffffff, bp->regview + offset);
5607
5608 val = readl(bp->regview + offset);
5609 if ((val & rw_mask) != rw_mask) {
5610 goto reg_test_err;
5611 }
5612
5613 if ((val & ro_mask) != (save_val & ro_mask)) {
5614 goto reg_test_err;
5615 }
5616
5617 writel(save_val, bp->regview + offset);
5618 continue;
5619
5620 reg_test_err:
5621 writel(save_val, bp->regview + offset);
5622 ret = -ENODEV;
5623 break;
5624 }
5625 return ret;
5626 }
5627
5628 static int
5629 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5630 {
5631 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5632 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5633 int i;
5634
5635 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5636 u32 offset;
5637
5638 for (offset = 0; offset < size; offset += 4) {
5639
5640 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5641
5642 if (bnx2_reg_rd_ind(bp, start + offset) !=
5643 test_pattern[i]) {
5644 return -ENODEV;
5645 }
5646 }
5647 }
5648 return 0;
5649 }
5650
5651 static int
5652 bnx2_test_memory(struct bnx2 *bp)
5653 {
5654 int ret = 0;
5655 int i;
5656 static struct mem_entry {
5657 u32 offset;
5658 u32 len;
5659 } mem_tbl_5706[] = {
5660 { 0x60000, 0x4000 },
5661 { 0xa0000, 0x3000 },
5662 { 0xe0000, 0x4000 },
5663 { 0x120000, 0x4000 },
5664 { 0x1a0000, 0x4000 },
5665 { 0x160000, 0x4000 },
5666 { 0xffffffff, 0 },
5667 },
5668 mem_tbl_5709[] = {
5669 { 0x60000, 0x4000 },
5670 { 0xa0000, 0x3000 },
5671 { 0xe0000, 0x4000 },
5672 { 0x120000, 0x4000 },
5673 { 0x1a0000, 0x4000 },
5674 { 0xffffffff, 0 },
5675 };
5676 struct mem_entry *mem_tbl;
5677
5678 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5679 mem_tbl = mem_tbl_5709;
5680 else
5681 mem_tbl = mem_tbl_5706;
5682
5683 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5684 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5685 mem_tbl[i].len)) != 0) {
5686 return ret;
5687 }
5688 }
5689
5690 return ret;
5691 }
5692
5693 #define BNX2_MAC_LOOPBACK 0
5694 #define BNX2_PHY_LOOPBACK 1
5695
5696 static int
5697 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5698 {
5699 unsigned int pkt_size, num_pkts, i;
5700 struct sk_buff *skb, *rx_skb;
5701 unsigned char *packet;
5702 u16 rx_start_idx, rx_idx;
5703 dma_addr_t map;
5704 struct tx_bd *txbd;
5705 struct sw_bd *rx_buf;
5706 struct l2_fhdr *rx_hdr;
5707 int ret = -ENODEV;
5708 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5709 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5710 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5711
5712 tx_napi = bnapi;
5713
5714 txr = &tx_napi->tx_ring;
5715 rxr = &bnapi->rx_ring;
5716 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5717 bp->loopback = MAC_LOOPBACK;
5718 bnx2_set_mac_loopback(bp);
5719 }
5720 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5721 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5722 return 0;
5723
5724 bp->loopback = PHY_LOOPBACK;
5725 bnx2_set_phy_loopback(bp);
5726 }
5727 else
5728 return -EINVAL;
5729
5730 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5731 skb = netdev_alloc_skb(bp->dev, pkt_size);
5732 if (!skb)
5733 return -ENOMEM;
5734 packet = skb_put(skb, pkt_size);
5735 memcpy(packet, bp->dev->dev_addr, 6);
5736 memset(packet + 6, 0x0, 8);
5737 for (i = 14; i < pkt_size; i++)
5738 packet[i] = (unsigned char) (i & 0xff);
5739
5740 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5741 PCI_DMA_TODEVICE);
5742 if (dma_mapping_error(&bp->pdev->dev, map)) {
5743 dev_kfree_skb(skb);
5744 return -EIO;
5745 }
5746
5747 REG_WR(bp, BNX2_HC_COMMAND,
5748 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5749
5750 REG_RD(bp, BNX2_HC_COMMAND);
5751
5752 udelay(5);
5753 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5754
5755 num_pkts = 0;
5756
5757 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5758
5759 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5760 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5761 txbd->tx_bd_mss_nbytes = pkt_size;
5762 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5763
5764 num_pkts++;
5765 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5766 txr->tx_prod_bseq += pkt_size;
5767
5768 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5769 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5770
5771 udelay(100);
5772
5773 REG_WR(bp, BNX2_HC_COMMAND,
5774 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5775
5776 REG_RD(bp, BNX2_HC_COMMAND);
5777
5778 udelay(5);
5779
5780 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
5781 dev_kfree_skb(skb);
5782
5783 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5784 goto loopback_test_done;
5785
5786 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5787 if (rx_idx != rx_start_idx + num_pkts) {
5788 goto loopback_test_done;
5789 }
5790
5791 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5792 rx_skb = rx_buf->skb;
5793
5794 rx_hdr = rx_buf->desc;
5795 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5796
5797 dma_sync_single_for_cpu(&bp->pdev->dev,
5798 dma_unmap_addr(rx_buf, mapping),
5799 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5800
5801 if (rx_hdr->l2_fhdr_status &
5802 (L2_FHDR_ERRORS_BAD_CRC |
5803 L2_FHDR_ERRORS_PHY_DECODE |
5804 L2_FHDR_ERRORS_ALIGNMENT |
5805 L2_FHDR_ERRORS_TOO_SHORT |
5806 L2_FHDR_ERRORS_GIANT_FRAME)) {
5807
5808 goto loopback_test_done;
5809 }
5810
5811 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5812 goto loopback_test_done;
5813 }
5814
5815 for (i = 14; i < pkt_size; i++) {
5816 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5817 goto loopback_test_done;
5818 }
5819 }
5820
5821 ret = 0;
5822
5823 loopback_test_done:
5824 bp->loopback = 0;
5825 return ret;
5826 }
5827
5828 #define BNX2_MAC_LOOPBACK_FAILED 1
5829 #define BNX2_PHY_LOOPBACK_FAILED 2
5830 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5831 BNX2_PHY_LOOPBACK_FAILED)
5832
5833 static int
5834 bnx2_test_loopback(struct bnx2 *bp)
5835 {
5836 int rc = 0;
5837
5838 if (!netif_running(bp->dev))
5839 return BNX2_LOOPBACK_FAILED;
5840
5841 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5842 spin_lock_bh(&bp->phy_lock);
5843 bnx2_init_phy(bp, 1);
5844 spin_unlock_bh(&bp->phy_lock);
5845 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5846 rc |= BNX2_MAC_LOOPBACK_FAILED;
5847 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5848 rc |= BNX2_PHY_LOOPBACK_FAILED;
5849 return rc;
5850 }
5851
5852 #define NVRAM_SIZE 0x200
5853 #define CRC32_RESIDUAL 0xdebb20e3
5854
5855 static int
5856 bnx2_test_nvram(struct bnx2 *bp)
5857 {
5858 __be32 buf[NVRAM_SIZE / 4];
5859 u8 *data = (u8 *) buf;
5860 int rc = 0;
5861 u32 magic, csum;
5862
5863 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5864 goto test_nvram_done;
5865
5866 magic = be32_to_cpu(buf[0]);
5867 if (magic != 0x669955aa) {
5868 rc = -ENODEV;
5869 goto test_nvram_done;
5870 }
5871
5872 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5873 goto test_nvram_done;
5874
5875 csum = ether_crc_le(0x100, data);
5876 if (csum != CRC32_RESIDUAL) {
5877 rc = -ENODEV;
5878 goto test_nvram_done;
5879 }
5880
5881 csum = ether_crc_le(0x100, data + 0x100);
5882 if (csum != CRC32_RESIDUAL) {
5883 rc = -ENODEV;
5884 }
5885
5886 test_nvram_done:
5887 return rc;
5888 }
5889
5890 static int
5891 bnx2_test_link(struct bnx2 *bp)
5892 {
5893 u32 bmsr;
5894
5895 if (!netif_running(bp->dev))
5896 return -ENODEV;
5897
5898 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5899 if (bp->link_up)
5900 return 0;
5901 return -ENODEV;
5902 }
5903 spin_lock_bh(&bp->phy_lock);
5904 bnx2_enable_bmsr1(bp);
5905 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5906 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5907 bnx2_disable_bmsr1(bp);
5908 spin_unlock_bh(&bp->phy_lock);
5909
5910 if (bmsr & BMSR_LSTATUS) {
5911 return 0;
5912 }
5913 return -ENODEV;
5914 }
5915
5916 static int
5917 bnx2_test_intr(struct bnx2 *bp)
5918 {
5919 int i;
5920 u16 status_idx;
5921
5922 if (!netif_running(bp->dev))
5923 return -ENODEV;
5924
5925 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5926
5927 /* This register is not touched during run-time. */
5928 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5929 REG_RD(bp, BNX2_HC_COMMAND);
5930
5931 for (i = 0; i < 10; i++) {
5932 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5933 status_idx) {
5934
5935 break;
5936 }
5937
5938 msleep_interruptible(10);
5939 }
5940 if (i < 10)
5941 return 0;
5942
5943 return -ENODEV;
5944 }
5945
5946 /* Determining link for parallel detection. */
5947 static int
5948 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5949 {
5950 u32 mode_ctl, an_dbg, exp;
5951
5952 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5953 return 0;
5954
5955 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5956 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5957
5958 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5959 return 0;
5960
5961 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5962 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5963 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5964
5965 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5966 return 0;
5967
5968 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5969 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5970 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5971
5972 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5973 return 0;
5974
5975 return 1;
5976 }
5977
5978 static void
5979 bnx2_5706_serdes_timer(struct bnx2 *bp)
5980 {
5981 int check_link = 1;
5982
5983 spin_lock(&bp->phy_lock);
5984 if (bp->serdes_an_pending) {
5985 bp->serdes_an_pending--;
5986 check_link = 0;
5987 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5988 u32 bmcr;
5989
5990 bp->current_interval = BNX2_TIMER_INTERVAL;
5991
5992 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5993
5994 if (bmcr & BMCR_ANENABLE) {
5995 if (bnx2_5706_serdes_has_link(bp)) {
5996 bmcr &= ~BMCR_ANENABLE;
5997 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5998 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5999 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
6000 }
6001 }
6002 }
6003 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
6004 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
6005 u32 phy2;
6006
6007 bnx2_write_phy(bp, 0x17, 0x0f01);
6008 bnx2_read_phy(bp, 0x15, &phy2);
6009 if (phy2 & 0x20) {
6010 u32 bmcr;
6011
6012 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6013 bmcr |= BMCR_ANENABLE;
6014 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6015
6016 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
6017 }
6018 } else
6019 bp->current_interval = BNX2_TIMER_INTERVAL;
6020
6021 if (check_link) {
6022 u32 val;
6023
6024 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6025 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6026 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6027
6028 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6029 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6030 bnx2_5706s_force_link_dn(bp, 1);
6031 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6032 } else
6033 bnx2_set_link(bp);
6034 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6035 bnx2_set_link(bp);
6036 }
6037 spin_unlock(&bp->phy_lock);
6038 }
6039
6040 static void
6041 bnx2_5708_serdes_timer(struct bnx2 *bp)
6042 {
6043 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6044 return;
6045
6046 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6047 bp->serdes_an_pending = 0;
6048 return;
6049 }
6050
6051 spin_lock(&bp->phy_lock);
6052 if (bp->serdes_an_pending)
6053 bp->serdes_an_pending--;
6054 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6055 u32 bmcr;
6056
6057 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6058 if (bmcr & BMCR_ANENABLE) {
6059 bnx2_enable_forced_2g5(bp);
6060 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6061 } else {
6062 bnx2_disable_forced_2g5(bp);
6063 bp->serdes_an_pending = 2;
6064 bp->current_interval = BNX2_TIMER_INTERVAL;
6065 }
6066
6067 } else
6068 bp->current_interval = BNX2_TIMER_INTERVAL;
6069
6070 spin_unlock(&bp->phy_lock);
6071 }
6072
6073 static void
6074 bnx2_timer(unsigned long data)
6075 {
6076 struct bnx2 *bp = (struct bnx2 *) data;
6077
6078 if (!netif_running(bp->dev))
6079 return;
6080
6081 if (atomic_read(&bp->intr_sem) != 0)
6082 goto bnx2_restart_timer;
6083
6084 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6085 BNX2_FLAG_USING_MSI)
6086 bnx2_chk_missed_msi(bp);
6087
6088 bnx2_send_heart_beat(bp);
6089
6090 bp->stats_blk->stat_FwRxDrop =
6091 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6092
6093 /* workaround occasional corrupted counters */
6094 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6095 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6096 BNX2_HC_COMMAND_STATS_NOW);
6097
6098 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6099 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6100 bnx2_5706_serdes_timer(bp);
6101 else
6102 bnx2_5708_serdes_timer(bp);
6103 }
6104
6105 bnx2_restart_timer:
6106 mod_timer(&bp->timer, jiffies + bp->current_interval);
6107 }
6108
6109 static int
6110 bnx2_request_irq(struct bnx2 *bp)
6111 {
6112 unsigned long flags;
6113 struct bnx2_irq *irq;
6114 int rc = 0, i;
6115
6116 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6117 flags = 0;
6118 else
6119 flags = IRQF_SHARED;
6120
6121 for (i = 0; i < bp->irq_nvecs; i++) {
6122 irq = &bp->irq_tbl[i];
6123 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6124 &bp->bnx2_napi[i]);
6125 if (rc)
6126 break;
6127 irq->requested = 1;
6128 }
6129 return rc;
6130 }
6131
6132 static void
6133 bnx2_free_irq(struct bnx2 *bp)
6134 {
6135 struct bnx2_irq *irq;
6136 int i;
6137
6138 for (i = 0; i < bp->irq_nvecs; i++) {
6139 irq = &bp->irq_tbl[i];
6140 if (irq->requested)
6141 free_irq(irq->vector, &bp->bnx2_napi[i]);
6142 irq->requested = 0;
6143 }
6144 if (bp->flags & BNX2_FLAG_USING_MSI)
6145 pci_disable_msi(bp->pdev);
6146 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6147 pci_disable_msix(bp->pdev);
6148
6149 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6150 }
6151
6152 static void
6153 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6154 {
6155 int i, rc;
6156 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6157 struct net_device *dev = bp->dev;
6158 const int len = sizeof(bp->irq_tbl[0].name);
6159
6160 bnx2_setup_msix_tbl(bp);
6161 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6162 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6163 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6164
6165 /* Need to flush the previous three writes to ensure MSI-X
6166 * is setup properly */
6167 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6168
6169 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6170 msix_ent[i].entry = i;
6171 msix_ent[i].vector = 0;
6172 }
6173
6174 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6175 if (rc != 0)
6176 return;
6177
6178 bp->irq_nvecs = msix_vecs;
6179 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6180 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6181 bp->irq_tbl[i].vector = msix_ent[i].vector;
6182 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6183 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6184 }
6185 }
6186
6187 static void
6188 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6189 {
6190 int cpus = num_online_cpus();
6191 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6192
6193 bp->irq_tbl[0].handler = bnx2_interrupt;
6194 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6195 bp->irq_nvecs = 1;
6196 bp->irq_tbl[0].vector = bp->pdev->irq;
6197
6198 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
6199 bnx2_enable_msix(bp, msix_vecs);
6200
6201 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6202 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6203 if (pci_enable_msi(bp->pdev) == 0) {
6204 bp->flags |= BNX2_FLAG_USING_MSI;
6205 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6206 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6207 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6208 } else
6209 bp->irq_tbl[0].handler = bnx2_msi;
6210
6211 bp->irq_tbl[0].vector = bp->pdev->irq;
6212 }
6213 }
6214
6215 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6216 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6217
6218 bp->num_rx_rings = bp->irq_nvecs;
6219 }
6220
6221 /* Called with rtnl_lock */
6222 static int
6223 bnx2_open(struct net_device *dev)
6224 {
6225 struct bnx2 *bp = netdev_priv(dev);
6226 int rc;
6227
6228 netif_carrier_off(dev);
6229
6230 bnx2_set_power_state(bp, PCI_D0);
6231 bnx2_disable_int(bp);
6232
6233 bnx2_setup_int_mode(bp, disable_msi);
6234 bnx2_init_napi(bp);
6235 bnx2_napi_enable(bp);
6236 rc = bnx2_alloc_mem(bp);
6237 if (rc)
6238 goto open_err;
6239
6240 rc = bnx2_request_irq(bp);
6241 if (rc)
6242 goto open_err;
6243
6244 rc = bnx2_init_nic(bp, 1);
6245 if (rc)
6246 goto open_err;
6247
6248 mod_timer(&bp->timer, jiffies + bp->current_interval);
6249
6250 atomic_set(&bp->intr_sem, 0);
6251
6252 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6253
6254 bnx2_enable_int(bp);
6255
6256 if (bp->flags & BNX2_FLAG_USING_MSI) {
6257 /* Test MSI to make sure it is working
6258 * If MSI test fails, go back to INTx mode
6259 */
6260 if (bnx2_test_intr(bp) != 0) {
6261 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6262
6263 bnx2_disable_int(bp);
6264 bnx2_free_irq(bp);
6265
6266 bnx2_setup_int_mode(bp, 1);
6267
6268 rc = bnx2_init_nic(bp, 0);
6269
6270 if (!rc)
6271 rc = bnx2_request_irq(bp);
6272
6273 if (rc) {
6274 del_timer_sync(&bp->timer);
6275 goto open_err;
6276 }
6277 bnx2_enable_int(bp);
6278 }
6279 }
6280 if (bp->flags & BNX2_FLAG_USING_MSI)
6281 netdev_info(dev, "using MSI\n");
6282 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6283 netdev_info(dev, "using MSIX\n");
6284
6285 netif_tx_start_all_queues(dev);
6286
6287 return 0;
6288
6289 open_err:
6290 bnx2_napi_disable(bp);
6291 bnx2_free_skbs(bp);
6292 bnx2_free_irq(bp);
6293 bnx2_free_mem(bp);
6294 bnx2_del_napi(bp);
6295 return rc;
6296 }
6297
6298 static void
6299 bnx2_reset_task(struct work_struct *work)
6300 {
6301 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6302
6303 rtnl_lock();
6304 if (!netif_running(bp->dev)) {
6305 rtnl_unlock();
6306 return;
6307 }
6308
6309 bnx2_netif_stop(bp, true);
6310
6311 bnx2_init_nic(bp, 1);
6312
6313 atomic_set(&bp->intr_sem, 1);
6314 bnx2_netif_start(bp, true);
6315 rtnl_unlock();
6316 }
6317
6318 static void
6319 bnx2_dump_state(struct bnx2 *bp)
6320 {
6321 struct net_device *dev = bp->dev;
6322 u32 mcp_p0, mcp_p1, val1, val2;
6323
6324 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6325 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6326 atomic_read(&bp->intr_sem), val1);
6327 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6328 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6329 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
6330 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6331 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6332 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6333 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6334 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6335 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6336 mcp_p0 = BNX2_MCP_STATE_P0;
6337 mcp_p1 = BNX2_MCP_STATE_P1;
6338 } else {
6339 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6340 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6341 }
6342 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6343 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
6344 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6345 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6346 if (bp->flags & BNX2_FLAG_USING_MSIX)
6347 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6348 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6349 }
6350
6351 static void
6352 bnx2_tx_timeout(struct net_device *dev)
6353 {
6354 struct bnx2 *bp = netdev_priv(dev);
6355
6356 bnx2_dump_state(bp);
6357
6358 /* This allows the netif to be shutdown gracefully before resetting */
6359 schedule_work(&bp->reset_task);
6360 }
6361
6362 #ifdef BCM_VLAN
6363 /* Called with rtnl_lock */
6364 static void
6365 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6366 {
6367 struct bnx2 *bp = netdev_priv(dev);
6368
6369 if (netif_running(dev))
6370 bnx2_netif_stop(bp, false);
6371
6372 bp->vlgrp = vlgrp;
6373
6374 if (!netif_running(dev))
6375 return;
6376
6377 bnx2_set_rx_mode(dev);
6378 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6379 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6380
6381 bnx2_netif_start(bp, false);
6382 }
6383 #endif
6384
6385 /* Called with netif_tx_lock.
6386 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6387 * netif_wake_queue().
6388 */
6389 static netdev_tx_t
6390 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6391 {
6392 struct bnx2 *bp = netdev_priv(dev);
6393 dma_addr_t mapping;
6394 struct tx_bd *txbd;
6395 struct sw_tx_bd *tx_buf;
6396 u32 len, vlan_tag_flags, last_frag, mss;
6397 u16 prod, ring_prod;
6398 int i;
6399 struct bnx2_napi *bnapi;
6400 struct bnx2_tx_ring_info *txr;
6401 struct netdev_queue *txq;
6402
6403 /* Determine which tx ring we will be placed on */
6404 i = skb_get_queue_mapping(skb);
6405 bnapi = &bp->bnx2_napi[i];
6406 txr = &bnapi->tx_ring;
6407 txq = netdev_get_tx_queue(dev, i);
6408
6409 if (unlikely(bnx2_tx_avail(bp, txr) <
6410 (skb_shinfo(skb)->nr_frags + 1))) {
6411 netif_tx_stop_queue(txq);
6412 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6413
6414 return NETDEV_TX_BUSY;
6415 }
6416 len = skb_headlen(skb);
6417 prod = txr->tx_prod;
6418 ring_prod = TX_RING_IDX(prod);
6419
6420 vlan_tag_flags = 0;
6421 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6422 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6423 }
6424
6425 #ifdef BCM_VLAN
6426 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6427 vlan_tag_flags |=
6428 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6429 }
6430 #endif
6431 if ((mss = skb_shinfo(skb)->gso_size)) {
6432 u32 tcp_opt_len;
6433 struct iphdr *iph;
6434
6435 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6436
6437 tcp_opt_len = tcp_optlen(skb);
6438
6439 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6440 u32 tcp_off = skb_transport_offset(skb) -
6441 sizeof(struct ipv6hdr) - ETH_HLEN;
6442
6443 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6444 TX_BD_FLAGS_SW_FLAGS;
6445 if (likely(tcp_off == 0))
6446 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6447 else {
6448 tcp_off >>= 3;
6449 vlan_tag_flags |= ((tcp_off & 0x3) <<
6450 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6451 ((tcp_off & 0x10) <<
6452 TX_BD_FLAGS_TCP6_OFF4_SHL);
6453 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6454 }
6455 } else {
6456 iph = ip_hdr(skb);
6457 if (tcp_opt_len || (iph->ihl > 5)) {
6458 vlan_tag_flags |= ((iph->ihl - 5) +
6459 (tcp_opt_len >> 2)) << 8;
6460 }
6461 }
6462 } else
6463 mss = 0;
6464
6465 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6466 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
6467 dev_kfree_skb(skb);
6468 return NETDEV_TX_OK;
6469 }
6470
6471 tx_buf = &txr->tx_buf_ring[ring_prod];
6472 tx_buf->skb = skb;
6473 dma_unmap_addr_set(tx_buf, mapping, mapping);
6474
6475 txbd = &txr->tx_desc_ring[ring_prod];
6476
6477 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6478 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6479 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6480 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6481
6482 last_frag = skb_shinfo(skb)->nr_frags;
6483 tx_buf->nr_frags = last_frag;
6484 tx_buf->is_gso = skb_is_gso(skb);
6485
6486 for (i = 0; i < last_frag; i++) {
6487 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6488
6489 prod = NEXT_TX_BD(prod);
6490 ring_prod = TX_RING_IDX(prod);
6491 txbd = &txr->tx_desc_ring[ring_prod];
6492
6493 len = frag->size;
6494 mapping = dma_map_page(&bp->pdev->dev, frag->page, frag->page_offset,
6495 len, PCI_DMA_TODEVICE);
6496 if (dma_mapping_error(&bp->pdev->dev, mapping))
6497 goto dma_error;
6498 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6499 mapping);
6500
6501 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6502 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6503 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6504 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6505
6506 }
6507 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6508
6509 prod = NEXT_TX_BD(prod);
6510 txr->tx_prod_bseq += skb->len;
6511
6512 REG_WR16(bp, txr->tx_bidx_addr, prod);
6513 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6514
6515 mmiowb();
6516
6517 txr->tx_prod = prod;
6518
6519 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6520 netif_tx_stop_queue(txq);
6521 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6522 netif_tx_wake_queue(txq);
6523 }
6524
6525 return NETDEV_TX_OK;
6526 dma_error:
6527 /* save value of frag that failed */
6528 last_frag = i;
6529
6530 /* start back at beginning and unmap skb */
6531 prod = txr->tx_prod;
6532 ring_prod = TX_RING_IDX(prod);
6533 tx_buf = &txr->tx_buf_ring[ring_prod];
6534 tx_buf->skb = NULL;
6535 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6536 skb_headlen(skb), PCI_DMA_TODEVICE);
6537
6538 /* unmap remaining mapped pages */
6539 for (i = 0; i < last_frag; i++) {
6540 prod = NEXT_TX_BD(prod);
6541 ring_prod = TX_RING_IDX(prod);
6542 tx_buf = &txr->tx_buf_ring[ring_prod];
6543 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
6544 skb_shinfo(skb)->frags[i].size,
6545 PCI_DMA_TODEVICE);
6546 }
6547
6548 dev_kfree_skb(skb);
6549 return NETDEV_TX_OK;
6550 }
6551
6552 /* Called with rtnl_lock */
6553 static int
6554 bnx2_close(struct net_device *dev)
6555 {
6556 struct bnx2 *bp = netdev_priv(dev);
6557
6558 cancel_work_sync(&bp->reset_task);
6559
6560 bnx2_disable_int_sync(bp);
6561 bnx2_napi_disable(bp);
6562 del_timer_sync(&bp->timer);
6563 bnx2_shutdown_chip(bp);
6564 bnx2_free_irq(bp);
6565 bnx2_free_skbs(bp);
6566 bnx2_free_mem(bp);
6567 bnx2_del_napi(bp);
6568 bp->link_up = 0;
6569 netif_carrier_off(bp->dev);
6570 bnx2_set_power_state(bp, PCI_D3hot);
6571 return 0;
6572 }
6573
6574 static void
6575 bnx2_save_stats(struct bnx2 *bp)
6576 {
6577 u32 *hw_stats = (u32 *) bp->stats_blk;
6578 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6579 int i;
6580
6581 /* The 1st 10 counters are 64-bit counters */
6582 for (i = 0; i < 20; i += 2) {
6583 u32 hi;
6584 u64 lo;
6585
6586 hi = temp_stats[i] + hw_stats[i];
6587 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6588 if (lo > 0xffffffff)
6589 hi++;
6590 temp_stats[i] = hi;
6591 temp_stats[i + 1] = lo & 0xffffffff;
6592 }
6593
6594 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6595 temp_stats[i] += hw_stats[i];
6596 }
6597
6598 #define GET_64BIT_NET_STATS64(ctr) \
6599 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
6600
6601 #define GET_64BIT_NET_STATS(ctr) \
6602 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6603 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6604
6605 #define GET_32BIT_NET_STATS(ctr) \
6606 (unsigned long) (bp->stats_blk->ctr + \
6607 bp->temp_stats_blk->ctr)
6608
6609 static struct rtnl_link_stats64 *
6610 bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
6611 {
6612 struct bnx2 *bp = netdev_priv(dev);
6613
6614 if (bp->stats_blk == NULL)
6615 return net_stats;
6616
6617 net_stats->rx_packets =
6618 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6619 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6620 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6621
6622 net_stats->tx_packets =
6623 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6624 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6625 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6626
6627 net_stats->rx_bytes =
6628 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6629
6630 net_stats->tx_bytes =
6631 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6632
6633 net_stats->multicast =
6634 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts);
6635
6636 net_stats->collisions =
6637 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6638
6639 net_stats->rx_length_errors =
6640 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6641 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6642
6643 net_stats->rx_over_errors =
6644 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6645 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6646
6647 net_stats->rx_frame_errors =
6648 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6649
6650 net_stats->rx_crc_errors =
6651 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6652
6653 net_stats->rx_errors = net_stats->rx_length_errors +
6654 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6655 net_stats->rx_crc_errors;
6656
6657 net_stats->tx_aborted_errors =
6658 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6659 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6660
6661 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6662 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6663 net_stats->tx_carrier_errors = 0;
6664 else {
6665 net_stats->tx_carrier_errors =
6666 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6667 }
6668
6669 net_stats->tx_errors =
6670 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6671 net_stats->tx_aborted_errors +
6672 net_stats->tx_carrier_errors;
6673
6674 net_stats->rx_missed_errors =
6675 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6676 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6677 GET_32BIT_NET_STATS(stat_FwRxDrop);
6678
6679 return net_stats;
6680 }
6681
6682 /* All ethtool functions called with rtnl_lock */
6683
6684 static int
6685 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6686 {
6687 struct bnx2 *bp = netdev_priv(dev);
6688 int support_serdes = 0, support_copper = 0;
6689
6690 cmd->supported = SUPPORTED_Autoneg;
6691 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6692 support_serdes = 1;
6693 support_copper = 1;
6694 } else if (bp->phy_port == PORT_FIBRE)
6695 support_serdes = 1;
6696 else
6697 support_copper = 1;
6698
6699 if (support_serdes) {
6700 cmd->supported |= SUPPORTED_1000baseT_Full |
6701 SUPPORTED_FIBRE;
6702 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6703 cmd->supported |= SUPPORTED_2500baseX_Full;
6704
6705 }
6706 if (support_copper) {
6707 cmd->supported |= SUPPORTED_10baseT_Half |
6708 SUPPORTED_10baseT_Full |
6709 SUPPORTED_100baseT_Half |
6710 SUPPORTED_100baseT_Full |
6711 SUPPORTED_1000baseT_Full |
6712 SUPPORTED_TP;
6713
6714 }
6715
6716 spin_lock_bh(&bp->phy_lock);
6717 cmd->port = bp->phy_port;
6718 cmd->advertising = bp->advertising;
6719
6720 if (bp->autoneg & AUTONEG_SPEED) {
6721 cmd->autoneg = AUTONEG_ENABLE;
6722 }
6723 else {
6724 cmd->autoneg = AUTONEG_DISABLE;
6725 }
6726
6727 if (netif_carrier_ok(dev)) {
6728 cmd->speed = bp->line_speed;
6729 cmd->duplex = bp->duplex;
6730 }
6731 else {
6732 cmd->speed = -1;
6733 cmd->duplex = -1;
6734 }
6735 spin_unlock_bh(&bp->phy_lock);
6736
6737 cmd->transceiver = XCVR_INTERNAL;
6738 cmd->phy_address = bp->phy_addr;
6739
6740 return 0;
6741 }
6742
6743 static int
6744 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6745 {
6746 struct bnx2 *bp = netdev_priv(dev);
6747 u8 autoneg = bp->autoneg;
6748 u8 req_duplex = bp->req_duplex;
6749 u16 req_line_speed = bp->req_line_speed;
6750 u32 advertising = bp->advertising;
6751 int err = -EINVAL;
6752
6753 spin_lock_bh(&bp->phy_lock);
6754
6755 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6756 goto err_out_unlock;
6757
6758 if (cmd->port != bp->phy_port &&
6759 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6760 goto err_out_unlock;
6761
6762 /* If device is down, we can store the settings only if the user
6763 * is setting the currently active port.
6764 */
6765 if (!netif_running(dev) && cmd->port != bp->phy_port)
6766 goto err_out_unlock;
6767
6768 if (cmd->autoneg == AUTONEG_ENABLE) {
6769 autoneg |= AUTONEG_SPEED;
6770
6771 advertising = cmd->advertising;
6772 if (cmd->port == PORT_TP) {
6773 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6774 if (!advertising)
6775 advertising = ETHTOOL_ALL_COPPER_SPEED;
6776 } else {
6777 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6778 if (!advertising)
6779 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6780 }
6781 advertising |= ADVERTISED_Autoneg;
6782 }
6783 else {
6784 if (cmd->port == PORT_FIBRE) {
6785 if ((cmd->speed != SPEED_1000 &&
6786 cmd->speed != SPEED_2500) ||
6787 (cmd->duplex != DUPLEX_FULL))
6788 goto err_out_unlock;
6789
6790 if (cmd->speed == SPEED_2500 &&
6791 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6792 goto err_out_unlock;
6793 }
6794 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6795 goto err_out_unlock;
6796
6797 autoneg &= ~AUTONEG_SPEED;
6798 req_line_speed = cmd->speed;
6799 req_duplex = cmd->duplex;
6800 advertising = 0;
6801 }
6802
6803 bp->autoneg = autoneg;
6804 bp->advertising = advertising;
6805 bp->req_line_speed = req_line_speed;
6806 bp->req_duplex = req_duplex;
6807
6808 err = 0;
6809 /* If device is down, the new settings will be picked up when it is
6810 * brought up.
6811 */
6812 if (netif_running(dev))
6813 err = bnx2_setup_phy(bp, cmd->port);
6814
6815 err_out_unlock:
6816 spin_unlock_bh(&bp->phy_lock);
6817
6818 return err;
6819 }
6820
6821 static void
6822 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6823 {
6824 struct bnx2 *bp = netdev_priv(dev);
6825
6826 strcpy(info->driver, DRV_MODULE_NAME);
6827 strcpy(info->version, DRV_MODULE_VERSION);
6828 strcpy(info->bus_info, pci_name(bp->pdev));
6829 strcpy(info->fw_version, bp->fw_version);
6830 }
6831
6832 #define BNX2_REGDUMP_LEN (32 * 1024)
6833
6834 static int
6835 bnx2_get_regs_len(struct net_device *dev)
6836 {
6837 return BNX2_REGDUMP_LEN;
6838 }
6839
6840 static void
6841 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6842 {
6843 u32 *p = _p, i, offset;
6844 u8 *orig_p = _p;
6845 struct bnx2 *bp = netdev_priv(dev);
6846 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6847 0x0800, 0x0880, 0x0c00, 0x0c10,
6848 0x0c30, 0x0d08, 0x1000, 0x101c,
6849 0x1040, 0x1048, 0x1080, 0x10a4,
6850 0x1400, 0x1490, 0x1498, 0x14f0,
6851 0x1500, 0x155c, 0x1580, 0x15dc,
6852 0x1600, 0x1658, 0x1680, 0x16d8,
6853 0x1800, 0x1820, 0x1840, 0x1854,
6854 0x1880, 0x1894, 0x1900, 0x1984,
6855 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6856 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6857 0x2000, 0x2030, 0x23c0, 0x2400,
6858 0x2800, 0x2820, 0x2830, 0x2850,
6859 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6860 0x3c00, 0x3c94, 0x4000, 0x4010,
6861 0x4080, 0x4090, 0x43c0, 0x4458,
6862 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6863 0x4fc0, 0x5010, 0x53c0, 0x5444,
6864 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6865 0x5fc0, 0x6000, 0x6400, 0x6428,
6866 0x6800, 0x6848, 0x684c, 0x6860,
6867 0x6888, 0x6910, 0x8000 };
6868
6869 regs->version = 0;
6870
6871 memset(p, 0, BNX2_REGDUMP_LEN);
6872
6873 if (!netif_running(bp->dev))
6874 return;
6875
6876 i = 0;
6877 offset = reg_boundaries[0];
6878 p += offset;
6879 while (offset < BNX2_REGDUMP_LEN) {
6880 *p++ = REG_RD(bp, offset);
6881 offset += 4;
6882 if (offset == reg_boundaries[i + 1]) {
6883 offset = reg_boundaries[i + 2];
6884 p = (u32 *) (orig_p + offset);
6885 i += 2;
6886 }
6887 }
6888 }
6889
6890 static void
6891 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6892 {
6893 struct bnx2 *bp = netdev_priv(dev);
6894
6895 if (bp->flags & BNX2_FLAG_NO_WOL) {
6896 wol->supported = 0;
6897 wol->wolopts = 0;
6898 }
6899 else {
6900 wol->supported = WAKE_MAGIC;
6901 if (bp->wol)
6902 wol->wolopts = WAKE_MAGIC;
6903 else
6904 wol->wolopts = 0;
6905 }
6906 memset(&wol->sopass, 0, sizeof(wol->sopass));
6907 }
6908
6909 static int
6910 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6911 {
6912 struct bnx2 *bp = netdev_priv(dev);
6913
6914 if (wol->wolopts & ~WAKE_MAGIC)
6915 return -EINVAL;
6916
6917 if (wol->wolopts & WAKE_MAGIC) {
6918 if (bp->flags & BNX2_FLAG_NO_WOL)
6919 return -EINVAL;
6920
6921 bp->wol = 1;
6922 }
6923 else {
6924 bp->wol = 0;
6925 }
6926 return 0;
6927 }
6928
6929 static int
6930 bnx2_nway_reset(struct net_device *dev)
6931 {
6932 struct bnx2 *bp = netdev_priv(dev);
6933 u32 bmcr;
6934
6935 if (!netif_running(dev))
6936 return -EAGAIN;
6937
6938 if (!(bp->autoneg & AUTONEG_SPEED)) {
6939 return -EINVAL;
6940 }
6941
6942 spin_lock_bh(&bp->phy_lock);
6943
6944 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6945 int rc;
6946
6947 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6948 spin_unlock_bh(&bp->phy_lock);
6949 return rc;
6950 }
6951
6952 /* Force a link down visible on the other side */
6953 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6954 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6955 spin_unlock_bh(&bp->phy_lock);
6956
6957 msleep(20);
6958
6959 spin_lock_bh(&bp->phy_lock);
6960
6961 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6962 bp->serdes_an_pending = 1;
6963 mod_timer(&bp->timer, jiffies + bp->current_interval);
6964 }
6965
6966 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6967 bmcr &= ~BMCR_LOOPBACK;
6968 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6969
6970 spin_unlock_bh(&bp->phy_lock);
6971
6972 return 0;
6973 }
6974
6975 static u32
6976 bnx2_get_link(struct net_device *dev)
6977 {
6978 struct bnx2 *bp = netdev_priv(dev);
6979
6980 return bp->link_up;
6981 }
6982
6983 static int
6984 bnx2_get_eeprom_len(struct net_device *dev)
6985 {
6986 struct bnx2 *bp = netdev_priv(dev);
6987
6988 if (bp->flash_info == NULL)
6989 return 0;
6990
6991 return (int) bp->flash_size;
6992 }
6993
6994 static int
6995 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6996 u8 *eebuf)
6997 {
6998 struct bnx2 *bp = netdev_priv(dev);
6999 int rc;
7000
7001 if (!netif_running(dev))
7002 return -EAGAIN;
7003
7004 /* parameters already validated in ethtool_get_eeprom */
7005
7006 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7007
7008 return rc;
7009 }
7010
7011 static int
7012 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7013 u8 *eebuf)
7014 {
7015 struct bnx2 *bp = netdev_priv(dev);
7016 int rc;
7017
7018 if (!netif_running(dev))
7019 return -EAGAIN;
7020
7021 /* parameters already validated in ethtool_set_eeprom */
7022
7023 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7024
7025 return rc;
7026 }
7027
7028 static int
7029 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7030 {
7031 struct bnx2 *bp = netdev_priv(dev);
7032
7033 memset(coal, 0, sizeof(struct ethtool_coalesce));
7034
7035 coal->rx_coalesce_usecs = bp->rx_ticks;
7036 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7037 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7038 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7039
7040 coal->tx_coalesce_usecs = bp->tx_ticks;
7041 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7042 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7043 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7044
7045 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7046
7047 return 0;
7048 }
7049
7050 static int
7051 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7052 {
7053 struct bnx2 *bp = netdev_priv(dev);
7054
7055 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7056 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7057
7058 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7059 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7060
7061 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7062 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7063
7064 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7065 if (bp->rx_quick_cons_trip_int > 0xff)
7066 bp->rx_quick_cons_trip_int = 0xff;
7067
7068 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7069 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7070
7071 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7072 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7073
7074 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7075 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7076
7077 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7078 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7079 0xff;
7080
7081 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7082 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7083 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7084 bp->stats_ticks = USEC_PER_SEC;
7085 }
7086 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7087 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7088 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7089
7090 if (netif_running(bp->dev)) {
7091 bnx2_netif_stop(bp, true);
7092 bnx2_init_nic(bp, 0);
7093 bnx2_netif_start(bp, true);
7094 }
7095
7096 return 0;
7097 }
7098
7099 static void
7100 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7101 {
7102 struct bnx2 *bp = netdev_priv(dev);
7103
7104 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7105 ering->rx_mini_max_pending = 0;
7106 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7107
7108 ering->rx_pending = bp->rx_ring_size;
7109 ering->rx_mini_pending = 0;
7110 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7111
7112 ering->tx_max_pending = MAX_TX_DESC_CNT;
7113 ering->tx_pending = bp->tx_ring_size;
7114 }
7115
7116 static int
7117 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7118 {
7119 if (netif_running(bp->dev)) {
7120 /* Reset will erase chipset stats; save them */
7121 bnx2_save_stats(bp);
7122
7123 bnx2_netif_stop(bp, true);
7124 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7125 bnx2_free_skbs(bp);
7126 bnx2_free_mem(bp);
7127 }
7128
7129 bnx2_set_rx_ring_size(bp, rx);
7130 bp->tx_ring_size = tx;
7131
7132 if (netif_running(bp->dev)) {
7133 int rc;
7134
7135 rc = bnx2_alloc_mem(bp);
7136 if (!rc)
7137 rc = bnx2_init_nic(bp, 0);
7138
7139 if (rc) {
7140 bnx2_napi_enable(bp);
7141 dev_close(bp->dev);
7142 return rc;
7143 }
7144 #ifdef BCM_CNIC
7145 mutex_lock(&bp->cnic_lock);
7146 /* Let cnic know about the new status block. */
7147 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7148 bnx2_setup_cnic_irq_info(bp);
7149 mutex_unlock(&bp->cnic_lock);
7150 #endif
7151 bnx2_netif_start(bp, true);
7152 }
7153 return 0;
7154 }
7155
7156 static int
7157 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7158 {
7159 struct bnx2 *bp = netdev_priv(dev);
7160 int rc;
7161
7162 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7163 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7164 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7165
7166 return -EINVAL;
7167 }
7168 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7169 return rc;
7170 }
7171
7172 static void
7173 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7174 {
7175 struct bnx2 *bp = netdev_priv(dev);
7176
7177 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7178 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7179 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7180 }
7181
7182 static int
7183 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7184 {
7185 struct bnx2 *bp = netdev_priv(dev);
7186
7187 bp->req_flow_ctrl = 0;
7188 if (epause->rx_pause)
7189 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7190 if (epause->tx_pause)
7191 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7192
7193 if (epause->autoneg) {
7194 bp->autoneg |= AUTONEG_FLOW_CTRL;
7195 }
7196 else {
7197 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7198 }
7199
7200 if (netif_running(dev)) {
7201 spin_lock_bh(&bp->phy_lock);
7202 bnx2_setup_phy(bp, bp->phy_port);
7203 spin_unlock_bh(&bp->phy_lock);
7204 }
7205
7206 return 0;
7207 }
7208
7209 static u32
7210 bnx2_get_rx_csum(struct net_device *dev)
7211 {
7212 struct bnx2 *bp = netdev_priv(dev);
7213
7214 return bp->rx_csum;
7215 }
7216
7217 static int
7218 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7219 {
7220 struct bnx2 *bp = netdev_priv(dev);
7221
7222 bp->rx_csum = data;
7223 return 0;
7224 }
7225
7226 static int
7227 bnx2_set_tso(struct net_device *dev, u32 data)
7228 {
7229 struct bnx2 *bp = netdev_priv(dev);
7230
7231 if (data) {
7232 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7233 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7234 dev->features |= NETIF_F_TSO6;
7235 } else
7236 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7237 NETIF_F_TSO_ECN);
7238 return 0;
7239 }
7240
7241 static struct {
7242 char string[ETH_GSTRING_LEN];
7243 } bnx2_stats_str_arr[] = {
7244 { "rx_bytes" },
7245 { "rx_error_bytes" },
7246 { "tx_bytes" },
7247 { "tx_error_bytes" },
7248 { "rx_ucast_packets" },
7249 { "rx_mcast_packets" },
7250 { "rx_bcast_packets" },
7251 { "tx_ucast_packets" },
7252 { "tx_mcast_packets" },
7253 { "tx_bcast_packets" },
7254 { "tx_mac_errors" },
7255 { "tx_carrier_errors" },
7256 { "rx_crc_errors" },
7257 { "rx_align_errors" },
7258 { "tx_single_collisions" },
7259 { "tx_multi_collisions" },
7260 { "tx_deferred" },
7261 { "tx_excess_collisions" },
7262 { "tx_late_collisions" },
7263 { "tx_total_collisions" },
7264 { "rx_fragments" },
7265 { "rx_jabbers" },
7266 { "rx_undersize_packets" },
7267 { "rx_oversize_packets" },
7268 { "rx_64_byte_packets" },
7269 { "rx_65_to_127_byte_packets" },
7270 { "rx_128_to_255_byte_packets" },
7271 { "rx_256_to_511_byte_packets" },
7272 { "rx_512_to_1023_byte_packets" },
7273 { "rx_1024_to_1522_byte_packets" },
7274 { "rx_1523_to_9022_byte_packets" },
7275 { "tx_64_byte_packets" },
7276 { "tx_65_to_127_byte_packets" },
7277 { "tx_128_to_255_byte_packets" },
7278 { "tx_256_to_511_byte_packets" },
7279 { "tx_512_to_1023_byte_packets" },
7280 { "tx_1024_to_1522_byte_packets" },
7281 { "tx_1523_to_9022_byte_packets" },
7282 { "rx_xon_frames" },
7283 { "rx_xoff_frames" },
7284 { "tx_xon_frames" },
7285 { "tx_xoff_frames" },
7286 { "rx_mac_ctrl_frames" },
7287 { "rx_filtered_packets" },
7288 { "rx_ftq_discards" },
7289 { "rx_discards" },
7290 { "rx_fw_discards" },
7291 };
7292
7293 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7294 sizeof(bnx2_stats_str_arr[0]))
7295
7296 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7297
7298 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7299 STATS_OFFSET32(stat_IfHCInOctets_hi),
7300 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7301 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7302 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7303 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7304 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7305 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7306 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7307 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7308 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7309 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7310 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7311 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7312 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7313 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7314 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7315 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7316 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7317 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7318 STATS_OFFSET32(stat_EtherStatsCollisions),
7319 STATS_OFFSET32(stat_EtherStatsFragments),
7320 STATS_OFFSET32(stat_EtherStatsJabbers),
7321 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7322 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7323 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7324 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7325 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7326 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7327 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7328 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7329 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7330 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7331 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7332 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7333 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7334 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7335 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7336 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7337 STATS_OFFSET32(stat_XonPauseFramesReceived),
7338 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7339 STATS_OFFSET32(stat_OutXonSent),
7340 STATS_OFFSET32(stat_OutXoffSent),
7341 STATS_OFFSET32(stat_MacControlFramesReceived),
7342 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7343 STATS_OFFSET32(stat_IfInFTQDiscards),
7344 STATS_OFFSET32(stat_IfInMBUFDiscards),
7345 STATS_OFFSET32(stat_FwRxDrop),
7346 };
7347
7348 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7349 * skipped because of errata.
7350 */
7351 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7352 8,0,8,8,8,8,8,8,8,8,
7353 4,0,4,4,4,4,4,4,4,4,
7354 4,4,4,4,4,4,4,4,4,4,
7355 4,4,4,4,4,4,4,4,4,4,
7356 4,4,4,4,4,4,4,
7357 };
7358
7359 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7360 8,0,8,8,8,8,8,8,8,8,
7361 4,4,4,4,4,4,4,4,4,4,
7362 4,4,4,4,4,4,4,4,4,4,
7363 4,4,4,4,4,4,4,4,4,4,
7364 4,4,4,4,4,4,4,
7365 };
7366
7367 #define BNX2_NUM_TESTS 6
7368
7369 static struct {
7370 char string[ETH_GSTRING_LEN];
7371 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7372 { "register_test (offline)" },
7373 { "memory_test (offline)" },
7374 { "loopback_test (offline)" },
7375 { "nvram_test (online)" },
7376 { "interrupt_test (online)" },
7377 { "link_test (online)" },
7378 };
7379
7380 static int
7381 bnx2_get_sset_count(struct net_device *dev, int sset)
7382 {
7383 switch (sset) {
7384 case ETH_SS_TEST:
7385 return BNX2_NUM_TESTS;
7386 case ETH_SS_STATS:
7387 return BNX2_NUM_STATS;
7388 default:
7389 return -EOPNOTSUPP;
7390 }
7391 }
7392
7393 static void
7394 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7395 {
7396 struct bnx2 *bp = netdev_priv(dev);
7397
7398 bnx2_set_power_state(bp, PCI_D0);
7399
7400 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7401 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7402 int i;
7403
7404 bnx2_netif_stop(bp, true);
7405 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7406 bnx2_free_skbs(bp);
7407
7408 if (bnx2_test_registers(bp) != 0) {
7409 buf[0] = 1;
7410 etest->flags |= ETH_TEST_FL_FAILED;
7411 }
7412 if (bnx2_test_memory(bp) != 0) {
7413 buf[1] = 1;
7414 etest->flags |= ETH_TEST_FL_FAILED;
7415 }
7416 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7417 etest->flags |= ETH_TEST_FL_FAILED;
7418
7419 if (!netif_running(bp->dev))
7420 bnx2_shutdown_chip(bp);
7421 else {
7422 bnx2_init_nic(bp, 1);
7423 bnx2_netif_start(bp, true);
7424 }
7425
7426 /* wait for link up */
7427 for (i = 0; i < 7; i++) {
7428 if (bp->link_up)
7429 break;
7430 msleep_interruptible(1000);
7431 }
7432 }
7433
7434 if (bnx2_test_nvram(bp) != 0) {
7435 buf[3] = 1;
7436 etest->flags |= ETH_TEST_FL_FAILED;
7437 }
7438 if (bnx2_test_intr(bp) != 0) {
7439 buf[4] = 1;
7440 etest->flags |= ETH_TEST_FL_FAILED;
7441 }
7442
7443 if (bnx2_test_link(bp) != 0) {
7444 buf[5] = 1;
7445 etest->flags |= ETH_TEST_FL_FAILED;
7446
7447 }
7448 if (!netif_running(bp->dev))
7449 bnx2_set_power_state(bp, PCI_D3hot);
7450 }
7451
7452 static void
7453 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7454 {
7455 switch (stringset) {
7456 case ETH_SS_STATS:
7457 memcpy(buf, bnx2_stats_str_arr,
7458 sizeof(bnx2_stats_str_arr));
7459 break;
7460 case ETH_SS_TEST:
7461 memcpy(buf, bnx2_tests_str_arr,
7462 sizeof(bnx2_tests_str_arr));
7463 break;
7464 }
7465 }
7466
7467 static void
7468 bnx2_get_ethtool_stats(struct net_device *dev,
7469 struct ethtool_stats *stats, u64 *buf)
7470 {
7471 struct bnx2 *bp = netdev_priv(dev);
7472 int i;
7473 u32 *hw_stats = (u32 *) bp->stats_blk;
7474 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7475 u8 *stats_len_arr = NULL;
7476
7477 if (hw_stats == NULL) {
7478 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7479 return;
7480 }
7481
7482 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7483 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7484 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7485 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7486 stats_len_arr = bnx2_5706_stats_len_arr;
7487 else
7488 stats_len_arr = bnx2_5708_stats_len_arr;
7489
7490 for (i = 0; i < BNX2_NUM_STATS; i++) {
7491 unsigned long offset;
7492
7493 if (stats_len_arr[i] == 0) {
7494 /* skip this counter */
7495 buf[i] = 0;
7496 continue;
7497 }
7498
7499 offset = bnx2_stats_offset_arr[i];
7500 if (stats_len_arr[i] == 4) {
7501 /* 4-byte counter */
7502 buf[i] = (u64) *(hw_stats + offset) +
7503 *(temp_stats + offset);
7504 continue;
7505 }
7506 /* 8-byte counter */
7507 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7508 *(hw_stats + offset + 1) +
7509 (((u64) *(temp_stats + offset)) << 32) +
7510 *(temp_stats + offset + 1);
7511 }
7512 }
7513
7514 static int
7515 bnx2_phys_id(struct net_device *dev, u32 data)
7516 {
7517 struct bnx2 *bp = netdev_priv(dev);
7518 int i;
7519 u32 save;
7520
7521 bnx2_set_power_state(bp, PCI_D0);
7522
7523 if (data == 0)
7524 data = 2;
7525
7526 save = REG_RD(bp, BNX2_MISC_CFG);
7527 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7528
7529 for (i = 0; i < (data * 2); i++) {
7530 if ((i % 2) == 0) {
7531 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7532 }
7533 else {
7534 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7535 BNX2_EMAC_LED_1000MB_OVERRIDE |
7536 BNX2_EMAC_LED_100MB_OVERRIDE |
7537 BNX2_EMAC_LED_10MB_OVERRIDE |
7538 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7539 BNX2_EMAC_LED_TRAFFIC);
7540 }
7541 msleep_interruptible(500);
7542 if (signal_pending(current))
7543 break;
7544 }
7545 REG_WR(bp, BNX2_EMAC_LED, 0);
7546 REG_WR(bp, BNX2_MISC_CFG, save);
7547
7548 if (!netif_running(dev))
7549 bnx2_set_power_state(bp, PCI_D3hot);
7550
7551 return 0;
7552 }
7553
7554 static int
7555 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7556 {
7557 struct bnx2 *bp = netdev_priv(dev);
7558
7559 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7560 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7561 else
7562 return (ethtool_op_set_tx_csum(dev, data));
7563 }
7564
7565 static int
7566 bnx2_set_flags(struct net_device *dev, u32 data)
7567 {
7568 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
7569 }
7570
7571 static const struct ethtool_ops bnx2_ethtool_ops = {
7572 .get_settings = bnx2_get_settings,
7573 .set_settings = bnx2_set_settings,
7574 .get_drvinfo = bnx2_get_drvinfo,
7575 .get_regs_len = bnx2_get_regs_len,
7576 .get_regs = bnx2_get_regs,
7577 .get_wol = bnx2_get_wol,
7578 .set_wol = bnx2_set_wol,
7579 .nway_reset = bnx2_nway_reset,
7580 .get_link = bnx2_get_link,
7581 .get_eeprom_len = bnx2_get_eeprom_len,
7582 .get_eeprom = bnx2_get_eeprom,
7583 .set_eeprom = bnx2_set_eeprom,
7584 .get_coalesce = bnx2_get_coalesce,
7585 .set_coalesce = bnx2_set_coalesce,
7586 .get_ringparam = bnx2_get_ringparam,
7587 .set_ringparam = bnx2_set_ringparam,
7588 .get_pauseparam = bnx2_get_pauseparam,
7589 .set_pauseparam = bnx2_set_pauseparam,
7590 .get_rx_csum = bnx2_get_rx_csum,
7591 .set_rx_csum = bnx2_set_rx_csum,
7592 .set_tx_csum = bnx2_set_tx_csum,
7593 .set_sg = ethtool_op_set_sg,
7594 .set_tso = bnx2_set_tso,
7595 .self_test = bnx2_self_test,
7596 .get_strings = bnx2_get_strings,
7597 .phys_id = bnx2_phys_id,
7598 .get_ethtool_stats = bnx2_get_ethtool_stats,
7599 .get_sset_count = bnx2_get_sset_count,
7600 .set_flags = bnx2_set_flags,
7601 .get_flags = ethtool_op_get_flags,
7602 };
7603
7604 /* Called with rtnl_lock */
7605 static int
7606 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7607 {
7608 struct mii_ioctl_data *data = if_mii(ifr);
7609 struct bnx2 *bp = netdev_priv(dev);
7610 int err;
7611
7612 switch(cmd) {
7613 case SIOCGMIIPHY:
7614 data->phy_id = bp->phy_addr;
7615
7616 /* fallthru */
7617 case SIOCGMIIREG: {
7618 u32 mii_regval;
7619
7620 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7621 return -EOPNOTSUPP;
7622
7623 if (!netif_running(dev))
7624 return -EAGAIN;
7625
7626 spin_lock_bh(&bp->phy_lock);
7627 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7628 spin_unlock_bh(&bp->phy_lock);
7629
7630 data->val_out = mii_regval;
7631
7632 return err;
7633 }
7634
7635 case SIOCSMIIREG:
7636 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7637 return -EOPNOTSUPP;
7638
7639 if (!netif_running(dev))
7640 return -EAGAIN;
7641
7642 spin_lock_bh(&bp->phy_lock);
7643 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7644 spin_unlock_bh(&bp->phy_lock);
7645
7646 return err;
7647
7648 default:
7649 /* do nothing */
7650 break;
7651 }
7652 return -EOPNOTSUPP;
7653 }
7654
7655 /* Called with rtnl_lock */
7656 static int
7657 bnx2_change_mac_addr(struct net_device *dev, void *p)
7658 {
7659 struct sockaddr *addr = p;
7660 struct bnx2 *bp = netdev_priv(dev);
7661
7662 if (!is_valid_ether_addr(addr->sa_data))
7663 return -EINVAL;
7664
7665 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7666 if (netif_running(dev))
7667 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7668
7669 return 0;
7670 }
7671
7672 /* Called with rtnl_lock */
7673 static int
7674 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7675 {
7676 struct bnx2 *bp = netdev_priv(dev);
7677
7678 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7679 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7680 return -EINVAL;
7681
7682 dev->mtu = new_mtu;
7683 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7684 }
7685
7686 #ifdef CONFIG_NET_POLL_CONTROLLER
7687 static void
7688 poll_bnx2(struct net_device *dev)
7689 {
7690 struct bnx2 *bp = netdev_priv(dev);
7691 int i;
7692
7693 for (i = 0; i < bp->irq_nvecs; i++) {
7694 struct bnx2_irq *irq = &bp->irq_tbl[i];
7695
7696 disable_irq(irq->vector);
7697 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7698 enable_irq(irq->vector);
7699 }
7700 }
7701 #endif
7702
7703 static void __devinit
7704 bnx2_get_5709_media(struct bnx2 *bp)
7705 {
7706 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7707 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7708 u32 strap;
7709
7710 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7711 return;
7712 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7713 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7714 return;
7715 }
7716
7717 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7718 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7719 else
7720 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7721
7722 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7723 switch (strap) {
7724 case 0x4:
7725 case 0x5:
7726 case 0x6:
7727 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7728 return;
7729 }
7730 } else {
7731 switch (strap) {
7732 case 0x1:
7733 case 0x2:
7734 case 0x4:
7735 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7736 return;
7737 }
7738 }
7739 }
7740
7741 static void __devinit
7742 bnx2_get_pci_speed(struct bnx2 *bp)
7743 {
7744 u32 reg;
7745
7746 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7747 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7748 u32 clkreg;
7749
7750 bp->flags |= BNX2_FLAG_PCIX;
7751
7752 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7753
7754 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7755 switch (clkreg) {
7756 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7757 bp->bus_speed_mhz = 133;
7758 break;
7759
7760 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7761 bp->bus_speed_mhz = 100;
7762 break;
7763
7764 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7765 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7766 bp->bus_speed_mhz = 66;
7767 break;
7768
7769 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7770 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7771 bp->bus_speed_mhz = 50;
7772 break;
7773
7774 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7775 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7776 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7777 bp->bus_speed_mhz = 33;
7778 break;
7779 }
7780 }
7781 else {
7782 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7783 bp->bus_speed_mhz = 66;
7784 else
7785 bp->bus_speed_mhz = 33;
7786 }
7787
7788 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7789 bp->flags |= BNX2_FLAG_PCI_32BIT;
7790
7791 }
7792
7793 static void __devinit
7794 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7795 {
7796 int rc, i, j;
7797 u8 *data;
7798 unsigned int block_end, rosize, len;
7799
7800 #define BNX2_VPD_NVRAM_OFFSET 0x300
7801 #define BNX2_VPD_LEN 128
7802 #define BNX2_MAX_VER_SLEN 30
7803
7804 data = kmalloc(256, GFP_KERNEL);
7805 if (!data)
7806 return;
7807
7808 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7809 BNX2_VPD_LEN);
7810 if (rc)
7811 goto vpd_done;
7812
7813 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7814 data[i] = data[i + BNX2_VPD_LEN + 3];
7815 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7816 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7817 data[i + 3] = data[i + BNX2_VPD_LEN];
7818 }
7819
7820 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7821 if (i < 0)
7822 goto vpd_done;
7823
7824 rosize = pci_vpd_lrdt_size(&data[i]);
7825 i += PCI_VPD_LRDT_TAG_SIZE;
7826 block_end = i + rosize;
7827
7828 if (block_end > BNX2_VPD_LEN)
7829 goto vpd_done;
7830
7831 j = pci_vpd_find_info_keyword(data, i, rosize,
7832 PCI_VPD_RO_KEYWORD_MFR_ID);
7833 if (j < 0)
7834 goto vpd_done;
7835
7836 len = pci_vpd_info_field_size(&data[j]);
7837
7838 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7839 if (j + len > block_end || len != 4 ||
7840 memcmp(&data[j], "1028", 4))
7841 goto vpd_done;
7842
7843 j = pci_vpd_find_info_keyword(data, i, rosize,
7844 PCI_VPD_RO_KEYWORD_VENDOR0);
7845 if (j < 0)
7846 goto vpd_done;
7847
7848 len = pci_vpd_info_field_size(&data[j]);
7849
7850 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7851 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7852 goto vpd_done;
7853
7854 memcpy(bp->fw_version, &data[j], len);
7855 bp->fw_version[len] = ' ';
7856
7857 vpd_done:
7858 kfree(data);
7859 }
7860
7861 static int __devinit
7862 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7863 {
7864 struct bnx2 *bp;
7865 unsigned long mem_len;
7866 int rc, i, j;
7867 u32 reg;
7868 u64 dma_mask, persist_dma_mask;
7869
7870 SET_NETDEV_DEV(dev, &pdev->dev);
7871 bp = netdev_priv(dev);
7872
7873 bp->flags = 0;
7874 bp->phy_flags = 0;
7875
7876 bp->temp_stats_blk =
7877 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7878
7879 if (bp->temp_stats_blk == NULL) {
7880 rc = -ENOMEM;
7881 goto err_out;
7882 }
7883
7884 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7885 rc = pci_enable_device(pdev);
7886 if (rc) {
7887 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7888 goto err_out;
7889 }
7890
7891 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7892 dev_err(&pdev->dev,
7893 "Cannot find PCI device base address, aborting\n");
7894 rc = -ENODEV;
7895 goto err_out_disable;
7896 }
7897
7898 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7899 if (rc) {
7900 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7901 goto err_out_disable;
7902 }
7903
7904 pci_set_master(pdev);
7905 pci_save_state(pdev);
7906
7907 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7908 if (bp->pm_cap == 0) {
7909 dev_err(&pdev->dev,
7910 "Cannot find power management capability, aborting\n");
7911 rc = -EIO;
7912 goto err_out_release;
7913 }
7914
7915 bp->dev = dev;
7916 bp->pdev = pdev;
7917
7918 spin_lock_init(&bp->phy_lock);
7919 spin_lock_init(&bp->indirect_lock);
7920 #ifdef BCM_CNIC
7921 mutex_init(&bp->cnic_lock);
7922 #endif
7923 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7924
7925 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7926 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7927 dev->mem_end = dev->mem_start + mem_len;
7928 dev->irq = pdev->irq;
7929
7930 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7931
7932 if (!bp->regview) {
7933 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7934 rc = -ENOMEM;
7935 goto err_out_release;
7936 }
7937
7938 /* Configure byte swap and enable write to the reg_window registers.
7939 * Rely on CPU to do target byte swapping on big endian systems
7940 * The chip's target access swapping will not swap all accesses
7941 */
7942 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7943 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7944 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7945
7946 bnx2_set_power_state(bp, PCI_D0);
7947
7948 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7949
7950 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7951 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7952 dev_err(&pdev->dev,
7953 "Cannot find PCIE capability, aborting\n");
7954 rc = -EIO;
7955 goto err_out_unmap;
7956 }
7957 bp->flags |= BNX2_FLAG_PCIE;
7958 if (CHIP_REV(bp) == CHIP_REV_Ax)
7959 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7960 } else {
7961 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7962 if (bp->pcix_cap == 0) {
7963 dev_err(&pdev->dev,
7964 "Cannot find PCIX capability, aborting\n");
7965 rc = -EIO;
7966 goto err_out_unmap;
7967 }
7968 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7969 }
7970
7971 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7972 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7973 bp->flags |= BNX2_FLAG_MSIX_CAP;
7974 }
7975
7976 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7977 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7978 bp->flags |= BNX2_FLAG_MSI_CAP;
7979 }
7980
7981 /* 5708 cannot support DMA addresses > 40-bit. */
7982 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7983 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7984 else
7985 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7986
7987 /* Configure DMA attributes. */
7988 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7989 dev->features |= NETIF_F_HIGHDMA;
7990 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7991 if (rc) {
7992 dev_err(&pdev->dev,
7993 "pci_set_consistent_dma_mask failed, aborting\n");
7994 goto err_out_unmap;
7995 }
7996 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7997 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7998 goto err_out_unmap;
7999 }
8000
8001 if (!(bp->flags & BNX2_FLAG_PCIE))
8002 bnx2_get_pci_speed(bp);
8003
8004 /* 5706A0 may falsely detect SERR and PERR. */
8005 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8006 reg = REG_RD(bp, PCI_COMMAND);
8007 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8008 REG_WR(bp, PCI_COMMAND, reg);
8009 }
8010 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
8011 !(bp->flags & BNX2_FLAG_PCIX)) {
8012
8013 dev_err(&pdev->dev,
8014 "5706 A1 can only be used in a PCIX bus, aborting\n");
8015 goto err_out_unmap;
8016 }
8017
8018 bnx2_init_nvram(bp);
8019
8020 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
8021
8022 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
8023 BNX2_SHM_HDR_SIGNATURE_SIG) {
8024 u32 off = PCI_FUNC(pdev->devfn) << 2;
8025
8026 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8027 } else
8028 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8029
8030 /* Get the permanent MAC address. First we need to make sure the
8031 * firmware is actually running.
8032 */
8033 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8034
8035 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8036 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8037 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8038 rc = -ENODEV;
8039 goto err_out_unmap;
8040 }
8041
8042 bnx2_read_vpd_fw_ver(bp);
8043
8044 j = strlen(bp->fw_version);
8045 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8046 for (i = 0; i < 3 && j < 24; i++) {
8047 u8 num, k, skip0;
8048
8049 if (i == 0) {
8050 bp->fw_version[j++] = 'b';
8051 bp->fw_version[j++] = 'c';
8052 bp->fw_version[j++] = ' ';
8053 }
8054 num = (u8) (reg >> (24 - (i * 8)));
8055 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8056 if (num >= k || !skip0 || k == 1) {
8057 bp->fw_version[j++] = (num / k) + '0';
8058 skip0 = 0;
8059 }
8060 }
8061 if (i != 2)
8062 bp->fw_version[j++] = '.';
8063 }
8064 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8065 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8066 bp->wol = 1;
8067
8068 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8069 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8070
8071 for (i = 0; i < 30; i++) {
8072 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8073 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8074 break;
8075 msleep(10);
8076 }
8077 }
8078 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8079 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8080 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8081 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8082 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8083
8084 if (j < 32)
8085 bp->fw_version[j++] = ' ';
8086 for (i = 0; i < 3 && j < 28; i++) {
8087 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8088 reg = swab32(reg);
8089 memcpy(&bp->fw_version[j], &reg, 4);
8090 j += 4;
8091 }
8092 }
8093
8094 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8095 bp->mac_addr[0] = (u8) (reg >> 8);
8096 bp->mac_addr[1] = (u8) reg;
8097
8098 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8099 bp->mac_addr[2] = (u8) (reg >> 24);
8100 bp->mac_addr[3] = (u8) (reg >> 16);
8101 bp->mac_addr[4] = (u8) (reg >> 8);
8102 bp->mac_addr[5] = (u8) reg;
8103
8104 bp->tx_ring_size = MAX_TX_DESC_CNT;
8105 bnx2_set_rx_ring_size(bp, 255);
8106
8107 bp->rx_csum = 1;
8108
8109 bp->tx_quick_cons_trip_int = 2;
8110 bp->tx_quick_cons_trip = 20;
8111 bp->tx_ticks_int = 18;
8112 bp->tx_ticks = 80;
8113
8114 bp->rx_quick_cons_trip_int = 2;
8115 bp->rx_quick_cons_trip = 12;
8116 bp->rx_ticks_int = 18;
8117 bp->rx_ticks = 18;
8118
8119 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8120
8121 bp->current_interval = BNX2_TIMER_INTERVAL;
8122
8123 bp->phy_addr = 1;
8124
8125 /* Disable WOL support if we are running on a SERDES chip. */
8126 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8127 bnx2_get_5709_media(bp);
8128 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8129 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8130
8131 bp->phy_port = PORT_TP;
8132 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8133 bp->phy_port = PORT_FIBRE;
8134 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8135 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8136 bp->flags |= BNX2_FLAG_NO_WOL;
8137 bp->wol = 0;
8138 }
8139 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8140 /* Don't do parallel detect on this board because of
8141 * some board problems. The link will not go down
8142 * if we do parallel detect.
8143 */
8144 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8145 pdev->subsystem_device == 0x310c)
8146 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8147 } else {
8148 bp->phy_addr = 2;
8149 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8150 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8151 }
8152 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8153 CHIP_NUM(bp) == CHIP_NUM_5708)
8154 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8155 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8156 (CHIP_REV(bp) == CHIP_REV_Ax ||
8157 CHIP_REV(bp) == CHIP_REV_Bx))
8158 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8159
8160 bnx2_init_fw_cap(bp);
8161
8162 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8163 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8164 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8165 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8166 bp->flags |= BNX2_FLAG_NO_WOL;
8167 bp->wol = 0;
8168 }
8169
8170 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8171 bp->tx_quick_cons_trip_int =
8172 bp->tx_quick_cons_trip;
8173 bp->tx_ticks_int = bp->tx_ticks;
8174 bp->rx_quick_cons_trip_int =
8175 bp->rx_quick_cons_trip;
8176 bp->rx_ticks_int = bp->rx_ticks;
8177 bp->comp_prod_trip_int = bp->comp_prod_trip;
8178 bp->com_ticks_int = bp->com_ticks;
8179 bp->cmd_ticks_int = bp->cmd_ticks;
8180 }
8181
8182 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8183 *
8184 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8185 * with byte enables disabled on the unused 32-bit word. This is legal
8186 * but causes problems on the AMD 8132 which will eventually stop
8187 * responding after a while.
8188 *
8189 * AMD believes this incompatibility is unique to the 5706, and
8190 * prefers to locally disable MSI rather than globally disabling it.
8191 */
8192 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8193 struct pci_dev *amd_8132 = NULL;
8194
8195 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8196 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8197 amd_8132))) {
8198
8199 if (amd_8132->revision >= 0x10 &&
8200 amd_8132->revision <= 0x13) {
8201 disable_msi = 1;
8202 pci_dev_put(amd_8132);
8203 break;
8204 }
8205 }
8206 }
8207
8208 bnx2_set_default_link(bp);
8209 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8210
8211 init_timer(&bp->timer);
8212 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8213 bp->timer.data = (unsigned long) bp;
8214 bp->timer.function = bnx2_timer;
8215
8216 return 0;
8217
8218 err_out_unmap:
8219 if (bp->regview) {
8220 iounmap(bp->regview);
8221 bp->regview = NULL;
8222 }
8223
8224 err_out_release:
8225 pci_release_regions(pdev);
8226
8227 err_out_disable:
8228 pci_disable_device(pdev);
8229 pci_set_drvdata(pdev, NULL);
8230
8231 err_out:
8232 return rc;
8233 }
8234
8235 static char * __devinit
8236 bnx2_bus_string(struct bnx2 *bp, char *str)
8237 {
8238 char *s = str;
8239
8240 if (bp->flags & BNX2_FLAG_PCIE) {
8241 s += sprintf(s, "PCI Express");
8242 } else {
8243 s += sprintf(s, "PCI");
8244 if (bp->flags & BNX2_FLAG_PCIX)
8245 s += sprintf(s, "-X");
8246 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8247 s += sprintf(s, " 32-bit");
8248 else
8249 s += sprintf(s, " 64-bit");
8250 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8251 }
8252 return str;
8253 }
8254
8255 static void
8256 bnx2_del_napi(struct bnx2 *bp)
8257 {
8258 int i;
8259
8260 for (i = 0; i < bp->irq_nvecs; i++)
8261 netif_napi_del(&bp->bnx2_napi[i].napi);
8262 }
8263
8264 static void
8265 bnx2_init_napi(struct bnx2 *bp)
8266 {
8267 int i;
8268
8269 for (i = 0; i < bp->irq_nvecs; i++) {
8270 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8271 int (*poll)(struct napi_struct *, int);
8272
8273 if (i == 0)
8274 poll = bnx2_poll;
8275 else
8276 poll = bnx2_poll_msix;
8277
8278 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8279 bnapi->bp = bp;
8280 }
8281 }
8282
8283 static const struct net_device_ops bnx2_netdev_ops = {
8284 .ndo_open = bnx2_open,
8285 .ndo_start_xmit = bnx2_start_xmit,
8286 .ndo_stop = bnx2_close,
8287 .ndo_get_stats64 = bnx2_get_stats64,
8288 .ndo_set_rx_mode = bnx2_set_rx_mode,
8289 .ndo_do_ioctl = bnx2_ioctl,
8290 .ndo_validate_addr = eth_validate_addr,
8291 .ndo_set_mac_address = bnx2_change_mac_addr,
8292 .ndo_change_mtu = bnx2_change_mtu,
8293 .ndo_tx_timeout = bnx2_tx_timeout,
8294 #ifdef BCM_VLAN
8295 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8296 #endif
8297 #ifdef CONFIG_NET_POLL_CONTROLLER
8298 .ndo_poll_controller = poll_bnx2,
8299 #endif
8300 };
8301
8302 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8303 {
8304 #ifdef BCM_VLAN
8305 dev->vlan_features |= flags;
8306 #endif
8307 }
8308
8309 static int __devinit
8310 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8311 {
8312 static int version_printed = 0;
8313 struct net_device *dev = NULL;
8314 struct bnx2 *bp;
8315 int rc;
8316 char str[40];
8317
8318 if (version_printed++ == 0)
8319 pr_info("%s", version);
8320
8321 /* dev zeroed in init_etherdev */
8322 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8323
8324 if (!dev)
8325 return -ENOMEM;
8326
8327 rc = bnx2_init_board(pdev, dev);
8328 if (rc < 0) {
8329 free_netdev(dev);
8330 return rc;
8331 }
8332
8333 dev->netdev_ops = &bnx2_netdev_ops;
8334 dev->watchdog_timeo = TX_TIMEOUT;
8335 dev->ethtool_ops = &bnx2_ethtool_ops;
8336
8337 bp = netdev_priv(dev);
8338
8339 pci_set_drvdata(pdev, dev);
8340
8341 rc = bnx2_request_firmware(bp);
8342 if (rc)
8343 goto error;
8344
8345 memcpy(dev->dev_addr, bp->mac_addr, 6);
8346 memcpy(dev->perm_addr, bp->mac_addr, 6);
8347
8348 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO |
8349 NETIF_F_RXHASH;
8350 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8351 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8352 dev->features |= NETIF_F_IPV6_CSUM;
8353 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8354 }
8355 #ifdef BCM_VLAN
8356 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8357 #endif
8358 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8359 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8360 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8361 dev->features |= NETIF_F_TSO6;
8362 vlan_features_add(dev, NETIF_F_TSO6);
8363 }
8364 if ((rc = register_netdev(dev))) {
8365 dev_err(&pdev->dev, "Cannot register net device\n");
8366 goto error;
8367 }
8368
8369 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8370 board_info[ent->driver_data].name,
8371 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8372 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8373 bnx2_bus_string(bp, str),
8374 dev->base_addr,
8375 bp->pdev->irq, dev->dev_addr);
8376
8377 return 0;
8378
8379 error:
8380 if (bp->mips_firmware)
8381 release_firmware(bp->mips_firmware);
8382 if (bp->rv2p_firmware)
8383 release_firmware(bp->rv2p_firmware);
8384
8385 if (bp->regview)
8386 iounmap(bp->regview);
8387 pci_release_regions(pdev);
8388 pci_disable_device(pdev);
8389 pci_set_drvdata(pdev, NULL);
8390 free_netdev(dev);
8391 return rc;
8392 }
8393
8394 static void __devexit
8395 bnx2_remove_one(struct pci_dev *pdev)
8396 {
8397 struct net_device *dev = pci_get_drvdata(pdev);
8398 struct bnx2 *bp = netdev_priv(dev);
8399
8400 flush_scheduled_work();
8401
8402 unregister_netdev(dev);
8403
8404 if (bp->mips_firmware)
8405 release_firmware(bp->mips_firmware);
8406 if (bp->rv2p_firmware)
8407 release_firmware(bp->rv2p_firmware);
8408
8409 if (bp->regview)
8410 iounmap(bp->regview);
8411
8412 kfree(bp->temp_stats_blk);
8413
8414 free_netdev(dev);
8415 pci_release_regions(pdev);
8416 pci_disable_device(pdev);
8417 pci_set_drvdata(pdev, NULL);
8418 }
8419
8420 static int
8421 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8422 {
8423 struct net_device *dev = pci_get_drvdata(pdev);
8424 struct bnx2 *bp = netdev_priv(dev);
8425
8426 /* PCI register 4 needs to be saved whether netif_running() or not.
8427 * MSI address and data need to be saved if using MSI and
8428 * netif_running().
8429 */
8430 pci_save_state(pdev);
8431 if (!netif_running(dev))
8432 return 0;
8433
8434 flush_scheduled_work();
8435 bnx2_netif_stop(bp, true);
8436 netif_device_detach(dev);
8437 del_timer_sync(&bp->timer);
8438 bnx2_shutdown_chip(bp);
8439 bnx2_free_skbs(bp);
8440 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8441 return 0;
8442 }
8443
8444 static int
8445 bnx2_resume(struct pci_dev *pdev)
8446 {
8447 struct net_device *dev = pci_get_drvdata(pdev);
8448 struct bnx2 *bp = netdev_priv(dev);
8449
8450 pci_restore_state(pdev);
8451 if (!netif_running(dev))
8452 return 0;
8453
8454 bnx2_set_power_state(bp, PCI_D0);
8455 netif_device_attach(dev);
8456 bnx2_init_nic(bp, 1);
8457 bnx2_netif_start(bp, true);
8458 return 0;
8459 }
8460
8461 /**
8462 * bnx2_io_error_detected - called when PCI error is detected
8463 * @pdev: Pointer to PCI device
8464 * @state: The current pci connection state
8465 *
8466 * This function is called after a PCI bus error affecting
8467 * this device has been detected.
8468 */
8469 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8470 pci_channel_state_t state)
8471 {
8472 struct net_device *dev = pci_get_drvdata(pdev);
8473 struct bnx2 *bp = netdev_priv(dev);
8474
8475 rtnl_lock();
8476 netif_device_detach(dev);
8477
8478 if (state == pci_channel_io_perm_failure) {
8479 rtnl_unlock();
8480 return PCI_ERS_RESULT_DISCONNECT;
8481 }
8482
8483 if (netif_running(dev)) {
8484 bnx2_netif_stop(bp, true);
8485 del_timer_sync(&bp->timer);
8486 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8487 }
8488
8489 pci_disable_device(pdev);
8490 rtnl_unlock();
8491
8492 /* Request a slot slot reset. */
8493 return PCI_ERS_RESULT_NEED_RESET;
8494 }
8495
8496 /**
8497 * bnx2_io_slot_reset - called after the pci bus has been reset.
8498 * @pdev: Pointer to PCI device
8499 *
8500 * Restart the card from scratch, as if from a cold-boot.
8501 */
8502 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8503 {
8504 struct net_device *dev = pci_get_drvdata(pdev);
8505 struct bnx2 *bp = netdev_priv(dev);
8506
8507 rtnl_lock();
8508 if (pci_enable_device(pdev)) {
8509 dev_err(&pdev->dev,
8510 "Cannot re-enable PCI device after reset\n");
8511 rtnl_unlock();
8512 return PCI_ERS_RESULT_DISCONNECT;
8513 }
8514 pci_set_master(pdev);
8515 pci_restore_state(pdev);
8516 pci_save_state(pdev);
8517
8518 if (netif_running(dev)) {
8519 bnx2_set_power_state(bp, PCI_D0);
8520 bnx2_init_nic(bp, 1);
8521 }
8522
8523 rtnl_unlock();
8524 return PCI_ERS_RESULT_RECOVERED;
8525 }
8526
8527 /**
8528 * bnx2_io_resume - called when traffic can start flowing again.
8529 * @pdev: Pointer to PCI device
8530 *
8531 * This callback is called when the error recovery driver tells us that
8532 * its OK to resume normal operation.
8533 */
8534 static void bnx2_io_resume(struct pci_dev *pdev)
8535 {
8536 struct net_device *dev = pci_get_drvdata(pdev);
8537 struct bnx2 *bp = netdev_priv(dev);
8538
8539 rtnl_lock();
8540 if (netif_running(dev))
8541 bnx2_netif_start(bp, true);
8542
8543 netif_device_attach(dev);
8544 rtnl_unlock();
8545 }
8546
8547 static struct pci_error_handlers bnx2_err_handler = {
8548 .error_detected = bnx2_io_error_detected,
8549 .slot_reset = bnx2_io_slot_reset,
8550 .resume = bnx2_io_resume,
8551 };
8552
8553 static struct pci_driver bnx2_pci_driver = {
8554 .name = DRV_MODULE_NAME,
8555 .id_table = bnx2_pci_tbl,
8556 .probe = bnx2_init_one,
8557 .remove = __devexit_p(bnx2_remove_one),
8558 .suspend = bnx2_suspend,
8559 .resume = bnx2_resume,
8560 .err_handler = &bnx2_err_handler,
8561 };
8562
8563 static int __init bnx2_init(void)
8564 {
8565 return pci_register_driver(&bnx2_pci_driver);
8566 }
8567
8568 static void __exit bnx2_cleanup(void)
8569 {
8570 pci_unregister_driver(&bnx2_pci_driver);
8571 }
8572
8573 module_init(bnx2_init);
8574 module_exit(bnx2_cleanup);
8575
8576
8577
Linux kernel - Deliverables
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