1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
17 #include <linux/ethtool.h>
18 #include <linux/netdevice.h>
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/crc32.h>
25 #include "bnx2x_cmn.h"
26 #include "bnx2x_dump.h"
27 #include "bnx2x_init.h"
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
34 #define MAX_QUEUE_NAME_LEN 4
38 char string
[ETH_GSTRING_LEN
];
39 } bnx2x_q_stats_arr
[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi
), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi
),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi
),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi
),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi
), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt
),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed
),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err
), 4, "[%s]: rx_csum_offload_errors" },
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi
), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi
),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi
),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi
),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi
),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi
),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi
), 8, "[%s]: tpa_bytes"}
68 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
74 #define STATS_FLAGS_PORT 1
75 #define STATS_FLAGS_FUNC 2
76 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string
[ETH_GSTRING_LEN
];
78 } bnx2x_stats_arr
[] = {
79 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi
),
80 8, STATS_FLAGS_BOTH
, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi
),
82 8, STATS_FLAGS_BOTH
, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi
),
84 8, STATS_FLAGS_BOTH
, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi
),
86 8, STATS_FLAGS_BOTH
, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi
),
88 8, STATS_FLAGS_BOTH
, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi
),
90 8, STATS_FLAGS_PORT
, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi
),
92 8, STATS_FLAGS_PORT
, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi
),
94 8, STATS_FLAGS_PORT
, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi
),
96 8, STATS_FLAGS_PORT
, "rx_oversize_packets" },
97 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi
),
98 8, STATS_FLAGS_PORT
, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi
),
100 8, STATS_FLAGS_PORT
, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi
),
102 8, STATS_FLAGS_BOTH
, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard
),
104 4, STATS_FLAGS_PORT
, "rx_filtered_packets" },
105 { STATS_OFFSET32(mf_tag_discard
),
106 4, STATS_FLAGS_PORT
, "rx_mf_tag_discard" },
107 { STATS_OFFSET32(brb_drop_hi
),
108 8, STATS_FLAGS_PORT
, "rx_brb_discard" },
109 { STATS_OFFSET32(brb_truncate_hi
),
110 8, STATS_FLAGS_PORT
, "rx_brb_truncate" },
111 { STATS_OFFSET32(pause_frames_received_hi
),
112 8, STATS_FLAGS_PORT
, "rx_pause_frames" },
113 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi
),
114 8, STATS_FLAGS_PORT
, "rx_mac_ctrl_frames" },
115 { STATS_OFFSET32(nig_timer_max
),
116 4, STATS_FLAGS_PORT
, "rx_constant_pause_events" },
117 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt
),
118 4, STATS_FLAGS_BOTH
, "rx_phy_ip_err_discards"},
119 { STATS_OFFSET32(rx_skb_alloc_failed
),
120 4, STATS_FLAGS_BOTH
, "rx_skb_alloc_discard" },
121 { STATS_OFFSET32(hw_csum_err
),
122 4, STATS_FLAGS_BOTH
, "rx_csum_offload_errors" },
124 { STATS_OFFSET32(total_bytes_transmitted_hi
),
125 8, STATS_FLAGS_BOTH
, "tx_bytes" },
126 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi
),
127 8, STATS_FLAGS_PORT
, "tx_error_bytes" },
128 { STATS_OFFSET32(total_unicast_packets_transmitted_hi
),
129 8, STATS_FLAGS_BOTH
, "tx_ucast_packets" },
130 { STATS_OFFSET32(total_multicast_packets_transmitted_hi
),
131 8, STATS_FLAGS_BOTH
, "tx_mcast_packets" },
132 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi
),
133 8, STATS_FLAGS_BOTH
, "tx_bcast_packets" },
134 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi
),
135 8, STATS_FLAGS_PORT
, "tx_mac_errors" },
136 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi
),
137 8, STATS_FLAGS_PORT
, "tx_carrier_errors" },
138 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi
),
139 8, STATS_FLAGS_PORT
, "tx_single_collisions" },
140 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi
),
141 8, STATS_FLAGS_PORT
, "tx_multi_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi
),
143 8, STATS_FLAGS_PORT
, "tx_deferred" },
144 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi
),
145 8, STATS_FLAGS_PORT
, "tx_excess_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi
),
147 8, STATS_FLAGS_PORT
, "tx_late_collisions" },
148 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi
),
149 8, STATS_FLAGS_PORT
, "tx_total_collisions" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi
),
151 8, STATS_FLAGS_PORT
, "tx_64_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi
),
153 8, STATS_FLAGS_PORT
, "tx_65_to_127_byte_packets" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi
),
155 8, STATS_FLAGS_PORT
, "tx_128_to_255_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi
),
157 8, STATS_FLAGS_PORT
, "tx_256_to_511_byte_packets" },
158 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi
),
159 8, STATS_FLAGS_PORT
, "tx_512_to_1023_byte_packets" },
160 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi
),
161 8, STATS_FLAGS_PORT
, "tx_1024_to_1522_byte_packets" },
162 { STATS_OFFSET32(etherstatspktsover1522octets_hi
),
163 8, STATS_FLAGS_PORT
, "tx_1523_to_9022_byte_packets" },
164 { STATS_OFFSET32(pause_frames_sent_hi
),
165 8, STATS_FLAGS_PORT
, "tx_pause_frames" },
166 { STATS_OFFSET32(total_tpa_aggregations_hi
),
167 8, STATS_FLAGS_FUNC
, "tpa_aggregations" },
168 { STATS_OFFSET32(total_tpa_aggregated_frames_hi
),
169 8, STATS_FLAGS_FUNC
, "tpa_aggregated_frames"},
170 { STATS_OFFSET32(total_tpa_bytes_hi
),
171 8, STATS_FLAGS_FUNC
, "tpa_bytes"}
174 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
175 static int bnx2x_get_port_type(struct bnx2x
*bp
)
178 u32 phy_idx
= bnx2x_get_cur_phy_idx(bp
);
179 switch (bp
->link_params
.phy
[phy_idx
].media_type
) {
180 case ETH_PHY_SFP_FIBER
:
181 case ETH_PHY_XFP_FIBER
:
184 port_type
= PORT_FIBRE
;
186 case ETH_PHY_DA_TWINAX
:
192 case ETH_PHY_NOT_PRESENT
:
193 port_type
= PORT_NONE
;
195 case ETH_PHY_UNSPECIFIED
:
197 port_type
= PORT_OTHER
;
203 static int bnx2x_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
205 struct bnx2x
*bp
= netdev_priv(dev
);
206 int cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
208 /* Dual Media boards present all available port types */
209 cmd
->supported
= bp
->port
.supported
[cfg_idx
] |
210 (bp
->port
.supported
[cfg_idx
^ 1] &
211 (SUPPORTED_TP
| SUPPORTED_FIBRE
));
212 cmd
->advertising
= bp
->port
.advertising
[cfg_idx
];
214 if ((bp
->state
== BNX2X_STATE_OPEN
) &&
215 !(bp
->flags
& MF_FUNC_DIS
) &&
216 (bp
->link_vars
.link_up
)) {
217 ethtool_cmd_speed_set(cmd
, bp
->link_vars
.line_speed
);
218 cmd
->duplex
= bp
->link_vars
.duplex
;
220 ethtool_cmd_speed_set(
221 cmd
, bp
->link_params
.req_line_speed
[cfg_idx
]);
222 cmd
->duplex
= bp
->link_params
.req_duplex
[cfg_idx
];
226 ethtool_cmd_speed_set(cmd
, bnx2x_get_mf_speed(bp
));
228 cmd
->port
= bnx2x_get_port_type(bp
);
230 cmd
->phy_address
= bp
->mdio
.prtad
;
231 cmd
->transceiver
= XCVR_INTERNAL
;
233 if (bp
->link_params
.req_line_speed
[cfg_idx
] == SPEED_AUTO_NEG
)
234 cmd
->autoneg
= AUTONEG_ENABLE
;
236 cmd
->autoneg
= AUTONEG_DISABLE
;
241 DP(NETIF_MSG_LINK
, "ethtool_cmd: cmd %d\n"
242 DP_LEVEL
" supported 0x%x advertising 0x%x speed %u\n"
243 DP_LEVEL
" duplex %d port %d phy_address %d transceiver %d\n"
244 DP_LEVEL
" autoneg %d maxtxpkt %d maxrxpkt %d\n",
245 cmd
->cmd
, cmd
->supported
, cmd
->advertising
,
246 ethtool_cmd_speed(cmd
),
247 cmd
->duplex
, cmd
->port
, cmd
->phy_address
, cmd
->transceiver
,
248 cmd
->autoneg
, cmd
->maxtxpkt
, cmd
->maxrxpkt
);
253 static int bnx2x_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
255 struct bnx2x
*bp
= netdev_priv(dev
);
256 u32 advertising
, cfg_idx
, old_multi_phy_config
, new_multi_phy_config
;
262 DP(NETIF_MSG_LINK
, "ethtool_cmd: cmd %d\n"
263 " supported 0x%x advertising 0x%x speed %u\n"
264 " duplex %d port %d phy_address %d transceiver %d\n"
265 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
266 cmd
->cmd
, cmd
->supported
, cmd
->advertising
,
267 ethtool_cmd_speed(cmd
),
268 cmd
->duplex
, cmd
->port
, cmd
->phy_address
, cmd
->transceiver
,
269 cmd
->autoneg
, cmd
->maxtxpkt
, cmd
->maxrxpkt
);
271 speed
= ethtool_cmd_speed(cmd
);
275 u32 line_speed
= bp
->link_vars
.line_speed
;
277 /* use 10G if no link detected */
281 if (bp
->common
.bc_ver
< REQ_BC_VER_4_SET_MF_BW
) {
282 BNX2X_DEV_INFO("To set speed BC %X or higher "
283 "is required, please upgrade BC\n",
284 REQ_BC_VER_4_SET_MF_BW
);
288 part
= (speed
* 100) / line_speed
;
290 if (line_speed
< speed
|| !part
) {
291 BNX2X_DEV_INFO("Speed setting should be in a range "
293 "of actual line speed\n");
297 if (bp
->state
!= BNX2X_STATE_OPEN
)
298 /* store value for following "load" */
299 bp
->pending_max
= part
;
301 bnx2x_update_max_mf_config(bp
, part
);
306 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
307 old_multi_phy_config
= bp
->link_params
.multi_phy_config
;
310 if (bp
->port
.supported
[cfg_idx
] & SUPPORTED_TP
)
311 break; /* no port change */
313 if (!(bp
->port
.supported
[0] & SUPPORTED_TP
||
314 bp
->port
.supported
[1] & SUPPORTED_TP
)) {
315 DP(NETIF_MSG_LINK
, "Unsupported port type\n");
318 bp
->link_params
.multi_phy_config
&=
319 ~PORT_HW_CFG_PHY_SELECTION_MASK
;
320 if (bp
->link_params
.multi_phy_config
&
321 PORT_HW_CFG_PHY_SWAPPED_ENABLED
)
322 bp
->link_params
.multi_phy_config
|=
323 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
;
325 bp
->link_params
.multi_phy_config
|=
326 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
;
329 if (bp
->port
.supported
[cfg_idx
] & SUPPORTED_FIBRE
)
330 break; /* no port change */
332 if (!(bp
->port
.supported
[0] & SUPPORTED_FIBRE
||
333 bp
->port
.supported
[1] & SUPPORTED_FIBRE
)) {
334 DP(NETIF_MSG_LINK
, "Unsupported port type\n");
337 bp
->link_params
.multi_phy_config
&=
338 ~PORT_HW_CFG_PHY_SELECTION_MASK
;
339 if (bp
->link_params
.multi_phy_config
&
340 PORT_HW_CFG_PHY_SWAPPED_ENABLED
)
341 bp
->link_params
.multi_phy_config
|=
342 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
;
344 bp
->link_params
.multi_phy_config
|=
345 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
;
348 DP(NETIF_MSG_LINK
, "Unsupported port type\n");
351 /* Save new config in case command complete successuly */
352 new_multi_phy_config
= bp
->link_params
.multi_phy_config
;
353 /* Get the new cfg_idx */
354 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
355 /* Restore old config in case command failed */
356 bp
->link_params
.multi_phy_config
= old_multi_phy_config
;
357 DP(NETIF_MSG_LINK
, "cfg_idx = %x\n", cfg_idx
);
359 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
360 if (!(bp
->port
.supported
[cfg_idx
] & SUPPORTED_Autoneg
)) {
361 DP(NETIF_MSG_LINK
, "Autoneg not supported\n");
365 /* advertise the requested speed and duplex if supported */
366 cmd
->advertising
&= bp
->port
.supported
[cfg_idx
];
368 bp
->link_params
.req_line_speed
[cfg_idx
] = SPEED_AUTO_NEG
;
369 bp
->link_params
.req_duplex
[cfg_idx
] = DUPLEX_FULL
;
370 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Autoneg
|
373 } else { /* forced speed */
374 /* advertise the requested speed and duplex if supported */
377 if (cmd
->duplex
== DUPLEX_FULL
) {
378 if (!(bp
->port
.supported
[cfg_idx
] &
379 SUPPORTED_10baseT_Full
)) {
381 "10M full not supported\n");
385 advertising
= (ADVERTISED_10baseT_Full
|
388 if (!(bp
->port
.supported
[cfg_idx
] &
389 SUPPORTED_10baseT_Half
)) {
391 "10M half not supported\n");
395 advertising
= (ADVERTISED_10baseT_Half
|
401 if (cmd
->duplex
== DUPLEX_FULL
) {
402 if (!(bp
->port
.supported
[cfg_idx
] &
403 SUPPORTED_100baseT_Full
)) {
405 "100M full not supported\n");
409 advertising
= (ADVERTISED_100baseT_Full
|
412 if (!(bp
->port
.supported
[cfg_idx
] &
413 SUPPORTED_100baseT_Half
)) {
415 "100M half not supported\n");
419 advertising
= (ADVERTISED_100baseT_Half
|
425 if (cmd
->duplex
!= DUPLEX_FULL
) {
426 DP(NETIF_MSG_LINK
, "1G half not supported\n");
430 if (!(bp
->port
.supported
[cfg_idx
] &
431 SUPPORTED_1000baseT_Full
)) {
432 DP(NETIF_MSG_LINK
, "1G full not supported\n");
436 advertising
= (ADVERTISED_1000baseT_Full
|
441 if (cmd
->duplex
!= DUPLEX_FULL
) {
443 "2.5G half not supported\n");
447 if (!(bp
->port
.supported
[cfg_idx
]
448 & SUPPORTED_2500baseX_Full
)) {
450 "2.5G full not supported\n");
454 advertising
= (ADVERTISED_2500baseX_Full
|
459 if (cmd
->duplex
!= DUPLEX_FULL
) {
460 DP(NETIF_MSG_LINK
, "10G half not supported\n");
464 if (!(bp
->port
.supported
[cfg_idx
]
465 & SUPPORTED_10000baseT_Full
)) {
466 DP(NETIF_MSG_LINK
, "10G full not supported\n");
470 advertising
= (ADVERTISED_10000baseT_Full
|
475 DP(NETIF_MSG_LINK
, "Unsupported speed %u\n", speed
);
479 bp
->link_params
.req_line_speed
[cfg_idx
] = speed
;
480 bp
->link_params
.req_duplex
[cfg_idx
] = cmd
->duplex
;
481 bp
->port
.advertising
[cfg_idx
] = advertising
;
484 DP(NETIF_MSG_LINK
, "req_line_speed %d\n"
485 DP_LEVEL
" req_duplex %d advertising 0x%x\n",
486 bp
->link_params
.req_line_speed
[cfg_idx
],
487 bp
->link_params
.req_duplex
[cfg_idx
],
488 bp
->port
.advertising
[cfg_idx
]);
491 bp
->link_params
.multi_phy_config
= new_multi_phy_config
;
492 if (netif_running(dev
)) {
493 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
500 #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
501 #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
502 #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
504 static int bnx2x_get_regs_len(struct net_device
*dev
)
506 struct bnx2x
*bp
= netdev_priv(dev
);
510 if (CHIP_IS_E1(bp
)) {
511 for (i
= 0; i
< REGS_COUNT
; i
++)
512 if (IS_E1_ONLINE(reg_addrs
[i
].info
))
513 regdump_len
+= reg_addrs
[i
].size
;
515 for (i
= 0; i
< WREGS_COUNT_E1
; i
++)
516 if (IS_E1_ONLINE(wreg_addrs_e1
[i
].info
))
517 regdump_len
+= wreg_addrs_e1
[i
].size
*
518 (1 + wreg_addrs_e1
[i
].read_regs_count
);
520 } else if (CHIP_IS_E1H(bp
)) {
521 for (i
= 0; i
< REGS_COUNT
; i
++)
522 if (IS_E1H_ONLINE(reg_addrs
[i
].info
))
523 regdump_len
+= reg_addrs
[i
].size
;
525 for (i
= 0; i
< WREGS_COUNT_E1H
; i
++)
526 if (IS_E1H_ONLINE(wreg_addrs_e1h
[i
].info
))
527 regdump_len
+= wreg_addrs_e1h
[i
].size
*
528 (1 + wreg_addrs_e1h
[i
].read_regs_count
);
529 } else if (!CHIP_IS_E1x(bp
)) {
530 for (i
= 0; i
< REGS_COUNT
; i
++)
531 if (IS_E2_ONLINE(reg_addrs
[i
].info
))
532 regdump_len
+= reg_addrs
[i
].size
;
534 for (i
= 0; i
< WREGS_COUNT_E2
; i
++)
535 if (IS_E2_ONLINE(wreg_addrs_e2
[i
].info
))
536 regdump_len
+= wreg_addrs_e2
[i
].size
*
537 (1 + wreg_addrs_e2
[i
].read_regs_count
);
539 for (i
= 0; i
< PAGE_MODE_VALUES_E2
; i
++)
540 for (j
= 0; j
< PAGE_WRITE_REGS_E2
; j
++) {
541 for (k
= 0; k
< PAGE_READ_REGS_E2
; k
++)
542 if (IS_E2_ONLINE(page_read_regs_e2
[k
].
545 page_read_regs_e2
[k
].size
;
549 regdump_len
+= sizeof(struct dump_hdr
);
554 static inline void bnx2x_read_pages_regs_e2(struct bnx2x
*bp
, u32
*p
)
558 for (i
= 0; i
< PAGE_MODE_VALUES_E2
; i
++) {
559 for (j
= 0; j
< PAGE_WRITE_REGS_E2
; j
++) {
560 REG_WR(bp
, page_write_regs_e2
[j
], page_vals_e2
[i
]);
561 for (k
= 0; k
< PAGE_READ_REGS_E2
; k
++)
562 if (IS_E2_ONLINE(page_read_regs_e2
[k
].info
))
564 page_read_regs_e2
[k
].size
; n
++)
566 page_read_regs_e2
[k
].addr
+ n
*4);
571 static void bnx2x_get_regs(struct net_device
*dev
,
572 struct ethtool_regs
*regs
, void *_p
)
575 struct bnx2x
*bp
= netdev_priv(dev
);
576 struct dump_hdr dump_hdr
= {0};
579 memset(p
, 0, regs
->len
);
581 if (!netif_running(bp
->dev
))
584 /* Disable parity attentions as long as following dump may
585 * cause false alarms by reading never written registers. We
586 * will re-enable parity attentions right after the dump.
588 bnx2x_disable_blocks_parity(bp
);
590 dump_hdr
.hdr_size
= (sizeof(struct dump_hdr
) / 4) - 1;
591 dump_hdr
.dump_sign
= dump_sign_all
;
592 dump_hdr
.xstorm_waitp
= REG_RD(bp
, XSTORM_WAITP_ADDR
);
593 dump_hdr
.tstorm_waitp
= REG_RD(bp
, TSTORM_WAITP_ADDR
);
594 dump_hdr
.ustorm_waitp
= REG_RD(bp
, USTORM_WAITP_ADDR
);
595 dump_hdr
.cstorm_waitp
= REG_RD(bp
, CSTORM_WAITP_ADDR
);
598 dump_hdr
.info
= RI_E1_ONLINE
;
599 else if (CHIP_IS_E1H(bp
))
600 dump_hdr
.info
= RI_E1H_ONLINE
;
601 else if (!CHIP_IS_E1x(bp
))
602 dump_hdr
.info
= RI_E2_ONLINE
|
603 (BP_PATH(bp
) ? RI_PATH1_DUMP
: RI_PATH0_DUMP
);
605 memcpy(p
, &dump_hdr
, sizeof(struct dump_hdr
));
606 p
+= dump_hdr
.hdr_size
+ 1;
608 if (CHIP_IS_E1(bp
)) {
609 for (i
= 0; i
< REGS_COUNT
; i
++)
610 if (IS_E1_ONLINE(reg_addrs
[i
].info
))
611 for (j
= 0; j
< reg_addrs
[i
].size
; j
++)
613 reg_addrs
[i
].addr
+ j
*4);
615 } else if (CHIP_IS_E1H(bp
)) {
616 for (i
= 0; i
< REGS_COUNT
; i
++)
617 if (IS_E1H_ONLINE(reg_addrs
[i
].info
))
618 for (j
= 0; j
< reg_addrs
[i
].size
; j
++)
620 reg_addrs
[i
].addr
+ j
*4);
622 } else if (!CHIP_IS_E1x(bp
)) {
623 for (i
= 0; i
< REGS_COUNT
; i
++)
624 if (IS_E2_ONLINE(reg_addrs
[i
].info
))
625 for (j
= 0; j
< reg_addrs
[i
].size
; j
++)
627 reg_addrs
[i
].addr
+ j
*4);
630 bnx2x_read_pages_regs_e2(bp
, p
);
632 /* E3 paged registers read is unimplemented yet */
635 /* Re-enable parity attentions */
636 bnx2x_clear_blocks_parity(bp
);
637 bnx2x_enable_blocks_parity(bp
);
640 static void bnx2x_get_drvinfo(struct net_device
*dev
,
641 struct ethtool_drvinfo
*info
)
643 struct bnx2x
*bp
= netdev_priv(dev
);
644 u8 phy_fw_ver
[PHY_FW_VER_LEN
];
646 strcpy(info
->driver
, DRV_MODULE_NAME
);
647 strcpy(info
->version
, DRV_MODULE_VERSION
);
649 phy_fw_ver
[0] = '\0';
651 bnx2x_acquire_phy_lock(bp
);
652 bnx2x_get_ext_phy_fw_version(&bp
->link_params
,
653 (bp
->state
!= BNX2X_STATE_CLOSED
),
654 phy_fw_ver
, PHY_FW_VER_LEN
);
655 bnx2x_release_phy_lock(bp
);
658 strncpy(info
->fw_version
, bp
->fw_ver
, 32);
659 snprintf(info
->fw_version
+ strlen(bp
->fw_ver
), 32 - strlen(bp
->fw_ver
),
661 (bp
->common
.bc_ver
& 0xff0000) >> 16,
662 (bp
->common
.bc_ver
& 0xff00) >> 8,
663 (bp
->common
.bc_ver
& 0xff),
664 ((phy_fw_ver
[0] != '\0') ? " phy " : ""), phy_fw_ver
);
665 strcpy(info
->bus_info
, pci_name(bp
->pdev
));
666 info
->n_stats
= BNX2X_NUM_STATS
;
667 info
->testinfo_len
= BNX2X_NUM_TESTS
;
668 info
->eedump_len
= bp
->common
.flash_size
;
669 info
->regdump_len
= bnx2x_get_regs_len(dev
);
672 static void bnx2x_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
674 struct bnx2x
*bp
= netdev_priv(dev
);
676 if (bp
->flags
& NO_WOL_FLAG
) {
680 wol
->supported
= WAKE_MAGIC
;
682 wol
->wolopts
= WAKE_MAGIC
;
686 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
689 static int bnx2x_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
691 struct bnx2x
*bp
= netdev_priv(dev
);
693 if (wol
->wolopts
& ~WAKE_MAGIC
)
696 if (wol
->wolopts
& WAKE_MAGIC
) {
697 if (bp
->flags
& NO_WOL_FLAG
)
707 static u32
bnx2x_get_msglevel(struct net_device
*dev
)
709 struct bnx2x
*bp
= netdev_priv(dev
);
711 return bp
->msg_enable
;
714 static void bnx2x_set_msglevel(struct net_device
*dev
, u32 level
)
716 struct bnx2x
*bp
= netdev_priv(dev
);
718 if (capable(CAP_NET_ADMIN
)) {
720 if (level
& BNX2X_MSG_MCP
)
721 bnx2x_fw_dump_lvl(bp
, KERN_INFO
);
722 bp
->msg_enable
= level
;
726 static int bnx2x_nway_reset(struct net_device
*dev
)
728 struct bnx2x
*bp
= netdev_priv(dev
);
733 if (netif_running(dev
)) {
734 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
741 static u32
bnx2x_get_link(struct net_device
*dev
)
743 struct bnx2x
*bp
= netdev_priv(dev
);
745 if (bp
->flags
& MF_FUNC_DIS
|| (bp
->state
!= BNX2X_STATE_OPEN
))
748 return bp
->link_vars
.link_up
;
751 static int bnx2x_get_eeprom_len(struct net_device
*dev
)
753 struct bnx2x
*bp
= netdev_priv(dev
);
755 return bp
->common
.flash_size
;
758 static int bnx2x_acquire_nvram_lock(struct bnx2x
*bp
)
760 int port
= BP_PORT(bp
);
764 /* adjust timeout for emulation/FPGA */
765 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
766 if (CHIP_REV_IS_SLOW(bp
))
769 /* request access to nvram interface */
770 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
771 (MCPR_NVM_SW_ARB_ARB_REQ_SET1
<< port
));
773 for (i
= 0; i
< count
*10; i
++) {
774 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_SW_ARB
);
775 if (val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
))
781 if (!(val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
))) {
782 DP(BNX2X_MSG_NVM
, "cannot get access to nvram interface\n");
789 static int bnx2x_release_nvram_lock(struct bnx2x
*bp
)
791 int port
= BP_PORT(bp
);
795 /* adjust timeout for emulation/FPGA */
796 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
797 if (CHIP_REV_IS_SLOW(bp
))
800 /* relinquish nvram interface */
801 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
802 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< port
));
804 for (i
= 0; i
< count
*10; i
++) {
805 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_SW_ARB
);
806 if (!(val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
)))
812 if (val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
)) {
813 DP(BNX2X_MSG_NVM
, "cannot free access to nvram interface\n");
820 static void bnx2x_enable_nvram_access(struct bnx2x
*bp
)
824 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
);
826 /* enable both bits, even on read */
827 REG_WR(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
,
828 (val
| MCPR_NVM_ACCESS_ENABLE_EN
|
829 MCPR_NVM_ACCESS_ENABLE_WR_EN
));
832 static void bnx2x_disable_nvram_access(struct bnx2x
*bp
)
836 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
);
838 /* disable both bits, even after read */
839 REG_WR(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
,
840 (val
& ~(MCPR_NVM_ACCESS_ENABLE_EN
|
841 MCPR_NVM_ACCESS_ENABLE_WR_EN
)));
844 static int bnx2x_nvram_read_dword(struct bnx2x
*bp
, u32 offset
, __be32
*ret_val
,
850 /* build the command word */
851 cmd_flags
|= MCPR_NVM_COMMAND_DOIT
;
853 /* need to clear DONE bit separately */
854 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, MCPR_NVM_COMMAND_DONE
);
856 /* address of the NVRAM to read from */
857 REG_WR(bp
, MCP_REG_MCPR_NVM_ADDR
,
858 (offset
& MCPR_NVM_ADDR_NVM_ADDR_VALUE
));
860 /* issue a read command */
861 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, cmd_flags
);
863 /* adjust timeout for emulation/FPGA */
864 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
865 if (CHIP_REV_IS_SLOW(bp
))
868 /* wait for completion */
871 for (i
= 0; i
< count
; i
++) {
873 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_COMMAND
);
875 if (val
& MCPR_NVM_COMMAND_DONE
) {
876 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_READ
);
877 /* we read nvram data in cpu order
878 * but ethtool sees it as an array of bytes
879 * converting to big-endian will do the work */
880 *ret_val
= cpu_to_be32(val
);
889 static int bnx2x_nvram_read(struct bnx2x
*bp
, u32 offset
, u8
*ret_buf
,
896 if ((offset
& 0x03) || (buf_size
& 0x03) || (buf_size
== 0)) {
898 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
903 if (offset
+ buf_size
> bp
->common
.flash_size
) {
904 DP(BNX2X_MSG_NVM
, "Invalid parameter: offset (0x%x) +"
905 " buf_size (0x%x) > flash_size (0x%x)\n",
906 offset
, buf_size
, bp
->common
.flash_size
);
910 /* request access to nvram interface */
911 rc
= bnx2x_acquire_nvram_lock(bp
);
915 /* enable access to nvram interface */
916 bnx2x_enable_nvram_access(bp
);
918 /* read the first word(s) */
919 cmd_flags
= MCPR_NVM_COMMAND_FIRST
;
920 while ((buf_size
> sizeof(u32
)) && (rc
== 0)) {
921 rc
= bnx2x_nvram_read_dword(bp
, offset
, &val
, cmd_flags
);
922 memcpy(ret_buf
, &val
, 4);
924 /* advance to the next dword */
925 offset
+= sizeof(u32
);
926 ret_buf
+= sizeof(u32
);
927 buf_size
-= sizeof(u32
);
932 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
933 rc
= bnx2x_nvram_read_dword(bp
, offset
, &val
, cmd_flags
);
934 memcpy(ret_buf
, &val
, 4);
937 /* disable access to nvram interface */
938 bnx2x_disable_nvram_access(bp
);
939 bnx2x_release_nvram_lock(bp
);
944 static int bnx2x_get_eeprom(struct net_device
*dev
,
945 struct ethtool_eeprom
*eeprom
, u8
*eebuf
)
947 struct bnx2x
*bp
= netdev_priv(dev
);
950 if (!netif_running(dev
))
953 DP(BNX2X_MSG_NVM
, "ethtool_eeprom: cmd %d\n"
954 DP_LEVEL
" magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
955 eeprom
->cmd
, eeprom
->magic
, eeprom
->offset
, eeprom
->offset
,
956 eeprom
->len
, eeprom
->len
);
958 /* parameters already validated in ethtool_get_eeprom */
960 rc
= bnx2x_nvram_read(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
965 static int bnx2x_nvram_write_dword(struct bnx2x
*bp
, u32 offset
, u32 val
,
970 /* build the command word */
971 cmd_flags
|= MCPR_NVM_COMMAND_DOIT
| MCPR_NVM_COMMAND_WR
;
973 /* need to clear DONE bit separately */
974 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, MCPR_NVM_COMMAND_DONE
);
977 REG_WR(bp
, MCP_REG_MCPR_NVM_WRITE
, val
);
979 /* address of the NVRAM to write to */
980 REG_WR(bp
, MCP_REG_MCPR_NVM_ADDR
,
981 (offset
& MCPR_NVM_ADDR_NVM_ADDR_VALUE
));
983 /* issue the write command */
984 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, cmd_flags
);
986 /* adjust timeout for emulation/FPGA */
987 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
988 if (CHIP_REV_IS_SLOW(bp
))
991 /* wait for completion */
993 for (i
= 0; i
< count
; i
++) {
995 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_COMMAND
);
996 if (val
& MCPR_NVM_COMMAND_DONE
) {
1005 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1007 static int bnx2x_nvram_write1(struct bnx2x
*bp
, u32 offset
, u8
*data_buf
,
1015 if (offset
+ buf_size
> bp
->common
.flash_size
) {
1016 DP(BNX2X_MSG_NVM
, "Invalid parameter: offset (0x%x) +"
1017 " buf_size (0x%x) > flash_size (0x%x)\n",
1018 offset
, buf_size
, bp
->common
.flash_size
);
1022 /* request access to nvram interface */
1023 rc
= bnx2x_acquire_nvram_lock(bp
);
1027 /* enable access to nvram interface */
1028 bnx2x_enable_nvram_access(bp
);
1030 cmd_flags
= (MCPR_NVM_COMMAND_FIRST
| MCPR_NVM_COMMAND_LAST
);
1031 align_offset
= (offset
& ~0x03);
1032 rc
= bnx2x_nvram_read_dword(bp
, align_offset
, &val
, cmd_flags
);
1035 val
&= ~(0xff << BYTE_OFFSET(offset
));
1036 val
|= (*data_buf
<< BYTE_OFFSET(offset
));
1038 /* nvram data is returned as an array of bytes
1039 * convert it back to cpu order */
1040 val
= be32_to_cpu(val
);
1042 rc
= bnx2x_nvram_write_dword(bp
, align_offset
, val
,
1046 /* disable access to nvram interface */
1047 bnx2x_disable_nvram_access(bp
);
1048 bnx2x_release_nvram_lock(bp
);
1053 static int bnx2x_nvram_write(struct bnx2x
*bp
, u32 offset
, u8
*data_buf
,
1061 if (buf_size
== 1) /* ethtool */
1062 return bnx2x_nvram_write1(bp
, offset
, data_buf
, buf_size
);
1064 if ((offset
& 0x03) || (buf_size
& 0x03) || (buf_size
== 0)) {
1066 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1071 if (offset
+ buf_size
> bp
->common
.flash_size
) {
1072 DP(BNX2X_MSG_NVM
, "Invalid parameter: offset (0x%x) +"
1073 " buf_size (0x%x) > flash_size (0x%x)\n",
1074 offset
, buf_size
, bp
->common
.flash_size
);
1078 /* request access to nvram interface */
1079 rc
= bnx2x_acquire_nvram_lock(bp
);
1083 /* enable access to nvram interface */
1084 bnx2x_enable_nvram_access(bp
);
1087 cmd_flags
= MCPR_NVM_COMMAND_FIRST
;
1088 while ((written_so_far
< buf_size
) && (rc
== 0)) {
1089 if (written_so_far
== (buf_size
- sizeof(u32
)))
1090 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
1091 else if (((offset
+ 4) % BNX2X_NVRAM_PAGE_SIZE
) == 0)
1092 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
1093 else if ((offset
% BNX2X_NVRAM_PAGE_SIZE
) == 0)
1094 cmd_flags
|= MCPR_NVM_COMMAND_FIRST
;
1096 memcpy(&val
, data_buf
, 4);
1098 rc
= bnx2x_nvram_write_dword(bp
, offset
, val
, cmd_flags
);
1100 /* advance to the next dword */
1101 offset
+= sizeof(u32
);
1102 data_buf
+= sizeof(u32
);
1103 written_so_far
+= sizeof(u32
);
1107 /* disable access to nvram interface */
1108 bnx2x_disable_nvram_access(bp
);
1109 bnx2x_release_nvram_lock(bp
);
1114 static int bnx2x_set_eeprom(struct net_device
*dev
,
1115 struct ethtool_eeprom
*eeprom
, u8
*eebuf
)
1117 struct bnx2x
*bp
= netdev_priv(dev
);
1118 int port
= BP_PORT(bp
);
1121 if (!netif_running(dev
))
1124 DP(BNX2X_MSG_NVM
, "ethtool_eeprom: cmd %d\n"
1125 DP_LEVEL
" magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1126 eeprom
->cmd
, eeprom
->magic
, eeprom
->offset
, eeprom
->offset
,
1127 eeprom
->len
, eeprom
->len
);
1129 /* parameters already validated in ethtool_set_eeprom */
1131 /* PHY eeprom can be accessed only by the PMF */
1132 if ((eeprom
->magic
>= 0x50485900) && (eeprom
->magic
<= 0x504859FF) &&
1138 dev_info
.port_hw_config
[port
].external_phy_config
);
1140 if (eeprom
->magic
== 0x50485950) {
1141 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1142 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
1144 bnx2x_acquire_phy_lock(bp
);
1145 rc
|= bnx2x_link_reset(&bp
->link_params
,
1147 if (XGXS_EXT_PHY_TYPE(ext_phy_config
) ==
1148 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
)
1149 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
1150 MISC_REGISTERS_GPIO_HIGH
, port
);
1151 bnx2x_release_phy_lock(bp
);
1152 bnx2x_link_report(bp
);
1154 } else if (eeprom
->magic
== 0x50485952) {
1155 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1156 if (bp
->state
== BNX2X_STATE_OPEN
) {
1157 bnx2x_acquire_phy_lock(bp
);
1158 rc
|= bnx2x_link_reset(&bp
->link_params
,
1161 rc
|= bnx2x_phy_init(&bp
->link_params
,
1163 bnx2x_release_phy_lock(bp
);
1164 bnx2x_calc_fc_adv(bp
);
1166 } else if (eeprom
->magic
== 0x53985943) {
1167 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1168 if (XGXS_EXT_PHY_TYPE(ext_phy_config
) ==
1169 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
) {
1171 /* DSP Remove Download Mode */
1172 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
1173 MISC_REGISTERS_GPIO_LOW
, port
);
1175 bnx2x_acquire_phy_lock(bp
);
1177 bnx2x_sfx7101_sp_sw_reset(bp
,
1178 &bp
->link_params
.phy
[EXT_PHY1
]);
1180 /* wait 0.5 sec to allow it to run */
1182 bnx2x_ext_phy_hw_reset(bp
, port
);
1184 bnx2x_release_phy_lock(bp
);
1187 rc
= bnx2x_nvram_write(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
1192 static int bnx2x_get_coalesce(struct net_device
*dev
,
1193 struct ethtool_coalesce
*coal
)
1195 struct bnx2x
*bp
= netdev_priv(dev
);
1197 memset(coal
, 0, sizeof(struct ethtool_coalesce
));
1199 coal
->rx_coalesce_usecs
= bp
->rx_ticks
;
1200 coal
->tx_coalesce_usecs
= bp
->tx_ticks
;
1205 static int bnx2x_set_coalesce(struct net_device
*dev
,
1206 struct ethtool_coalesce
*coal
)
1208 struct bnx2x
*bp
= netdev_priv(dev
);
1210 bp
->rx_ticks
= (u16
)coal
->rx_coalesce_usecs
;
1211 if (bp
->rx_ticks
> BNX2X_MAX_COALESCE_TOUT
)
1212 bp
->rx_ticks
= BNX2X_MAX_COALESCE_TOUT
;
1214 bp
->tx_ticks
= (u16
)coal
->tx_coalesce_usecs
;
1215 if (bp
->tx_ticks
> BNX2X_MAX_COALESCE_TOUT
)
1216 bp
->tx_ticks
= BNX2X_MAX_COALESCE_TOUT
;
1218 if (netif_running(dev
))
1219 bnx2x_update_coalesce(bp
);
1224 static void bnx2x_get_ringparam(struct net_device
*dev
,
1225 struct ethtool_ringparam
*ering
)
1227 struct bnx2x
*bp
= netdev_priv(dev
);
1229 ering
->rx_max_pending
= MAX_RX_AVAIL
;
1230 ering
->rx_mini_max_pending
= 0;
1231 ering
->rx_jumbo_max_pending
= 0;
1233 if (bp
->rx_ring_size
)
1234 ering
->rx_pending
= bp
->rx_ring_size
;
1236 if (bp
->state
== BNX2X_STATE_OPEN
&& bp
->num_queues
)
1237 ering
->rx_pending
= MAX_RX_AVAIL
/bp
->num_queues
;
1239 ering
->rx_pending
= MAX_RX_AVAIL
;
1241 ering
->rx_mini_pending
= 0;
1242 ering
->rx_jumbo_pending
= 0;
1244 ering
->tx_max_pending
= MAX_TX_AVAIL
;
1245 ering
->tx_pending
= bp
->tx_ring_size
;
1248 static int bnx2x_set_ringparam(struct net_device
*dev
,
1249 struct ethtool_ringparam
*ering
)
1251 struct bnx2x
*bp
= netdev_priv(dev
);
1253 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
1254 printk(KERN_ERR
"Handling parity error recovery. Try again later\n");
1258 if ((ering
->rx_pending
> MAX_RX_AVAIL
) ||
1259 (ering
->rx_pending
< (bp
->disable_tpa
? MIN_RX_SIZE_NONTPA
:
1260 MIN_RX_SIZE_TPA
)) ||
1261 (ering
->tx_pending
> MAX_TX_AVAIL
) ||
1262 (ering
->tx_pending
<= MAX_SKB_FRAGS
+ 4))
1265 bp
->rx_ring_size
= ering
->rx_pending
;
1266 bp
->tx_ring_size
= ering
->tx_pending
;
1268 return bnx2x_reload_if_running(dev
);
1271 static void bnx2x_get_pauseparam(struct net_device
*dev
,
1272 struct ethtool_pauseparam
*epause
)
1274 struct bnx2x
*bp
= netdev_priv(dev
);
1275 int cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
1276 epause
->autoneg
= (bp
->link_params
.req_flow_ctrl
[cfg_idx
] ==
1277 BNX2X_FLOW_CTRL_AUTO
);
1279 epause
->rx_pause
= ((bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_RX
) ==
1280 BNX2X_FLOW_CTRL_RX
);
1281 epause
->tx_pause
= ((bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
) ==
1282 BNX2X_FLOW_CTRL_TX
);
1284 DP(NETIF_MSG_LINK
, "ethtool_pauseparam: cmd %d\n"
1285 DP_LEVEL
" autoneg %d rx_pause %d tx_pause %d\n",
1286 epause
->cmd
, epause
->autoneg
, epause
->rx_pause
, epause
->tx_pause
);
1289 static int bnx2x_set_pauseparam(struct net_device
*dev
,
1290 struct ethtool_pauseparam
*epause
)
1292 struct bnx2x
*bp
= netdev_priv(dev
);
1293 u32 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
1297 DP(NETIF_MSG_LINK
, "ethtool_pauseparam: cmd %d\n"
1298 DP_LEVEL
" autoneg %d rx_pause %d tx_pause %d\n",
1299 epause
->cmd
, epause
->autoneg
, epause
->rx_pause
, epause
->tx_pause
);
1301 bp
->link_params
.req_flow_ctrl
[cfg_idx
] = BNX2X_FLOW_CTRL_AUTO
;
1303 if (epause
->rx_pause
)
1304 bp
->link_params
.req_flow_ctrl
[cfg_idx
] |= BNX2X_FLOW_CTRL_RX
;
1306 if (epause
->tx_pause
)
1307 bp
->link_params
.req_flow_ctrl
[cfg_idx
] |= BNX2X_FLOW_CTRL_TX
;
1309 if (bp
->link_params
.req_flow_ctrl
[cfg_idx
] == BNX2X_FLOW_CTRL_AUTO
)
1310 bp
->link_params
.req_flow_ctrl
[cfg_idx
] = BNX2X_FLOW_CTRL_NONE
;
1312 if (epause
->autoneg
) {
1313 if (!(bp
->port
.supported
[cfg_idx
] & SUPPORTED_Autoneg
)) {
1314 DP(NETIF_MSG_LINK
, "autoneg not supported\n");
1318 if (bp
->link_params
.req_line_speed
[cfg_idx
] == SPEED_AUTO_NEG
) {
1319 bp
->link_params
.req_flow_ctrl
[cfg_idx
] =
1320 BNX2X_FLOW_CTRL_AUTO
;
1325 "req_flow_ctrl 0x%x\n", bp
->link_params
.req_flow_ctrl
[cfg_idx
]);
1327 if (netif_running(dev
)) {
1328 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
1335 static const struct {
1336 char string
[ETH_GSTRING_LEN
];
1337 } bnx2x_tests_str_arr
[BNX2X_NUM_TESTS
] = {
1338 { "register_test (offline)" },
1339 { "memory_test (offline)" },
1340 { "loopback_test (offline)" },
1341 { "nvram_test (online)" },
1342 { "interrupt_test (online)" },
1343 { "link_test (online)" },
1344 { "idle check (online)" }
1348 BNX2X_CHIP_E1_OFST
= 0,
1349 BNX2X_CHIP_E1H_OFST
,
1352 BNX2X_CHIP_E3B0_OFST
,
1356 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1357 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1358 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1359 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1360 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1362 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1363 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1365 static int bnx2x_test_registers(struct bnx2x
*bp
)
1367 int idx
, i
, rc
= -ENODEV
;
1369 int port
= BP_PORT(bp
);
1370 static const struct {
1376 /* 0 */ { BNX2X_CHIP_MASK_ALL
,
1377 BRB1_REG_PAUSE_LOW_THRESHOLD_0
, 4, 0x000003ff },
1378 { BNX2X_CHIP_MASK_ALL
,
1379 DORQ_REG_DB_ADDR0
, 4, 0xffffffff },
1380 { BNX2X_CHIP_MASK_E1X
,
1381 HC_REG_AGG_INT_0
, 4, 0x000003ff },
1382 { BNX2X_CHIP_MASK_ALL
,
1383 PBF_REG_MAC_IF0_ENABLE
, 4, 0x00000001 },
1384 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
| BNX2X_CHIP_MASK_E3
,
1385 PBF_REG_P0_INIT_CRD
, 4, 0x000007ff },
1386 { BNX2X_CHIP_MASK_E3B0
,
1387 PBF_REG_INIT_CRD_Q0
, 4, 0x000007ff },
1388 { BNX2X_CHIP_MASK_ALL
,
1389 PRS_REG_CID_PORT_0
, 4, 0x00ffffff },
1390 { BNX2X_CHIP_MASK_ALL
,
1391 PXP2_REG_PSWRQ_CDU0_L2P
, 4, 0x000fffff },
1392 { BNX2X_CHIP_MASK_ALL
,
1393 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR
, 8, 0x0003ffff },
1394 { BNX2X_CHIP_MASK_ALL
,
1395 PXP2_REG_PSWRQ_TM0_L2P
, 4, 0x000fffff },
1396 /* 10 */ { BNX2X_CHIP_MASK_ALL
,
1397 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR
, 8, 0x0003ffff },
1398 { BNX2X_CHIP_MASK_ALL
,
1399 PXP2_REG_PSWRQ_TSDM0_L2P
, 4, 0x000fffff },
1400 { BNX2X_CHIP_MASK_ALL
,
1401 QM_REG_CONNNUM_0
, 4, 0x000fffff },
1402 { BNX2X_CHIP_MASK_ALL
,
1403 TM_REG_LIN0_MAX_ACTIVE_CID
, 4, 0x0003ffff },
1404 { BNX2X_CHIP_MASK_ALL
,
1405 SRC_REG_KEYRSS0_0
, 40, 0xffffffff },
1406 { BNX2X_CHIP_MASK_ALL
,
1407 SRC_REG_KEYRSS0_7
, 40, 0xffffffff },
1408 { BNX2X_CHIP_MASK_ALL
,
1409 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00
, 4, 0x00000001 },
1410 { BNX2X_CHIP_MASK_ALL
,
1411 XCM_REG_WU_DA_CNT_CMD00
, 4, 0x00000003 },
1412 { BNX2X_CHIP_MASK_ALL
,
1413 XCM_REG_GLB_DEL_ACK_MAX_CNT_0
, 4, 0x000000ff },
1414 { BNX2X_CHIP_MASK_ALL
,
1415 NIG_REG_LLH0_T_BIT
, 4, 0x00000001 },
1416 /* 20 */ { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
1417 NIG_REG_EMAC0_IN_EN
, 4, 0x00000001 },
1418 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
1419 NIG_REG_BMAC0_IN_EN
, 4, 0x00000001 },
1420 { BNX2X_CHIP_MASK_ALL
,
1421 NIG_REG_XCM0_OUT_EN
, 4, 0x00000001 },
1422 { BNX2X_CHIP_MASK_ALL
,
1423 NIG_REG_BRB0_OUT_EN
, 4, 0x00000001 },
1424 { BNX2X_CHIP_MASK_ALL
,
1425 NIG_REG_LLH0_XCM_MASK
, 4, 0x00000007 },
1426 { BNX2X_CHIP_MASK_ALL
,
1427 NIG_REG_LLH0_ACPI_PAT_6_LEN
, 68, 0x000000ff },
1428 { BNX2X_CHIP_MASK_ALL
,
1429 NIG_REG_LLH0_ACPI_PAT_0_CRC
, 68, 0xffffffff },
1430 { BNX2X_CHIP_MASK_ALL
,
1431 NIG_REG_LLH0_DEST_MAC_0_0
, 160, 0xffffffff },
1432 { BNX2X_CHIP_MASK_ALL
,
1433 NIG_REG_LLH0_DEST_IP_0_1
, 160, 0xffffffff },
1434 { BNX2X_CHIP_MASK_ALL
,
1435 NIG_REG_LLH0_IPV4_IPV6_0
, 160, 0x00000001 },
1436 /* 30 */ { BNX2X_CHIP_MASK_ALL
,
1437 NIG_REG_LLH0_DEST_UDP_0
, 160, 0x0000ffff },
1438 { BNX2X_CHIP_MASK_ALL
,
1439 NIG_REG_LLH0_DEST_TCP_0
, 160, 0x0000ffff },
1440 { BNX2X_CHIP_MASK_ALL
,
1441 NIG_REG_LLH0_VLAN_ID_0
, 160, 0x00000fff },
1442 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
1443 NIG_REG_XGXS_SERDES0_MODE_SEL
, 4, 0x00000001 },
1444 { BNX2X_CHIP_MASK_ALL
,
1445 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
, 4, 0x00000001},
1446 { BNX2X_CHIP_MASK_ALL
,
1447 NIG_REG_STATUS_INTERRUPT_PORT0
, 4, 0x07ffffff },
1448 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
1449 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST
, 24, 0x00000001 },
1450 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
1451 NIG_REG_SERDES0_CTRL_PHY_ADDR
, 16, 0x0000001f },
1453 { BNX2X_CHIP_MASK_ALL
, 0xffffffff, 0, 0x00000000 }
1456 if (!netif_running(bp
->dev
))
1460 hw
= BNX2X_CHIP_MASK_E1
;
1461 else if (CHIP_IS_E1H(bp
))
1462 hw
= BNX2X_CHIP_MASK_E1H
;
1463 else if (CHIP_IS_E2(bp
))
1464 hw
= BNX2X_CHIP_MASK_E2
;
1465 else if (CHIP_IS_E3B0(bp
))
1466 hw
= BNX2X_CHIP_MASK_E3B0
;
1468 hw
= BNX2X_CHIP_MASK_E3
;
1470 /* Repeat the test twice:
1471 First by writing 0x00000000, second by writing 0xffffffff */
1472 for (idx
= 0; idx
< 2; idx
++) {
1479 wr_val
= 0xffffffff;
1483 for (i
= 0; reg_tbl
[i
].offset0
!= 0xffffffff; i
++) {
1484 u32 offset
, mask
, save_val
, val
;
1485 if (!(hw
& reg_tbl
[i
].hw
))
1488 offset
= reg_tbl
[i
].offset0
+ port
*reg_tbl
[i
].offset1
;
1489 mask
= reg_tbl
[i
].mask
;
1491 save_val
= REG_RD(bp
, offset
);
1493 REG_WR(bp
, offset
, wr_val
& mask
);
1495 val
= REG_RD(bp
, offset
);
1497 /* Restore the original register's value */
1498 REG_WR(bp
, offset
, save_val
);
1500 /* verify value is as expected */
1501 if ((val
& mask
) != (wr_val
& mask
)) {
1503 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1504 offset
, val
, wr_val
, mask
);
1516 static int bnx2x_test_memory(struct bnx2x
*bp
)
1518 int i
, j
, rc
= -ENODEV
;
1520 static const struct {
1524 { CCM_REG_XX_DESCR_TABLE
, CCM_REG_XX_DESCR_TABLE_SIZE
},
1525 { CFC_REG_ACTIVITY_COUNTER
, CFC_REG_ACTIVITY_COUNTER_SIZE
},
1526 { CFC_REG_LINK_LIST
, CFC_REG_LINK_LIST_SIZE
},
1527 { DMAE_REG_CMD_MEM
, DMAE_REG_CMD_MEM_SIZE
},
1528 { TCM_REG_XX_DESCR_TABLE
, TCM_REG_XX_DESCR_TABLE_SIZE
},
1529 { UCM_REG_XX_DESCR_TABLE
, UCM_REG_XX_DESCR_TABLE_SIZE
},
1530 { XCM_REG_XX_DESCR_TABLE
, XCM_REG_XX_DESCR_TABLE_SIZE
},
1535 static const struct {
1538 u32 hw_mask
[BNX2X_CHIP_MAX_OFST
];
1540 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS
,
1541 {0x3ffc0, 0, 0, 0} },
1542 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS
,
1544 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS
,
1546 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS
,
1547 {0x3ffc0, 0, 0, 0} },
1548 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS
,
1549 {0x3ffc0, 0, 0, 0} },
1550 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS
,
1551 {0x3ffc1, 0, 0, 0} },
1553 { NULL
, 0xffffffff, {0, 0, 0, 0} }
1556 if (!netif_running(bp
->dev
))
1560 index
= BNX2X_CHIP_E1_OFST
;
1561 else if (CHIP_IS_E1H(bp
))
1562 index
= BNX2X_CHIP_E1H_OFST
;
1563 else if (CHIP_IS_E2(bp
))
1564 index
= BNX2X_CHIP_E2_OFST
;
1566 index
= BNX2X_CHIP_E3_OFST
;
1568 /* pre-Check the parity status */
1569 for (i
= 0; prty_tbl
[i
].offset
!= 0xffffffff; i
++) {
1570 val
= REG_RD(bp
, prty_tbl
[i
].offset
);
1571 if (val
& ~(prty_tbl
[i
].hw_mask
[index
])) {
1573 "%s is 0x%x\n", prty_tbl
[i
].name
, val
);
1578 /* Go through all the memories */
1579 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++)
1580 for (j
= 0; j
< mem_tbl
[i
].size
; j
++)
1581 REG_RD(bp
, mem_tbl
[i
].offset
+ j
*4);
1583 /* Check the parity status */
1584 for (i
= 0; prty_tbl
[i
].offset
!= 0xffffffff; i
++) {
1585 val
= REG_RD(bp
, prty_tbl
[i
].offset
);
1586 if (val
& ~(prty_tbl
[i
].hw_mask
[index
])) {
1588 "%s is 0x%x\n", prty_tbl
[i
].name
, val
);
1599 static void bnx2x_wait_for_link(struct bnx2x
*bp
, u8 link_up
, u8 is_serdes
)
1604 while (bnx2x_link_test(bp
, is_serdes
) && cnt
--)
1607 if (cnt
<= 0 && bnx2x_link_test(bp
, is_serdes
))
1608 DP(NETIF_MSG_LINK
, "Timeout waiting for link up\n");
1612 static int bnx2x_run_loopback(struct bnx2x
*bp
, int loopback_mode
)
1614 unsigned int pkt_size
, num_pkts
, i
;
1615 struct sk_buff
*skb
;
1616 unsigned char *packet
;
1617 struct bnx2x_fastpath
*fp_rx
= &bp
->fp
[0];
1618 struct bnx2x_fastpath
*fp_tx
= &bp
->fp
[0];
1619 u16 tx_start_idx
, tx_idx
;
1620 u16 rx_start_idx
, rx_idx
;
1621 u16 pkt_prod
, bd_prod
, rx_comp_cons
;
1622 struct sw_tx_bd
*tx_buf
;
1623 struct eth_tx_start_bd
*tx_start_bd
;
1624 struct eth_tx_parse_bd_e1x
*pbd_e1x
= NULL
;
1625 struct eth_tx_parse_bd_e2
*pbd_e2
= NULL
;
1627 union eth_rx_cqe
*cqe
;
1628 u8 cqe_fp_flags
, cqe_fp_type
;
1629 struct sw_rx_bd
*rx_buf
;
1633 /* check the loopback mode */
1634 switch (loopback_mode
) {
1635 case BNX2X_PHY_LOOPBACK
:
1636 if (bp
->link_params
.loopback_mode
!= LOOPBACK_XGXS
)
1639 case BNX2X_MAC_LOOPBACK
:
1640 bp
->link_params
.loopback_mode
= CHIP_IS_E3(bp
) ?
1641 LOOPBACK_XMAC
: LOOPBACK_BMAC
;
1642 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
1648 /* prepare the loopback packet */
1649 pkt_size
= (((bp
->dev
->mtu
< ETH_MAX_PACKET_SIZE
) ?
1650 bp
->dev
->mtu
: ETH_MAX_PACKET_SIZE
) + ETH_HLEN
);
1651 skb
= netdev_alloc_skb(bp
->dev
, fp_rx
->rx_buf_size
);
1654 goto test_loopback_exit
;
1656 packet
= skb_put(skb
, pkt_size
);
1657 memcpy(packet
, bp
->dev
->dev_addr
, ETH_ALEN
);
1658 memset(packet
+ ETH_ALEN
, 0, ETH_ALEN
);
1659 memset(packet
+ 2*ETH_ALEN
, 0x77, (ETH_HLEN
- 2*ETH_ALEN
));
1660 for (i
= ETH_HLEN
; i
< pkt_size
; i
++)
1661 packet
[i
] = (unsigned char) (i
& 0xff);
1662 mapping
= dma_map_single(&bp
->pdev
->dev
, skb
->data
,
1663 skb_headlen(skb
), DMA_TO_DEVICE
);
1664 if (unlikely(dma_mapping_error(&bp
->pdev
->dev
, mapping
))) {
1667 BNX2X_ERR("Unable to map SKB\n");
1668 goto test_loopback_exit
;
1671 /* send the loopback packet */
1673 tx_start_idx
= le16_to_cpu(*fp_tx
->tx_cons_sb
);
1674 rx_start_idx
= le16_to_cpu(*fp_rx
->rx_cons_sb
);
1676 pkt_prod
= fp_tx
->tx_pkt_prod
++;
1677 tx_buf
= &fp_tx
->tx_buf_ring
[TX_BD(pkt_prod
)];
1678 tx_buf
->first_bd
= fp_tx
->tx_bd_prod
;
1682 bd_prod
= TX_BD(fp_tx
->tx_bd_prod
);
1683 tx_start_bd
= &fp_tx
->tx_desc_ring
[bd_prod
].start_bd
;
1684 tx_start_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
1685 tx_start_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
1686 tx_start_bd
->nbd
= cpu_to_le16(2); /* start + pbd */
1687 tx_start_bd
->nbytes
= cpu_to_le16(skb_headlen(skb
));
1688 tx_start_bd
->vlan_or_ethertype
= cpu_to_le16(pkt_prod
);
1689 tx_start_bd
->bd_flags
.as_bitfield
= ETH_TX_BD_FLAGS_START_BD
;
1690 SET_FLAG(tx_start_bd
->general_data
,
1691 ETH_TX_START_BD_ETH_ADDR_TYPE
,
1693 SET_FLAG(tx_start_bd
->general_data
,
1694 ETH_TX_START_BD_HDR_NBDS
,
1697 /* turn on parsing and get a BD */
1698 bd_prod
= TX_BD(NEXT_TX_IDX(bd_prod
));
1700 pbd_e1x
= &fp_tx
->tx_desc_ring
[bd_prod
].parse_bd_e1x
;
1701 pbd_e2
= &fp_tx
->tx_desc_ring
[bd_prod
].parse_bd_e2
;
1703 memset(pbd_e2
, 0, sizeof(struct eth_tx_parse_bd_e2
));
1704 memset(pbd_e1x
, 0, sizeof(struct eth_tx_parse_bd_e1x
));
1708 fp_tx
->tx_db
.data
.prod
+= 2;
1710 DOORBELL(bp
, fp_tx
->index
, fp_tx
->tx_db
.raw
);
1716 fp_tx
->tx_bd_prod
+= 2; /* start + pbd */
1720 tx_idx
= le16_to_cpu(*fp_tx
->tx_cons_sb
);
1721 if (tx_idx
!= tx_start_idx
+ num_pkts
)
1722 goto test_loopback_exit
;
1724 /* Unlike HC IGU won't generate an interrupt for status block
1725 * updates that have been performed while interrupts were
1728 if (bp
->common
.int_block
== INT_BLOCK_IGU
) {
1729 /* Disable local BHes to prevent a dead-lock situation between
1730 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1731 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1734 bnx2x_tx_int(fp_tx
);
1738 rx_idx
= le16_to_cpu(*fp_rx
->rx_cons_sb
);
1739 if (rx_idx
!= rx_start_idx
+ num_pkts
)
1740 goto test_loopback_exit
;
1742 rx_comp_cons
= le16_to_cpu(fp_rx
->rx_comp_cons
);
1743 cqe
= &fp_rx
->rx_comp_ring
[RCQ_BD(rx_comp_cons
)];
1744 cqe_fp_flags
= cqe
->fast_path_cqe
.type_error_flags
;
1745 cqe_fp_type
= cqe_fp_flags
& ETH_FAST_PATH_RX_CQE_TYPE
;
1746 if (!CQE_TYPE_FAST(cqe_fp_type
) || (cqe_fp_flags
& ETH_RX_ERROR_FALGS
))
1747 goto test_loopback_rx_exit
;
1749 len
= le16_to_cpu(cqe
->fast_path_cqe
.pkt_len
);
1750 if (len
!= pkt_size
)
1751 goto test_loopback_rx_exit
;
1753 rx_buf
= &fp_rx
->rx_buf_ring
[RX_BD(fp_rx
->rx_bd_cons
)];
1754 dma_sync_single_for_device(&bp
->pdev
->dev
,
1755 dma_unmap_addr(rx_buf
, mapping
),
1756 fp_rx
->rx_buf_size
, DMA_FROM_DEVICE
);
1758 skb_reserve(skb
, cqe
->fast_path_cqe
.placement_offset
);
1759 for (i
= ETH_HLEN
; i
< pkt_size
; i
++)
1760 if (*(skb
->data
+ i
) != (unsigned char) (i
& 0xff))
1761 goto test_loopback_rx_exit
;
1765 test_loopback_rx_exit
:
1767 fp_rx
->rx_bd_cons
= NEXT_RX_IDX(fp_rx
->rx_bd_cons
);
1768 fp_rx
->rx_bd_prod
= NEXT_RX_IDX(fp_rx
->rx_bd_prod
);
1769 fp_rx
->rx_comp_cons
= NEXT_RCQ_IDX(fp_rx
->rx_comp_cons
);
1770 fp_rx
->rx_comp_prod
= NEXT_RCQ_IDX(fp_rx
->rx_comp_prod
);
1772 /* Update producers */
1773 bnx2x_update_rx_prod(bp
, fp_rx
, fp_rx
->rx_bd_prod
, fp_rx
->rx_comp_prod
,
1774 fp_rx
->rx_sge_prod
);
1777 bp
->link_params
.loopback_mode
= LOOPBACK_NONE
;
1782 static int bnx2x_test_loopback(struct bnx2x
*bp
)
1789 if (!netif_running(bp
->dev
))
1790 return BNX2X_LOOPBACK_FAILED
;
1792 bnx2x_netif_stop(bp
, 1);
1793 bnx2x_acquire_phy_lock(bp
);
1795 res
= bnx2x_run_loopback(bp
, BNX2X_PHY_LOOPBACK
);
1797 DP(NETIF_MSG_PROBE
, " PHY loopback failed (res %d)\n", res
);
1798 rc
|= BNX2X_PHY_LOOPBACK_FAILED
;
1801 res
= bnx2x_run_loopback(bp
, BNX2X_MAC_LOOPBACK
);
1803 DP(NETIF_MSG_PROBE
, " MAC loopback failed (res %d)\n", res
);
1804 rc
|= BNX2X_MAC_LOOPBACK_FAILED
;
1807 bnx2x_release_phy_lock(bp
);
1808 bnx2x_netif_start(bp
);
1813 #define CRC32_RESIDUAL 0xdebb20e3
1815 static int bnx2x_test_nvram(struct bnx2x
*bp
)
1817 static const struct {
1821 { 0, 0x14 }, /* bootstrap */
1822 { 0x14, 0xec }, /* dir */
1823 { 0x100, 0x350 }, /* manuf_info */
1824 { 0x450, 0xf0 }, /* feature_info */
1825 { 0x640, 0x64 }, /* upgrade_key_info */
1826 { 0x708, 0x70 }, /* manuf_key_info */
1829 __be32 buf
[0x350 / 4];
1830 u8
*data
= (u8
*)buf
;
1837 rc
= bnx2x_nvram_read(bp
, 0, data
, 4);
1839 DP(NETIF_MSG_PROBE
, "magic value read (rc %d)\n", rc
);
1840 goto test_nvram_exit
;
1843 magic
= be32_to_cpu(buf
[0]);
1844 if (magic
!= 0x669955aa) {
1845 DP(NETIF_MSG_PROBE
, "magic value (0x%08x)\n", magic
);
1847 goto test_nvram_exit
;
1850 for (i
= 0; nvram_tbl
[i
].size
; i
++) {
1852 rc
= bnx2x_nvram_read(bp
, nvram_tbl
[i
].offset
, data
,
1856 "nvram_tbl[%d] read data (rc %d)\n", i
, rc
);
1857 goto test_nvram_exit
;
1860 crc
= ether_crc_le(nvram_tbl
[i
].size
, data
);
1861 if (crc
!= CRC32_RESIDUAL
) {
1863 "nvram_tbl[%d] crc value (0x%08x)\n", i
, crc
);
1865 goto test_nvram_exit
;
1873 /* Send an EMPTY ramrod on the first queue */
1874 static int bnx2x_test_intr(struct bnx2x
*bp
)
1876 struct bnx2x_queue_state_params params
= {0};
1878 if (!netif_running(bp
->dev
))
1881 params
.q_obj
= &bp
->fp
->q_obj
;
1882 params
.cmd
= BNX2X_Q_CMD_EMPTY
;
1884 __set_bit(RAMROD_COMP_WAIT
, ¶ms
.ramrod_flags
);
1886 return bnx2x_queue_state_change(bp
, ¶ms
);
1889 static void bnx2x_self_test(struct net_device
*dev
,
1890 struct ethtool_test
*etest
, u64
*buf
)
1892 struct bnx2x
*bp
= netdev_priv(dev
);
1894 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
1895 printk(KERN_ERR
"Handling parity error recovery. Try again later\n");
1896 etest
->flags
|= ETH_TEST_FL_FAILED
;
1900 memset(buf
, 0, sizeof(u64
) * BNX2X_NUM_TESTS
);
1902 if (!netif_running(dev
))
1905 /* offline tests are not supported in MF mode */
1907 etest
->flags
&= ~ETH_TEST_FL_OFFLINE
;
1908 is_serdes
= (bp
->link_vars
.link_status
& LINK_STATUS_SERDES_LINK
) > 0;
1910 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
1911 int port
= BP_PORT(bp
);
1915 /* save current value of input enable for TX port IF */
1916 val
= REG_RD(bp
, NIG_REG_EGRESS_UMP0_IN_EN
+ port
*4);
1917 /* disable input for TX port IF */
1918 REG_WR(bp
, NIG_REG_EGRESS_UMP0_IN_EN
+ port
*4, 0);
1920 link_up
= bp
->link_vars
.link_up
;
1922 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
1923 bnx2x_nic_load(bp
, LOAD_DIAG
);
1924 /* wait until link state is restored */
1925 bnx2x_wait_for_link(bp
, 1, is_serdes
);
1927 if (bnx2x_test_registers(bp
) != 0) {
1929 etest
->flags
|= ETH_TEST_FL_FAILED
;
1931 if (bnx2x_test_memory(bp
) != 0) {
1933 etest
->flags
|= ETH_TEST_FL_FAILED
;
1936 buf
[2] = bnx2x_test_loopback(bp
);
1938 etest
->flags
|= ETH_TEST_FL_FAILED
;
1940 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
1942 /* restore input for TX port IF */
1943 REG_WR(bp
, NIG_REG_EGRESS_UMP0_IN_EN
+ port
*4, val
);
1945 bnx2x_nic_load(bp
, LOAD_NORMAL
);
1946 /* wait until link state is restored */
1947 bnx2x_wait_for_link(bp
, link_up
, is_serdes
);
1949 if (bnx2x_test_nvram(bp
) != 0) {
1951 etest
->flags
|= ETH_TEST_FL_FAILED
;
1953 if (bnx2x_test_intr(bp
) != 0) {
1955 etest
->flags
|= ETH_TEST_FL_FAILED
;
1958 if (bnx2x_link_test(bp
, is_serdes
) != 0) {
1960 etest
->flags
|= ETH_TEST_FL_FAILED
;
1963 #ifdef BNX2X_EXTRA_DEBUG
1964 bnx2x_panic_dump(bp
);
1968 #define IS_PORT_STAT(i) \
1969 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1970 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1971 #define IS_MF_MODE_STAT(bp) \
1972 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1974 /* ethtool statistics are displayed for all regular ethernet queues and the
1975 * fcoe L2 queue if not disabled
1977 static inline int bnx2x_num_stat_queues(struct bnx2x
*bp
)
1979 return BNX2X_NUM_ETH_QUEUES(bp
);
1982 static int bnx2x_get_sset_count(struct net_device
*dev
, int stringset
)
1984 struct bnx2x
*bp
= netdev_priv(dev
);
1987 switch (stringset
) {
1990 num_stats
= bnx2x_num_stat_queues(bp
) *
1992 if (!IS_MF_MODE_STAT(bp
))
1993 num_stats
+= BNX2X_NUM_STATS
;
1995 if (IS_MF_MODE_STAT(bp
)) {
1997 for (i
= 0; i
< BNX2X_NUM_STATS
; i
++)
1998 if (IS_FUNC_STAT(i
))
2001 num_stats
= BNX2X_NUM_STATS
;
2006 return BNX2X_NUM_TESTS
;
2013 static void bnx2x_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
2015 struct bnx2x
*bp
= netdev_priv(dev
);
2017 char queue_name
[MAX_QUEUE_NAME_LEN
+1];
2019 switch (stringset
) {
2023 for_each_eth_queue(bp
, i
) {
2024 memset(queue_name
, 0, sizeof(queue_name
));
2025 sprintf(queue_name
, "%d", i
);
2026 for (j
= 0; j
< BNX2X_NUM_Q_STATS
; j
++)
2027 snprintf(buf
+ (k
+ j
)*ETH_GSTRING_LEN
,
2029 bnx2x_q_stats_arr
[j
].string
,
2031 k
+= BNX2X_NUM_Q_STATS
;
2033 if (IS_MF_MODE_STAT(bp
))
2035 for (j
= 0; j
< BNX2X_NUM_STATS
; j
++)
2036 strcpy(buf
+ (k
+ j
)*ETH_GSTRING_LEN
,
2037 bnx2x_stats_arr
[j
].string
);
2039 for (i
= 0, j
= 0; i
< BNX2X_NUM_STATS
; i
++) {
2040 if (IS_MF_MODE_STAT(bp
) && IS_PORT_STAT(i
))
2042 strcpy(buf
+ j
*ETH_GSTRING_LEN
,
2043 bnx2x_stats_arr
[i
].string
);
2050 memcpy(buf
, bnx2x_tests_str_arr
, sizeof(bnx2x_tests_str_arr
));
2055 static void bnx2x_get_ethtool_stats(struct net_device
*dev
,
2056 struct ethtool_stats
*stats
, u64
*buf
)
2058 struct bnx2x
*bp
= netdev_priv(dev
);
2059 u32
*hw_stats
, *offset
;
2064 for_each_eth_queue(bp
, i
) {
2065 hw_stats
= (u32
*)&bp
->fp
[i
].eth_q_stats
;
2066 for (j
= 0; j
< BNX2X_NUM_Q_STATS
; j
++) {
2067 if (bnx2x_q_stats_arr
[j
].size
== 0) {
2068 /* skip this counter */
2072 offset
= (hw_stats
+
2073 bnx2x_q_stats_arr
[j
].offset
);
2074 if (bnx2x_q_stats_arr
[j
].size
== 4) {
2075 /* 4-byte counter */
2076 buf
[k
+ j
] = (u64
) *offset
;
2079 /* 8-byte counter */
2080 buf
[k
+ j
] = HILO_U64(*offset
, *(offset
+ 1));
2082 k
+= BNX2X_NUM_Q_STATS
;
2084 if (IS_MF_MODE_STAT(bp
))
2086 hw_stats
= (u32
*)&bp
->eth_stats
;
2087 for (j
= 0; j
< BNX2X_NUM_STATS
; j
++) {
2088 if (bnx2x_stats_arr
[j
].size
== 0) {
2089 /* skip this counter */
2093 offset
= (hw_stats
+ bnx2x_stats_arr
[j
].offset
);
2094 if (bnx2x_stats_arr
[j
].size
== 4) {
2095 /* 4-byte counter */
2096 buf
[k
+ j
] = (u64
) *offset
;
2099 /* 8-byte counter */
2100 buf
[k
+ j
] = HILO_U64(*offset
, *(offset
+ 1));
2103 hw_stats
= (u32
*)&bp
->eth_stats
;
2104 for (i
= 0, j
= 0; i
< BNX2X_NUM_STATS
; i
++) {
2105 if (IS_MF_MODE_STAT(bp
) && IS_PORT_STAT(i
))
2107 if (bnx2x_stats_arr
[i
].size
== 0) {
2108 /* skip this counter */
2113 offset
= (hw_stats
+ bnx2x_stats_arr
[i
].offset
);
2114 if (bnx2x_stats_arr
[i
].size
== 4) {
2115 /* 4-byte counter */
2116 buf
[j
] = (u64
) *offset
;
2120 /* 8-byte counter */
2121 buf
[j
] = HILO_U64(*offset
, *(offset
+ 1));
2127 static int bnx2x_set_phys_id(struct net_device
*dev
,
2128 enum ethtool_phys_id_state state
)
2130 struct bnx2x
*bp
= netdev_priv(dev
);
2132 if (!netif_running(dev
))
2139 case ETHTOOL_ID_ACTIVE
:
2140 return 1; /* cycle on/off once per second */
2143 bnx2x_set_led(&bp
->link_params
, &bp
->link_vars
,
2144 LED_MODE_ON
, SPEED_1000
);
2147 case ETHTOOL_ID_OFF
:
2148 bnx2x_set_led(&bp
->link_params
, &bp
->link_vars
,
2149 LED_MODE_FRONT_PANEL_OFF
, 0);
2153 case ETHTOOL_ID_INACTIVE
:
2154 bnx2x_set_led(&bp
->link_params
, &bp
->link_vars
,
2156 bp
->link_vars
.line_speed
);
2162 static int bnx2x_get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
2163 void *rules __always_unused
)
2165 struct bnx2x
*bp
= netdev_priv(dev
);
2167 switch (info
->cmd
) {
2168 case ETHTOOL_GRXRINGS
:
2169 info
->data
= BNX2X_NUM_ETH_QUEUES(bp
);
2177 static int bnx2x_get_rxfh_indir(struct net_device
*dev
,
2178 struct ethtool_rxfh_indir
*indir
)
2180 struct bnx2x
*bp
= netdev_priv(dev
);
2182 min_t(size_t, indir
->size
, T_ETH_INDIRECTION_TABLE_SIZE
);
2183 u8 ind_table
[T_ETH_INDIRECTION_TABLE_SIZE
] = {0};
2186 if (bp
->multi_mode
== ETH_RSS_MODE_DISABLED
)
2189 /* Get the current configuration of the RSS indirection table */
2190 bnx2x_get_rss_ind_table(&bp
->rss_conf_obj
, ind_table
);
2193 * We can't use a memcpy() as an internal storage of an
2194 * indirection table is a u8 array while indir->ring_index
2195 * points to an array of u32.
2197 * Indirection table contains the FW Client IDs, so we need to
2198 * align the returned table to the Client ID of the leading RSS
2201 for (i
= 0; i
< copy_size
; i
++)
2202 indir
->ring_index
[i
] = ind_table
[i
] - bp
->fp
->cl_id
;
2204 indir
->size
= T_ETH_INDIRECTION_TABLE_SIZE
;
2209 static int bnx2x_set_rxfh_indir(struct net_device
*dev
,
2210 const struct ethtool_rxfh_indir
*indir
)
2212 struct bnx2x
*bp
= netdev_priv(dev
);
2214 u8 ind_table
[T_ETH_INDIRECTION_TABLE_SIZE
] = {0};
2215 u32 num_eth_queues
= BNX2X_NUM_ETH_QUEUES(bp
);
2217 if (bp
->multi_mode
== ETH_RSS_MODE_DISABLED
)
2220 /* validate the size */
2221 if (indir
->size
!= T_ETH_INDIRECTION_TABLE_SIZE
)
2224 for (i
= 0; i
< T_ETH_INDIRECTION_TABLE_SIZE
; i
++) {
2225 /* validate the indices */
2226 if (indir
->ring_index
[i
] >= num_eth_queues
)
2229 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2230 * as an internal storage of an indirection table is a u8 array
2231 * while indir->ring_index points to an array of u32.
2233 * Indirection table contains the FW Client IDs, so we need to
2234 * align the received table to the Client ID of the leading RSS
2237 ind_table
[i
] = indir
->ring_index
[i
] + bp
->fp
->cl_id
;
2240 return bnx2x_config_rss_pf(bp
, ind_table
, false);
2243 static const struct ethtool_ops bnx2x_ethtool_ops
= {
2244 .get_settings
= bnx2x_get_settings
,
2245 .set_settings
= bnx2x_set_settings
,
2246 .get_drvinfo
= bnx2x_get_drvinfo
,
2247 .get_regs_len
= bnx2x_get_regs_len
,
2248 .get_regs
= bnx2x_get_regs
,
2249 .get_wol
= bnx2x_get_wol
,
2250 .set_wol
= bnx2x_set_wol
,
2251 .get_msglevel
= bnx2x_get_msglevel
,
2252 .set_msglevel
= bnx2x_set_msglevel
,
2253 .nway_reset
= bnx2x_nway_reset
,
2254 .get_link
= bnx2x_get_link
,
2255 .get_eeprom_len
= bnx2x_get_eeprom_len
,
2256 .get_eeprom
= bnx2x_get_eeprom
,
2257 .set_eeprom
= bnx2x_set_eeprom
,
2258 .get_coalesce
= bnx2x_get_coalesce
,
2259 .set_coalesce
= bnx2x_set_coalesce
,
2260 .get_ringparam
= bnx2x_get_ringparam
,
2261 .set_ringparam
= bnx2x_set_ringparam
,
2262 .get_pauseparam
= bnx2x_get_pauseparam
,
2263 .set_pauseparam
= bnx2x_set_pauseparam
,
2264 .self_test
= bnx2x_self_test
,
2265 .get_sset_count
= bnx2x_get_sset_count
,
2266 .get_strings
= bnx2x_get_strings
,
2267 .set_phys_id
= bnx2x_set_phys_id
,
2268 .get_ethtool_stats
= bnx2x_get_ethtool_stats
,
2269 .get_rxnfc
= bnx2x_get_rxnfc
,
2270 .get_rxfh_indir
= bnx2x_get_rxfh_indir
,
2271 .set_rxfh_indir
= bnx2x_set_rxfh_indir
,
2274 void bnx2x_set_ethtool_ops(struct net_device
*netdev
)
2276 SET_ETHTOOL_OPS(netdev
, &bnx2x_ethtool_ops
);