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bnx2x: use bnx2x_reload_if_running
[deliverable/linux.git] / drivers / net / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #include <linux/ethtool.h>
18 #include <linux/netdevice.h>
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/crc32.h>
22
23
24 #include "bnx2x.h"
25 #include "bnx2x_cmn.h"
26 #include "bnx2x_dump.h"
27 #include "bnx2x_init.h"
28
29 /* Note: in the format strings below %s is replaced by the queue-name which is
30 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
31 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
32 */
33 #define MAX_QUEUE_NAME_LEN 4
34 static const struct {
35 long offset;
36 int size;
37 char string[ETH_GSTRING_LEN];
38 } bnx2x_q_stats_arr[] = {
39 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
40 { Q_STATS_OFFSET32(error_bytes_received_hi),
41 8, "[%s]: rx_error_bytes" },
42 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
43 8, "[%s]: rx_ucast_packets" },
44 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
45 8, "[%s]: rx_mcast_packets" },
46 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
47 8, "[%s]: rx_bcast_packets" },
48 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
49 { Q_STATS_OFFSET32(rx_err_discard_pkt),
50 4, "[%s]: rx_phy_ip_err_discards"},
51 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
52 4, "[%s]: rx_skb_alloc_discard" },
53 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
54
55 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
56 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
57 8, "[%s]: tx_ucast_packets" },
58 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
59 8, "[%s]: tx_mcast_packets" },
60 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
61 8, "[%s]: tx_bcast_packets" }
62 };
63
64 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
65
66 static const struct {
67 long offset;
68 int size;
69 u32 flags;
70 #define STATS_FLAGS_PORT 1
71 #define STATS_FLAGS_FUNC 2
72 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
73 char string[ETH_GSTRING_LEN];
74 } bnx2x_stats_arr[] = {
75 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
76 8, STATS_FLAGS_BOTH, "rx_bytes" },
77 { STATS_OFFSET32(error_bytes_received_hi),
78 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
79 { STATS_OFFSET32(total_unicast_packets_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
81 { STATS_OFFSET32(total_multicast_packets_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
83 { STATS_OFFSET32(total_broadcast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
85 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
86 8, STATS_FLAGS_PORT, "rx_crc_errors" },
87 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
88 8, STATS_FLAGS_PORT, "rx_align_errors" },
89 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
90 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
91 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
92 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
93 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
94 8, STATS_FLAGS_PORT, "rx_fragments" },
95 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
96 8, STATS_FLAGS_PORT, "rx_jabbers" },
97 { STATS_OFFSET32(no_buff_discard_hi),
98 8, STATS_FLAGS_BOTH, "rx_discards" },
99 { STATS_OFFSET32(mac_filter_discard),
100 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
101 { STATS_OFFSET32(xxoverflow_discard),
102 4, STATS_FLAGS_PORT, "rx_fw_discards" },
103 { STATS_OFFSET32(brb_drop_hi),
104 8, STATS_FLAGS_PORT, "rx_brb_discard" },
105 { STATS_OFFSET32(brb_truncate_hi),
106 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
107 { STATS_OFFSET32(pause_frames_received_hi),
108 8, STATS_FLAGS_PORT, "rx_pause_frames" },
109 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
110 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
111 { STATS_OFFSET32(nig_timer_max),
112 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
113 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
114 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
115 { STATS_OFFSET32(rx_skb_alloc_failed),
116 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
117 { STATS_OFFSET32(hw_csum_err),
118 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
119
120 { STATS_OFFSET32(total_bytes_transmitted_hi),
121 8, STATS_FLAGS_BOTH, "tx_bytes" },
122 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
123 8, STATS_FLAGS_PORT, "tx_error_bytes" },
124 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
126 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
127 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
128 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
130 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
131 8, STATS_FLAGS_PORT, "tx_mac_errors" },
132 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
133 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
134 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
135 8, STATS_FLAGS_PORT, "tx_single_collisions" },
136 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
137 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
138 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
139 8, STATS_FLAGS_PORT, "tx_deferred" },
140 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
141 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
143 8, STATS_FLAGS_PORT, "tx_late_collisions" },
144 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_total_collisions" },
146 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
147 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
148 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
149 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
151 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
153 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
154 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
155 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
156 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
157 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
158 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
159 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
160 { STATS_OFFSET32(pause_frames_sent_hi),
161 8, STATS_FLAGS_PORT, "tx_pause_frames" }
162 };
163
164 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
165 static int bnx2x_get_port_type(struct bnx2x *bp)
166 {
167 int port_type;
168 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
169 switch (bp->link_params.phy[phy_idx].media_type) {
170 case ETH_PHY_SFP_FIBER:
171 case ETH_PHY_XFP_FIBER:
172 case ETH_PHY_KR:
173 case ETH_PHY_CX4:
174 port_type = PORT_FIBRE;
175 break;
176 case ETH_PHY_DA_TWINAX:
177 port_type = PORT_DA;
178 break;
179 case ETH_PHY_BASE_T:
180 port_type = PORT_TP;
181 break;
182 case ETH_PHY_NOT_PRESENT:
183 port_type = PORT_NONE;
184 break;
185 case ETH_PHY_UNSPECIFIED:
186 default:
187 port_type = PORT_OTHER;
188 break;
189 }
190 return port_type;
191 }
192
193 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
194 {
195 struct bnx2x *bp = netdev_priv(dev);
196 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
197
198 /* Dual Media boards present all available port types */
199 cmd->supported = bp->port.supported[cfg_idx] |
200 (bp->port.supported[cfg_idx ^ 1] &
201 (SUPPORTED_TP | SUPPORTED_FIBRE));
202 cmd->advertising = bp->port.advertising[cfg_idx];
203
204 if ((bp->state == BNX2X_STATE_OPEN) &&
205 !(bp->flags & MF_FUNC_DIS) &&
206 (bp->link_vars.link_up)) {
207 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
208 cmd->duplex = bp->link_vars.duplex;
209 } else {
210 ethtool_cmd_speed_set(
211 cmd, bp->link_params.req_line_speed[cfg_idx]);
212 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
213 }
214
215 if (IS_MF(bp))
216 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
217
218 cmd->port = bnx2x_get_port_type(bp);
219
220 cmd->phy_address = bp->mdio.prtad;
221 cmd->transceiver = XCVR_INTERNAL;
222
223 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
224 cmd->autoneg = AUTONEG_ENABLE;
225 else
226 cmd->autoneg = AUTONEG_DISABLE;
227
228 cmd->maxtxpkt = 0;
229 cmd->maxrxpkt = 0;
230
231 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
232 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n"
233 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
234 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
235 cmd->cmd, cmd->supported, cmd->advertising,
236 ethtool_cmd_speed(cmd),
237 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
238 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
239
240 return 0;
241 }
242
243 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
244 {
245 struct bnx2x *bp = netdev_priv(dev);
246 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
247 u32 speed;
248
249 if (IS_MF_SD(bp))
250 return 0;
251
252 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
253 " supported 0x%x advertising 0x%x speed %u\n"
254 " duplex %d port %d phy_address %d transceiver %d\n"
255 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
256 cmd->cmd, cmd->supported, cmd->advertising,
257 ethtool_cmd_speed(cmd),
258 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
259 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
260
261 speed = ethtool_cmd_speed(cmd);
262
263 if (IS_MF_SI(bp)) {
264 u32 part;
265 u32 line_speed = bp->link_vars.line_speed;
266
267 /* use 10G if no link detected */
268 if (!line_speed)
269 line_speed = 10000;
270
271 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
272 BNX2X_DEV_INFO("To set speed BC %X or higher "
273 "is required, please upgrade BC\n",
274 REQ_BC_VER_4_SET_MF_BW);
275 return -EINVAL;
276 }
277
278 part = (speed * 100) / line_speed;
279
280 if (line_speed < speed || !part) {
281 BNX2X_DEV_INFO("Speed setting should be in a range "
282 "from 1%% to 100%% "
283 "of actual line speed\n");
284 return -EINVAL;
285 }
286
287 if (bp->state != BNX2X_STATE_OPEN)
288 /* store value for following "load" */
289 bp->pending_max = part;
290 else
291 bnx2x_update_max_mf_config(bp, part);
292
293 return 0;
294 }
295
296 cfg_idx = bnx2x_get_link_cfg_idx(bp);
297 old_multi_phy_config = bp->link_params.multi_phy_config;
298 switch (cmd->port) {
299 case PORT_TP:
300 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
301 break; /* no port change */
302
303 if (!(bp->port.supported[0] & SUPPORTED_TP ||
304 bp->port.supported[1] & SUPPORTED_TP)) {
305 DP(NETIF_MSG_LINK, "Unsupported port type\n");
306 return -EINVAL;
307 }
308 bp->link_params.multi_phy_config &=
309 ~PORT_HW_CFG_PHY_SELECTION_MASK;
310 if (bp->link_params.multi_phy_config &
311 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
312 bp->link_params.multi_phy_config |=
313 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
314 else
315 bp->link_params.multi_phy_config |=
316 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
317 break;
318 case PORT_FIBRE:
319 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
320 break; /* no port change */
321
322 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
323 bp->port.supported[1] & SUPPORTED_FIBRE)) {
324 DP(NETIF_MSG_LINK, "Unsupported port type\n");
325 return -EINVAL;
326 }
327 bp->link_params.multi_phy_config &=
328 ~PORT_HW_CFG_PHY_SELECTION_MASK;
329 if (bp->link_params.multi_phy_config &
330 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
331 bp->link_params.multi_phy_config |=
332 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
333 else
334 bp->link_params.multi_phy_config |=
335 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
336 break;
337 default:
338 DP(NETIF_MSG_LINK, "Unsupported port type\n");
339 return -EINVAL;
340 }
341 /* Save new config in case command complete successuly */
342 new_multi_phy_config = bp->link_params.multi_phy_config;
343 /* Get the new cfg_idx */
344 cfg_idx = bnx2x_get_link_cfg_idx(bp);
345 /* Restore old config in case command failed */
346 bp->link_params.multi_phy_config = old_multi_phy_config;
347 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
348
349 if (cmd->autoneg == AUTONEG_ENABLE) {
350 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
351 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
352 return -EINVAL;
353 }
354
355 /* advertise the requested speed and duplex if supported */
356 cmd->advertising &= bp->port.supported[cfg_idx];
357
358 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
359 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
360 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
361 cmd->advertising);
362
363 } else { /* forced speed */
364 /* advertise the requested speed and duplex if supported */
365 switch (speed) {
366 case SPEED_10:
367 if (cmd->duplex == DUPLEX_FULL) {
368 if (!(bp->port.supported[cfg_idx] &
369 SUPPORTED_10baseT_Full)) {
370 DP(NETIF_MSG_LINK,
371 "10M full not supported\n");
372 return -EINVAL;
373 }
374
375 advertising = (ADVERTISED_10baseT_Full |
376 ADVERTISED_TP);
377 } else {
378 if (!(bp->port.supported[cfg_idx] &
379 SUPPORTED_10baseT_Half)) {
380 DP(NETIF_MSG_LINK,
381 "10M half not supported\n");
382 return -EINVAL;
383 }
384
385 advertising = (ADVERTISED_10baseT_Half |
386 ADVERTISED_TP);
387 }
388 break;
389
390 case SPEED_100:
391 if (cmd->duplex == DUPLEX_FULL) {
392 if (!(bp->port.supported[cfg_idx] &
393 SUPPORTED_100baseT_Full)) {
394 DP(NETIF_MSG_LINK,
395 "100M full not supported\n");
396 return -EINVAL;
397 }
398
399 advertising = (ADVERTISED_100baseT_Full |
400 ADVERTISED_TP);
401 } else {
402 if (!(bp->port.supported[cfg_idx] &
403 SUPPORTED_100baseT_Half)) {
404 DP(NETIF_MSG_LINK,
405 "100M half not supported\n");
406 return -EINVAL;
407 }
408
409 advertising = (ADVERTISED_100baseT_Half |
410 ADVERTISED_TP);
411 }
412 break;
413
414 case SPEED_1000:
415 if (cmd->duplex != DUPLEX_FULL) {
416 DP(NETIF_MSG_LINK, "1G half not supported\n");
417 return -EINVAL;
418 }
419
420 if (!(bp->port.supported[cfg_idx] &
421 SUPPORTED_1000baseT_Full)) {
422 DP(NETIF_MSG_LINK, "1G full not supported\n");
423 return -EINVAL;
424 }
425
426 advertising = (ADVERTISED_1000baseT_Full |
427 ADVERTISED_TP);
428 break;
429
430 case SPEED_2500:
431 if (cmd->duplex != DUPLEX_FULL) {
432 DP(NETIF_MSG_LINK,
433 "2.5G half not supported\n");
434 return -EINVAL;
435 }
436
437 if (!(bp->port.supported[cfg_idx]
438 & SUPPORTED_2500baseX_Full)) {
439 DP(NETIF_MSG_LINK,
440 "2.5G full not supported\n");
441 return -EINVAL;
442 }
443
444 advertising = (ADVERTISED_2500baseX_Full |
445 ADVERTISED_TP);
446 break;
447
448 case SPEED_10000:
449 if (cmd->duplex != DUPLEX_FULL) {
450 DP(NETIF_MSG_LINK, "10G half not supported\n");
451 return -EINVAL;
452 }
453
454 if (!(bp->port.supported[cfg_idx]
455 & SUPPORTED_10000baseT_Full)) {
456 DP(NETIF_MSG_LINK, "10G full not supported\n");
457 return -EINVAL;
458 }
459
460 advertising = (ADVERTISED_10000baseT_Full |
461 ADVERTISED_FIBRE);
462 break;
463
464 default:
465 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
466 return -EINVAL;
467 }
468
469 bp->link_params.req_line_speed[cfg_idx] = speed;
470 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
471 bp->port.advertising[cfg_idx] = advertising;
472 }
473
474 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
475 DP_LEVEL " req_duplex %d advertising 0x%x\n",
476 bp->link_params.req_line_speed[cfg_idx],
477 bp->link_params.req_duplex[cfg_idx],
478 bp->port.advertising[cfg_idx]);
479
480 /* Set new config */
481 bp->link_params.multi_phy_config = new_multi_phy_config;
482 if (netif_running(dev)) {
483 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
484 bnx2x_link_set(bp);
485 }
486
487 return 0;
488 }
489
490 #define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
491 #define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
492 #define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
493
494 static int bnx2x_get_regs_len(struct net_device *dev)
495 {
496 struct bnx2x *bp = netdev_priv(dev);
497 int regdump_len = 0;
498 int i, j, k;
499
500 if (CHIP_IS_E1(bp)) {
501 for (i = 0; i < REGS_COUNT; i++)
502 if (IS_E1_ONLINE(reg_addrs[i].info))
503 regdump_len += reg_addrs[i].size;
504
505 for (i = 0; i < WREGS_COUNT_E1; i++)
506 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
507 regdump_len += wreg_addrs_e1[i].size *
508 (1 + wreg_addrs_e1[i].read_regs_count);
509
510 } else if (CHIP_IS_E1H(bp)) {
511 for (i = 0; i < REGS_COUNT; i++)
512 if (IS_E1H_ONLINE(reg_addrs[i].info))
513 regdump_len += reg_addrs[i].size;
514
515 for (i = 0; i < WREGS_COUNT_E1H; i++)
516 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
517 regdump_len += wreg_addrs_e1h[i].size *
518 (1 + wreg_addrs_e1h[i].read_regs_count);
519 } else if (CHIP_IS_E2(bp)) {
520 for (i = 0; i < REGS_COUNT; i++)
521 if (IS_E2_ONLINE(reg_addrs[i].info))
522 regdump_len += reg_addrs[i].size;
523
524 for (i = 0; i < WREGS_COUNT_E2; i++)
525 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
526 regdump_len += wreg_addrs_e2[i].size *
527 (1 + wreg_addrs_e2[i].read_regs_count);
528
529 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
530 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
531 for (k = 0; k < PAGE_READ_REGS_E2; k++)
532 if (IS_E2_ONLINE(page_read_regs_e2[k].
533 info))
534 regdump_len +=
535 page_read_regs_e2[k].size;
536 }
537 }
538 regdump_len *= 4;
539 regdump_len += sizeof(struct dump_hdr);
540
541 return regdump_len;
542 }
543
544 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
545 {
546 u32 i, j, k, n;
547
548 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
549 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
550 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
551 for (k = 0; k < PAGE_READ_REGS_E2; k++)
552 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
553 for (n = 0; n <
554 page_read_regs_e2[k].size; n++)
555 *p++ = REG_RD(bp,
556 page_read_regs_e2[k].addr + n*4);
557 }
558 }
559 }
560
561 static void bnx2x_get_regs(struct net_device *dev,
562 struct ethtool_regs *regs, void *_p)
563 {
564 u32 *p = _p, i, j;
565 struct bnx2x *bp = netdev_priv(dev);
566 struct dump_hdr dump_hdr = {0};
567
568 regs->version = 0;
569 memset(p, 0, regs->len);
570
571 if (!netif_running(bp->dev))
572 return;
573
574 /* Disable parity attentions as long as following dump may
575 * cause false alarms by reading never written registers. We
576 * will re-enable parity attentions right after the dump.
577 */
578 bnx2x_disable_blocks_parity(bp);
579
580 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
581 dump_hdr.dump_sign = dump_sign_all;
582 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
583 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
584 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
585 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
586
587 if (CHIP_IS_E1(bp))
588 dump_hdr.info = RI_E1_ONLINE;
589 else if (CHIP_IS_E1H(bp))
590 dump_hdr.info = RI_E1H_ONLINE;
591 else if (CHIP_IS_E2(bp))
592 dump_hdr.info = RI_E2_ONLINE |
593 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
594
595 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
596 p += dump_hdr.hdr_size + 1;
597
598 if (CHIP_IS_E1(bp)) {
599 for (i = 0; i < REGS_COUNT; i++)
600 if (IS_E1_ONLINE(reg_addrs[i].info))
601 for (j = 0; j < reg_addrs[i].size; j++)
602 *p++ = REG_RD(bp,
603 reg_addrs[i].addr + j*4);
604
605 } else if (CHIP_IS_E1H(bp)) {
606 for (i = 0; i < REGS_COUNT; i++)
607 if (IS_E1H_ONLINE(reg_addrs[i].info))
608 for (j = 0; j < reg_addrs[i].size; j++)
609 *p++ = REG_RD(bp,
610 reg_addrs[i].addr + j*4);
611
612 } else if (CHIP_IS_E2(bp)) {
613 for (i = 0; i < REGS_COUNT; i++)
614 if (IS_E2_ONLINE(reg_addrs[i].info))
615 for (j = 0; j < reg_addrs[i].size; j++)
616 *p++ = REG_RD(bp,
617 reg_addrs[i].addr + j*4);
618
619 bnx2x_read_pages_regs_e2(bp, p);
620 }
621 /* Re-enable parity attentions */
622 bnx2x_clear_blocks_parity(bp);
623 if (CHIP_PARITY_ENABLED(bp))
624 bnx2x_enable_blocks_parity(bp);
625 }
626
627 #define PHY_FW_VER_LEN 20
628
629 static void bnx2x_get_drvinfo(struct net_device *dev,
630 struct ethtool_drvinfo *info)
631 {
632 struct bnx2x *bp = netdev_priv(dev);
633 u8 phy_fw_ver[PHY_FW_VER_LEN];
634
635 strcpy(info->driver, DRV_MODULE_NAME);
636 strcpy(info->version, DRV_MODULE_VERSION);
637
638 phy_fw_ver[0] = '\0';
639 if (bp->port.pmf) {
640 bnx2x_acquire_phy_lock(bp);
641 bnx2x_get_ext_phy_fw_version(&bp->link_params,
642 (bp->state != BNX2X_STATE_CLOSED),
643 phy_fw_ver, PHY_FW_VER_LEN);
644 bnx2x_release_phy_lock(bp);
645 }
646
647 strncpy(info->fw_version, bp->fw_ver, 32);
648 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
649 "bc %d.%d.%d%s%s",
650 (bp->common.bc_ver & 0xff0000) >> 16,
651 (bp->common.bc_ver & 0xff00) >> 8,
652 (bp->common.bc_ver & 0xff),
653 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
654 strcpy(info->bus_info, pci_name(bp->pdev));
655 info->n_stats = BNX2X_NUM_STATS;
656 info->testinfo_len = BNX2X_NUM_TESTS;
657 info->eedump_len = bp->common.flash_size;
658 info->regdump_len = bnx2x_get_regs_len(dev);
659 }
660
661 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
662 {
663 struct bnx2x *bp = netdev_priv(dev);
664
665 if (bp->flags & NO_WOL_FLAG) {
666 wol->supported = 0;
667 wol->wolopts = 0;
668 } else {
669 wol->supported = WAKE_MAGIC;
670 if (bp->wol)
671 wol->wolopts = WAKE_MAGIC;
672 else
673 wol->wolopts = 0;
674 }
675 memset(&wol->sopass, 0, sizeof(wol->sopass));
676 }
677
678 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
679 {
680 struct bnx2x *bp = netdev_priv(dev);
681
682 if (wol->wolopts & ~WAKE_MAGIC)
683 return -EINVAL;
684
685 if (wol->wolopts & WAKE_MAGIC) {
686 if (bp->flags & NO_WOL_FLAG)
687 return -EINVAL;
688
689 bp->wol = 1;
690 } else
691 bp->wol = 0;
692
693 return 0;
694 }
695
696 static u32 bnx2x_get_msglevel(struct net_device *dev)
697 {
698 struct bnx2x *bp = netdev_priv(dev);
699
700 return bp->msg_enable;
701 }
702
703 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
704 {
705 struct bnx2x *bp = netdev_priv(dev);
706
707 if (capable(CAP_NET_ADMIN)) {
708 /* dump MCP trace */
709 if (level & BNX2X_MSG_MCP)
710 bnx2x_fw_dump_lvl(bp, KERN_INFO);
711 bp->msg_enable = level;
712 }
713 }
714
715 static int bnx2x_nway_reset(struct net_device *dev)
716 {
717 struct bnx2x *bp = netdev_priv(dev);
718
719 if (!bp->port.pmf)
720 return 0;
721
722 if (netif_running(dev)) {
723 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
724 bnx2x_link_set(bp);
725 }
726
727 return 0;
728 }
729
730 static u32 bnx2x_get_link(struct net_device *dev)
731 {
732 struct bnx2x *bp = netdev_priv(dev);
733
734 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
735 return 0;
736
737 return bp->link_vars.link_up;
738 }
739
740 static int bnx2x_get_eeprom_len(struct net_device *dev)
741 {
742 struct bnx2x *bp = netdev_priv(dev);
743
744 return bp->common.flash_size;
745 }
746
747 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
748 {
749 int port = BP_PORT(bp);
750 int count, i;
751 u32 val = 0;
752
753 /* adjust timeout for emulation/FPGA */
754 count = NVRAM_TIMEOUT_COUNT;
755 if (CHIP_REV_IS_SLOW(bp))
756 count *= 100;
757
758 /* request access to nvram interface */
759 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
760 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
761
762 for (i = 0; i < count*10; i++) {
763 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
764 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
765 break;
766
767 udelay(5);
768 }
769
770 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
771 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
772 return -EBUSY;
773 }
774
775 return 0;
776 }
777
778 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
779 {
780 int port = BP_PORT(bp);
781 int count, i;
782 u32 val = 0;
783
784 /* adjust timeout for emulation/FPGA */
785 count = NVRAM_TIMEOUT_COUNT;
786 if (CHIP_REV_IS_SLOW(bp))
787 count *= 100;
788
789 /* relinquish nvram interface */
790 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
791 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
792
793 for (i = 0; i < count*10; i++) {
794 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
795 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
796 break;
797
798 udelay(5);
799 }
800
801 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
802 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
803 return -EBUSY;
804 }
805
806 return 0;
807 }
808
809 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
810 {
811 u32 val;
812
813 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
814
815 /* enable both bits, even on read */
816 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
817 (val | MCPR_NVM_ACCESS_ENABLE_EN |
818 MCPR_NVM_ACCESS_ENABLE_WR_EN));
819 }
820
821 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
822 {
823 u32 val;
824
825 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
826
827 /* disable both bits, even after read */
828 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
829 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
830 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
831 }
832
833 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
834 u32 cmd_flags)
835 {
836 int count, i, rc;
837 u32 val;
838
839 /* build the command word */
840 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
841
842 /* need to clear DONE bit separately */
843 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
844
845 /* address of the NVRAM to read from */
846 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
847 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
848
849 /* issue a read command */
850 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
851
852 /* adjust timeout for emulation/FPGA */
853 count = NVRAM_TIMEOUT_COUNT;
854 if (CHIP_REV_IS_SLOW(bp))
855 count *= 100;
856
857 /* wait for completion */
858 *ret_val = 0;
859 rc = -EBUSY;
860 for (i = 0; i < count; i++) {
861 udelay(5);
862 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
863
864 if (val & MCPR_NVM_COMMAND_DONE) {
865 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
866 /* we read nvram data in cpu order
867 * but ethtool sees it as an array of bytes
868 * converting to big-endian will do the work */
869 *ret_val = cpu_to_be32(val);
870 rc = 0;
871 break;
872 }
873 }
874
875 return rc;
876 }
877
878 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
879 int buf_size)
880 {
881 int rc;
882 u32 cmd_flags;
883 __be32 val;
884
885 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
886 DP(BNX2X_MSG_NVM,
887 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
888 offset, buf_size);
889 return -EINVAL;
890 }
891
892 if (offset + buf_size > bp->common.flash_size) {
893 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
894 " buf_size (0x%x) > flash_size (0x%x)\n",
895 offset, buf_size, bp->common.flash_size);
896 return -EINVAL;
897 }
898
899 /* request access to nvram interface */
900 rc = bnx2x_acquire_nvram_lock(bp);
901 if (rc)
902 return rc;
903
904 /* enable access to nvram interface */
905 bnx2x_enable_nvram_access(bp);
906
907 /* read the first word(s) */
908 cmd_flags = MCPR_NVM_COMMAND_FIRST;
909 while ((buf_size > sizeof(u32)) && (rc == 0)) {
910 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
911 memcpy(ret_buf, &val, 4);
912
913 /* advance to the next dword */
914 offset += sizeof(u32);
915 ret_buf += sizeof(u32);
916 buf_size -= sizeof(u32);
917 cmd_flags = 0;
918 }
919
920 if (rc == 0) {
921 cmd_flags |= MCPR_NVM_COMMAND_LAST;
922 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
923 memcpy(ret_buf, &val, 4);
924 }
925
926 /* disable access to nvram interface */
927 bnx2x_disable_nvram_access(bp);
928 bnx2x_release_nvram_lock(bp);
929
930 return rc;
931 }
932
933 static int bnx2x_get_eeprom(struct net_device *dev,
934 struct ethtool_eeprom *eeprom, u8 *eebuf)
935 {
936 struct bnx2x *bp = netdev_priv(dev);
937 int rc;
938
939 if (!netif_running(dev))
940 return -EAGAIN;
941
942 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
943 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
944 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
945 eeprom->len, eeprom->len);
946
947 /* parameters already validated in ethtool_get_eeprom */
948
949 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
950
951 return rc;
952 }
953
954 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
955 u32 cmd_flags)
956 {
957 int count, i, rc;
958
959 /* build the command word */
960 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
961
962 /* need to clear DONE bit separately */
963 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
964
965 /* write the data */
966 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
967
968 /* address of the NVRAM to write to */
969 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
970 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
971
972 /* issue the write command */
973 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
974
975 /* adjust timeout for emulation/FPGA */
976 count = NVRAM_TIMEOUT_COUNT;
977 if (CHIP_REV_IS_SLOW(bp))
978 count *= 100;
979
980 /* wait for completion */
981 rc = -EBUSY;
982 for (i = 0; i < count; i++) {
983 udelay(5);
984 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
985 if (val & MCPR_NVM_COMMAND_DONE) {
986 rc = 0;
987 break;
988 }
989 }
990
991 return rc;
992 }
993
994 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
995
996 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
997 int buf_size)
998 {
999 int rc;
1000 u32 cmd_flags;
1001 u32 align_offset;
1002 __be32 val;
1003
1004 if (offset + buf_size > bp->common.flash_size) {
1005 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1006 " buf_size (0x%x) > flash_size (0x%x)\n",
1007 offset, buf_size, bp->common.flash_size);
1008 return -EINVAL;
1009 }
1010
1011 /* request access to nvram interface */
1012 rc = bnx2x_acquire_nvram_lock(bp);
1013 if (rc)
1014 return rc;
1015
1016 /* enable access to nvram interface */
1017 bnx2x_enable_nvram_access(bp);
1018
1019 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1020 align_offset = (offset & ~0x03);
1021 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1022
1023 if (rc == 0) {
1024 val &= ~(0xff << BYTE_OFFSET(offset));
1025 val |= (*data_buf << BYTE_OFFSET(offset));
1026
1027 /* nvram data is returned as an array of bytes
1028 * convert it back to cpu order */
1029 val = be32_to_cpu(val);
1030
1031 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1032 cmd_flags);
1033 }
1034
1035 /* disable access to nvram interface */
1036 bnx2x_disable_nvram_access(bp);
1037 bnx2x_release_nvram_lock(bp);
1038
1039 return rc;
1040 }
1041
1042 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1043 int buf_size)
1044 {
1045 int rc;
1046 u32 cmd_flags;
1047 u32 val;
1048 u32 written_so_far;
1049
1050 if (buf_size == 1) /* ethtool */
1051 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1052
1053 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1054 DP(BNX2X_MSG_NVM,
1055 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1056 offset, buf_size);
1057 return -EINVAL;
1058 }
1059
1060 if (offset + buf_size > bp->common.flash_size) {
1061 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1062 " buf_size (0x%x) > flash_size (0x%x)\n",
1063 offset, buf_size, bp->common.flash_size);
1064 return -EINVAL;
1065 }
1066
1067 /* request access to nvram interface */
1068 rc = bnx2x_acquire_nvram_lock(bp);
1069 if (rc)
1070 return rc;
1071
1072 /* enable access to nvram interface */
1073 bnx2x_enable_nvram_access(bp);
1074
1075 written_so_far = 0;
1076 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1077 while ((written_so_far < buf_size) && (rc == 0)) {
1078 if (written_so_far == (buf_size - sizeof(u32)))
1079 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1080 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1081 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1082 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1083 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1084
1085 memcpy(&val, data_buf, 4);
1086
1087 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1088
1089 /* advance to the next dword */
1090 offset += sizeof(u32);
1091 data_buf += sizeof(u32);
1092 written_so_far += sizeof(u32);
1093 cmd_flags = 0;
1094 }
1095
1096 /* disable access to nvram interface */
1097 bnx2x_disable_nvram_access(bp);
1098 bnx2x_release_nvram_lock(bp);
1099
1100 return rc;
1101 }
1102
1103 static int bnx2x_set_eeprom(struct net_device *dev,
1104 struct ethtool_eeprom *eeprom, u8 *eebuf)
1105 {
1106 struct bnx2x *bp = netdev_priv(dev);
1107 int port = BP_PORT(bp);
1108 int rc = 0;
1109 u32 ext_phy_config;
1110 if (!netif_running(dev))
1111 return -EAGAIN;
1112
1113 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1114 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1115 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1116 eeprom->len, eeprom->len);
1117
1118 /* parameters already validated in ethtool_set_eeprom */
1119
1120 /* PHY eeprom can be accessed only by the PMF */
1121 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1122 !bp->port.pmf)
1123 return -EINVAL;
1124
1125 ext_phy_config =
1126 SHMEM_RD(bp,
1127 dev_info.port_hw_config[port].external_phy_config);
1128
1129 if (eeprom->magic == 0x50485950) {
1130 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1131 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1132
1133 bnx2x_acquire_phy_lock(bp);
1134 rc |= bnx2x_link_reset(&bp->link_params,
1135 &bp->link_vars, 0);
1136 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1137 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1138 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1139 MISC_REGISTERS_GPIO_HIGH, port);
1140 bnx2x_release_phy_lock(bp);
1141 bnx2x_link_report(bp);
1142
1143 } else if (eeprom->magic == 0x50485952) {
1144 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1145 if (bp->state == BNX2X_STATE_OPEN) {
1146 bnx2x_acquire_phy_lock(bp);
1147 rc |= bnx2x_link_reset(&bp->link_params,
1148 &bp->link_vars, 1);
1149
1150 rc |= bnx2x_phy_init(&bp->link_params,
1151 &bp->link_vars);
1152 bnx2x_release_phy_lock(bp);
1153 bnx2x_calc_fc_adv(bp);
1154 }
1155 } else if (eeprom->magic == 0x53985943) {
1156 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1157 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1158 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1159
1160 /* DSP Remove Download Mode */
1161 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1162 MISC_REGISTERS_GPIO_LOW, port);
1163
1164 bnx2x_acquire_phy_lock(bp);
1165
1166 bnx2x_sfx7101_sp_sw_reset(bp,
1167 &bp->link_params.phy[EXT_PHY1]);
1168
1169 /* wait 0.5 sec to allow it to run */
1170 msleep(500);
1171 bnx2x_ext_phy_hw_reset(bp, port);
1172 msleep(500);
1173 bnx2x_release_phy_lock(bp);
1174 }
1175 } else
1176 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1177
1178 return rc;
1179 }
1180
1181 static int bnx2x_get_coalesce(struct net_device *dev,
1182 struct ethtool_coalesce *coal)
1183 {
1184 struct bnx2x *bp = netdev_priv(dev);
1185
1186 memset(coal, 0, sizeof(struct ethtool_coalesce));
1187
1188 coal->rx_coalesce_usecs = bp->rx_ticks;
1189 coal->tx_coalesce_usecs = bp->tx_ticks;
1190
1191 return 0;
1192 }
1193
1194 static int bnx2x_set_coalesce(struct net_device *dev,
1195 struct ethtool_coalesce *coal)
1196 {
1197 struct bnx2x *bp = netdev_priv(dev);
1198
1199 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1200 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1201 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1202
1203 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1204 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1205 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1206
1207 if (netif_running(dev))
1208 bnx2x_update_coalesce(bp);
1209
1210 return 0;
1211 }
1212
1213 static void bnx2x_get_ringparam(struct net_device *dev,
1214 struct ethtool_ringparam *ering)
1215 {
1216 struct bnx2x *bp = netdev_priv(dev);
1217
1218 ering->rx_max_pending = MAX_RX_AVAIL;
1219 ering->rx_mini_max_pending = 0;
1220 ering->rx_jumbo_max_pending = 0;
1221
1222 if (bp->rx_ring_size)
1223 ering->rx_pending = bp->rx_ring_size;
1224 else
1225 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1226 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1227 else
1228 ering->rx_pending = MAX_RX_AVAIL;
1229
1230 ering->rx_mini_pending = 0;
1231 ering->rx_jumbo_pending = 0;
1232
1233 ering->tx_max_pending = MAX_TX_AVAIL;
1234 ering->tx_pending = bp->tx_ring_size;
1235 }
1236
1237 static int bnx2x_set_ringparam(struct net_device *dev,
1238 struct ethtool_ringparam *ering)
1239 {
1240 struct bnx2x *bp = netdev_priv(dev);
1241
1242 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1243 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1244 return -EAGAIN;
1245 }
1246
1247 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1248 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1249 MIN_RX_SIZE_TPA)) ||
1250 (ering->tx_pending > MAX_TX_AVAIL) ||
1251 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1252 return -EINVAL;
1253
1254 bp->rx_ring_size = ering->rx_pending;
1255 bp->tx_ring_size = ering->tx_pending;
1256
1257 return bnx2x_reload_if_running(dev);
1258 }
1259
1260 static void bnx2x_get_pauseparam(struct net_device *dev,
1261 struct ethtool_pauseparam *epause)
1262 {
1263 struct bnx2x *bp = netdev_priv(dev);
1264 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1265 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1266 BNX2X_FLOW_CTRL_AUTO);
1267
1268 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1269 BNX2X_FLOW_CTRL_RX);
1270 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1271 BNX2X_FLOW_CTRL_TX);
1272
1273 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1274 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1275 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1276 }
1277
1278 static int bnx2x_set_pauseparam(struct net_device *dev,
1279 struct ethtool_pauseparam *epause)
1280 {
1281 struct bnx2x *bp = netdev_priv(dev);
1282 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1283 if (IS_MF(bp))
1284 return 0;
1285
1286 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1287 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1288 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1289
1290 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1291
1292 if (epause->rx_pause)
1293 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1294
1295 if (epause->tx_pause)
1296 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1297
1298 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1299 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1300
1301 if (epause->autoneg) {
1302 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1303 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1304 return -EINVAL;
1305 }
1306
1307 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1308 bp->link_params.req_flow_ctrl[cfg_idx] =
1309 BNX2X_FLOW_CTRL_AUTO;
1310 }
1311 }
1312
1313 DP(NETIF_MSG_LINK,
1314 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1315
1316 if (netif_running(dev)) {
1317 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1318 bnx2x_link_set(bp);
1319 }
1320
1321 return 0;
1322 }
1323
1324 static const struct {
1325 char string[ETH_GSTRING_LEN];
1326 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1327 { "register_test (offline)" },
1328 { "memory_test (offline)" },
1329 { "loopback_test (offline)" },
1330 { "nvram_test (online)" },
1331 { "interrupt_test (online)" },
1332 { "link_test (online)" },
1333 { "idle check (online)" }
1334 };
1335
1336 static int bnx2x_test_registers(struct bnx2x *bp)
1337 {
1338 int idx, i, rc = -ENODEV;
1339 u32 wr_val = 0;
1340 int port = BP_PORT(bp);
1341 static const struct {
1342 u32 offset0;
1343 u32 offset1;
1344 u32 mask;
1345 } reg_tbl[] = {
1346 /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1347 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1348 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1349 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1350 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1351 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1352 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1353 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1354 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1355 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1356 /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1357 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1358 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1359 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1360 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1361 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1362 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1363 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1364 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1365 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1366 /* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1367 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1368 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1369 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1370 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1371 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1372 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1373 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1374 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1375 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1376 /* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1377 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1378 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1379 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1380 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1381 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1382 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1383
1384 { 0xffffffff, 0, 0x00000000 }
1385 };
1386
1387 if (!netif_running(bp->dev))
1388 return rc;
1389
1390 /* Repeat the test twice:
1391 First by writing 0x00000000, second by writing 0xffffffff */
1392 for (idx = 0; idx < 2; idx++) {
1393
1394 switch (idx) {
1395 case 0:
1396 wr_val = 0;
1397 break;
1398 case 1:
1399 wr_val = 0xffffffff;
1400 break;
1401 }
1402
1403 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1404 u32 offset, mask, save_val, val;
1405 if (CHIP_IS_E2(bp) &&
1406 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1407 continue;
1408
1409 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1410 mask = reg_tbl[i].mask;
1411
1412 save_val = REG_RD(bp, offset);
1413
1414 REG_WR(bp, offset, wr_val & mask);
1415
1416 val = REG_RD(bp, offset);
1417
1418 /* Restore the original register's value */
1419 REG_WR(bp, offset, save_val);
1420
1421 /* verify value is as expected */
1422 if ((val & mask) != (wr_val & mask)) {
1423 DP(NETIF_MSG_PROBE,
1424 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1425 offset, val, wr_val, mask);
1426 goto test_reg_exit;
1427 }
1428 }
1429 }
1430
1431 rc = 0;
1432
1433 test_reg_exit:
1434 return rc;
1435 }
1436
1437 static int bnx2x_test_memory(struct bnx2x *bp)
1438 {
1439 int i, j, rc = -ENODEV;
1440 u32 val;
1441 static const struct {
1442 u32 offset;
1443 int size;
1444 } mem_tbl[] = {
1445 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1446 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1447 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1448 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1449 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1450 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1451 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1452
1453 { 0xffffffff, 0 }
1454 };
1455 static const struct {
1456 char *name;
1457 u32 offset;
1458 u32 e1_mask;
1459 u32 e1h_mask;
1460 u32 e2_mask;
1461 } prty_tbl[] = {
1462 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1463 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1464 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1465 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1466 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1467 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1468
1469 { NULL, 0xffffffff, 0, 0, 0 }
1470 };
1471
1472 if (!netif_running(bp->dev))
1473 return rc;
1474
1475 /* pre-Check the parity status */
1476 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1477 val = REG_RD(bp, prty_tbl[i].offset);
1478 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1479 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1480 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1481 DP(NETIF_MSG_HW,
1482 "%s is 0x%x\n", prty_tbl[i].name, val);
1483 goto test_mem_exit;
1484 }
1485 }
1486
1487 /* Go through all the memories */
1488 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1489 for (j = 0; j < mem_tbl[i].size; j++)
1490 REG_RD(bp, mem_tbl[i].offset + j*4);
1491
1492 /* Check the parity status */
1493 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1494 val = REG_RD(bp, prty_tbl[i].offset);
1495 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1496 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1497 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1498 DP(NETIF_MSG_HW,
1499 "%s is 0x%x\n", prty_tbl[i].name, val);
1500 goto test_mem_exit;
1501 }
1502 }
1503
1504 rc = 0;
1505
1506 test_mem_exit:
1507 return rc;
1508 }
1509
1510 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1511 {
1512 int cnt = 1400;
1513
1514 if (link_up)
1515 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1516 msleep(10);
1517 }
1518
1519 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1520 {
1521 unsigned int pkt_size, num_pkts, i;
1522 struct sk_buff *skb;
1523 unsigned char *packet;
1524 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1525 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1526 u16 tx_start_idx, tx_idx;
1527 u16 rx_start_idx, rx_idx;
1528 u16 pkt_prod, bd_prod;
1529 struct sw_tx_bd *tx_buf;
1530 struct eth_tx_start_bd *tx_start_bd;
1531 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1532 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
1533 dma_addr_t mapping;
1534 union eth_rx_cqe *cqe;
1535 u8 cqe_fp_flags;
1536 struct sw_rx_bd *rx_buf;
1537 u16 len;
1538 int rc = -ENODEV;
1539
1540 /* check the loopback mode */
1541 switch (loopback_mode) {
1542 case BNX2X_PHY_LOOPBACK:
1543 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1544 return -EINVAL;
1545 break;
1546 case BNX2X_MAC_LOOPBACK:
1547 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1548 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1549 break;
1550 default:
1551 return -EINVAL;
1552 }
1553
1554 /* prepare the loopback packet */
1555 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1556 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1557 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1558 if (!skb) {
1559 rc = -ENOMEM;
1560 goto test_loopback_exit;
1561 }
1562 packet = skb_put(skb, pkt_size);
1563 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1564 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1565 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1566 for (i = ETH_HLEN; i < pkt_size; i++)
1567 packet[i] = (unsigned char) (i & 0xff);
1568
1569 /* send the loopback packet */
1570 num_pkts = 0;
1571 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1572 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1573
1574 pkt_prod = fp_tx->tx_pkt_prod++;
1575 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1576 tx_buf->first_bd = fp_tx->tx_bd_prod;
1577 tx_buf->skb = skb;
1578 tx_buf->flags = 0;
1579
1580 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1581 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1582 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1583 skb_headlen(skb), DMA_TO_DEVICE);
1584 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1585 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1586 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1587 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1588 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1589 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1590 SET_FLAG(tx_start_bd->general_data,
1591 ETH_TX_START_BD_ETH_ADDR_TYPE,
1592 UNICAST_ADDRESS);
1593 SET_FLAG(tx_start_bd->general_data,
1594 ETH_TX_START_BD_HDR_NBDS,
1595 1);
1596
1597 /* turn on parsing and get a BD */
1598 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1599
1600 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1601 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1602
1603 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1604 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1605
1606 wmb();
1607
1608 fp_tx->tx_db.data.prod += 2;
1609 barrier();
1610 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1611
1612 mmiowb();
1613
1614 num_pkts++;
1615 fp_tx->tx_bd_prod += 2; /* start + pbd */
1616
1617 udelay(100);
1618
1619 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1620 if (tx_idx != tx_start_idx + num_pkts)
1621 goto test_loopback_exit;
1622
1623 /* Unlike HC IGU won't generate an interrupt for status block
1624 * updates that have been performed while interrupts were
1625 * disabled.
1626 */
1627 if (bp->common.int_block == INT_BLOCK_IGU) {
1628 /* Disable local BHes to prevent a dead-lock situation between
1629 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1630 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1631 */
1632 local_bh_disable();
1633 bnx2x_tx_int(fp_tx);
1634 local_bh_enable();
1635 }
1636
1637 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1638 if (rx_idx != rx_start_idx + num_pkts)
1639 goto test_loopback_exit;
1640
1641 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1642 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1643 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1644 goto test_loopback_rx_exit;
1645
1646 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1647 if (len != pkt_size)
1648 goto test_loopback_rx_exit;
1649
1650 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1651 skb = rx_buf->skb;
1652 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1653 for (i = ETH_HLEN; i < pkt_size; i++)
1654 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1655 goto test_loopback_rx_exit;
1656
1657 rc = 0;
1658
1659 test_loopback_rx_exit:
1660
1661 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1662 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1663 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1664 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1665
1666 /* Update producers */
1667 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1668 fp_rx->rx_sge_prod);
1669
1670 test_loopback_exit:
1671 bp->link_params.loopback_mode = LOOPBACK_NONE;
1672
1673 return rc;
1674 }
1675
1676 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1677 {
1678 int rc = 0, res;
1679
1680 if (BP_NOMCP(bp))
1681 return rc;
1682
1683 if (!netif_running(bp->dev))
1684 return BNX2X_LOOPBACK_FAILED;
1685
1686 bnx2x_netif_stop(bp, 1);
1687 bnx2x_acquire_phy_lock(bp);
1688
1689 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1690 if (res) {
1691 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1692 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1693 }
1694
1695 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1696 if (res) {
1697 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1698 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1699 }
1700
1701 bnx2x_release_phy_lock(bp);
1702 bnx2x_netif_start(bp);
1703
1704 return rc;
1705 }
1706
1707 #define CRC32_RESIDUAL 0xdebb20e3
1708
1709 static int bnx2x_test_nvram(struct bnx2x *bp)
1710 {
1711 static const struct {
1712 int offset;
1713 int size;
1714 } nvram_tbl[] = {
1715 { 0, 0x14 }, /* bootstrap */
1716 { 0x14, 0xec }, /* dir */
1717 { 0x100, 0x350 }, /* manuf_info */
1718 { 0x450, 0xf0 }, /* feature_info */
1719 { 0x640, 0x64 }, /* upgrade_key_info */
1720 { 0x708, 0x70 }, /* manuf_key_info */
1721 { 0, 0 }
1722 };
1723 __be32 buf[0x350 / 4];
1724 u8 *data = (u8 *)buf;
1725 int i, rc;
1726 u32 magic, crc;
1727
1728 if (BP_NOMCP(bp))
1729 return 0;
1730
1731 rc = bnx2x_nvram_read(bp, 0, data, 4);
1732 if (rc) {
1733 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1734 goto test_nvram_exit;
1735 }
1736
1737 magic = be32_to_cpu(buf[0]);
1738 if (magic != 0x669955aa) {
1739 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1740 rc = -ENODEV;
1741 goto test_nvram_exit;
1742 }
1743
1744 for (i = 0; nvram_tbl[i].size; i++) {
1745
1746 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1747 nvram_tbl[i].size);
1748 if (rc) {
1749 DP(NETIF_MSG_PROBE,
1750 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1751 goto test_nvram_exit;
1752 }
1753
1754 crc = ether_crc_le(nvram_tbl[i].size, data);
1755 if (crc != CRC32_RESIDUAL) {
1756 DP(NETIF_MSG_PROBE,
1757 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1758 rc = -ENODEV;
1759 goto test_nvram_exit;
1760 }
1761 }
1762
1763 test_nvram_exit:
1764 return rc;
1765 }
1766
1767 static int bnx2x_test_intr(struct bnx2x *bp)
1768 {
1769 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1770 int i, rc;
1771
1772 if (!netif_running(bp->dev))
1773 return -ENODEV;
1774
1775 config->hdr.length = 0;
1776 if (CHIP_IS_E1(bp))
1777 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1778 else
1779 config->hdr.offset = BP_FUNC(bp);
1780 config->hdr.client_id = bp->fp->cl_id;
1781 config->hdr.reserved1 = 0;
1782
1783 bp->set_mac_pending = 1;
1784 smp_wmb();
1785 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1786 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1787 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1788 if (rc == 0) {
1789 for (i = 0; i < 10; i++) {
1790 if (!bp->set_mac_pending)
1791 break;
1792 smp_rmb();
1793 msleep_interruptible(10);
1794 }
1795 if (i == 10)
1796 rc = -ENODEV;
1797 }
1798
1799 return rc;
1800 }
1801
1802 static void bnx2x_self_test(struct net_device *dev,
1803 struct ethtool_test *etest, u64 *buf)
1804 {
1805 struct bnx2x *bp = netdev_priv(dev);
1806 u8 is_serdes;
1807 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1808 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1809 etest->flags |= ETH_TEST_FL_FAILED;
1810 return;
1811 }
1812
1813 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1814
1815 if (!netif_running(dev))
1816 return;
1817
1818 /* offline tests are not supported in MF mode */
1819 if (IS_MF(bp))
1820 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1821 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1822
1823 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1824 int port = BP_PORT(bp);
1825 u32 val;
1826 u8 link_up;
1827
1828 /* save current value of input enable for TX port IF */
1829 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1830 /* disable input for TX port IF */
1831 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1832
1833 link_up = bp->link_vars.link_up;
1834
1835 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1836 bnx2x_nic_load(bp, LOAD_DIAG);
1837 /* wait until link state is restored */
1838 bnx2x_wait_for_link(bp, link_up, is_serdes);
1839
1840 if (bnx2x_test_registers(bp) != 0) {
1841 buf[0] = 1;
1842 etest->flags |= ETH_TEST_FL_FAILED;
1843 }
1844 if (bnx2x_test_memory(bp) != 0) {
1845 buf[1] = 1;
1846 etest->flags |= ETH_TEST_FL_FAILED;
1847 }
1848
1849 buf[2] = bnx2x_test_loopback(bp, link_up);
1850 if (buf[2] != 0)
1851 etest->flags |= ETH_TEST_FL_FAILED;
1852
1853 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1854
1855 /* restore input for TX port IF */
1856 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1857
1858 bnx2x_nic_load(bp, LOAD_NORMAL);
1859 /* wait until link state is restored */
1860 bnx2x_wait_for_link(bp, link_up, is_serdes);
1861 }
1862 if (bnx2x_test_nvram(bp) != 0) {
1863 buf[3] = 1;
1864 etest->flags |= ETH_TEST_FL_FAILED;
1865 }
1866 if (bnx2x_test_intr(bp) != 0) {
1867 buf[4] = 1;
1868 etest->flags |= ETH_TEST_FL_FAILED;
1869 }
1870
1871 if (bnx2x_link_test(bp, is_serdes) != 0) {
1872 buf[5] = 1;
1873 etest->flags |= ETH_TEST_FL_FAILED;
1874 }
1875
1876 #ifdef BNX2X_EXTRA_DEBUG
1877 bnx2x_panic_dump(bp);
1878 #endif
1879 }
1880
1881 #define IS_PORT_STAT(i) \
1882 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1883 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1884 #define IS_MF_MODE_STAT(bp) \
1885 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1886
1887 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1888 {
1889 struct bnx2x *bp = netdev_priv(dev);
1890 int i, num_stats;
1891
1892 switch (stringset) {
1893 case ETH_SS_STATS:
1894 if (is_multi(bp)) {
1895 num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1896 BNX2X_NUM_Q_STATS;
1897 if (!IS_MF_MODE_STAT(bp))
1898 num_stats += BNX2X_NUM_STATS;
1899 } else {
1900 if (IS_MF_MODE_STAT(bp)) {
1901 num_stats = 0;
1902 for (i = 0; i < BNX2X_NUM_STATS; i++)
1903 if (IS_FUNC_STAT(i))
1904 num_stats++;
1905 } else
1906 num_stats = BNX2X_NUM_STATS;
1907 }
1908 return num_stats;
1909
1910 case ETH_SS_TEST:
1911 return BNX2X_NUM_TESTS;
1912
1913 default:
1914 return -EINVAL;
1915 }
1916 }
1917
1918 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1919 {
1920 struct bnx2x *bp = netdev_priv(dev);
1921 int i, j, k;
1922 char queue_name[MAX_QUEUE_NAME_LEN+1];
1923
1924 switch (stringset) {
1925 case ETH_SS_STATS:
1926 if (is_multi(bp)) {
1927 k = 0;
1928 for_each_napi_queue(bp, i) {
1929 memset(queue_name, 0, sizeof(queue_name));
1930
1931 if (IS_FCOE_IDX(i))
1932 sprintf(queue_name, "fcoe");
1933 else
1934 sprintf(queue_name, "%d", i);
1935
1936 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1937 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
1938 ETH_GSTRING_LEN,
1939 bnx2x_q_stats_arr[j].string,
1940 queue_name);
1941 k += BNX2X_NUM_Q_STATS;
1942 }
1943 if (IS_MF_MODE_STAT(bp))
1944 break;
1945 for (j = 0; j < BNX2X_NUM_STATS; j++)
1946 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1947 bnx2x_stats_arr[j].string);
1948 } else {
1949 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1950 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1951 continue;
1952 strcpy(buf + j*ETH_GSTRING_LEN,
1953 bnx2x_stats_arr[i].string);
1954 j++;
1955 }
1956 }
1957 break;
1958
1959 case ETH_SS_TEST:
1960 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1961 break;
1962 }
1963 }
1964
1965 static void bnx2x_get_ethtool_stats(struct net_device *dev,
1966 struct ethtool_stats *stats, u64 *buf)
1967 {
1968 struct bnx2x *bp = netdev_priv(dev);
1969 u32 *hw_stats, *offset;
1970 int i, j, k;
1971
1972 if (is_multi(bp)) {
1973 k = 0;
1974 for_each_napi_queue(bp, i) {
1975 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1976 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1977 if (bnx2x_q_stats_arr[j].size == 0) {
1978 /* skip this counter */
1979 buf[k + j] = 0;
1980 continue;
1981 }
1982 offset = (hw_stats +
1983 bnx2x_q_stats_arr[j].offset);
1984 if (bnx2x_q_stats_arr[j].size == 4) {
1985 /* 4-byte counter */
1986 buf[k + j] = (u64) *offset;
1987 continue;
1988 }
1989 /* 8-byte counter */
1990 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1991 }
1992 k += BNX2X_NUM_Q_STATS;
1993 }
1994 if (IS_MF_MODE_STAT(bp))
1995 return;
1996 hw_stats = (u32 *)&bp->eth_stats;
1997 for (j = 0; j < BNX2X_NUM_STATS; j++) {
1998 if (bnx2x_stats_arr[j].size == 0) {
1999 /* skip this counter */
2000 buf[k + j] = 0;
2001 continue;
2002 }
2003 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2004 if (bnx2x_stats_arr[j].size == 4) {
2005 /* 4-byte counter */
2006 buf[k + j] = (u64) *offset;
2007 continue;
2008 }
2009 /* 8-byte counter */
2010 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2011 }
2012 } else {
2013 hw_stats = (u32 *)&bp->eth_stats;
2014 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2015 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2016 continue;
2017 if (bnx2x_stats_arr[i].size == 0) {
2018 /* skip this counter */
2019 buf[j] = 0;
2020 j++;
2021 continue;
2022 }
2023 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2024 if (bnx2x_stats_arr[i].size == 4) {
2025 /* 4-byte counter */
2026 buf[j] = (u64) *offset;
2027 j++;
2028 continue;
2029 }
2030 /* 8-byte counter */
2031 buf[j] = HILO_U64(*offset, *(offset + 1));
2032 j++;
2033 }
2034 }
2035 }
2036
2037 static int bnx2x_set_phys_id(struct net_device *dev,
2038 enum ethtool_phys_id_state state)
2039 {
2040 struct bnx2x *bp = netdev_priv(dev);
2041
2042 if (!netif_running(dev))
2043 return -EAGAIN;
2044
2045 if (!bp->port.pmf)
2046 return -EOPNOTSUPP;
2047
2048 switch (state) {
2049 case ETHTOOL_ID_ACTIVE:
2050 return 1; /* cycle on/off once per second */
2051
2052 case ETHTOOL_ID_ON:
2053 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2054 LED_MODE_ON, SPEED_1000);
2055 break;
2056
2057 case ETHTOOL_ID_OFF:
2058 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2059 LED_MODE_FRONT_PANEL_OFF, 0);
2060
2061 break;
2062
2063 case ETHTOOL_ID_INACTIVE:
2064 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2065 LED_MODE_OPER,
2066 bp->link_vars.line_speed);
2067 }
2068
2069 return 0;
2070 }
2071
2072 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2073 void *rules __always_unused)
2074 {
2075 struct bnx2x *bp = netdev_priv(dev);
2076
2077 switch (info->cmd) {
2078 case ETHTOOL_GRXRINGS:
2079 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2080 return 0;
2081
2082 default:
2083 return -EOPNOTSUPP;
2084 }
2085 }
2086
2087 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2088 struct ethtool_rxfh_indir *indir)
2089 {
2090 struct bnx2x *bp = netdev_priv(dev);
2091 size_t copy_size =
2092 min_t(size_t, indir->size, TSTORM_INDIRECTION_TABLE_SIZE);
2093
2094 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2095 return -EOPNOTSUPP;
2096
2097 indir->size = TSTORM_INDIRECTION_TABLE_SIZE;
2098 memcpy(indir->ring_index, bp->rx_indir_table,
2099 copy_size * sizeof(bp->rx_indir_table[0]));
2100 return 0;
2101 }
2102
2103 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2104 const struct ethtool_rxfh_indir *indir)
2105 {
2106 struct bnx2x *bp = netdev_priv(dev);
2107 size_t i;
2108
2109 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2110 return -EOPNOTSUPP;
2111
2112 /* Validate size and indices */
2113 if (indir->size != TSTORM_INDIRECTION_TABLE_SIZE)
2114 return -EINVAL;
2115 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
2116 if (indir->ring_index[i] >= BNX2X_NUM_ETH_QUEUES(bp))
2117 return -EINVAL;
2118
2119 memcpy(bp->rx_indir_table, indir->ring_index,
2120 indir->size * sizeof(bp->rx_indir_table[0]));
2121 bnx2x_push_indir_table(bp);
2122 return 0;
2123 }
2124
2125 static const struct ethtool_ops bnx2x_ethtool_ops = {
2126 .get_settings = bnx2x_get_settings,
2127 .set_settings = bnx2x_set_settings,
2128 .get_drvinfo = bnx2x_get_drvinfo,
2129 .get_regs_len = bnx2x_get_regs_len,
2130 .get_regs = bnx2x_get_regs,
2131 .get_wol = bnx2x_get_wol,
2132 .set_wol = bnx2x_set_wol,
2133 .get_msglevel = bnx2x_get_msglevel,
2134 .set_msglevel = bnx2x_set_msglevel,
2135 .nway_reset = bnx2x_nway_reset,
2136 .get_link = bnx2x_get_link,
2137 .get_eeprom_len = bnx2x_get_eeprom_len,
2138 .get_eeprom = bnx2x_get_eeprom,
2139 .set_eeprom = bnx2x_set_eeprom,
2140 .get_coalesce = bnx2x_get_coalesce,
2141 .set_coalesce = bnx2x_set_coalesce,
2142 .get_ringparam = bnx2x_get_ringparam,
2143 .set_ringparam = bnx2x_set_ringparam,
2144 .get_pauseparam = bnx2x_get_pauseparam,
2145 .set_pauseparam = bnx2x_set_pauseparam,
2146 .self_test = bnx2x_self_test,
2147 .get_sset_count = bnx2x_get_sset_count,
2148 .get_strings = bnx2x_get_strings,
2149 .set_phys_id = bnx2x_set_phys_id,
2150 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2151 .get_rxnfc = bnx2x_get_rxnfc,
2152 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2153 .set_rxfh_indir = bnx2x_set_rxfh_indir,
2154 };
2155
2156 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2157 {
2158 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2159 }
Linux kernel - Deliverables
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