1 /* bnx2x_fw_defs.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
11 #define CSTORM_ASSERT_LIST_INDEX_OFFSET \
12 (IS_E1H_OFFSET? 0x7000 : 0x1000)
13 #define CSTORM_ASSERT_LIST_OFFSET(idx) \
14 (IS_E1H_OFFSET? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
15 #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
16 (IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \
17 * 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \
19 #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
20 (IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \
21 * 0x100)) : (0x1900 + (function * 0x40)))
22 #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
23 (IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \
24 * 0x100)) : (0x1908 + (function * 0x40)))
25 #define CSTORM_FUNCTION_MODE_OFFSET \
26 (IS_E1H_OFFSET? 0x11e8 : 0xffffffff)
27 #define CSTORM_HC_BTR_OFFSET(port) \
28 (IS_E1H_OFFSET? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
29 #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
30 (IS_E1H_OFFSET? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
31 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
33 #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
34 (IS_E1H_OFFSET? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
35 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
37 #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
38 (IS_E1H_OFFSET? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
39 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
40 #define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
41 (IS_E1H_OFFSET? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
42 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
43 #define CSTORM_STATS_FLAGS_OFFSET(function) \
44 (IS_E1H_OFFSET? (0x1108 + (function * 0x8)) : (0x5108 + \
46 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
47 (IS_E1H_OFFSET? (0x31c0 + (function * 0x20)) : 0xffffffff)
48 #define TSTORM_ASSERT_LIST_INDEX_OFFSET \
49 (IS_E1H_OFFSET? 0xa000 : 0x1000)
50 #define TSTORM_ASSERT_LIST_OFFSET(idx) \
51 (IS_E1H_OFFSET? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
52 #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
53 (IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \
54 (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
55 #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
56 (IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \
57 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
59 #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
60 (IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \
61 * 0xa0)) : (0x1400 + (function * 0x28)))
62 #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
63 (IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \
64 * 0xa0)) : (0x1408 + (function * 0x28)))
65 #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
66 (IS_E1H_OFFSET? (0x2b80 + (function * 0x8)) : (0x4b68 + \
68 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
69 (IS_E1H_OFFSET? (0x3000 + (function * 0x38)) : (0x1500 + \
71 #define TSTORM_FUNCTION_MODE_OFFSET \
72 (IS_E1H_OFFSET? 0x1ad0 : 0xffffffff)
73 #define TSTORM_HC_BTR_OFFSET(port) \
74 (IS_E1H_OFFSET? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
75 #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
76 (IS_E1H_OFFSET? (0x12c8 + (function * 0x80)) : (0x22c8 + \
78 #define TSTORM_INDIRECTION_TABLE_SIZE 0x80
79 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
80 (IS_E1H_OFFSET? (0x3008 + (function * 0x38)) : (0x1508 + \
82 #define TSTORM_RX_PRODS_OFFSET(port, client_id) \
83 (IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \
84 (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
85 #define TSTORM_STATS_FLAGS_OFFSET(function) \
86 (IS_E1H_OFFSET? (0x2c00 + (function * 0x8)) : (0x4b88 + \
88 #define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET? 0x3b30 : 0x1c20)
89 #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET? 0xa040 : 0x2c10)
90 #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET? 0x2440 : 0x1200)
91 #define USTORM_ASSERT_LIST_INDEX_OFFSET \
92 (IS_E1H_OFFSET? 0x8000 : 0x1000)
93 #define USTORM_ASSERT_LIST_OFFSET(idx) \
94 (IS_E1H_OFFSET? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
95 #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
96 (IS_E1H_OFFSET? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
97 (0x5450 + (port * 0x1c8) + (clientId * 0x18)))
98 #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
99 (IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \
100 * 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \
102 #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
103 (IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \
104 * 0xa0)) : (0x1900 + (function * 0x28)))
105 #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
106 (IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \
107 * 0xa0)) : (0x1908 + (function * 0x28)))
108 #define USTORM_FUNCTION_MODE_OFFSET \
109 (IS_E1H_OFFSET? 0x2448 : 0xffffffff)
110 #define USTORM_HC_BTR_OFFSET(port) \
111 (IS_E1H_OFFSET? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
112 #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
113 (IS_E1H_OFFSET? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
114 (0x5448 + (port * 0x1c8) + (clientId * 0x18)))
115 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
116 (IS_E1H_OFFSET? (0x2408 + (function * 0x8)) : (0x5408 + \
118 #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
119 (IS_E1H_OFFSET? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
120 (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
122 #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
123 (IS_E1H_OFFSET? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
124 (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
126 #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
127 (IS_E1H_OFFSET? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
128 (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
129 #define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
130 (IS_E1H_OFFSET? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
131 (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
132 #define XSTORM_ASSERT_LIST_INDEX_OFFSET \
133 (IS_E1H_OFFSET? 0x9000 : 0x1000)
134 #define XSTORM_ASSERT_LIST_OFFSET(idx) \
135 (IS_E1H_OFFSET? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
136 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
137 (IS_E1H_OFFSET? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
138 #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
139 (IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \
140 * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
142 #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
143 (IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \
144 * 0xa0)) : (0x1400 + (function * 0x28)))
145 #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
146 (IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \
147 * 0xa0)) : (0x1408 + (function * 0x28)))
148 #define XSTORM_E1HOV_OFFSET(function) \
149 (IS_E1H_OFFSET? (0x2ab8 + (function * 0x2)) : 0xffffffff)
150 #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
151 (IS_E1H_OFFSET? (0x2418 + (function * 0x8)) : (0x3b70 + \
153 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
154 (IS_E1H_OFFSET? (0x2568 + (function * 0x70)) : (0x3c60 + \
156 #define XSTORM_FUNCTION_MODE_OFFSET \
157 (IS_E1H_OFFSET? 0x2ac8 : 0xffffffff)
158 #define XSTORM_HC_BTR_OFFSET(port) \
159 (IS_E1H_OFFSET? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
160 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
161 (IS_E1H_OFFSET? (0x2528 + (function * 0x70)) : (0x3c20 + \
163 #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
164 (IS_E1H_OFFSET? (0x2000 + (function * 0x10)) : (0x3328 + \
166 #define XSTORM_SPQ_PROD_OFFSET(function) \
167 (IS_E1H_OFFSET? (0x2008 + (function * 0x10)) : (0x3330 + \
169 #define XSTORM_STATS_FLAGS_OFFSET(function) \
170 (IS_E1H_OFFSET? (0x23d8 + (function * 0x8)) : (0x3b60 + \
172 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
175 * This file defines HSI constatnts for the ETH flow
177 #ifdef _EVEREST_MICROCODE
178 #include "microcode_constants.h"
179 #include "eth_rx_bd.h"
180 #include "eth_tx_bd.h"
181 #include "eth_rx_cqe.h"
182 #include "eth_rx_sge.h"
183 #include "eth_rx_cqe_next_page.h"
187 #define DEFAULT_HASH_TYPE 0
188 #define IPV4_HASH_TYPE 1
189 #define TCP_IPV4_HASH_TYPE 2
190 #define IPV6_HASH_TYPE 3
191 #define TCP_IPV6_HASH_TYPE 4
193 /* Ethernet Ring parmaters */
194 #define X_ETH_LOCAL_RING_SIZE 13
195 #define FIRST_BD_IN_PKT 0
196 #define PARSE_BD_INDEX 1
197 #define NUM_OF_ETH_BDS_IN_PAGE \
198 ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
202 #define U_ETH_LOCAL_BD_RING_SIZE (16)
203 #define U_ETH_LOCAL_SGE_RING_SIZE (12)
204 #define U_ETH_SGL_SIZE (8)
207 #define U_ETH_BDS_PER_PAGE_MASK \
208 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
209 #define U_ETH_CQE_PER_PAGE_MASK \
210 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
211 #define U_ETH_SGES_PER_PAGE_MASK \
212 ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1)
214 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
215 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
218 #define TU_ETH_CQES_PER_PAGE \
219 (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
220 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
221 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
223 #define U_ETH_UNDEFINED_Q 0xFF
225 /* values of command IDs in the ramrod message */
226 #define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
227 #define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
228 #define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
229 #define RAMROD_CMD_ID_ETH_UPDATE (100)
230 #define RAMROD_CMD_ID_ETH_HALT (105)
231 #define RAMROD_CMD_ID_ETH_SET_MAC (110)
232 #define RAMROD_CMD_ID_ETH_CFC_DEL (115)
233 #define RAMROD_CMD_ID_ETH_PORT_DEL (120)
234 #define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
237 /* command values for set mac command */
238 #define T_ETH_MAC_COMMAND_SET 0
239 #define T_ETH_MAC_COMMAND_INVALIDATE 1
241 #define T_ETH_INDIRECTION_TABLE_SIZE 128
243 /*The CRC32 seed, that is used for the hash(reduction) multicast address */
244 #define T_ETH_CRC32_HASH_SEED 0x00000000
246 /* Maximal L2 clients supported */
247 #define ETH_MAX_RX_CLIENTS_E1 19
248 #define ETH_MAX_RX_CLIENTS_E1H 25
250 /* Maximal aggregation queues supported */
251 #define ETH_MAX_AGGREGATION_QUEUES_E1 (32)
252 #define ETH_MAX_AGGREGATION_QUEUES_E1H (64)
256 * This file defines HSI constatnts common to all microcode flows
259 /* Connection types */
260 #define ETH_CONNECTION_TYPE 0
261 #define TOE_CONNECTION_TYPE 1
262 #define RDMA_CONNECTION_TYPE 2
263 #define ISCSI_CONNECTION_TYPE 3
264 #define FCOE_CONNECTION_TYPE 4
265 #define RESERVED_CONNECTION_TYPE_0 5
266 #define RESERVED_CONNECTION_TYPE_1 6
267 #define RESERVED_CONNECTION_TYPE_2 7
270 #define PROTOCOL_STATE_BIT_OFFSET 6
272 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
273 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
274 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
275 #define ISCSI_STATE \
276 (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
277 #define FCOE_STATE (FCOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
279 /* microcode fixed page page size 4K (chains and ring segments) */
280 #define MC_PAGE_SIZE (4096)
283 /* Host coalescing constants */
286 #define HC_USTORM_DEF_SB_NUM_INDICES 4
287 #define HC_CSTORM_DEF_SB_NUM_INDICES 8
288 #define HC_XSTORM_DEF_SB_NUM_INDICES 4
289 #define HC_TSTORM_DEF_SB_NUM_INDICES 4
290 #define HC_USTORM_SB_NUM_INDICES 4
291 #define HC_CSTORM_SB_NUM_INDICES 4
293 /* index values - which counterto update */
295 #define HC_INDEX_U_TOE_RX_CQ_CONS 0
296 #define HC_INDEX_U_ETH_RX_CQ_CONS 1
297 #define HC_INDEX_U_ETH_RX_BD_CONS 2
298 #define HC_INDEX_U_FCOE_EQ_CONS 3
300 #define HC_INDEX_C_TOE_TX_CQ_CONS 0
301 #define HC_INDEX_C_ETH_TX_CQ_CONS 1
302 #define HC_INDEX_C_ISCSI_EQ_CONS 2
304 #define HC_INDEX_DEF_X_SPQ_CONS 0
306 #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
307 #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
308 #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
309 #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
310 #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
311 #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
313 #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
314 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
315 #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2
316 #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3
319 /* used by the driver to get the SB offset */
324 #define ATTENTION_ID 4
326 /* max number of slow path commands per port */
327 #define MAX_RAMRODS_PER_PORT (8)
329 /* values for RX ETH CQE type field */
330 #define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
331 #define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
334 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
335 #define EMULATION_FREQUENCY_FACTOR (1600)
336 #define FPGA_FREQUENCY_FACTOR (100)
338 #define TIMERS_TICK_SIZE_CHIP (1e-3)
339 #define TIMERS_TICK_SIZE_EMUL \
340 ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
341 #define TIMERS_TICK_SIZE_FPGA \
342 ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
344 #define TSEMI_CLK1_RESUL_CHIP (1e-3)
345 #define TSEMI_CLK1_RESUL_EMUL \
346 ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
347 #define TSEMI_CLK1_RESUL_FPGA \
348 ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
350 #define USEMI_CLK1_RESUL_CHIP \
351 (TIMERS_TICK_SIZE_CHIP)
352 #define USEMI_CLK1_RESUL_EMUL \
353 (TIMERS_TICK_SIZE_EMUL)
354 #define USEMI_CLK1_RESUL_FPGA \
355 (TIMERS_TICK_SIZE_FPGA)
357 #define XSEMI_CLK1_RESUL_CHIP (1e-3)
358 #define XSEMI_CLK1_RESUL_EMUL \
359 ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
360 #define XSEMI_CLK1_RESUL_FPGA \
361 ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
363 #define XSEMI_CLK2_RESUL_CHIP (1e-6)
364 #define XSEMI_CLK2_RESUL_EMUL \
365 ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
366 #define XSEMI_CLK2_RESUL_FPGA \
367 ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
369 #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
370 #define SDM_TIMER_TICK_RESUL_EMUL \
371 ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
372 #define SDM_TIMER_TICK_RESUL_FPGA \
373 ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
376 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
377 #define XSTORM_IP_ID_ROLL_HALF 0x8000
378 #define XSTORM_IP_ID_ROLL_ALL 0
380 #define FW_LOG_LIST_SIZE (50)
382 #define NUM_OF_PROTOCOLS 4
383 #define MAX_COS_NUMBER 16
384 #define MAX_T_STAT_COUNTER_ID 18
385 #define MAX_X_STAT_COUNTER_ID 18
387 #define UNKNOWN_ADDRESS 0
388 #define UNICAST_ADDRESS 1
389 #define MULTICAST_ADDRESS 2
390 #define BROADCAST_ADDRESS 3
392 #define SINGLE_FUNCTION 0
393 #define MULTI_FUNCTION 1
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