2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
41 #define DRV_NAME "flexcan"
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95 /* FLEXCAN control register 2 (CTRL2) bits */
96 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
97 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
98 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
99 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
100 #define FLEXCAN_CTRL2_MRP BIT(18)
101 #define FLEXCAN_CTRL2_RRS BIT(17)
102 #define FLEXCAN_CTRL2_EACEN BIT(16)
104 /* FLEXCAN memory error control register (MECR) bits */
105 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
106 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
107 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
108 #define FLEXCAN_MECR_CEI_MSK BIT(16)
109 #define FLEXCAN_MECR_HAERRIE BIT(15)
110 #define FLEXCAN_MECR_FAERRIE BIT(14)
111 #define FLEXCAN_MECR_EXTERRIE BIT(13)
112 #define FLEXCAN_MECR_RERRDIS BIT(9)
113 #define FLEXCAN_MECR_ECCDIS BIT(8)
114 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
116 /* FLEXCAN error and status register (ESR) bits */
117 #define FLEXCAN_ESR_TWRN_INT BIT(17)
118 #define FLEXCAN_ESR_RWRN_INT BIT(16)
119 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
120 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
121 #define FLEXCAN_ESR_ACK_ERR BIT(13)
122 #define FLEXCAN_ESR_CRC_ERR BIT(12)
123 #define FLEXCAN_ESR_FRM_ERR BIT(11)
124 #define FLEXCAN_ESR_STF_ERR BIT(10)
125 #define FLEXCAN_ESR_TX_WRN BIT(9)
126 #define FLEXCAN_ESR_RX_WRN BIT(8)
127 #define FLEXCAN_ESR_IDLE BIT(7)
128 #define FLEXCAN_ESR_TXRX BIT(6)
129 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
130 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
133 #define FLEXCAN_ESR_BOFF_INT BIT(2)
134 #define FLEXCAN_ESR_ERR_INT BIT(1)
135 #define FLEXCAN_ESR_WAK_INT BIT(0)
136 #define FLEXCAN_ESR_ERR_BUS \
137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
140 #define FLEXCAN_ESR_ERR_STATE \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
142 #define FLEXCAN_ESR_ERR_ALL \
143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
144 #define FLEXCAN_ESR_ALL_INT \
145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
148 /* FLEXCAN interrupt flag register (IFLAG) bits */
149 /* Errata ERR005829 step7: Reserve first valid MB */
150 #define FLEXCAN_TX_BUF_RESERVED 8
151 #define FLEXCAN_TX_BUF_ID 9
152 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
153 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
154 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
155 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
156 #define FLEXCAN_IFLAG_DEFAULT \
157 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
158 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
162 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
163 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
164 #define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24)
165 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
167 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
168 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
169 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
170 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
172 #define FLEXCAN_MB_CNT_SRR BIT(22)
173 #define FLEXCAN_MB_CNT_IDE BIT(21)
174 #define FLEXCAN_MB_CNT_RTR BIT(20)
175 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
176 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
178 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
180 #define FLEXCAN_TIMEOUT_US (50)
183 * FLEXCAN hardware feature flags
185 * Below is some version info we got:
186 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
187 * Filter? connected? detection ception in MB
188 * MX25 FlexCAN2 03.00.00.00 no no no no
189 * MX28 FlexCAN2 03.00.04.00 yes yes no no
190 * MX35 FlexCAN2 03.00.00.00 no no no no
191 * MX53 FlexCAN2 03.00.00.00 yes no no no
192 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
193 * VF610 FlexCAN3 ? no yes yes yes?
195 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
197 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
198 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
199 #define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
201 /* Structure of the message buffer */
208 /* Structure of the hardware registers */
209 struct flexcan_regs
{
212 u32 timer
; /* 0x08 */
213 u32 _reserved1
; /* 0x0c */
214 u32 rxgmask
; /* 0x10 */
215 u32 rx14mask
; /* 0x14 */
216 u32 rx15mask
; /* 0x18 */
219 u32 imask2
; /* 0x24 */
220 u32 imask1
; /* 0x28 */
221 u32 iflag2
; /* 0x2c */
222 u32 iflag1
; /* 0x30 */
223 u32 ctrl2
; /* 0x34 */
225 u32 imeur
; /* 0x3c */
228 u32 rxfgmask
; /* 0x48 */
229 u32 rxfir
; /* 0x4c */
230 u32 _reserved3
[12]; /* 0x50 */
231 struct flexcan_mb cantxfg
[64]; /* 0x80 */
234 * 0x080...0x08f 0 RX message buffer
235 * 0x090...0x0df 1-5 reserverd
236 * 0x0e0...0x0ff 6-7 8 entry ID table
237 * (mx25, mx28, mx35, mx53)
238 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
239 * size conf'ed via ctrl2::RFFN
243 u32 mecr
; /* 0xae0 */
244 u32 erriar
; /* 0xae4 */
245 u32 erridpr
; /* 0xae8 */
246 u32 errippr
; /* 0xaec */
247 u32 rerrar
; /* 0xaf0 */
248 u32 rerrdr
; /* 0xaf4 */
249 u32 rerrsynr
; /* 0xaf8 */
250 u32 errsr
; /* 0xafc */
253 struct flexcan_devtype_data
{
254 u32 features
; /* hardware controller features */
257 struct flexcan_priv
{
259 struct napi_struct napi
;
263 u32 reg_ctrl_default
;
267 struct flexcan_platform_data
*pdata
;
268 const struct flexcan_devtype_data
*devtype_data
;
269 struct regulator
*reg_xceiver
;
272 static struct flexcan_devtype_data fsl_p1010_devtype_data
= {
273 .features
= FLEXCAN_HAS_BROKEN_ERR_STATE
,
275 static struct flexcan_devtype_data fsl_imx28_devtype_data
;
276 static struct flexcan_devtype_data fsl_imx6q_devtype_data
= {
277 .features
= FLEXCAN_HAS_V10_FEATURES
,
279 static struct flexcan_devtype_data fsl_vf610_devtype_data
= {
280 .features
= FLEXCAN_HAS_V10_FEATURES
| FLEXCAN_HAS_MECR_FEATURES
,
283 static const struct can_bittiming_const flexcan_bittiming_const
= {
296 * Abstract off the read/write for arm versus ppc. This
297 * assumes that PPC uses big-endian registers and everything
298 * else uses little-endian registers, independent of CPU
301 #if defined(CONFIG_PPC)
302 static inline u32
flexcan_read(void __iomem
*addr
)
304 return in_be32(addr
);
307 static inline void flexcan_write(u32 val
, void __iomem
*addr
)
312 static inline u32
flexcan_read(void __iomem
*addr
)
317 static inline void flexcan_write(u32 val
, void __iomem
*addr
)
323 static inline int flexcan_transceiver_enable(const struct flexcan_priv
*priv
)
325 if (!priv
->reg_xceiver
)
328 return regulator_enable(priv
->reg_xceiver
);
331 static inline int flexcan_transceiver_disable(const struct flexcan_priv
*priv
)
333 if (!priv
->reg_xceiver
)
336 return regulator_disable(priv
->reg_xceiver
);
339 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv
*priv
,
342 return (priv
->can
.ctrlmode
& CAN_CTRLMODE_BERR_REPORTING
) &&
343 (reg_esr
& FLEXCAN_ESR_ERR_BUS
);
346 static int flexcan_chip_enable(struct flexcan_priv
*priv
)
348 struct flexcan_regs __iomem
*regs
= priv
->base
;
349 unsigned int timeout
= FLEXCAN_TIMEOUT_US
/ 10;
352 reg
= flexcan_read(®s
->mcr
);
353 reg
&= ~FLEXCAN_MCR_MDIS
;
354 flexcan_write(reg
, ®s
->mcr
);
356 while (timeout
-- && (flexcan_read(®s
->mcr
) & FLEXCAN_MCR_LPM_ACK
))
359 if (flexcan_read(®s
->mcr
) & FLEXCAN_MCR_LPM_ACK
)
365 static int flexcan_chip_disable(struct flexcan_priv
*priv
)
367 struct flexcan_regs __iomem
*regs
= priv
->base
;
368 unsigned int timeout
= FLEXCAN_TIMEOUT_US
/ 10;
371 reg
= flexcan_read(®s
->mcr
);
372 reg
|= FLEXCAN_MCR_MDIS
;
373 flexcan_write(reg
, ®s
->mcr
);
375 while (timeout
-- && !(flexcan_read(®s
->mcr
) & FLEXCAN_MCR_LPM_ACK
))
378 if (!(flexcan_read(®s
->mcr
) & FLEXCAN_MCR_LPM_ACK
))
384 static int flexcan_chip_freeze(struct flexcan_priv
*priv
)
386 struct flexcan_regs __iomem
*regs
= priv
->base
;
387 unsigned int timeout
= 1000 * 1000 * 10 / priv
->can
.bittiming
.bitrate
;
390 reg
= flexcan_read(®s
->mcr
);
391 reg
|= FLEXCAN_MCR_HALT
;
392 flexcan_write(reg
, ®s
->mcr
);
394 while (timeout
-- && !(flexcan_read(®s
->mcr
) & FLEXCAN_MCR_FRZ_ACK
))
397 if (!(flexcan_read(®s
->mcr
) & FLEXCAN_MCR_FRZ_ACK
))
403 static int flexcan_chip_unfreeze(struct flexcan_priv
*priv
)
405 struct flexcan_regs __iomem
*regs
= priv
->base
;
406 unsigned int timeout
= FLEXCAN_TIMEOUT_US
/ 10;
409 reg
= flexcan_read(®s
->mcr
);
410 reg
&= ~FLEXCAN_MCR_HALT
;
411 flexcan_write(reg
, ®s
->mcr
);
413 while (timeout
-- && (flexcan_read(®s
->mcr
) & FLEXCAN_MCR_FRZ_ACK
))
416 if (flexcan_read(®s
->mcr
) & FLEXCAN_MCR_FRZ_ACK
)
422 static int flexcan_chip_softreset(struct flexcan_priv
*priv
)
424 struct flexcan_regs __iomem
*regs
= priv
->base
;
425 unsigned int timeout
= FLEXCAN_TIMEOUT_US
/ 10;
427 flexcan_write(FLEXCAN_MCR_SOFTRST
, ®s
->mcr
);
428 while (timeout
-- && (flexcan_read(®s
->mcr
) & FLEXCAN_MCR_SOFTRST
))
431 if (flexcan_read(®s
->mcr
) & FLEXCAN_MCR_SOFTRST
)
438 static int __flexcan_get_berr_counter(const struct net_device
*dev
,
439 struct can_berr_counter
*bec
)
441 const struct flexcan_priv
*priv
= netdev_priv(dev
);
442 struct flexcan_regs __iomem
*regs
= priv
->base
;
443 u32 reg
= flexcan_read(®s
->ecr
);
445 bec
->txerr
= (reg
>> 0) & 0xff;
446 bec
->rxerr
= (reg
>> 8) & 0xff;
451 static int flexcan_get_berr_counter(const struct net_device
*dev
,
452 struct can_berr_counter
*bec
)
454 const struct flexcan_priv
*priv
= netdev_priv(dev
);
457 err
= clk_prepare_enable(priv
->clk_ipg
);
461 err
= clk_prepare_enable(priv
->clk_per
);
463 goto out_disable_ipg
;
465 err
= __flexcan_get_berr_counter(dev
, bec
);
467 clk_disable_unprepare(priv
->clk_per
);
469 clk_disable_unprepare(priv
->clk_ipg
);
474 static int flexcan_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
476 const struct flexcan_priv
*priv
= netdev_priv(dev
);
477 struct flexcan_regs __iomem
*regs
= priv
->base
;
478 struct can_frame
*cf
= (struct can_frame
*)skb
->data
;
480 u32 ctrl
= FLEXCAN_MB_CODE_TX_DATA
| (cf
->can_dlc
<< 16);
482 if (can_dropped_invalid_skb(dev
, skb
))
485 netif_stop_queue(dev
);
487 if (cf
->can_id
& CAN_EFF_FLAG
) {
488 can_id
= cf
->can_id
& CAN_EFF_MASK
;
489 ctrl
|= FLEXCAN_MB_CNT_IDE
| FLEXCAN_MB_CNT_SRR
;
491 can_id
= (cf
->can_id
& CAN_SFF_MASK
) << 18;
494 if (cf
->can_id
& CAN_RTR_FLAG
)
495 ctrl
|= FLEXCAN_MB_CNT_RTR
;
497 if (cf
->can_dlc
> 0) {
498 u32 data
= be32_to_cpup((__be32
*)&cf
->data
[0]);
499 flexcan_write(data
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].data
[0]);
501 if (cf
->can_dlc
> 3) {
502 u32 data
= be32_to_cpup((__be32
*)&cf
->data
[4]);
503 flexcan_write(data
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].data
[1]);
506 can_put_echo_skb(skb
, dev
, 0);
508 flexcan_write(can_id
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].can_id
);
509 flexcan_write(ctrl
, ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].can_ctrl
);
511 /* Errata ERR005829 step8:
512 * Write twice INACTIVE(0x8) code to first MB.
514 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE
,
515 ®s
->cantxfg
[FLEXCAN_TX_BUF_RESERVED
].can_ctrl
);
516 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE
,
517 ®s
->cantxfg
[FLEXCAN_TX_BUF_RESERVED
].can_ctrl
);
522 static void do_bus_err(struct net_device
*dev
,
523 struct can_frame
*cf
, u32 reg_esr
)
525 struct flexcan_priv
*priv
= netdev_priv(dev
);
526 int rx_errors
= 0, tx_errors
= 0;
528 cf
->can_id
|= CAN_ERR_PROT
| CAN_ERR_BUSERROR
;
530 if (reg_esr
& FLEXCAN_ESR_BIT1_ERR
) {
531 netdev_dbg(dev
, "BIT1_ERR irq\n");
532 cf
->data
[2] |= CAN_ERR_PROT_BIT1
;
535 if (reg_esr
& FLEXCAN_ESR_BIT0_ERR
) {
536 netdev_dbg(dev
, "BIT0_ERR irq\n");
537 cf
->data
[2] |= CAN_ERR_PROT_BIT0
;
540 if (reg_esr
& FLEXCAN_ESR_ACK_ERR
) {
541 netdev_dbg(dev
, "ACK_ERR irq\n");
542 cf
->can_id
|= CAN_ERR_ACK
;
543 cf
->data
[3] |= CAN_ERR_PROT_LOC_ACK
;
546 if (reg_esr
& FLEXCAN_ESR_CRC_ERR
) {
547 netdev_dbg(dev
, "CRC_ERR irq\n");
548 cf
->data
[2] |= CAN_ERR_PROT_BIT
;
549 cf
->data
[3] |= CAN_ERR_PROT_LOC_CRC_SEQ
;
552 if (reg_esr
& FLEXCAN_ESR_FRM_ERR
) {
553 netdev_dbg(dev
, "FRM_ERR irq\n");
554 cf
->data
[2] |= CAN_ERR_PROT_FORM
;
557 if (reg_esr
& FLEXCAN_ESR_STF_ERR
) {
558 netdev_dbg(dev
, "STF_ERR irq\n");
559 cf
->data
[2] |= CAN_ERR_PROT_STUFF
;
563 priv
->can
.can_stats
.bus_error
++;
565 dev
->stats
.rx_errors
++;
567 dev
->stats
.tx_errors
++;
570 static int flexcan_poll_bus_err(struct net_device
*dev
, u32 reg_esr
)
573 struct can_frame
*cf
;
575 skb
= alloc_can_err_skb(dev
, &cf
);
579 do_bus_err(dev
, cf
, reg_esr
);
581 dev
->stats
.rx_packets
++;
582 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
583 netif_receive_skb(skb
);
588 static int flexcan_poll_state(struct net_device
*dev
, u32 reg_esr
)
590 struct flexcan_priv
*priv
= netdev_priv(dev
);
592 struct can_frame
*cf
;
593 enum can_state new_state
= 0, rx_state
= 0, tx_state
= 0;
595 struct can_berr_counter bec
;
597 flt
= reg_esr
& FLEXCAN_ESR_FLT_CONF_MASK
;
598 if (likely(flt
== FLEXCAN_ESR_FLT_CONF_ACTIVE
)) {
599 tx_state
= unlikely(reg_esr
& FLEXCAN_ESR_TX_WRN
) ?
600 CAN_STATE_ERROR_WARNING
: CAN_STATE_ERROR_ACTIVE
;
601 rx_state
= unlikely(reg_esr
& FLEXCAN_ESR_RX_WRN
) ?
602 CAN_STATE_ERROR_WARNING
: CAN_STATE_ERROR_ACTIVE
;
603 new_state
= max(tx_state
, rx_state
);
605 __flexcan_get_berr_counter(dev
, &bec
);
606 new_state
= flt
== FLEXCAN_ESR_FLT_CONF_PASSIVE
?
607 CAN_STATE_ERROR_PASSIVE
: CAN_STATE_BUS_OFF
;
608 rx_state
= bec
.rxerr
>= bec
.txerr
? new_state
: 0;
609 tx_state
= bec
.rxerr
<= bec
.txerr
? new_state
: 0;
612 /* state hasn't changed */
613 if (likely(new_state
== priv
->can
.state
))
616 skb
= alloc_can_err_skb(dev
, &cf
);
620 can_change_state(dev
, cf
, tx_state
, rx_state
);
622 if (unlikely(new_state
== CAN_STATE_BUS_OFF
))
625 dev
->stats
.rx_packets
++;
626 dev
->stats
.rx_bytes
+= cf
->can_dlc
;
627 netif_receive_skb(skb
);
632 static void flexcan_read_fifo(const struct net_device
*dev
,
633 struct can_frame
*cf
)
635 const struct flexcan_priv
*priv
= netdev_priv(dev
);
636 struct flexcan_regs __iomem
*regs
= priv
->base
;
637 struct flexcan_mb __iomem
*mb
= ®s
->cantxfg
[0];
638 u32 reg_ctrl
, reg_id
;
640 reg_ctrl
= flexcan_read(&mb
->can_ctrl
);
641 reg_id
= flexcan_read(&mb
->can_id
);
642 if (reg_ctrl
& FLEXCAN_MB_CNT_IDE
)
643 cf
->can_id
= ((reg_id
>> 0) & CAN_EFF_MASK
) | CAN_EFF_FLAG
;
645 cf
->can_id
= (reg_id
>> 18) & CAN_SFF_MASK
;
647 if (reg_ctrl
& FLEXCAN_MB_CNT_RTR
)
648 cf
->can_id
|= CAN_RTR_FLAG
;
649 cf
->can_dlc
= get_can_dlc((reg_ctrl
>> 16) & 0xf);
651 *(__be32
*)(cf
->data
+ 0) = cpu_to_be32(flexcan_read(&mb
->data
[0]));
652 *(__be32
*)(cf
->data
+ 4) = cpu_to_be32(flexcan_read(&mb
->data
[1]));
655 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
, ®s
->iflag1
);
656 flexcan_read(®s
->timer
);
659 static int flexcan_read_frame(struct net_device
*dev
)
661 struct net_device_stats
*stats
= &dev
->stats
;
662 struct can_frame
*cf
;
665 skb
= alloc_can_skb(dev
, &cf
);
666 if (unlikely(!skb
)) {
671 flexcan_read_fifo(dev
, cf
);
674 stats
->rx_bytes
+= cf
->can_dlc
;
675 netif_receive_skb(skb
);
677 can_led_event(dev
, CAN_LED_EVENT_RX
);
682 static int flexcan_poll(struct napi_struct
*napi
, int quota
)
684 struct net_device
*dev
= napi
->dev
;
685 const struct flexcan_priv
*priv
= netdev_priv(dev
);
686 struct flexcan_regs __iomem
*regs
= priv
->base
;
687 u32 reg_iflag1
, reg_esr
;
691 * The error bits are cleared on read,
692 * use saved value from irq handler.
694 reg_esr
= flexcan_read(®s
->esr
) | priv
->reg_esr
;
696 /* handle state changes */
697 work_done
+= flexcan_poll_state(dev
, reg_esr
);
700 reg_iflag1
= flexcan_read(®s
->iflag1
);
701 while (reg_iflag1
& FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
&&
703 work_done
+= flexcan_read_frame(dev
);
704 reg_iflag1
= flexcan_read(®s
->iflag1
);
707 /* report bus errors */
708 if (flexcan_has_and_handle_berr(priv
, reg_esr
) && work_done
< quota
)
709 work_done
+= flexcan_poll_bus_err(dev
, reg_esr
);
711 if (work_done
< quota
) {
714 flexcan_write(FLEXCAN_IFLAG_DEFAULT
, ®s
->imask1
);
715 flexcan_write(priv
->reg_ctrl_default
, ®s
->ctrl
);
721 static irqreturn_t
flexcan_irq(int irq
, void *dev_id
)
723 struct net_device
*dev
= dev_id
;
724 struct net_device_stats
*stats
= &dev
->stats
;
725 struct flexcan_priv
*priv
= netdev_priv(dev
);
726 struct flexcan_regs __iomem
*regs
= priv
->base
;
727 u32 reg_iflag1
, reg_esr
;
729 reg_iflag1
= flexcan_read(®s
->iflag1
);
730 reg_esr
= flexcan_read(®s
->esr
);
731 /* ACK all bus error and state change IRQ sources */
732 if (reg_esr
& FLEXCAN_ESR_ALL_INT
)
733 flexcan_write(reg_esr
& FLEXCAN_ESR_ALL_INT
, ®s
->esr
);
736 * schedule NAPI in case of:
739 * - bus error IRQ and bus error reporting is activated
741 if ((reg_iflag1
& FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
) ||
742 (reg_esr
& FLEXCAN_ESR_ERR_STATE
) ||
743 flexcan_has_and_handle_berr(priv
, reg_esr
)) {
745 * The error bits are cleared on read,
746 * save them for later use.
748 priv
->reg_esr
= reg_esr
& FLEXCAN_ESR_ERR_BUS
;
749 flexcan_write(FLEXCAN_IFLAG_DEFAULT
&
750 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE
, ®s
->imask1
);
751 flexcan_write(priv
->reg_ctrl_default
& ~FLEXCAN_CTRL_ERR_ALL
,
753 napi_schedule(&priv
->napi
);
757 if (reg_iflag1
& FLEXCAN_IFLAG_RX_FIFO_OVERFLOW
) {
758 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW
, ®s
->iflag1
);
759 dev
->stats
.rx_over_errors
++;
760 dev
->stats
.rx_errors
++;
763 /* transmission complete interrupt */
764 if (reg_iflag1
& (1 << FLEXCAN_TX_BUF_ID
)) {
765 stats
->tx_bytes
+= can_get_echo_skb(dev
, 0);
767 can_led_event(dev
, CAN_LED_EVENT_TX
);
768 /* after sending a RTR frame mailbox is in RX mode */
769 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE
,
770 ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].can_ctrl
);
771 flexcan_write((1 << FLEXCAN_TX_BUF_ID
), ®s
->iflag1
);
772 netif_wake_queue(dev
);
778 static void flexcan_set_bittiming(struct net_device
*dev
)
780 const struct flexcan_priv
*priv
= netdev_priv(dev
);
781 const struct can_bittiming
*bt
= &priv
->can
.bittiming
;
782 struct flexcan_regs __iomem
*regs
= priv
->base
;
785 reg
= flexcan_read(®s
->ctrl
);
786 reg
&= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
787 FLEXCAN_CTRL_RJW(0x3) |
788 FLEXCAN_CTRL_PSEG1(0x7) |
789 FLEXCAN_CTRL_PSEG2(0x7) |
790 FLEXCAN_CTRL_PROPSEG(0x7) |
795 reg
|= FLEXCAN_CTRL_PRESDIV(bt
->brp
- 1) |
796 FLEXCAN_CTRL_PSEG1(bt
->phase_seg1
- 1) |
797 FLEXCAN_CTRL_PSEG2(bt
->phase_seg2
- 1) |
798 FLEXCAN_CTRL_RJW(bt
->sjw
- 1) |
799 FLEXCAN_CTRL_PROPSEG(bt
->prop_seg
- 1);
801 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
)
802 reg
|= FLEXCAN_CTRL_LPB
;
803 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
)
804 reg
|= FLEXCAN_CTRL_LOM
;
805 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
)
806 reg
|= FLEXCAN_CTRL_SMP
;
808 netdev_info(dev
, "writing ctrl=0x%08x\n", reg
);
809 flexcan_write(reg
, ®s
->ctrl
);
811 /* print chip status */
812 netdev_dbg(dev
, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__
,
813 flexcan_read(®s
->mcr
), flexcan_read(®s
->ctrl
));
819 * this functions is entered with clocks enabled
822 static int flexcan_chip_start(struct net_device
*dev
)
824 struct flexcan_priv
*priv
= netdev_priv(dev
);
825 struct flexcan_regs __iomem
*regs
= priv
->base
;
826 u32 reg_mcr
, reg_ctrl
, reg_ctrl2
, reg_mecr
;
830 err
= flexcan_chip_enable(priv
);
835 err
= flexcan_chip_softreset(priv
);
837 goto out_chip_disable
;
839 flexcan_set_bittiming(dev
);
847 * only supervisor access
853 reg_mcr
= flexcan_read(®s
->mcr
);
854 reg_mcr
&= ~FLEXCAN_MCR_MAXMB(0xff);
855 reg_mcr
|= FLEXCAN_MCR_FRZ
| FLEXCAN_MCR_FEN
| FLEXCAN_MCR_HALT
|
856 FLEXCAN_MCR_SUPV
| FLEXCAN_MCR_WRN_EN
|
857 FLEXCAN_MCR_IDAM_C
| FLEXCAN_MCR_SRX_DIS
|
858 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID
);
859 netdev_dbg(dev
, "%s: writing mcr=0x%08x", __func__
, reg_mcr
);
860 flexcan_write(reg_mcr
, ®s
->mcr
);
865 * disable timer sync feature
867 * disable auto busoff recovery
868 * transmit lowest buffer first
870 * enable tx and rx warning interrupt
871 * enable bus off interrupt
872 * (== FLEXCAN_CTRL_ERR_STATE)
874 reg_ctrl
= flexcan_read(®s
->ctrl
);
875 reg_ctrl
&= ~FLEXCAN_CTRL_TSYN
;
876 reg_ctrl
|= FLEXCAN_CTRL_BOFF_REC
| FLEXCAN_CTRL_LBUF
|
877 FLEXCAN_CTRL_ERR_STATE
;
879 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
880 * on most Flexcan cores, too. Otherwise we don't get
881 * any error warning or passive interrupts.
883 if (priv
->devtype_data
->features
& FLEXCAN_HAS_BROKEN_ERR_STATE
||
884 priv
->can
.ctrlmode
& CAN_CTRLMODE_BERR_REPORTING
)
885 reg_ctrl
|= FLEXCAN_CTRL_ERR_MSK
;
887 reg_ctrl
&= ~FLEXCAN_CTRL_ERR_MSK
;
889 /* save for later use */
890 priv
->reg_ctrl_default
= reg_ctrl
;
891 netdev_dbg(dev
, "%s: writing ctrl=0x%08x", __func__
, reg_ctrl
);
892 flexcan_write(reg_ctrl
, ®s
->ctrl
);
894 /* clear and invalidate all mailboxes first */
895 for (i
= FLEXCAN_TX_BUF_ID
; i
< ARRAY_SIZE(regs
->cantxfg
); i
++) {
896 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE
,
897 ®s
->cantxfg
[i
].can_ctrl
);
900 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
901 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE
,
902 ®s
->cantxfg
[FLEXCAN_TX_BUF_RESERVED
].can_ctrl
);
904 /* mark TX mailbox as INACTIVE */
905 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE
,
906 ®s
->cantxfg
[FLEXCAN_TX_BUF_ID
].can_ctrl
);
908 /* acceptance mask/acceptance code (accept everything) */
909 flexcan_write(0x0, ®s
->rxgmask
);
910 flexcan_write(0x0, ®s
->rx14mask
);
911 flexcan_write(0x0, ®s
->rx15mask
);
913 if (priv
->devtype_data
->features
& FLEXCAN_HAS_V10_FEATURES
)
914 flexcan_write(0x0, ®s
->rxfgmask
);
917 * On Vybrid, disable memory error detection interrupts
919 * This also works around errata e5295 which generates
920 * false positive memory errors and put the device in
923 if (priv
->devtype_data
->features
& FLEXCAN_HAS_MECR_FEATURES
) {
925 * Follow the protocol as described in "Detection
926 * and Correction of Memory Errors" to write to
929 reg_ctrl2
= flexcan_read(®s
->ctrl2
);
930 reg_ctrl2
|= FLEXCAN_CTRL2_ECRWRE
;
931 flexcan_write(reg_ctrl2
, ®s
->ctrl2
);
933 reg_mecr
= flexcan_read(®s
->mecr
);
934 reg_mecr
&= ~FLEXCAN_MECR_ECRWRDIS
;
935 flexcan_write(reg_mecr
, ®s
->mecr
);
936 reg_mecr
&= ~(FLEXCAN_MECR_NCEFAFRZ
| FLEXCAN_MECR_HANCEI_MSK
|
937 FLEXCAN_MECR_FANCEI_MSK
);
938 flexcan_write(reg_mecr
, ®s
->mecr
);
941 err
= flexcan_transceiver_enable(priv
);
943 goto out_chip_disable
;
945 /* synchronize with the can bus */
946 err
= flexcan_chip_unfreeze(priv
);
948 goto out_transceiver_disable
;
950 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
952 /* enable FIFO interrupts */
953 flexcan_write(FLEXCAN_IFLAG_DEFAULT
, ®s
->imask1
);
955 /* print chip status */
956 netdev_dbg(dev
, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__
,
957 flexcan_read(®s
->mcr
), flexcan_read(®s
->ctrl
));
961 out_transceiver_disable
:
962 flexcan_transceiver_disable(priv
);
964 flexcan_chip_disable(priv
);
971 * this functions is entered with clocks enabled
974 static void flexcan_chip_stop(struct net_device
*dev
)
976 struct flexcan_priv
*priv
= netdev_priv(dev
);
977 struct flexcan_regs __iomem
*regs
= priv
->base
;
979 /* freeze + disable module */
980 flexcan_chip_freeze(priv
);
981 flexcan_chip_disable(priv
);
983 /* Disable all interrupts */
984 flexcan_write(0, ®s
->imask1
);
985 flexcan_write(priv
->reg_ctrl_default
& ~FLEXCAN_CTRL_ERR_ALL
,
988 flexcan_transceiver_disable(priv
);
989 priv
->can
.state
= CAN_STATE_STOPPED
;
994 static int flexcan_open(struct net_device
*dev
)
996 struct flexcan_priv
*priv
= netdev_priv(dev
);
999 err
= clk_prepare_enable(priv
->clk_ipg
);
1003 err
= clk_prepare_enable(priv
->clk_per
);
1005 goto out_disable_ipg
;
1007 err
= open_candev(dev
);
1009 goto out_disable_per
;
1011 err
= request_irq(dev
->irq
, flexcan_irq
, IRQF_SHARED
, dev
->name
, dev
);
1015 /* start chip and queuing */
1016 err
= flexcan_chip_start(dev
);
1020 can_led_event(dev
, CAN_LED_EVENT_OPEN
);
1022 napi_enable(&priv
->napi
);
1023 netif_start_queue(dev
);
1028 free_irq(dev
->irq
, dev
);
1032 clk_disable_unprepare(priv
->clk_per
);
1034 clk_disable_unprepare(priv
->clk_ipg
);
1039 static int flexcan_close(struct net_device
*dev
)
1041 struct flexcan_priv
*priv
= netdev_priv(dev
);
1043 netif_stop_queue(dev
);
1044 napi_disable(&priv
->napi
);
1045 flexcan_chip_stop(dev
);
1047 free_irq(dev
->irq
, dev
);
1048 clk_disable_unprepare(priv
->clk_per
);
1049 clk_disable_unprepare(priv
->clk_ipg
);
1053 can_led_event(dev
, CAN_LED_EVENT_STOP
);
1058 static int flexcan_set_mode(struct net_device
*dev
, enum can_mode mode
)
1063 case CAN_MODE_START
:
1064 err
= flexcan_chip_start(dev
);
1068 netif_wake_queue(dev
);
1078 static const struct net_device_ops flexcan_netdev_ops
= {
1079 .ndo_open
= flexcan_open
,
1080 .ndo_stop
= flexcan_close
,
1081 .ndo_start_xmit
= flexcan_start_xmit
,
1082 .ndo_change_mtu
= can_change_mtu
,
1085 static int register_flexcandev(struct net_device
*dev
)
1087 struct flexcan_priv
*priv
= netdev_priv(dev
);
1088 struct flexcan_regs __iomem
*regs
= priv
->base
;
1091 err
= clk_prepare_enable(priv
->clk_ipg
);
1095 err
= clk_prepare_enable(priv
->clk_per
);
1097 goto out_disable_ipg
;
1099 /* select "bus clock", chip must be disabled */
1100 err
= flexcan_chip_disable(priv
);
1102 goto out_disable_per
;
1103 reg
= flexcan_read(®s
->ctrl
);
1104 reg
|= FLEXCAN_CTRL_CLK_SRC
;
1105 flexcan_write(reg
, ®s
->ctrl
);
1107 err
= flexcan_chip_enable(priv
);
1109 goto out_chip_disable
;
1111 /* set freeze, halt and activate FIFO, restrict register access */
1112 reg
= flexcan_read(®s
->mcr
);
1113 reg
|= FLEXCAN_MCR_FRZ
| FLEXCAN_MCR_HALT
|
1114 FLEXCAN_MCR_FEN
| FLEXCAN_MCR_SUPV
;
1115 flexcan_write(reg
, ®s
->mcr
);
1118 * Currently we only support newer versions of this core
1119 * featuring a RX FIFO. Older cores found on some Coldfire
1120 * derivates are not yet supported.
1122 reg
= flexcan_read(®s
->mcr
);
1123 if (!(reg
& FLEXCAN_MCR_FEN
)) {
1124 netdev_err(dev
, "Could not enable RX FIFO, unsupported core\n");
1126 goto out_chip_disable
;
1129 err
= register_candev(dev
);
1131 /* disable core and turn off clocks */
1133 flexcan_chip_disable(priv
);
1135 clk_disable_unprepare(priv
->clk_per
);
1137 clk_disable_unprepare(priv
->clk_ipg
);
1142 static void unregister_flexcandev(struct net_device
*dev
)
1144 unregister_candev(dev
);
1147 static const struct of_device_id flexcan_of_match
[] = {
1148 { .compatible
= "fsl,imx6q-flexcan", .data
= &fsl_imx6q_devtype_data
, },
1149 { .compatible
= "fsl,imx28-flexcan", .data
= &fsl_imx28_devtype_data
, },
1150 { .compatible
= "fsl,p1010-flexcan", .data
= &fsl_p1010_devtype_data
, },
1151 { .compatible
= "fsl,vf610-flexcan", .data
= &fsl_vf610_devtype_data
, },
1154 MODULE_DEVICE_TABLE(of
, flexcan_of_match
);
1156 static const struct platform_device_id flexcan_id_table
[] = {
1157 { .name
= "flexcan", .driver_data
= (kernel_ulong_t
)&fsl_p1010_devtype_data
, },
1160 MODULE_DEVICE_TABLE(platform
, flexcan_id_table
);
1162 static int flexcan_probe(struct platform_device
*pdev
)
1164 const struct of_device_id
*of_id
;
1165 const struct flexcan_devtype_data
*devtype_data
;
1166 struct net_device
*dev
;
1167 struct flexcan_priv
*priv
;
1168 struct regulator
*reg_xceiver
;
1169 struct resource
*mem
;
1170 struct clk
*clk_ipg
= NULL
, *clk_per
= NULL
;
1175 reg_xceiver
= devm_regulator_get(&pdev
->dev
, "xceiver");
1176 if (PTR_ERR(reg_xceiver
) == -EPROBE_DEFER
)
1177 return -EPROBE_DEFER
;
1178 else if (IS_ERR(reg_xceiver
))
1181 if (pdev
->dev
.of_node
)
1182 of_property_read_u32(pdev
->dev
.of_node
,
1183 "clock-frequency", &clock_freq
);
1186 clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
1187 if (IS_ERR(clk_ipg
)) {
1188 dev_err(&pdev
->dev
, "no ipg clock defined\n");
1189 return PTR_ERR(clk_ipg
);
1192 clk_per
= devm_clk_get(&pdev
->dev
, "per");
1193 if (IS_ERR(clk_per
)) {
1194 dev_err(&pdev
->dev
, "no per clock defined\n");
1195 return PTR_ERR(clk_per
);
1197 clock_freq
= clk_get_rate(clk_per
);
1200 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1201 irq
= platform_get_irq(pdev
, 0);
1205 base
= devm_ioremap_resource(&pdev
->dev
, mem
);
1207 return PTR_ERR(base
);
1209 of_id
= of_match_device(flexcan_of_match
, &pdev
->dev
);
1211 devtype_data
= of_id
->data
;
1212 } else if (platform_get_device_id(pdev
)->driver_data
) {
1213 devtype_data
= (struct flexcan_devtype_data
*)
1214 platform_get_device_id(pdev
)->driver_data
;
1219 dev
= alloc_candev(sizeof(struct flexcan_priv
), 1);
1223 dev
->netdev_ops
= &flexcan_netdev_ops
;
1225 dev
->flags
|= IFF_ECHO
;
1227 priv
= netdev_priv(dev
);
1228 priv
->can
.clock
.freq
= clock_freq
;
1229 priv
->can
.bittiming_const
= &flexcan_bittiming_const
;
1230 priv
->can
.do_set_mode
= flexcan_set_mode
;
1231 priv
->can
.do_get_berr_counter
= flexcan_get_berr_counter
;
1232 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_LOOPBACK
|
1233 CAN_CTRLMODE_LISTENONLY
| CAN_CTRLMODE_3_SAMPLES
|
1234 CAN_CTRLMODE_BERR_REPORTING
;
1236 priv
->clk_ipg
= clk_ipg
;
1237 priv
->clk_per
= clk_per
;
1238 priv
->pdata
= dev_get_platdata(&pdev
->dev
);
1239 priv
->devtype_data
= devtype_data
;
1241 priv
->reg_xceiver
= reg_xceiver
;
1243 netif_napi_add(dev
, &priv
->napi
, flexcan_poll
, FLEXCAN_NAPI_WEIGHT
);
1245 platform_set_drvdata(pdev
, dev
);
1246 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1248 err
= register_flexcandev(dev
);
1250 dev_err(&pdev
->dev
, "registering netdev failed\n");
1251 goto failed_register
;
1254 devm_can_led_init(dev
);
1256 dev_info(&pdev
->dev
, "device registered (reg_base=%p, irq=%d)\n",
1257 priv
->base
, dev
->irq
);
1266 static int flexcan_remove(struct platform_device
*pdev
)
1268 struct net_device
*dev
= platform_get_drvdata(pdev
);
1269 struct flexcan_priv
*priv
= netdev_priv(dev
);
1271 unregister_flexcandev(dev
);
1272 netif_napi_del(&priv
->napi
);
1278 static int __maybe_unused
flexcan_suspend(struct device
*device
)
1280 struct net_device
*dev
= dev_get_drvdata(device
);
1281 struct flexcan_priv
*priv
= netdev_priv(dev
);
1284 err
= flexcan_chip_disable(priv
);
1288 if (netif_running(dev
)) {
1289 netif_stop_queue(dev
);
1290 netif_device_detach(dev
);
1292 priv
->can
.state
= CAN_STATE_SLEEPING
;
1297 static int __maybe_unused
flexcan_resume(struct device
*device
)
1299 struct net_device
*dev
= dev_get_drvdata(device
);
1300 struct flexcan_priv
*priv
= netdev_priv(dev
);
1302 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
1303 if (netif_running(dev
)) {
1304 netif_device_attach(dev
);
1305 netif_start_queue(dev
);
1307 return flexcan_chip_enable(priv
);
1310 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops
, flexcan_suspend
, flexcan_resume
);
1312 static struct platform_driver flexcan_driver
= {
1315 .pm
= &flexcan_pm_ops
,
1316 .of_match_table
= flexcan_of_match
,
1318 .probe
= flexcan_probe
,
1319 .remove
= flexcan_remove
,
1320 .id_table
= flexcan_id_table
,
1323 module_platform_driver(flexcan_driver
);
1325 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1326 "Marc Kleine-Budde <kernel@pengutronix.de>");
1327 MODULE_LICENSE("GPL v2");
1328 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");