2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 * Your platform definition file should specify something like:
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .power_enable = mcp251x_power_enable,
42 * .transceiver_enable = NULL,
45 * static struct spi_board_info spi_board_info[] = {
47 * .modalias = "mcp2510",
48 * // or "mcp2515" depending on your controller
49 * .platform_data = &mcp251x_info,
51 * .max_speed_hz = 2*1000*1000,
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
61 #include <linux/can/core.h>
62 #include <linux/can/dev.h>
63 #include <linux/can/platform/mcp251x.h>
64 #include <linux/completion.h>
65 #include <linux/delay.h>
66 #include <linux/device.h>
67 #include <linux/dma-mapping.h>
68 #include <linux/freezer.h>
69 #include <linux/interrupt.h>
71 #include <linux/kernel.h>
72 #include <linux/module.h>
73 #include <linux/netdevice.h>
74 #include <linux/platform_device.h>
75 #include <linux/slab.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
79 /* SPI interface instruction set */
80 #define INSTRUCTION_WRITE 0x02
81 #define INSTRUCTION_READ 0x03
82 #define INSTRUCTION_BIT_MODIFY 0x05
83 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85 #define INSTRUCTION_RESET 0xC0
87 /* MPC251x registers */
90 # define CANCTRL_REQOP_MASK 0xe0
91 # define CANCTRL_REQOP_CONF 0x80
92 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
93 # define CANCTRL_REQOP_LOOPBACK 0x40
94 # define CANCTRL_REQOP_SLEEP 0x20
95 # define CANCTRL_REQOP_NORMAL 0x00
96 # define CANCTRL_OSM 0x08
97 # define CANCTRL_ABAT 0x10
101 # define CNF1_SJW_SHIFT 6
103 # define CNF2_BTLMODE 0x80
104 # define CNF2_SAM 0x40
105 # define CNF2_PS1_SHIFT 3
107 # define CNF3_SOF 0x08
108 # define CNF3_WAKFIL 0x04
109 # define CNF3_PHSEG2_MASK 0x07
111 # define CANINTE_MERRE 0x80
112 # define CANINTE_WAKIE 0x40
113 # define CANINTE_ERRIE 0x20
114 # define CANINTE_TX2IE 0x10
115 # define CANINTE_TX1IE 0x08
116 # define CANINTE_TX0IE 0x04
117 # define CANINTE_RX1IE 0x02
118 # define CANINTE_RX0IE 0x01
120 # define CANINTF_MERRF 0x80
121 # define CANINTF_WAKIF 0x40
122 # define CANINTF_ERRIF 0x20
123 # define CANINTF_TX2IF 0x10
124 # define CANINTF_TX1IF 0x08
125 # define CANINTF_TX0IF 0x04
126 # define CANINTF_RX1IF 0x02
127 # define CANINTF_RX0IF 0x01
128 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
129 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
130 # define CANINTF_ERR (CANINTF_ERRIF)
132 # define EFLG_EWARN 0x01
133 # define EFLG_RXWAR 0x02
134 # define EFLG_TXWAR 0x04
135 # define EFLG_RXEP 0x08
136 # define EFLG_TXEP 0x10
137 # define EFLG_TXBO 0x20
138 # define EFLG_RX0OVR 0x40
139 # define EFLG_RX1OVR 0x80
140 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
141 # define TXBCTRL_ABTF 0x40
142 # define TXBCTRL_MLOA 0x20
143 # define TXBCTRL_TXERR 0x10
144 # define TXBCTRL_TXREQ 0x08
145 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
146 # define SIDH_SHIFT 3
147 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
148 # define SIDL_SID_MASK 7
149 # define SIDL_SID_SHIFT 5
150 # define SIDL_EXIDE_SHIFT 3
151 # define SIDL_EID_SHIFT 16
152 # define SIDL_EID_MASK 3
153 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
154 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
155 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
156 # define DLC_RTR_SHIFT 6
157 #define TXBCTRL_OFF 0
158 #define TXBSIDH_OFF 1
159 #define TXBSIDL_OFF 2
160 #define TXBEID8_OFF 3
161 #define TXBEID0_OFF 4
164 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
165 # define RXBCTRL_BUKT 0x04
166 # define RXBCTRL_RXM0 0x20
167 # define RXBCTRL_RXM1 0x40
168 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
169 # define RXBSIDH_SHIFT 3
170 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
171 # define RXBSIDL_IDE 0x08
172 # define RXBSIDL_EID 3
173 # define RXBSIDL_SHIFT 5
174 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
175 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
176 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
177 # define RXBDLC_LEN_MASK 0x0f
178 # define RXBDLC_RTR 0x40
179 #define RXBCTRL_OFF 0
180 #define RXBSIDH_OFF 1
181 #define RXBSIDL_OFF 2
182 #define RXBEID8_OFF 3
183 #define RXBEID0_OFF 4
186 #define RXFSIDH(n) ((n) * 4)
187 #define RXFSIDL(n) ((n) * 4 + 1)
188 #define RXFEID8(n) ((n) * 4 + 2)
189 #define RXFEID0(n) ((n) * 4 + 3)
190 #define RXMSIDH(n) ((n) * 4 + 0x20)
191 #define RXMSIDL(n) ((n) * 4 + 0x21)
192 #define RXMEID8(n) ((n) * 4 + 0x22)
193 #define RXMEID0(n) ((n) * 4 + 0x23)
195 #define GET_BYTE(val, byte) \
196 (((val) >> ((byte) * 8)) & 0xff)
197 #define SET_BYTE(val, byte) \
198 (((val) & 0xff) << ((byte) * 8))
201 * Buffer size required for the largest SPI transfer (i.e., reading a
204 #define CAN_FRAME_MAX_DATA_LEN 8
205 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
206 #define CAN_FRAME_MAX_BITS 128
208 #define TX_ECHO_SKB_MAX 1
210 #define DEVICE_NAME "mcp251x"
212 static int mcp251x_enable_dma
; /* Enable SPI DMA. Default: 0 (Off) */
213 module_param(mcp251x_enable_dma
, int, S_IRUGO
);
214 MODULE_PARM_DESC(mcp251x_enable_dma
, "Enable SPI DMA. Default: 0 (Off)");
216 static struct can_bittiming_const mcp251x_bittiming_const
= {
229 CAN_MCP251X_MCP2510
= 0x2510,
230 CAN_MCP251X_MCP2515
= 0x2515,
233 struct mcp251x_priv
{
235 struct net_device
*net
;
236 struct spi_device
*spi
;
237 enum mcp251x_model model
;
239 struct mutex mcp_lock
; /* SPI device lock */
243 dma_addr_t spi_tx_dma
;
244 dma_addr_t spi_rx_dma
;
246 struct sk_buff
*tx_skb
;
249 struct workqueue_struct
*wq
;
250 struct work_struct tx_work
;
251 struct work_struct restart_work
;
255 #define AFTER_SUSPEND_UP 1
256 #define AFTER_SUSPEND_DOWN 2
257 #define AFTER_SUSPEND_POWER 4
258 #define AFTER_SUSPEND_RESTART 8
262 #define MCP251X_IS(_model) \
263 static inline int mcp251x_is_##_model(struct spi_device *spi) \
265 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \
266 return priv->model == CAN_MCP251X_MCP##_model; \
272 static void mcp251x_clean(struct net_device
*net
)
274 struct mcp251x_priv
*priv
= netdev_priv(net
);
276 if (priv
->tx_skb
|| priv
->tx_len
)
277 net
->stats
.tx_errors
++;
279 dev_kfree_skb(priv
->tx_skb
);
281 can_free_echo_skb(priv
->net
, 0);
287 * Note about handling of error return of mcp251x_spi_trans: accessing
288 * registers via SPI is not really different conceptually than using
289 * normal I/O assembler instructions, although it's much more
290 * complicated from a practical POV. So it's not advisable to always
291 * check the return value of this function. Imagine that every
292 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
293 * error();", it would be a great mess (well there are some situation
294 * when exception handling C++ like could be useful after all). So we
295 * just check that transfers are OK at the beginning of our
296 * conversation with the chip and to avoid doing really nasty things
297 * (like injecting bogus packets in the network stack).
299 static int mcp251x_spi_trans(struct spi_device
*spi
, int len
)
301 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
302 struct spi_transfer t
= {
303 .tx_buf
= priv
->spi_tx_buf
,
304 .rx_buf
= priv
->spi_rx_buf
,
308 struct spi_message m
;
311 spi_message_init(&m
);
313 if (mcp251x_enable_dma
) {
314 t
.tx_dma
= priv
->spi_tx_dma
;
315 t
.rx_dma
= priv
->spi_rx_dma
;
319 spi_message_add_tail(&t
, &m
);
321 ret
= spi_sync(spi
, &m
);
323 dev_err(&spi
->dev
, "spi transfer failed: ret = %d\n", ret
);
327 static u8
mcp251x_read_reg(struct spi_device
*spi
, uint8_t reg
)
329 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
332 priv
->spi_tx_buf
[0] = INSTRUCTION_READ
;
333 priv
->spi_tx_buf
[1] = reg
;
335 mcp251x_spi_trans(spi
, 3);
336 val
= priv
->spi_rx_buf
[2];
341 static void mcp251x_read_2regs(struct spi_device
*spi
, uint8_t reg
,
342 uint8_t *v1
, uint8_t *v2
)
344 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
346 priv
->spi_tx_buf
[0] = INSTRUCTION_READ
;
347 priv
->spi_tx_buf
[1] = reg
;
349 mcp251x_spi_trans(spi
, 4);
351 *v1
= priv
->spi_rx_buf
[2];
352 *v2
= priv
->spi_rx_buf
[3];
355 static void mcp251x_write_reg(struct spi_device
*spi
, u8 reg
, uint8_t val
)
357 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
359 priv
->spi_tx_buf
[0] = INSTRUCTION_WRITE
;
360 priv
->spi_tx_buf
[1] = reg
;
361 priv
->spi_tx_buf
[2] = val
;
363 mcp251x_spi_trans(spi
, 3);
366 static void mcp251x_write_bits(struct spi_device
*spi
, u8 reg
,
367 u8 mask
, uint8_t val
)
369 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
371 priv
->spi_tx_buf
[0] = INSTRUCTION_BIT_MODIFY
;
372 priv
->spi_tx_buf
[1] = reg
;
373 priv
->spi_tx_buf
[2] = mask
;
374 priv
->spi_tx_buf
[3] = val
;
376 mcp251x_spi_trans(spi
, 4);
379 static void mcp251x_hw_tx_frame(struct spi_device
*spi
, u8
*buf
,
380 int len
, int tx_buf_idx
)
382 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
384 if (mcp251x_is_2510(spi
)) {
387 for (i
= 1; i
< TXBDAT_OFF
+ len
; i
++)
388 mcp251x_write_reg(spi
, TXBCTRL(tx_buf_idx
) + i
,
391 memcpy(priv
->spi_tx_buf
, buf
, TXBDAT_OFF
+ len
);
392 mcp251x_spi_trans(spi
, TXBDAT_OFF
+ len
);
396 static void mcp251x_hw_tx(struct spi_device
*spi
, struct can_frame
*frame
,
399 u32 sid
, eid
, exide
, rtr
;
400 u8 buf
[SPI_TRANSFER_BUF_LEN
];
402 exide
= (frame
->can_id
& CAN_EFF_FLAG
) ? 1 : 0; /* Extended ID Enable */
404 sid
= (frame
->can_id
& CAN_EFF_MASK
) >> 18;
406 sid
= frame
->can_id
& CAN_SFF_MASK
; /* Standard ID */
407 eid
= frame
->can_id
& CAN_EFF_MASK
; /* Extended ID */
408 rtr
= (frame
->can_id
& CAN_RTR_FLAG
) ? 1 : 0; /* Remote transmission */
410 buf
[TXBCTRL_OFF
] = INSTRUCTION_LOAD_TXB(tx_buf_idx
);
411 buf
[TXBSIDH_OFF
] = sid
>> SIDH_SHIFT
;
412 buf
[TXBSIDL_OFF
] = ((sid
& SIDL_SID_MASK
) << SIDL_SID_SHIFT
) |
413 (exide
<< SIDL_EXIDE_SHIFT
) |
414 ((eid
>> SIDL_EID_SHIFT
) & SIDL_EID_MASK
);
415 buf
[TXBEID8_OFF
] = GET_BYTE(eid
, 1);
416 buf
[TXBEID0_OFF
] = GET_BYTE(eid
, 0);
417 buf
[TXBDLC_OFF
] = (rtr
<< DLC_RTR_SHIFT
) | frame
->can_dlc
;
418 memcpy(buf
+ TXBDAT_OFF
, frame
->data
, frame
->can_dlc
);
419 mcp251x_hw_tx_frame(spi
, buf
, frame
->can_dlc
, tx_buf_idx
);
420 mcp251x_write_reg(spi
, TXBCTRL(tx_buf_idx
), TXBCTRL_TXREQ
);
423 static void mcp251x_hw_rx_frame(struct spi_device
*spi
, u8
*buf
,
426 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
428 if (mcp251x_is_2510(spi
)) {
431 for (i
= 1; i
< RXBDAT_OFF
; i
++)
432 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
434 len
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
435 for (; i
< (RXBDAT_OFF
+ len
); i
++)
436 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
438 priv
->spi_tx_buf
[RXBCTRL_OFF
] = INSTRUCTION_READ_RXB(buf_idx
);
439 mcp251x_spi_trans(spi
, SPI_TRANSFER_BUF_LEN
);
440 memcpy(buf
, priv
->spi_rx_buf
, SPI_TRANSFER_BUF_LEN
);
444 static void mcp251x_hw_rx(struct spi_device
*spi
, int buf_idx
)
446 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
448 struct can_frame
*frame
;
449 u8 buf
[SPI_TRANSFER_BUF_LEN
];
451 skb
= alloc_can_skb(priv
->net
, &frame
);
453 dev_err(&spi
->dev
, "cannot allocate RX skb\n");
454 priv
->net
->stats
.rx_dropped
++;
458 mcp251x_hw_rx_frame(spi
, buf
, buf_idx
);
459 if (buf
[RXBSIDL_OFF
] & RXBSIDL_IDE
) {
460 /* Extended ID format */
461 frame
->can_id
= CAN_EFF_FLAG
;
463 /* Extended ID part */
464 SET_BYTE(buf
[RXBSIDL_OFF
] & RXBSIDL_EID
, 2) |
465 SET_BYTE(buf
[RXBEID8_OFF
], 1) |
466 SET_BYTE(buf
[RXBEID0_OFF
], 0) |
467 /* Standard ID part */
468 (((buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
469 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
)) << 18);
470 /* Remote transmission request */
471 if (buf
[RXBDLC_OFF
] & RXBDLC_RTR
)
472 frame
->can_id
|= CAN_RTR_FLAG
;
474 /* Standard ID format */
476 (buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
477 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
);
480 frame
->can_dlc
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
481 memcpy(frame
->data
, buf
+ RXBDAT_OFF
, frame
->can_dlc
);
483 priv
->net
->stats
.rx_packets
++;
484 priv
->net
->stats
.rx_bytes
+= frame
->can_dlc
;
488 static void mcp251x_hw_sleep(struct spi_device
*spi
)
490 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_SLEEP
);
493 static netdev_tx_t
mcp251x_hard_start_xmit(struct sk_buff
*skb
,
494 struct net_device
*net
)
496 struct mcp251x_priv
*priv
= netdev_priv(net
);
497 struct spi_device
*spi
= priv
->spi
;
499 if (priv
->tx_skb
|| priv
->tx_len
) {
500 dev_warn(&spi
->dev
, "hard_xmit called while tx busy\n");
501 return NETDEV_TX_BUSY
;
504 if (can_dropped_invalid_skb(net
, skb
))
507 netif_stop_queue(net
);
509 queue_work(priv
->wq
, &priv
->tx_work
);
514 static int mcp251x_do_set_mode(struct net_device
*net
, enum can_mode mode
)
516 struct mcp251x_priv
*priv
= netdev_priv(net
);
521 /* We have to delay work since SPI I/O may sleep */
522 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
523 priv
->restart_tx
= 1;
524 if (priv
->can
.restart_ms
== 0)
525 priv
->after_suspend
= AFTER_SUSPEND_RESTART
;
526 queue_work(priv
->wq
, &priv
->restart_work
);
535 static int mcp251x_set_normal_mode(struct spi_device
*spi
)
537 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
538 unsigned long timeout
;
540 /* Enable interrupts */
541 mcp251x_write_reg(spi
, CANINTE
,
542 CANINTE_ERRIE
| CANINTE_TX2IE
| CANINTE_TX1IE
|
543 CANINTE_TX0IE
| CANINTE_RX1IE
| CANINTE_RX0IE
);
545 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
) {
546 /* Put device into loopback mode */
547 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_LOOPBACK
);
548 } else if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LISTENONLY
) {
549 /* Put device into listen-only mode */
550 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_LISTEN_ONLY
);
552 /* Put device into normal mode */
553 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_NORMAL
);
555 /* Wait for the device to enter normal mode */
556 timeout
= jiffies
+ HZ
;
557 while (mcp251x_read_reg(spi
, CANSTAT
) & CANCTRL_REQOP_MASK
) {
559 if (time_after(jiffies
, timeout
)) {
560 dev_err(&spi
->dev
, "MCP251x didn't"
561 " enter in normal mode\n");
566 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
570 static int mcp251x_do_set_bittiming(struct net_device
*net
)
572 struct mcp251x_priv
*priv
= netdev_priv(net
);
573 struct can_bittiming
*bt
= &priv
->can
.bittiming
;
574 struct spi_device
*spi
= priv
->spi
;
576 mcp251x_write_reg(spi
, CNF1
, ((bt
->sjw
- 1) << CNF1_SJW_SHIFT
) |
578 mcp251x_write_reg(spi
, CNF2
, CNF2_BTLMODE
|
579 (priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
?
581 ((bt
->phase_seg1
- 1) << CNF2_PS1_SHIFT
) |
583 mcp251x_write_bits(spi
, CNF3
, CNF3_PHSEG2_MASK
,
584 (bt
->phase_seg2
- 1));
585 dev_info(&spi
->dev
, "CNF: 0x%02x 0x%02x 0x%02x\n",
586 mcp251x_read_reg(spi
, CNF1
),
587 mcp251x_read_reg(spi
, CNF2
),
588 mcp251x_read_reg(spi
, CNF3
));
593 static int mcp251x_setup(struct net_device
*net
, struct mcp251x_priv
*priv
,
594 struct spi_device
*spi
)
596 mcp251x_do_set_bittiming(net
);
598 mcp251x_write_reg(spi
, RXBCTRL(0),
599 RXBCTRL_BUKT
| RXBCTRL_RXM0
| RXBCTRL_RXM1
);
600 mcp251x_write_reg(spi
, RXBCTRL(1),
601 RXBCTRL_RXM0
| RXBCTRL_RXM1
);
605 static int mcp251x_hw_reset(struct spi_device
*spi
)
607 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
609 unsigned long timeout
;
611 priv
->spi_tx_buf
[0] = INSTRUCTION_RESET
;
612 ret
= spi_write(spi
, priv
->spi_tx_buf
, 1);
614 dev_err(&spi
->dev
, "reset failed: ret = %d\n", ret
);
618 /* Wait for reset to finish */
619 timeout
= jiffies
+ HZ
;
621 while ((mcp251x_read_reg(spi
, CANSTAT
) & CANCTRL_REQOP_MASK
)
622 != CANCTRL_REQOP_CONF
) {
624 if (time_after(jiffies
, timeout
)) {
625 dev_err(&spi
->dev
, "MCP251x didn't"
626 " enter in conf mode after reset\n");
633 static int mcp251x_hw_probe(struct spi_device
*spi
)
637 mcp251x_hw_reset(spi
);
640 * Please note that these are "magic values" based on after
641 * reset defaults taken from data sheet which allows us to see
642 * if we really have a chip on the bus (we avoid common all
643 * zeroes or all ones situations)
645 st1
= mcp251x_read_reg(spi
, CANSTAT
) & 0xEE;
646 st2
= mcp251x_read_reg(spi
, CANCTRL
) & 0x17;
648 dev_dbg(&spi
->dev
, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1
, st2
);
650 /* Check for power up default values */
651 return (st1
== 0x80 && st2
== 0x07) ? 1 : 0;
654 static void mcp251x_open_clean(struct net_device
*net
)
656 struct mcp251x_priv
*priv
= netdev_priv(net
);
657 struct spi_device
*spi
= priv
->spi
;
658 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
660 free_irq(spi
->irq
, priv
);
661 mcp251x_hw_sleep(spi
);
662 if (pdata
->transceiver_enable
)
663 pdata
->transceiver_enable(0);
667 static int mcp251x_stop(struct net_device
*net
)
669 struct mcp251x_priv
*priv
= netdev_priv(net
);
670 struct spi_device
*spi
= priv
->spi
;
671 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
675 priv
->force_quit
= 1;
676 free_irq(spi
->irq
, priv
);
677 destroy_workqueue(priv
->wq
);
680 mutex_lock(&priv
->mcp_lock
);
682 /* Disable and clear pending interrupts */
683 mcp251x_write_reg(spi
, CANINTE
, 0x00);
684 mcp251x_write_reg(spi
, CANINTF
, 0x00);
686 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
689 mcp251x_hw_sleep(spi
);
691 if (pdata
->transceiver_enable
)
692 pdata
->transceiver_enable(0);
694 priv
->can
.state
= CAN_STATE_STOPPED
;
696 mutex_unlock(&priv
->mcp_lock
);
701 static void mcp251x_error_skb(struct net_device
*net
, int can_id
, int data1
)
704 struct can_frame
*frame
;
706 skb
= alloc_can_err_skb(net
, &frame
);
708 frame
->can_id
= can_id
;
709 frame
->data
[1] = data1
;
713 "cannot allocate error skb\n");
717 static void mcp251x_tx_work_handler(struct work_struct
*ws
)
719 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
721 struct spi_device
*spi
= priv
->spi
;
722 struct net_device
*net
= priv
->net
;
723 struct can_frame
*frame
;
725 mutex_lock(&priv
->mcp_lock
);
727 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
730 frame
= (struct can_frame
*)priv
->tx_skb
->data
;
732 if (frame
->can_dlc
> CAN_FRAME_MAX_DATA_LEN
)
733 frame
->can_dlc
= CAN_FRAME_MAX_DATA_LEN
;
734 mcp251x_hw_tx(spi
, frame
, 0);
735 priv
->tx_len
= 1 + frame
->can_dlc
;
736 can_put_echo_skb(priv
->tx_skb
, net
, 0);
740 mutex_unlock(&priv
->mcp_lock
);
743 static void mcp251x_restart_work_handler(struct work_struct
*ws
)
745 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
747 struct spi_device
*spi
= priv
->spi
;
748 struct net_device
*net
= priv
->net
;
750 mutex_lock(&priv
->mcp_lock
);
751 if (priv
->after_suspend
) {
753 mcp251x_hw_reset(spi
);
754 mcp251x_setup(net
, priv
, spi
);
755 if (priv
->after_suspend
& AFTER_SUSPEND_RESTART
) {
756 mcp251x_set_normal_mode(spi
);
757 } else if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
758 netif_device_attach(net
);
760 mcp251x_set_normal_mode(spi
);
761 netif_wake_queue(net
);
763 mcp251x_hw_sleep(spi
);
765 priv
->after_suspend
= 0;
766 priv
->force_quit
= 0;
769 if (priv
->restart_tx
) {
770 priv
->restart_tx
= 0;
771 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
773 netif_wake_queue(net
);
774 mcp251x_error_skb(net
, CAN_ERR_RESTARTED
, 0);
776 mutex_unlock(&priv
->mcp_lock
);
779 static irqreturn_t
mcp251x_can_ist(int irq
, void *dev_id
)
781 struct mcp251x_priv
*priv
= dev_id
;
782 struct spi_device
*spi
= priv
->spi
;
783 struct net_device
*net
= priv
->net
;
785 mutex_lock(&priv
->mcp_lock
);
786 while (!priv
->force_quit
) {
787 enum can_state new_state
;
790 int can_id
= 0, data1
= 0;
792 mcp251x_read_2regs(spi
, CANINTF
, &intf
, &eflag
);
794 /* mask out flags we don't care about */
795 intf
&= CANINTF_RX
| CANINTF_TX
| CANINTF_ERR
;
797 /* receive buffer 0 */
798 if (intf
& CANINTF_RX0IF
) {
799 mcp251x_hw_rx(spi
, 0);
801 * Free one buffer ASAP
802 * (The MCP2515 does this automatically.)
804 if (mcp251x_is_2510(spi
))
805 mcp251x_write_bits(spi
, CANINTF
, CANINTF_RX0IF
, 0x00);
808 /* receive buffer 1 */
809 if (intf
& CANINTF_RX1IF
) {
810 mcp251x_hw_rx(spi
, 1);
811 /* the MCP2515 does this automatically */
812 if (mcp251x_is_2510(spi
))
813 clear_intf
|= CANINTF_RX1IF
;
816 /* any error or tx interrupt we need to clear? */
817 if (intf
& (CANINTF_ERR
| CANINTF_TX
))
818 clear_intf
|= intf
& (CANINTF_ERR
| CANINTF_TX
);
820 mcp251x_write_bits(spi
, CANINTF
, clear_intf
, 0x00);
823 mcp251x_write_bits(spi
, EFLG
, eflag
, 0x00);
825 /* Update can state */
826 if (eflag
& EFLG_TXBO
) {
827 new_state
= CAN_STATE_BUS_OFF
;
828 can_id
|= CAN_ERR_BUSOFF
;
829 } else if (eflag
& EFLG_TXEP
) {
830 new_state
= CAN_STATE_ERROR_PASSIVE
;
831 can_id
|= CAN_ERR_CRTL
;
832 data1
|= CAN_ERR_CRTL_TX_PASSIVE
;
833 } else if (eflag
& EFLG_RXEP
) {
834 new_state
= CAN_STATE_ERROR_PASSIVE
;
835 can_id
|= CAN_ERR_CRTL
;
836 data1
|= CAN_ERR_CRTL_RX_PASSIVE
;
837 } else if (eflag
& EFLG_TXWAR
) {
838 new_state
= CAN_STATE_ERROR_WARNING
;
839 can_id
|= CAN_ERR_CRTL
;
840 data1
|= CAN_ERR_CRTL_TX_WARNING
;
841 } else if (eflag
& EFLG_RXWAR
) {
842 new_state
= CAN_STATE_ERROR_WARNING
;
843 can_id
|= CAN_ERR_CRTL
;
844 data1
|= CAN_ERR_CRTL_RX_WARNING
;
846 new_state
= CAN_STATE_ERROR_ACTIVE
;
849 /* Update can state statistics */
850 switch (priv
->can
.state
) {
851 case CAN_STATE_ERROR_ACTIVE
:
852 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
853 new_state
<= CAN_STATE_BUS_OFF
)
854 priv
->can
.can_stats
.error_warning
++;
855 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
856 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
857 new_state
<= CAN_STATE_BUS_OFF
)
858 priv
->can
.can_stats
.error_passive
++;
863 priv
->can
.state
= new_state
;
865 if (intf
& CANINTF_ERRIF
) {
866 /* Handle overflow counters */
867 if (eflag
& (EFLG_RX0OVR
| EFLG_RX1OVR
)) {
868 if (eflag
& EFLG_RX0OVR
) {
869 net
->stats
.rx_over_errors
++;
870 net
->stats
.rx_errors
++;
872 if (eflag
& EFLG_RX1OVR
) {
873 net
->stats
.rx_over_errors
++;
874 net
->stats
.rx_errors
++;
876 can_id
|= CAN_ERR_CRTL
;
877 data1
|= CAN_ERR_CRTL_RX_OVERFLOW
;
879 mcp251x_error_skb(net
, can_id
, data1
);
882 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
883 if (priv
->can
.restart_ms
== 0) {
884 priv
->force_quit
= 1;
886 mcp251x_hw_sleep(spi
);
894 if (intf
& CANINTF_TX
) {
895 net
->stats
.tx_packets
++;
896 net
->stats
.tx_bytes
+= priv
->tx_len
- 1;
898 can_get_echo_skb(net
, 0);
901 netif_wake_queue(net
);
905 mutex_unlock(&priv
->mcp_lock
);
909 static int mcp251x_open(struct net_device
*net
)
911 struct mcp251x_priv
*priv
= netdev_priv(net
);
912 struct spi_device
*spi
= priv
->spi
;
913 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
916 ret
= open_candev(net
);
918 dev_err(&spi
->dev
, "unable to set initial baudrate!\n");
922 mutex_lock(&priv
->mcp_lock
);
923 if (pdata
->transceiver_enable
)
924 pdata
->transceiver_enable(1);
926 priv
->force_quit
= 0;
930 ret
= request_threaded_irq(spi
->irq
, NULL
, mcp251x_can_ist
,
931 IRQF_TRIGGER_FALLING
, DEVICE_NAME
, priv
);
933 dev_err(&spi
->dev
, "failed to acquire irq %d\n", spi
->irq
);
934 if (pdata
->transceiver_enable
)
935 pdata
->transceiver_enable(0);
940 priv
->wq
= create_freezeable_workqueue("mcp251x_wq");
941 INIT_WORK(&priv
->tx_work
, mcp251x_tx_work_handler
);
942 INIT_WORK(&priv
->restart_work
, mcp251x_restart_work_handler
);
944 ret
= mcp251x_hw_reset(spi
);
946 mcp251x_open_clean(net
);
949 ret
= mcp251x_setup(net
, priv
, spi
);
951 mcp251x_open_clean(net
);
954 ret
= mcp251x_set_normal_mode(spi
);
956 mcp251x_open_clean(net
);
959 netif_wake_queue(net
);
962 mutex_unlock(&priv
->mcp_lock
);
966 static const struct net_device_ops mcp251x_netdev_ops
= {
967 .ndo_open
= mcp251x_open
,
968 .ndo_stop
= mcp251x_stop
,
969 .ndo_start_xmit
= mcp251x_hard_start_xmit
,
972 static int __devinit
mcp251x_can_probe(struct spi_device
*spi
)
974 struct net_device
*net
;
975 struct mcp251x_priv
*priv
;
976 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
980 /* Platform data is required for osc freq */
983 /* Allocate can/net device */
984 net
= alloc_candev(sizeof(struct mcp251x_priv
), TX_ECHO_SKB_MAX
);
990 net
->netdev_ops
= &mcp251x_netdev_ops
;
991 net
->flags
|= IFF_ECHO
;
993 priv
= netdev_priv(net
);
994 priv
->can
.bittiming_const
= &mcp251x_bittiming_const
;
995 priv
->can
.do_set_mode
= mcp251x_do_set_mode
;
996 priv
->can
.clock
.freq
= pdata
->oscillator_frequency
/ 2;
997 priv
->can
.ctrlmode_supported
= CAN_CTRLMODE_3_SAMPLES
|
998 CAN_CTRLMODE_LOOPBACK
| CAN_CTRLMODE_LISTENONLY
;
999 priv
->model
= spi_get_device_id(spi
)->driver_data
;
1001 dev_set_drvdata(&spi
->dev
, priv
);
1004 mutex_init(&priv
->mcp_lock
);
1006 /* If requested, allocate DMA buffers */
1007 if (mcp251x_enable_dma
) {
1008 spi
->dev
.coherent_dma_mask
= ~0;
1011 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1012 * that much and share it between Tx and Rx DMA buffers.
1014 priv
->spi_tx_buf
= dma_alloc_coherent(&spi
->dev
,
1019 if (priv
->spi_tx_buf
) {
1020 priv
->spi_rx_buf
= (u8
*)(priv
->spi_tx_buf
+
1022 priv
->spi_rx_dma
= (dma_addr_t
)(priv
->spi_tx_dma
+
1025 /* Fall back to non-DMA */
1026 mcp251x_enable_dma
= 0;
1030 /* Allocate non-DMA buffers */
1031 if (!mcp251x_enable_dma
) {
1032 priv
->spi_tx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
1033 if (!priv
->spi_tx_buf
) {
1037 priv
->spi_rx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
1038 if (!priv
->spi_rx_buf
) {
1044 if (pdata
->power_enable
)
1045 pdata
->power_enable(1);
1047 /* Call out to platform specific setup */
1048 if (pdata
->board_specific_setup
)
1049 pdata
->board_specific_setup(spi
);
1051 SET_NETDEV_DEV(net
, &spi
->dev
);
1053 /* Configure the SPI bus */
1054 spi
->mode
= SPI_MODE_0
;
1055 spi
->bits_per_word
= 8;
1058 /* Here is OK to not lock the MCP, no one knows about it yet */
1059 if (!mcp251x_hw_probe(spi
)) {
1060 dev_info(&spi
->dev
, "Probe failed\n");
1063 mcp251x_hw_sleep(spi
);
1065 if (pdata
->transceiver_enable
)
1066 pdata
->transceiver_enable(0);
1068 ret
= register_candev(net
);
1070 dev_info(&spi
->dev
, "probed\n");
1074 if (!mcp251x_enable_dma
)
1075 kfree(priv
->spi_rx_buf
);
1077 if (!mcp251x_enable_dma
)
1078 kfree(priv
->spi_tx_buf
);
1081 if (mcp251x_enable_dma
)
1082 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1083 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1085 if (pdata
->power_enable
)
1086 pdata
->power_enable(0);
1087 dev_err(&spi
->dev
, "probe failed\n");
1092 static int __devexit
mcp251x_can_remove(struct spi_device
*spi
)
1094 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1095 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1096 struct net_device
*net
= priv
->net
;
1098 unregister_candev(net
);
1101 if (mcp251x_enable_dma
) {
1102 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1103 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1105 kfree(priv
->spi_tx_buf
);
1106 kfree(priv
->spi_rx_buf
);
1109 if (pdata
->power_enable
)
1110 pdata
->power_enable(0);
1116 static int mcp251x_can_suspend(struct spi_device
*spi
, pm_message_t state
)
1118 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1119 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1120 struct net_device
*net
= priv
->net
;
1122 priv
->force_quit
= 1;
1123 disable_irq(spi
->irq
);
1125 * Note: at this point neither IST nor workqueues are running.
1126 * open/stop cannot be called anyway so locking is not needed
1128 if (netif_running(net
)) {
1129 netif_device_detach(net
);
1131 mcp251x_hw_sleep(spi
);
1132 if (pdata
->transceiver_enable
)
1133 pdata
->transceiver_enable(0);
1134 priv
->after_suspend
= AFTER_SUSPEND_UP
;
1136 priv
->after_suspend
= AFTER_SUSPEND_DOWN
;
1139 if (pdata
->power_enable
) {
1140 pdata
->power_enable(0);
1141 priv
->after_suspend
|= AFTER_SUSPEND_POWER
;
1147 static int mcp251x_can_resume(struct spi_device
*spi
)
1149 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1150 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1152 if (priv
->after_suspend
& AFTER_SUSPEND_POWER
) {
1153 pdata
->power_enable(1);
1154 queue_work(priv
->wq
, &priv
->restart_work
);
1156 if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
1157 if (pdata
->transceiver_enable
)
1158 pdata
->transceiver_enable(1);
1159 queue_work(priv
->wq
, &priv
->restart_work
);
1161 priv
->after_suspend
= 0;
1164 priv
->force_quit
= 0;
1165 enable_irq(spi
->irq
);
1169 #define mcp251x_can_suspend NULL
1170 #define mcp251x_can_resume NULL
1173 static const struct spi_device_id mcp251x_id_table
[] = {
1174 { "mcp2510", CAN_MCP251X_MCP2510
},
1175 { "mcp2515", CAN_MCP251X_MCP2515
},
1179 MODULE_DEVICE_TABLE(spi
, mcp251x_id_table
);
1181 static struct spi_driver mcp251x_can_driver
= {
1183 .name
= DEVICE_NAME
,
1184 .bus
= &spi_bus_type
,
1185 .owner
= THIS_MODULE
,
1188 .id_table
= mcp251x_id_table
,
1189 .probe
= mcp251x_can_probe
,
1190 .remove
= __devexit_p(mcp251x_can_remove
),
1191 .suspend
= mcp251x_can_suspend
,
1192 .resume
= mcp251x_can_resume
,
1195 static int __init
mcp251x_can_init(void)
1197 return spi_register_driver(&mcp251x_can_driver
);
1200 static void __exit
mcp251x_can_exit(void)
1202 spi_unregister_driver(&mcp251x_can_driver
);
1205 module_init(mcp251x_can_init
);
1206 module_exit(mcp251x_can_exit
);
1208 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1209 "Christian Pellegrin <chripell@evolware.org>");
1210 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1211 MODULE_LICENSE("GPL v2");