2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 * Your platform definition file should specify something like:
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .model = CAN_MCP251X_MCP2510,
42 * .power_enable = mcp251x_power_enable,
43 * .transceiver_enable = NULL,
46 * static struct spi_board_info spi_board_info[] = {
48 * .modalias = "mcp251x",
49 * .platform_data = &mcp251x_info,
51 * .max_speed_hz = 2*1000*1000,
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
61 #include <linux/can.h>
62 #include <linux/can/core.h>
63 #include <linux/can/dev.h>
64 #include <linux/can/platform/mcp251x.h>
65 #include <linux/completion.h>
66 #include <linux/delay.h>
67 #include <linux/device.h>
68 #include <linux/dma-mapping.h>
69 #include <linux/freezer.h>
70 #include <linux/interrupt.h>
72 #include <linux/kernel.h>
73 #include <linux/module.h>
74 #include <linux/netdevice.h>
75 #include <linux/platform_device.h>
76 #include <linux/spi/spi.h>
77 #include <linux/uaccess.h>
79 /* SPI interface instruction set */
80 #define INSTRUCTION_WRITE 0x02
81 #define INSTRUCTION_READ 0x03
82 #define INSTRUCTION_BIT_MODIFY 0x05
83 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85 #define INSTRUCTION_RESET 0xC0
87 /* MPC251x registers */
90 # define CANCTRL_REQOP_MASK 0xe0
91 # define CANCTRL_REQOP_CONF 0x80
92 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
93 # define CANCTRL_REQOP_LOOPBACK 0x40
94 # define CANCTRL_REQOP_SLEEP 0x20
95 # define CANCTRL_REQOP_NORMAL 0x00
96 # define CANCTRL_OSM 0x08
97 # define CANCTRL_ABAT 0x10
101 # define CNF1_SJW_SHIFT 6
103 # define CNF2_BTLMODE 0x80
104 # define CNF2_SAM 0x40
105 # define CNF2_PS1_SHIFT 3
107 # define CNF3_SOF 0x08
108 # define CNF3_WAKFIL 0x04
109 # define CNF3_PHSEG2_MASK 0x07
111 # define CANINTE_MERRE 0x80
112 # define CANINTE_WAKIE 0x40
113 # define CANINTE_ERRIE 0x20
114 # define CANINTE_TX2IE 0x10
115 # define CANINTE_TX1IE 0x08
116 # define CANINTE_TX0IE 0x04
117 # define CANINTE_RX1IE 0x02
118 # define CANINTE_RX0IE 0x01
120 # define CANINTF_MERRF 0x80
121 # define CANINTF_WAKIF 0x40
122 # define CANINTF_ERRIF 0x20
123 # define CANINTF_TX2IF 0x10
124 # define CANINTF_TX1IF 0x08
125 # define CANINTF_TX0IF 0x04
126 # define CANINTF_RX1IF 0x02
127 # define CANINTF_RX0IF 0x01
129 # define EFLG_EWARN 0x01
130 # define EFLG_RXWAR 0x02
131 # define EFLG_TXWAR 0x04
132 # define EFLG_RXEP 0x08
133 # define EFLG_TXEP 0x10
134 # define EFLG_TXBO 0x20
135 # define EFLG_RX0OVR 0x40
136 # define EFLG_RX1OVR 0x80
137 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
138 # define TXBCTRL_ABTF 0x40
139 # define TXBCTRL_MLOA 0x20
140 # define TXBCTRL_TXERR 0x10
141 # define TXBCTRL_TXREQ 0x08
142 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
143 # define SIDH_SHIFT 3
144 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
145 # define SIDL_SID_MASK 7
146 # define SIDL_SID_SHIFT 5
147 # define SIDL_EXIDE_SHIFT 3
148 # define SIDL_EID_SHIFT 16
149 # define SIDL_EID_MASK 3
150 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
151 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
152 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
153 # define DLC_RTR_SHIFT 6
154 #define TXBCTRL_OFF 0
155 #define TXBSIDH_OFF 1
156 #define TXBSIDL_OFF 2
157 #define TXBEID8_OFF 3
158 #define TXBEID0_OFF 4
161 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
162 # define RXBCTRL_BUKT 0x04
163 # define RXBCTRL_RXM0 0x20
164 # define RXBCTRL_RXM1 0x40
165 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
166 # define RXBSIDH_SHIFT 3
167 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
168 # define RXBSIDL_IDE 0x08
169 # define RXBSIDL_EID 3
170 # define RXBSIDL_SHIFT 5
171 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
172 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
173 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
174 # define RXBDLC_LEN_MASK 0x0f
175 # define RXBDLC_RTR 0x40
176 #define RXBCTRL_OFF 0
177 #define RXBSIDH_OFF 1
178 #define RXBSIDL_OFF 2
179 #define RXBEID8_OFF 3
180 #define RXBEID0_OFF 4
184 #define GET_BYTE(val, byte) \
185 (((val) >> ((byte) * 8)) & 0xff)
186 #define SET_BYTE(val, byte) \
187 (((val) & 0xff) << ((byte) * 8))
190 * Buffer size required for the largest SPI transfer (i.e., reading a
193 #define CAN_FRAME_MAX_DATA_LEN 8
194 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
195 #define CAN_FRAME_MAX_BITS 128
197 #define TX_ECHO_SKB_MAX 1
199 #define DEVICE_NAME "mcp251x"
201 static int mcp251x_enable_dma
; /* Enable SPI DMA. Default: 0 (Off) */
202 module_param(mcp251x_enable_dma
, int, S_IRUGO
);
203 MODULE_PARM_DESC(mcp251x_enable_dma
, "Enable SPI DMA. Default: 0 (Off)");
205 static struct can_bittiming_const mcp251x_bittiming_const
= {
217 struct mcp251x_priv
{
219 struct net_device
*net
;
220 struct spi_device
*spi
;
222 struct mutex spi_lock
; /* SPI buffer lock */
225 dma_addr_t spi_tx_dma
;
226 dma_addr_t spi_rx_dma
;
228 struct sk_buff
*tx_skb
;
230 struct workqueue_struct
*wq
;
231 struct work_struct tx_work
;
232 struct work_struct irq_work
;
233 struct completion awake
;
237 #define AFTER_SUSPEND_UP 1
238 #define AFTER_SUSPEND_DOWN 2
239 #define AFTER_SUSPEND_POWER 4
240 #define AFTER_SUSPEND_RESTART 8
244 static void mcp251x_clean(struct net_device
*net
)
246 struct mcp251x_priv
*priv
= netdev_priv(net
);
248 net
->stats
.tx_errors
++;
250 dev_kfree_skb(priv
->tx_skb
);
252 can_free_echo_skb(priv
->net
, 0);
258 * Note about handling of error return of mcp251x_spi_trans: accessing
259 * registers via SPI is not really different conceptually than using
260 * normal I/O assembler instructions, although it's much more
261 * complicated from a practical POV. So it's not advisable to always
262 * check the return value of this function. Imagine that every
263 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
264 * error();", it would be a great mess (well there are some situation
265 * when exception handling C++ like could be useful after all). So we
266 * just check that transfers are OK at the beginning of our
267 * conversation with the chip and to avoid doing really nasty things
268 * (like injecting bogus packets in the network stack).
270 static int mcp251x_spi_trans(struct spi_device
*spi
, int len
)
272 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
273 struct spi_transfer t
= {
274 .tx_buf
= priv
->spi_tx_buf
,
275 .rx_buf
= priv
->spi_rx_buf
,
279 struct spi_message m
;
282 spi_message_init(&m
);
284 if (mcp251x_enable_dma
) {
285 t
.tx_dma
= priv
->spi_tx_dma
;
286 t
.rx_dma
= priv
->spi_rx_dma
;
290 spi_message_add_tail(&t
, &m
);
292 ret
= spi_sync(spi
, &m
);
294 dev_err(&spi
->dev
, "spi transfer failed: ret = %d\n", ret
);
298 static u8
mcp251x_read_reg(struct spi_device
*spi
, uint8_t reg
)
300 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
303 mutex_lock(&priv
->spi_lock
);
305 priv
->spi_tx_buf
[0] = INSTRUCTION_READ
;
306 priv
->spi_tx_buf
[1] = reg
;
308 mcp251x_spi_trans(spi
, 3);
309 val
= priv
->spi_rx_buf
[2];
311 mutex_unlock(&priv
->spi_lock
);
316 static void mcp251x_write_reg(struct spi_device
*spi
, u8 reg
, uint8_t val
)
318 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
320 mutex_lock(&priv
->spi_lock
);
322 priv
->spi_tx_buf
[0] = INSTRUCTION_WRITE
;
323 priv
->spi_tx_buf
[1] = reg
;
324 priv
->spi_tx_buf
[2] = val
;
326 mcp251x_spi_trans(spi
, 3);
328 mutex_unlock(&priv
->spi_lock
);
331 static void mcp251x_write_bits(struct spi_device
*spi
, u8 reg
,
332 u8 mask
, uint8_t val
)
334 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
336 mutex_lock(&priv
->spi_lock
);
338 priv
->spi_tx_buf
[0] = INSTRUCTION_BIT_MODIFY
;
339 priv
->spi_tx_buf
[1] = reg
;
340 priv
->spi_tx_buf
[2] = mask
;
341 priv
->spi_tx_buf
[3] = val
;
343 mcp251x_spi_trans(spi
, 4);
345 mutex_unlock(&priv
->spi_lock
);
348 static void mcp251x_hw_tx_frame(struct spi_device
*spi
, u8
*buf
,
349 int len
, int tx_buf_idx
)
351 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
352 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
354 if (pdata
->model
== CAN_MCP251X_MCP2510
) {
357 for (i
= 1; i
< TXBDAT_OFF
+ len
; i
++)
358 mcp251x_write_reg(spi
, TXBCTRL(tx_buf_idx
) + i
,
361 mutex_lock(&priv
->spi_lock
);
362 memcpy(priv
->spi_tx_buf
, buf
, TXBDAT_OFF
+ len
);
363 mcp251x_spi_trans(spi
, TXBDAT_OFF
+ len
);
364 mutex_unlock(&priv
->spi_lock
);
368 static void mcp251x_hw_tx(struct spi_device
*spi
, struct can_frame
*frame
,
371 u32 sid
, eid
, exide
, rtr
;
372 u8 buf
[SPI_TRANSFER_BUF_LEN
];
374 exide
= (frame
->can_id
& CAN_EFF_FLAG
) ? 1 : 0; /* Extended ID Enable */
376 sid
= (frame
->can_id
& CAN_EFF_MASK
) >> 18;
378 sid
= frame
->can_id
& CAN_SFF_MASK
; /* Standard ID */
379 eid
= frame
->can_id
& CAN_EFF_MASK
; /* Extended ID */
380 rtr
= (frame
->can_id
& CAN_RTR_FLAG
) ? 1 : 0; /* Remote transmission */
382 buf
[TXBCTRL_OFF
] = INSTRUCTION_LOAD_TXB(tx_buf_idx
);
383 buf
[TXBSIDH_OFF
] = sid
>> SIDH_SHIFT
;
384 buf
[TXBSIDL_OFF
] = ((sid
& SIDL_SID_MASK
) << SIDL_SID_SHIFT
) |
385 (exide
<< SIDL_EXIDE_SHIFT
) |
386 ((eid
>> SIDL_EID_SHIFT
) & SIDL_EID_MASK
);
387 buf
[TXBEID8_OFF
] = GET_BYTE(eid
, 1);
388 buf
[TXBEID0_OFF
] = GET_BYTE(eid
, 0);
389 buf
[TXBDLC_OFF
] = (rtr
<< DLC_RTR_SHIFT
) | frame
->can_dlc
;
390 memcpy(buf
+ TXBDAT_OFF
, frame
->data
, frame
->can_dlc
);
391 mcp251x_hw_tx_frame(spi
, buf
, frame
->can_dlc
, tx_buf_idx
);
392 mcp251x_write_reg(spi
, TXBCTRL(tx_buf_idx
), TXBCTRL_TXREQ
);
395 static void mcp251x_hw_rx_frame(struct spi_device
*spi
, u8
*buf
,
398 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
399 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
401 if (pdata
->model
== CAN_MCP251X_MCP2510
) {
404 for (i
= 1; i
< RXBDAT_OFF
; i
++)
405 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
407 len
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
408 for (; i
< (RXBDAT_OFF
+ len
); i
++)
409 buf
[i
] = mcp251x_read_reg(spi
, RXBCTRL(buf_idx
) + i
);
411 mutex_lock(&priv
->spi_lock
);
413 priv
->spi_tx_buf
[RXBCTRL_OFF
] = INSTRUCTION_READ_RXB(buf_idx
);
414 mcp251x_spi_trans(spi
, SPI_TRANSFER_BUF_LEN
);
415 memcpy(buf
, priv
->spi_rx_buf
, SPI_TRANSFER_BUF_LEN
);
417 mutex_unlock(&priv
->spi_lock
);
421 static void mcp251x_hw_rx(struct spi_device
*spi
, int buf_idx
)
423 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
425 struct can_frame
*frame
;
426 u8 buf
[SPI_TRANSFER_BUF_LEN
];
428 skb
= alloc_can_skb(priv
->net
, &frame
);
430 dev_err(&spi
->dev
, "cannot allocate RX skb\n");
431 priv
->net
->stats
.rx_dropped
++;
435 mcp251x_hw_rx_frame(spi
, buf
, buf_idx
);
436 if (buf
[RXBSIDL_OFF
] & RXBSIDL_IDE
) {
437 /* Extended ID format */
438 frame
->can_id
= CAN_EFF_FLAG
;
440 /* Extended ID part */
441 SET_BYTE(buf
[RXBSIDL_OFF
] & RXBSIDL_EID
, 2) |
442 SET_BYTE(buf
[RXBEID8_OFF
], 1) |
443 SET_BYTE(buf
[RXBEID0_OFF
], 0) |
444 /* Standard ID part */
445 (((buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
446 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
)) << 18);
447 /* Remote transmission request */
448 if (buf
[RXBDLC_OFF
] & RXBDLC_RTR
)
449 frame
->can_id
|= CAN_RTR_FLAG
;
451 /* Standard ID format */
453 (buf
[RXBSIDH_OFF
] << RXBSIDH_SHIFT
) |
454 (buf
[RXBSIDL_OFF
] >> RXBSIDL_SHIFT
);
457 frame
->can_dlc
= get_can_dlc(buf
[RXBDLC_OFF
] & RXBDLC_LEN_MASK
);
458 memcpy(frame
->data
, buf
+ RXBDAT_OFF
, frame
->can_dlc
);
460 priv
->net
->stats
.rx_packets
++;
461 priv
->net
->stats
.rx_bytes
+= frame
->can_dlc
;
465 static void mcp251x_hw_sleep(struct spi_device
*spi
)
467 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_SLEEP
);
470 static void mcp251x_hw_wakeup(struct spi_device
*spi
)
472 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
476 /* Can only wake up by generating a wake-up interrupt. */
477 mcp251x_write_bits(spi
, CANINTE
, CANINTE_WAKIE
, CANINTE_WAKIE
);
478 mcp251x_write_bits(spi
, CANINTF
, CANINTF_WAKIF
, CANINTF_WAKIF
);
480 /* Wait until the device is awake */
481 if (!wait_for_completion_timeout(&priv
->awake
, HZ
))
482 dev_err(&spi
->dev
, "MCP251x didn't wake-up\n");
485 static netdev_tx_t
mcp251x_hard_start_xmit(struct sk_buff
*skb
,
486 struct net_device
*net
)
488 struct mcp251x_priv
*priv
= netdev_priv(net
);
489 struct spi_device
*spi
= priv
->spi
;
491 if (priv
->tx_skb
|| priv
->tx_len
) {
492 dev_warn(&spi
->dev
, "hard_xmit called while tx busy\n");
493 netif_stop_queue(net
);
494 return NETDEV_TX_BUSY
;
497 if (skb
->len
!= sizeof(struct can_frame
)) {
498 dev_err(&spi
->dev
, "dropping packet - bad length\n");
500 net
->stats
.tx_dropped
++;
504 netif_stop_queue(net
);
506 net
->trans_start
= jiffies
;
507 queue_work(priv
->wq
, &priv
->tx_work
);
512 static int mcp251x_do_set_mode(struct net_device
*net
, enum can_mode mode
)
514 struct mcp251x_priv
*priv
= netdev_priv(net
);
518 /* We have to delay work since SPI I/O may sleep */
519 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
520 priv
->restart_tx
= 1;
521 if (priv
->can
.restart_ms
== 0)
522 priv
->after_suspend
= AFTER_SUSPEND_RESTART
;
523 queue_work(priv
->wq
, &priv
->irq_work
);
532 static void mcp251x_set_normal_mode(struct spi_device
*spi
)
534 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
535 unsigned long timeout
;
537 /* Enable interrupts */
538 mcp251x_write_reg(spi
, CANINTE
,
539 CANINTE_ERRIE
| CANINTE_TX2IE
| CANINTE_TX1IE
|
540 CANINTE_TX0IE
| CANINTE_RX1IE
| CANINTE_RX0IE
|
543 if (priv
->can
.ctrlmode
& CAN_CTRLMODE_LOOPBACK
) {
544 /* Put device into loopback mode */
545 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_LOOPBACK
);
547 /* Put device into normal mode */
548 mcp251x_write_reg(spi
, CANCTRL
, CANCTRL_REQOP_NORMAL
);
550 /* Wait for the device to enter normal mode */
551 timeout
= jiffies
+ HZ
;
552 while (mcp251x_read_reg(spi
, CANSTAT
) & CANCTRL_REQOP_MASK
) {
554 if (time_after(jiffies
, timeout
)) {
555 dev_err(&spi
->dev
, "MCP251x didn't"
556 " enter in normal mode\n");
561 priv
->can
.state
= CAN_STATE_ERROR_ACTIVE
;
564 static int mcp251x_do_set_bittiming(struct net_device
*net
)
566 struct mcp251x_priv
*priv
= netdev_priv(net
);
567 struct can_bittiming
*bt
= &priv
->can
.bittiming
;
568 struct spi_device
*spi
= priv
->spi
;
570 mcp251x_write_reg(spi
, CNF1
, ((bt
->sjw
- 1) << CNF1_SJW_SHIFT
) |
572 mcp251x_write_reg(spi
, CNF2
, CNF2_BTLMODE
|
573 (priv
->can
.ctrlmode
& CAN_CTRLMODE_3_SAMPLES
?
575 ((bt
->phase_seg1
- 1) << CNF2_PS1_SHIFT
) |
577 mcp251x_write_bits(spi
, CNF3
, CNF3_PHSEG2_MASK
,
578 (bt
->phase_seg2
- 1));
579 dev_info(&spi
->dev
, "CNF: 0x%02x 0x%02x 0x%02x\n",
580 mcp251x_read_reg(spi
, CNF1
),
581 mcp251x_read_reg(spi
, CNF2
),
582 mcp251x_read_reg(spi
, CNF3
));
587 static int mcp251x_setup(struct net_device
*net
, struct mcp251x_priv
*priv
,
588 struct spi_device
*spi
)
590 mcp251x_do_set_bittiming(net
);
592 /* Enable RX0->RX1 buffer roll over and disable filters */
593 mcp251x_write_bits(spi
, RXBCTRL(0),
594 RXBCTRL_BUKT
| RXBCTRL_RXM0
| RXBCTRL_RXM1
,
595 RXBCTRL_BUKT
| RXBCTRL_RXM0
| RXBCTRL_RXM1
);
596 mcp251x_write_bits(spi
, RXBCTRL(1),
597 RXBCTRL_RXM0
| RXBCTRL_RXM1
,
598 RXBCTRL_RXM0
| RXBCTRL_RXM1
);
602 static void mcp251x_hw_reset(struct spi_device
*spi
)
604 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
607 mutex_lock(&priv
->spi_lock
);
609 priv
->spi_tx_buf
[0] = INSTRUCTION_RESET
;
611 ret
= spi_write(spi
, priv
->spi_tx_buf
, 1);
613 mutex_unlock(&priv
->spi_lock
);
616 dev_err(&spi
->dev
, "reset failed: ret = %d\n", ret
);
617 /* Wait for reset to finish */
621 static int mcp251x_hw_probe(struct spi_device
*spi
)
625 mcp251x_hw_reset(spi
);
628 * Please note that these are "magic values" based on after
629 * reset defaults taken from data sheet which allows us to see
630 * if we really have a chip on the bus (we avoid common all
631 * zeroes or all ones situations)
633 st1
= mcp251x_read_reg(spi
, CANSTAT
) & 0xEE;
634 st2
= mcp251x_read_reg(spi
, CANCTRL
) & 0x17;
636 dev_dbg(&spi
->dev
, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1
, st2
);
638 /* Check for power up default values */
639 return (st1
== 0x80 && st2
== 0x07) ? 1 : 0;
642 static irqreturn_t
mcp251x_can_isr(int irq
, void *dev_id
)
644 struct net_device
*net
= (struct net_device
*)dev_id
;
645 struct mcp251x_priv
*priv
= netdev_priv(net
);
647 /* Schedule bottom half */
648 if (!work_pending(&priv
->irq_work
))
649 queue_work(priv
->wq
, &priv
->irq_work
);
654 static int mcp251x_open(struct net_device
*net
)
656 struct mcp251x_priv
*priv
= netdev_priv(net
);
657 struct spi_device
*spi
= priv
->spi
;
658 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
661 ret
= open_candev(net
);
663 dev_err(&spi
->dev
, "unable to set initial baudrate!\n");
667 if (pdata
->transceiver_enable
)
668 pdata
->transceiver_enable(1);
670 priv
->force_quit
= 0;
674 ret
= request_irq(spi
->irq
, mcp251x_can_isr
,
675 IRQF_TRIGGER_FALLING
, DEVICE_NAME
, net
);
677 dev_err(&spi
->dev
, "failed to acquire irq %d\n", spi
->irq
);
678 if (pdata
->transceiver_enable
)
679 pdata
->transceiver_enable(0);
684 mcp251x_hw_wakeup(spi
);
685 mcp251x_hw_reset(spi
);
686 ret
= mcp251x_setup(net
, priv
, spi
);
688 free_irq(spi
->irq
, net
);
689 mcp251x_hw_sleep(spi
);
690 if (pdata
->transceiver_enable
)
691 pdata
->transceiver_enable(0);
695 mcp251x_set_normal_mode(spi
);
696 netif_wake_queue(net
);
701 static int mcp251x_stop(struct net_device
*net
)
703 struct mcp251x_priv
*priv
= netdev_priv(net
);
704 struct spi_device
*spi
= priv
->spi
;
705 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
709 /* Disable and clear pending interrupts */
710 mcp251x_write_reg(spi
, CANINTE
, 0x00);
711 mcp251x_write_reg(spi
, CANINTF
, 0x00);
713 priv
->force_quit
= 1;
714 free_irq(spi
->irq
, net
);
715 flush_workqueue(priv
->wq
);
717 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
718 if (priv
->tx_skb
|| priv
->tx_len
)
721 mcp251x_hw_sleep(spi
);
723 if (pdata
->transceiver_enable
)
724 pdata
->transceiver_enable(0);
726 priv
->can
.state
= CAN_STATE_STOPPED
;
731 static void mcp251x_tx_work_handler(struct work_struct
*ws
)
733 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
735 struct spi_device
*spi
= priv
->spi
;
736 struct net_device
*net
= priv
->net
;
737 struct can_frame
*frame
;
740 frame
= (struct can_frame
*)priv
->tx_skb
->data
;
742 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
744 netif_wake_queue(net
);
747 if (frame
->can_dlc
> CAN_FRAME_MAX_DATA_LEN
)
748 frame
->can_dlc
= CAN_FRAME_MAX_DATA_LEN
;
749 mcp251x_hw_tx(spi
, frame
, 0);
750 priv
->tx_len
= 1 + frame
->can_dlc
;
751 can_put_echo_skb(priv
->tx_skb
, net
, 0);
756 static void mcp251x_irq_work_handler(struct work_struct
*ws
)
758 struct mcp251x_priv
*priv
= container_of(ws
, struct mcp251x_priv
,
760 struct spi_device
*spi
= priv
->spi
;
761 struct net_device
*net
= priv
->net
;
764 enum can_state new_state
;
766 if (priv
->after_suspend
) {
768 mcp251x_hw_reset(spi
);
769 mcp251x_setup(net
, priv
, spi
);
770 if (priv
->after_suspend
& AFTER_SUSPEND_RESTART
) {
771 mcp251x_set_normal_mode(spi
);
772 } else if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
773 netif_device_attach(net
);
774 /* Clean since we lost tx buffer */
775 if (priv
->tx_skb
|| priv
->tx_len
) {
777 netif_wake_queue(net
);
779 mcp251x_set_normal_mode(spi
);
781 mcp251x_hw_sleep(spi
);
783 priv
->after_suspend
= 0;
786 if (priv
->can
.restart_ms
== 0 && priv
->can
.state
== CAN_STATE_BUS_OFF
)
789 while (!priv
->force_quit
&& !freezing(current
)) {
790 u8 eflag
= mcp251x_read_reg(spi
, EFLG
);
791 int can_id
= 0, data1
= 0;
793 mcp251x_write_reg(spi
, EFLG
, 0x00);
795 if (priv
->restart_tx
) {
796 priv
->restart_tx
= 0;
797 mcp251x_write_reg(spi
, TXBCTRL(0), 0);
798 if (priv
->tx_skb
|| priv
->tx_len
)
800 netif_wake_queue(net
);
801 can_id
|= CAN_ERR_RESTARTED
;
805 /* Wait whilst the device wakes up */
810 intf
= mcp251x_read_reg(spi
, CANINTF
);
811 mcp251x_write_bits(spi
, CANINTF
, intf
, 0x00);
813 /* Update can state */
814 if (eflag
& EFLG_TXBO
) {
815 new_state
= CAN_STATE_BUS_OFF
;
816 can_id
|= CAN_ERR_BUSOFF
;
817 } else if (eflag
& EFLG_TXEP
) {
818 new_state
= CAN_STATE_ERROR_PASSIVE
;
819 can_id
|= CAN_ERR_CRTL
;
820 data1
|= CAN_ERR_CRTL_TX_PASSIVE
;
821 } else if (eflag
& EFLG_RXEP
) {
822 new_state
= CAN_STATE_ERROR_PASSIVE
;
823 can_id
|= CAN_ERR_CRTL
;
824 data1
|= CAN_ERR_CRTL_RX_PASSIVE
;
825 } else if (eflag
& EFLG_TXWAR
) {
826 new_state
= CAN_STATE_ERROR_WARNING
;
827 can_id
|= CAN_ERR_CRTL
;
828 data1
|= CAN_ERR_CRTL_TX_WARNING
;
829 } else if (eflag
& EFLG_RXWAR
) {
830 new_state
= CAN_STATE_ERROR_WARNING
;
831 can_id
|= CAN_ERR_CRTL
;
832 data1
|= CAN_ERR_CRTL_RX_WARNING
;
834 new_state
= CAN_STATE_ERROR_ACTIVE
;
837 /* Update can state statistics */
838 switch (priv
->can
.state
) {
839 case CAN_STATE_ERROR_ACTIVE
:
840 if (new_state
>= CAN_STATE_ERROR_WARNING
&&
841 new_state
<= CAN_STATE_BUS_OFF
)
842 priv
->can
.can_stats
.error_warning
++;
843 case CAN_STATE_ERROR_WARNING
: /* fallthrough */
844 if (new_state
>= CAN_STATE_ERROR_PASSIVE
&&
845 new_state
<= CAN_STATE_BUS_OFF
)
846 priv
->can
.can_stats
.error_passive
++;
851 priv
->can
.state
= new_state
;
853 if ((intf
& CANINTF_ERRIF
) || (can_id
& CAN_ERR_RESTARTED
)) {
855 struct can_frame
*frame
;
857 /* Create error frame */
858 skb
= alloc_can_err_skb(net
, &frame
);
860 /* Set error frame flags based on bus state */
861 frame
->can_id
= can_id
;
862 frame
->data
[1] = data1
;
864 /* Update net stats for overflows */
865 if (eflag
& (EFLG_RX0OVR
| EFLG_RX1OVR
)) {
866 if (eflag
& EFLG_RX0OVR
)
867 net
->stats
.rx_over_errors
++;
868 if (eflag
& EFLG_RX1OVR
)
869 net
->stats
.rx_over_errors
++;
870 frame
->can_id
|= CAN_ERR_CRTL
;
872 CAN_ERR_CRTL_RX_OVERFLOW
;
878 "cannot allocate error skb\n");
882 if (priv
->can
.state
== CAN_STATE_BUS_OFF
) {
883 if (priv
->can
.restart_ms
== 0) {
885 mcp251x_hw_sleep(spi
);
893 if (intf
& CANINTF_WAKIF
)
894 complete(&priv
->awake
);
896 if (intf
& CANINTF_MERRF
) {
897 /* If there are pending Tx buffers, restart queue */
898 txbnctrl
= mcp251x_read_reg(spi
, TXBCTRL(0));
899 if (!(txbnctrl
& TXBCTRL_TXREQ
)) {
900 if (priv
->tx_skb
|| priv
->tx_len
)
902 netif_wake_queue(net
);
906 if (intf
& (CANINTF_TX2IF
| CANINTF_TX1IF
| CANINTF_TX0IF
)) {
907 net
->stats
.tx_packets
++;
908 net
->stats
.tx_bytes
+= priv
->tx_len
- 1;
910 can_get_echo_skb(net
, 0);
913 netif_wake_queue(net
);
916 if (intf
& CANINTF_RX0IF
)
917 mcp251x_hw_rx(spi
, 0);
919 if (intf
& CANINTF_RX1IF
)
920 mcp251x_hw_rx(spi
, 1);
924 static const struct net_device_ops mcp251x_netdev_ops
= {
925 .ndo_open
= mcp251x_open
,
926 .ndo_stop
= mcp251x_stop
,
927 .ndo_start_xmit
= mcp251x_hard_start_xmit
,
930 static int __devinit
mcp251x_can_probe(struct spi_device
*spi
)
932 struct net_device
*net
;
933 struct mcp251x_priv
*priv
;
934 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
938 /* Platform data is required for osc freq */
941 /* Allocate can/net device */
942 net
= alloc_candev(sizeof(struct mcp251x_priv
), TX_ECHO_SKB_MAX
);
948 net
->netdev_ops
= &mcp251x_netdev_ops
;
949 net
->flags
|= IFF_ECHO
;
951 priv
= netdev_priv(net
);
952 priv
->can
.bittiming_const
= &mcp251x_bittiming_const
;
953 priv
->can
.do_set_mode
= mcp251x_do_set_mode
;
954 priv
->can
.clock
.freq
= pdata
->oscillator_frequency
/ 2;
956 dev_set_drvdata(&spi
->dev
, priv
);
959 mutex_init(&priv
->spi_lock
);
961 /* If requested, allocate DMA buffers */
962 if (mcp251x_enable_dma
) {
963 spi
->dev
.coherent_dma_mask
= ~0;
966 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
967 * that much and share it between Tx and Rx DMA buffers.
969 priv
->spi_tx_buf
= dma_alloc_coherent(&spi
->dev
,
974 if (priv
->spi_tx_buf
) {
975 priv
->spi_rx_buf
= (u8
*)(priv
->spi_tx_buf
+
977 priv
->spi_rx_dma
= (dma_addr_t
)(priv
->spi_tx_dma
+
980 /* Fall back to non-DMA */
981 mcp251x_enable_dma
= 0;
985 /* Allocate non-DMA buffers */
986 if (!mcp251x_enable_dma
) {
987 priv
->spi_tx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
988 if (!priv
->spi_tx_buf
) {
992 priv
->spi_rx_buf
= kmalloc(SPI_TRANSFER_BUF_LEN
, GFP_KERNEL
);
993 if (!priv
->spi_tx_buf
) {
999 if (pdata
->power_enable
)
1000 pdata
->power_enable(1);
1002 /* Call out to platform specific setup */
1003 if (pdata
->board_specific_setup
)
1004 pdata
->board_specific_setup(spi
);
1006 SET_NETDEV_DEV(net
, &spi
->dev
);
1008 priv
->wq
= create_freezeable_workqueue("mcp251x_wq");
1010 INIT_WORK(&priv
->tx_work
, mcp251x_tx_work_handler
);
1011 INIT_WORK(&priv
->irq_work
, mcp251x_irq_work_handler
);
1013 init_completion(&priv
->awake
);
1015 /* Configure the SPI bus */
1016 spi
->mode
= SPI_MODE_0
;
1017 spi
->bits_per_word
= 8;
1020 if (!mcp251x_hw_probe(spi
)) {
1021 dev_info(&spi
->dev
, "Probe failed\n");
1024 mcp251x_hw_sleep(spi
);
1026 if (pdata
->transceiver_enable
)
1027 pdata
->transceiver_enable(0);
1029 ret
= register_candev(net
);
1031 dev_info(&spi
->dev
, "probed\n");
1035 if (!mcp251x_enable_dma
)
1036 kfree(priv
->spi_rx_buf
);
1038 if (!mcp251x_enable_dma
)
1039 kfree(priv
->spi_tx_buf
);
1042 if (mcp251x_enable_dma
)
1043 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1044 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1046 if (pdata
->power_enable
)
1047 pdata
->power_enable(0);
1048 dev_err(&spi
->dev
, "probe failed\n");
1053 static int __devexit
mcp251x_can_remove(struct spi_device
*spi
)
1055 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1056 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1057 struct net_device
*net
= priv
->net
;
1059 unregister_candev(net
);
1062 priv
->force_quit
= 1;
1063 flush_workqueue(priv
->wq
);
1064 destroy_workqueue(priv
->wq
);
1066 if (mcp251x_enable_dma
) {
1067 dma_free_coherent(&spi
->dev
, PAGE_SIZE
,
1068 priv
->spi_tx_buf
, priv
->spi_tx_dma
);
1070 kfree(priv
->spi_tx_buf
);
1071 kfree(priv
->spi_rx_buf
);
1074 if (pdata
->power_enable
)
1075 pdata
->power_enable(0);
1081 static int mcp251x_can_suspend(struct spi_device
*spi
, pm_message_t state
)
1083 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1084 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1085 struct net_device
*net
= priv
->net
;
1087 if (netif_running(net
)) {
1088 netif_device_detach(net
);
1090 mcp251x_hw_sleep(spi
);
1091 if (pdata
->transceiver_enable
)
1092 pdata
->transceiver_enable(0);
1093 priv
->after_suspend
= AFTER_SUSPEND_UP
;
1095 priv
->after_suspend
= AFTER_SUSPEND_DOWN
;
1098 if (pdata
->power_enable
) {
1099 pdata
->power_enable(0);
1100 priv
->after_suspend
|= AFTER_SUSPEND_POWER
;
1106 static int mcp251x_can_resume(struct spi_device
*spi
)
1108 struct mcp251x_platform_data
*pdata
= spi
->dev
.platform_data
;
1109 struct mcp251x_priv
*priv
= dev_get_drvdata(&spi
->dev
);
1111 if (priv
->after_suspend
& AFTER_SUSPEND_POWER
) {
1112 pdata
->power_enable(1);
1113 queue_work(priv
->wq
, &priv
->irq_work
);
1115 if (priv
->after_suspend
& AFTER_SUSPEND_UP
) {
1116 if (pdata
->transceiver_enable
)
1117 pdata
->transceiver_enable(1);
1118 queue_work(priv
->wq
, &priv
->irq_work
);
1120 priv
->after_suspend
= 0;
1126 #define mcp251x_can_suspend NULL
1127 #define mcp251x_can_resume NULL
1130 static struct spi_driver mcp251x_can_driver
= {
1132 .name
= DEVICE_NAME
,
1133 .bus
= &spi_bus_type
,
1134 .owner
= THIS_MODULE
,
1137 .probe
= mcp251x_can_probe
,
1138 .remove
= __devexit_p(mcp251x_can_remove
),
1139 .suspend
= mcp251x_can_suspend
,
1140 .resume
= mcp251x_can_resume
,
1143 static int __init
mcp251x_can_init(void)
1145 return spi_register_driver(&mcp251x_can_driver
);
1148 static void __exit
mcp251x_can_exit(void)
1150 spi_unregister_driver(&mcp251x_can_driver
);
1153 module_init(mcp251x_can_init
);
1154 module_exit(mcp251x_can_exit
);
1156 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1157 "Christian Pellegrin <chripell@evolware.org>");
1158 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1159 MODULE_LICENSE("GPL v2");