1 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
3 * Copyright (C) 2004 Sun Microsystems Inc.
4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
21 * This driver uses the sungem driver (c) David Miller
22 * (davem@redhat.com) as its basis.
24 * The cassini chip has a number of features that distinguish it from
26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or
27 * load balancing (non-VLAN mode)
28 * batching of multiple packets
29 * multiple CPU dispatching
30 * page-based RX descriptor engine with separate completion rings
31 * Gigabit support (GMII and PCS interface)
32 * MIF link up/down detection works
34 * RX is handled by page sized buffers that are attached as fragments to
35 * the skb. here's what's done:
36 * -- driver allocates pages at a time and keeps reference counts
38 * -- the upper protocol layers assume that the header is in the skb
39 * itself. as a result, cassini will copy a small amount (64 bytes)
41 * -- driver appends the rest of the data pages as frags to skbuffs
42 * and increments the reference count
43 * -- on page reclamation, the driver swaps the page with a spare page.
44 * if that page is still in use, it frees its reference to that page,
45 * and allocates a new page for use. otherwise, it just recycles the
48 * NOTE: cassini can parse the header. however, it's not worth it
49 * as long as the network stack requires a header copy.
51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targetted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose
58 * RX DATA: the rx completion ring has all the info, but the rx desc
59 * ring has all of the data. RX can conceivably come in under multiple
60 * interrupts, but the INT# assignment needs to be set up properly by
61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
62 * that. also, the two descriptor rings are designed to distinguish between
63 * encrypted and non-encrypted packets, but we use them for buffering
66 * by default, the selective clear mask is set up to process rx packets.
69 #include <linux/config.h>
70 #include <linux/version.h>
72 #include <linux/module.h>
73 #include <linux/kernel.h>
74 #include <linux/types.h>
75 #include <linux/compiler.h>
76 #include <linux/slab.h>
77 #include <linux/delay.h>
78 #include <linux/init.h>
79 #include <linux/ioport.h>
80 #include <linux/pci.h>
82 #include <linux/highmem.h>
83 #include <linux/list.h>
84 #include <linux/dma-mapping.h>
86 #include <linux/netdevice.h>
87 #include <linux/etherdevice.h>
88 #include <linux/skbuff.h>
89 #include <linux/ethtool.h>
90 #include <linux/crc32.h>
91 #include <linux/random.h>
92 #include <linux/mii.h>
94 #include <linux/tcp.h>
96 #include <net/checksum.h>
98 #include <asm/atomic.h>
99 #include <asm/system.h>
101 #include <asm/byteorder.h>
102 #include <asm/uaccess.h>
104 #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
105 #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
106 #define CAS_NCPUS num_online_cpus()
108 #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
110 #define cas_skb_release(x) netif_receive_skb(x)
112 #define cas_skb_release(x) netif_rx(x)
115 /* select which firmware to use */
116 #define USE_HP_WORKAROUND
117 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
118 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
122 #define USE_TX_COMPWB /* use completion writeback registers */
123 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
124 #define USE_RX_BLANK /* hw interrupt mitigation */
125 #undef USE_ENTROPY_DEV /* don't test for entropy device */
127 /* NOTE: these aren't useable unless PCI interrupts can be assigned.
128 * also, we need to make cp->lock finer-grained.
135 #undef USE_VPD_DEBUG /* debug vpd information if defined */
137 /* rx processing options */
138 #define USE_PAGE_ORDER /* specify to allocate large rx pages */
139 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
140 #define RX_COPY_ALWAYS 0 /* if 0, use frags */
141 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
142 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
144 #define DRV_MODULE_NAME "cassini"
145 #define PFX DRV_MODULE_NAME ": "
146 #define DRV_MODULE_VERSION "1.4"
147 #define DRV_MODULE_RELDATE "1 July 2004"
149 #define CAS_DEF_MSG_ENABLE \
159 /* length of time before we decide the hardware is borked,
160 * and dev->tx_timeout() should be called to fix the problem
162 #define CAS_TX_TIMEOUT (HZ)
163 #define CAS_LINK_TIMEOUT (22*HZ/10)
164 #define CAS_LINK_FAST_TIMEOUT (1)
166 /* timeout values for state changing. these specify the number
167 * of 10us delays to be used before giving up.
169 #define STOP_TRIES_PHY 1000
170 #define STOP_TRIES 5000
172 /* specify a minimum frame size to deal with some fifo issues
173 * max mtu == 2 * page size - ethernet header - 64 - swivel =
174 * 2 * page_size - 0x50
176 #define CAS_MIN_FRAME 97
177 #define CAS_1000MB_MIN_FRAME 255
178 #define CAS_MIN_MTU 60
179 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
183 * Eliminate these and use separate atomic counters for each, to
184 * avoid a race condition.
187 #define CAS_RESET_MTU 1
188 #define CAS_RESET_ALL 2
189 #define CAS_RESET_SPARE 3
192 static char version
[] __devinitdata
=
193 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
195 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
196 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
197 MODULE_LICENSE("GPL");
198 MODULE_PARM(cassini_debug
, "i");
199 MODULE_PARM_DESC(cassini_debug
, "Cassini bitmapped debugging message enable value");
200 MODULE_PARM(link_mode
, "i");
201 MODULE_PARM_DESC(link_mode
, "default link mode");
204 * Work around for a PCS bug in which the link goes down due to the chip
205 * being confused and never showing a link status of "up."
207 #define DEFAULT_LINKDOWN_TIMEOUT 5
209 * Value in seconds, for user input.
211 static int linkdown_timeout
= DEFAULT_LINKDOWN_TIMEOUT
;
212 MODULE_PARM(linkdown_timeout
, "i");
213 MODULE_PARM_DESC(linkdown_timeout
,
214 "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
217 * value in 'ticks' (units used by jiffies). Set when we init the
218 * module because 'HZ' in actually a function call on some flavors of
219 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
221 static int link_transition_timeout
;
224 static int cassini_debug
= -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
225 static int link_mode
;
227 static u16 link_modes
[] __devinitdata
= {
228 BMCR_ANENABLE
, /* 0 : autoneg */
229 0, /* 1 : 10bt half duplex */
230 BMCR_SPEED100
, /* 2 : 100bt half duplex */
231 BMCR_FULLDPLX
, /* 3 : 10bt full duplex */
232 BMCR_SPEED100
|BMCR_FULLDPLX
, /* 4 : 100bt full duplex */
233 CAS_BMCR_SPEED1000
|BMCR_FULLDPLX
/* 5 : 1000bt full duplex */
236 static struct pci_device_id cas_pci_tbl
[] __devinitdata
= {
237 { PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_CASSINI
,
238 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
239 { PCI_VENDOR_ID_NS
, PCI_DEVICE_ID_NS_SATURN
,
240 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
244 MODULE_DEVICE_TABLE(pci
, cas_pci_tbl
);
246 static void cas_set_link_modes(struct cas
*cp
);
248 static inline void cas_lock_tx(struct cas
*cp
)
252 for (i
= 0; i
< N_TX_RINGS
; i
++)
253 spin_lock(&cp
->tx_lock
[i
]);
256 static inline void cas_lock_all(struct cas
*cp
)
258 spin_lock_irq(&cp
->lock
);
262 /* WTZ: QA was finding deadlock problems with the previous
263 * versions after long test runs with multiple cards per machine.
264 * See if replacing cas_lock_all with safer versions helps. The
265 * symptoms QA is reporting match those we'd expect if interrupts
266 * aren't being properly restored, and we fixed a previous deadlock
267 * with similar symptoms by using save/restore versions in other
270 #define cas_lock_all_save(cp, flags) \
272 struct cas *xxxcp = (cp); \
273 spin_lock_irqsave(&xxxcp->lock, flags); \
274 cas_lock_tx(xxxcp); \
277 static inline void cas_unlock_tx(struct cas
*cp
)
281 for (i
= N_TX_RINGS
; i
> 0; i
--)
282 spin_unlock(&cp
->tx_lock
[i
- 1]);
285 static inline void cas_unlock_all(struct cas
*cp
)
288 spin_unlock_irq(&cp
->lock
);
291 #define cas_unlock_all_restore(cp, flags) \
293 struct cas *xxxcp = (cp); \
294 cas_unlock_tx(xxxcp); \
295 spin_unlock_irqrestore(&xxxcp->lock, flags); \
298 static void cas_disable_irq(struct cas
*cp
, const int ring
)
300 /* Make sure we won't get any more interrupts */
302 writel(0xFFFFFFFF, cp
->regs
+ REG_INTR_MASK
);
306 /* disable completion interrupts and selectively mask */
307 if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) {
309 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
319 writel(INTRN_MASK_CLEAR_ALL
| INTRN_MASK_RX_EN
,
320 cp
->regs
+ REG_PLUS_INTRN_MASK(ring
));
324 writel(INTRN_MASK_CLEAR_ALL
, cp
->regs
+
325 REG_PLUS_INTRN_MASK(ring
));
331 static inline void cas_mask_intr(struct cas
*cp
)
335 for (i
= 0; i
< N_RX_COMP_RINGS
; i
++)
336 cas_disable_irq(cp
, i
);
339 static void cas_enable_irq(struct cas
*cp
, const int ring
)
341 if (ring
== 0) { /* all but TX_DONE */
342 writel(INTR_TX_DONE
, cp
->regs
+ REG_INTR_MASK
);
346 if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) {
348 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
358 writel(INTRN_MASK_RX_EN
, cp
->regs
+
359 REG_PLUS_INTRN_MASK(ring
));
368 static inline void cas_unmask_intr(struct cas
*cp
)
372 for (i
= 0; i
< N_RX_COMP_RINGS
; i
++)
373 cas_enable_irq(cp
, i
);
376 static inline void cas_entropy_gather(struct cas
*cp
)
378 #ifdef USE_ENTROPY_DEV
379 if ((cp
->cas_flags
& CAS_FLAG_ENTROPY_DEV
) == 0)
382 batch_entropy_store(readl(cp
->regs
+ REG_ENTROPY_IV
),
383 readl(cp
->regs
+ REG_ENTROPY_IV
),
388 static inline void cas_entropy_reset(struct cas
*cp
)
390 #ifdef USE_ENTROPY_DEV
391 if ((cp
->cas_flags
& CAS_FLAG_ENTROPY_DEV
) == 0)
394 writel(BIM_LOCAL_DEV_PAD
| BIM_LOCAL_DEV_PROM
| BIM_LOCAL_DEV_EXT
,
395 cp
->regs
+ REG_BIM_LOCAL_DEV_EN
);
396 writeb(ENTROPY_RESET_STC_MODE
, cp
->regs
+ REG_ENTROPY_RESET
);
397 writeb(0x55, cp
->regs
+ REG_ENTROPY_RAND_REG
);
399 /* if we read back 0x0, we don't have an entropy device */
400 if (readb(cp
->regs
+ REG_ENTROPY_RAND_REG
) == 0)
401 cp
->cas_flags
&= ~CAS_FLAG_ENTROPY_DEV
;
405 /* access to the phy. the following assumes that we've initialized the MIF to
406 * be in frame rather than bit-bang mode
408 static u16
cas_phy_read(struct cas
*cp
, int reg
)
411 int limit
= STOP_TRIES_PHY
;
413 cmd
= MIF_FRAME_ST
| MIF_FRAME_OP_READ
;
414 cmd
|= CAS_BASE(MIF_FRAME_PHY_ADDR
, cp
->phy_addr
);
415 cmd
|= CAS_BASE(MIF_FRAME_REG_ADDR
, reg
);
416 cmd
|= MIF_FRAME_TURN_AROUND_MSB
;
417 writel(cmd
, cp
->regs
+ REG_MIF_FRAME
);
419 /* poll for completion */
420 while (limit
-- > 0) {
422 cmd
= readl(cp
->regs
+ REG_MIF_FRAME
);
423 if (cmd
& MIF_FRAME_TURN_AROUND_LSB
)
424 return (cmd
& MIF_FRAME_DATA_MASK
);
426 return 0xFFFF; /* -1 */
429 static int cas_phy_write(struct cas
*cp
, int reg
, u16 val
)
431 int limit
= STOP_TRIES_PHY
;
434 cmd
= MIF_FRAME_ST
| MIF_FRAME_OP_WRITE
;
435 cmd
|= CAS_BASE(MIF_FRAME_PHY_ADDR
, cp
->phy_addr
);
436 cmd
|= CAS_BASE(MIF_FRAME_REG_ADDR
, reg
);
437 cmd
|= MIF_FRAME_TURN_AROUND_MSB
;
438 cmd
|= val
& MIF_FRAME_DATA_MASK
;
439 writel(cmd
, cp
->regs
+ REG_MIF_FRAME
);
441 /* poll for completion */
442 while (limit
-- > 0) {
444 cmd
= readl(cp
->regs
+ REG_MIF_FRAME
);
445 if (cmd
& MIF_FRAME_TURN_AROUND_LSB
)
451 static void cas_phy_powerup(struct cas
*cp
)
453 u16 ctl
= cas_phy_read(cp
, MII_BMCR
);
455 if ((ctl
& BMCR_PDOWN
) == 0)
458 cas_phy_write(cp
, MII_BMCR
, ctl
);
461 static void cas_phy_powerdown(struct cas
*cp
)
463 u16 ctl
= cas_phy_read(cp
, MII_BMCR
);
465 if (ctl
& BMCR_PDOWN
)
468 cas_phy_write(cp
, MII_BMCR
, ctl
);
471 /* cp->lock held. note: the last put_page will free the buffer */
472 static int cas_page_free(struct cas
*cp
, cas_page_t
*page
)
474 pci_unmap_page(cp
->pdev
, page
->dma_addr
, cp
->page_size
,
476 __free_pages(page
->buffer
, cp
->page_order
);
481 #ifdef RX_COUNT_BUFFERS
482 #define RX_USED_ADD(x, y) ((x)->used += (y))
483 #define RX_USED_SET(x, y) ((x)->used = (y))
485 #define RX_USED_ADD(x, y)
486 #define RX_USED_SET(x, y)
489 /* local page allocation routines for the receive buffers. jumbo pages
490 * require at least 8K contiguous and 8K aligned buffers.
492 static cas_page_t
*cas_page_alloc(struct cas
*cp
, const int flags
)
496 page
= kmalloc(sizeof(cas_page_t
), flags
);
500 INIT_LIST_HEAD(&page
->list
);
501 RX_USED_SET(page
, 0);
502 page
->buffer
= alloc_pages(flags
, cp
->page_order
);
505 page
->dma_addr
= pci_map_page(cp
->pdev
, page
->buffer
, 0,
506 cp
->page_size
, PCI_DMA_FROMDEVICE
);
514 /* initialize spare pool of rx buffers, but allocate during the open */
515 static void cas_spare_init(struct cas
*cp
)
517 spin_lock(&cp
->rx_inuse_lock
);
518 INIT_LIST_HEAD(&cp
->rx_inuse_list
);
519 spin_unlock(&cp
->rx_inuse_lock
);
521 spin_lock(&cp
->rx_spare_lock
);
522 INIT_LIST_HEAD(&cp
->rx_spare_list
);
523 cp
->rx_spares_needed
= RX_SPARE_COUNT
;
524 spin_unlock(&cp
->rx_spare_lock
);
527 /* used on close. free all the spare buffers. */
528 static void cas_spare_free(struct cas
*cp
)
530 struct list_head list
, *elem
, *tmp
;
532 /* free spare buffers */
533 INIT_LIST_HEAD(&list
);
534 spin_lock(&cp
->rx_spare_lock
);
535 list_splice(&cp
->rx_spare_list
, &list
);
536 INIT_LIST_HEAD(&cp
->rx_spare_list
);
537 spin_unlock(&cp
->rx_spare_lock
);
538 list_for_each_safe(elem
, tmp
, &list
) {
539 cas_page_free(cp
, list_entry(elem
, cas_page_t
, list
));
542 INIT_LIST_HEAD(&list
);
545 * Looks like Adrian had protected this with a different
546 * lock than used everywhere else to manipulate this list.
548 spin_lock(&cp
->rx_inuse_lock
);
549 list_splice(&cp
->rx_inuse_list
, &list
);
550 INIT_LIST_HEAD(&cp
->rx_inuse_list
);
551 spin_unlock(&cp
->rx_inuse_lock
);
553 spin_lock(&cp
->rx_spare_lock
);
554 list_splice(&cp
->rx_inuse_list
, &list
);
555 INIT_LIST_HEAD(&cp
->rx_inuse_list
);
556 spin_unlock(&cp
->rx_spare_lock
);
558 list_for_each_safe(elem
, tmp
, &list
) {
559 cas_page_free(cp
, list_entry(elem
, cas_page_t
, list
));
563 /* replenish spares if needed */
564 static void cas_spare_recover(struct cas
*cp
, const int flags
)
566 struct list_head list
, *elem
, *tmp
;
569 /* check inuse list. if we don't need any more free buffers,
573 /* make a local copy of the list */
574 INIT_LIST_HEAD(&list
);
575 spin_lock(&cp
->rx_inuse_lock
);
576 list_splice(&cp
->rx_inuse_list
, &list
);
577 INIT_LIST_HEAD(&cp
->rx_inuse_list
);
578 spin_unlock(&cp
->rx_inuse_lock
);
580 list_for_each_safe(elem
, tmp
, &list
) {
581 cas_page_t
*page
= list_entry(elem
, cas_page_t
, list
);
583 if (page_count(page
->buffer
) > 1)
587 spin_lock(&cp
->rx_spare_lock
);
588 if (cp
->rx_spares_needed
> 0) {
589 list_add(elem
, &cp
->rx_spare_list
);
590 cp
->rx_spares_needed
--;
591 spin_unlock(&cp
->rx_spare_lock
);
593 spin_unlock(&cp
->rx_spare_lock
);
594 cas_page_free(cp
, page
);
598 /* put any inuse buffers back on the list */
599 if (!list_empty(&list
)) {
600 spin_lock(&cp
->rx_inuse_lock
);
601 list_splice(&list
, &cp
->rx_inuse_list
);
602 spin_unlock(&cp
->rx_inuse_lock
);
605 spin_lock(&cp
->rx_spare_lock
);
606 needed
= cp
->rx_spares_needed
;
607 spin_unlock(&cp
->rx_spare_lock
);
611 /* we still need spares, so try to allocate some */
612 INIT_LIST_HEAD(&list
);
615 cas_page_t
*spare
= cas_page_alloc(cp
, flags
);
618 list_add(&spare
->list
, &list
);
622 spin_lock(&cp
->rx_spare_lock
);
623 list_splice(&list
, &cp
->rx_spare_list
);
624 cp
->rx_spares_needed
-= i
;
625 spin_unlock(&cp
->rx_spare_lock
);
628 /* pull a page from the list. */
629 static cas_page_t
*cas_page_dequeue(struct cas
*cp
)
631 struct list_head
*entry
;
634 spin_lock(&cp
->rx_spare_lock
);
635 if (list_empty(&cp
->rx_spare_list
)) {
636 /* try to do a quick recovery */
637 spin_unlock(&cp
->rx_spare_lock
);
638 cas_spare_recover(cp
, GFP_ATOMIC
);
639 spin_lock(&cp
->rx_spare_lock
);
640 if (list_empty(&cp
->rx_spare_list
)) {
641 if (netif_msg_rx_err(cp
))
642 printk(KERN_ERR
"%s: no spare buffers "
643 "available.\n", cp
->dev
->name
);
644 spin_unlock(&cp
->rx_spare_lock
);
649 entry
= cp
->rx_spare_list
.next
;
651 recover
= ++cp
->rx_spares_needed
;
652 spin_unlock(&cp
->rx_spare_lock
);
654 /* trigger the timer to do the recovery */
655 if ((recover
& (RX_SPARE_RECOVER_VAL
- 1)) == 0) {
657 atomic_inc(&cp
->reset_task_pending
);
658 atomic_inc(&cp
->reset_task_pending_spare
);
659 schedule_work(&cp
->reset_task
);
661 atomic_set(&cp
->reset_task_pending
, CAS_RESET_SPARE
);
662 schedule_work(&cp
->reset_task
);
665 return list_entry(entry
, cas_page_t
, list
);
669 static void cas_mif_poll(struct cas
*cp
, const int enable
)
673 cfg
= readl(cp
->regs
+ REG_MIF_CFG
);
674 cfg
&= (MIF_CFG_MDIO_0
| MIF_CFG_MDIO_1
);
676 if (cp
->phy_type
& CAS_PHY_MII_MDIO1
)
677 cfg
|= MIF_CFG_PHY_SELECT
;
679 /* poll and interrupt on link status change. */
681 cfg
|= MIF_CFG_POLL_EN
;
682 cfg
|= CAS_BASE(MIF_CFG_POLL_REG
, MII_BMSR
);
683 cfg
|= CAS_BASE(MIF_CFG_POLL_PHY
, cp
->phy_addr
);
685 writel((enable
) ? ~(BMSR_LSTATUS
| BMSR_ANEGCOMPLETE
) : 0xFFFF,
686 cp
->regs
+ REG_MIF_MASK
);
687 writel(cfg
, cp
->regs
+ REG_MIF_CFG
);
690 /* Must be invoked under cp->lock */
691 static void cas_begin_auto_negotiation(struct cas
*cp
, struct ethtool_cmd
*ep
)
697 int oldstate
= cp
->lstate
;
698 int link_was_not_down
= !(oldstate
== link_down
);
700 /* Setup link parameters */
703 lcntl
= cp
->link_cntl
;
704 if (ep
->autoneg
== AUTONEG_ENABLE
)
705 cp
->link_cntl
= BMCR_ANENABLE
;
708 if (ep
->speed
== SPEED_100
)
709 cp
->link_cntl
|= BMCR_SPEED100
;
710 else if (ep
->speed
== SPEED_1000
)
711 cp
->link_cntl
|= CAS_BMCR_SPEED1000
;
712 if (ep
->duplex
== DUPLEX_FULL
)
713 cp
->link_cntl
|= BMCR_FULLDPLX
;
716 changed
= (lcntl
!= cp
->link_cntl
);
719 if (cp
->lstate
== link_up
) {
720 printk(KERN_INFO
"%s: PCS link down.\n",
724 printk(KERN_INFO
"%s: link configuration changed\n",
728 cp
->lstate
= link_down
;
729 cp
->link_transition
= LINK_TRANSITION_LINK_DOWN
;
734 * WTZ: If the old state was link_up, we turn off the carrier
735 * to replicate everything we do elsewhere on a link-down
736 * event when we were already in a link-up state..
738 if (oldstate
== link_up
)
739 netif_carrier_off(cp
->dev
);
740 if (changed
&& link_was_not_down
) {
742 * WTZ: This branch will simply schedule a full reset after
743 * we explicitly changed link modes in an ioctl. See if this
744 * fixes the link-problems we were having for forced mode.
746 atomic_inc(&cp
->reset_task_pending
);
747 atomic_inc(&cp
->reset_task_pending_all
);
748 schedule_work(&cp
->reset_task
);
750 mod_timer(&cp
->link_timer
, jiffies
+ CAS_LINK_TIMEOUT
);
754 if (cp
->phy_type
& CAS_PHY_SERDES
) {
755 u32 val
= readl(cp
->regs
+ REG_PCS_MII_CTRL
);
757 if (cp
->link_cntl
& BMCR_ANENABLE
) {
758 val
|= (PCS_MII_RESTART_AUTONEG
| PCS_MII_AUTONEG_EN
);
759 cp
->lstate
= link_aneg
;
761 if (cp
->link_cntl
& BMCR_FULLDPLX
)
762 val
|= PCS_MII_CTRL_DUPLEX
;
763 val
&= ~PCS_MII_AUTONEG_EN
;
764 cp
->lstate
= link_force_ok
;
766 cp
->link_transition
= LINK_TRANSITION_LINK_CONFIG
;
767 writel(val
, cp
->regs
+ REG_PCS_MII_CTRL
);
771 ctl
= cas_phy_read(cp
, MII_BMCR
);
772 ctl
&= ~(BMCR_FULLDPLX
| BMCR_SPEED100
|
773 CAS_BMCR_SPEED1000
| BMCR_ANENABLE
);
774 ctl
|= cp
->link_cntl
;
775 if (ctl
& BMCR_ANENABLE
) {
776 ctl
|= BMCR_ANRESTART
;
777 cp
->lstate
= link_aneg
;
779 cp
->lstate
= link_force_ok
;
781 cp
->link_transition
= LINK_TRANSITION_LINK_CONFIG
;
782 cas_phy_write(cp
, MII_BMCR
, ctl
);
787 mod_timer(&cp
->link_timer
, jiffies
+ CAS_LINK_TIMEOUT
);
790 /* Must be invoked under cp->lock. */
791 static int cas_reset_mii_phy(struct cas
*cp
)
793 int limit
= STOP_TRIES_PHY
;
796 cas_phy_write(cp
, MII_BMCR
, BMCR_RESET
);
799 val
= cas_phy_read(cp
, MII_BMCR
);
800 if ((val
& BMCR_RESET
) == 0)
807 static void cas_saturn_firmware_load(struct cas
*cp
)
809 cas_saturn_patch_t
*patch
= cas_saturn_patch
;
811 cas_phy_powerdown(cp
);
813 /* expanded memory access mode */
814 cas_phy_write(cp
, DP83065_MII_MEM
, 0x0);
816 /* pointer configuration for new firmware */
817 cas_phy_write(cp
, DP83065_MII_REGE
, 0x8ff9);
818 cas_phy_write(cp
, DP83065_MII_REGD
, 0xbd);
819 cas_phy_write(cp
, DP83065_MII_REGE
, 0x8ffa);
820 cas_phy_write(cp
, DP83065_MII_REGD
, 0x82);
821 cas_phy_write(cp
, DP83065_MII_REGE
, 0x8ffb);
822 cas_phy_write(cp
, DP83065_MII_REGD
, 0x0);
823 cas_phy_write(cp
, DP83065_MII_REGE
, 0x8ffc);
824 cas_phy_write(cp
, DP83065_MII_REGD
, 0x39);
826 /* download new firmware */
827 cas_phy_write(cp
, DP83065_MII_MEM
, 0x1);
828 cas_phy_write(cp
, DP83065_MII_REGE
, patch
->addr
);
829 while (patch
->addr
) {
830 cas_phy_write(cp
, DP83065_MII_REGD
, patch
->val
);
834 /* enable firmware */
835 cas_phy_write(cp
, DP83065_MII_REGE
, 0x8ff8);
836 cas_phy_write(cp
, DP83065_MII_REGD
, 0x1);
840 /* phy initialization */
841 static void cas_phy_init(struct cas
*cp
)
845 /* if we're in MII/GMII mode, set up phy */
846 if (CAS_PHY_MII(cp
->phy_type
)) {
847 writel(PCS_DATAPATH_MODE_MII
,
848 cp
->regs
+ REG_PCS_DATAPATH_MODE
);
851 cas_reset_mii_phy(cp
); /* take out of isolate mode */
853 if (PHY_LUCENT_B0
== cp
->phy_id
) {
854 /* workaround link up/down issue with lucent */
855 cas_phy_write(cp
, LUCENT_MII_REG
, 0x8000);
856 cas_phy_write(cp
, MII_BMCR
, 0x00f1);
857 cas_phy_write(cp
, LUCENT_MII_REG
, 0x0);
859 } else if (PHY_BROADCOM_B0
== (cp
->phy_id
& 0xFFFFFFFC)) {
860 /* workarounds for broadcom phy */
861 cas_phy_write(cp
, BROADCOM_MII_REG8
, 0x0C20);
862 cas_phy_write(cp
, BROADCOM_MII_REG7
, 0x0012);
863 cas_phy_write(cp
, BROADCOM_MII_REG5
, 0x1804);
864 cas_phy_write(cp
, BROADCOM_MII_REG7
, 0x0013);
865 cas_phy_write(cp
, BROADCOM_MII_REG5
, 0x1204);
866 cas_phy_write(cp
, BROADCOM_MII_REG7
, 0x8006);
867 cas_phy_write(cp
, BROADCOM_MII_REG5
, 0x0132);
868 cas_phy_write(cp
, BROADCOM_MII_REG7
, 0x8006);
869 cas_phy_write(cp
, BROADCOM_MII_REG5
, 0x0232);
870 cas_phy_write(cp
, BROADCOM_MII_REG7
, 0x201F);
871 cas_phy_write(cp
, BROADCOM_MII_REG5
, 0x0A20);
873 } else if (PHY_BROADCOM_5411
== cp
->phy_id
) {
874 val
= cas_phy_read(cp
, BROADCOM_MII_REG4
);
875 val
= cas_phy_read(cp
, BROADCOM_MII_REG4
);
877 /* link workaround */
878 cas_phy_write(cp
, BROADCOM_MII_REG4
,
882 } else if (cp
->cas_flags
& CAS_FLAG_SATURN
) {
883 writel((cp
->phy_type
& CAS_PHY_MII_MDIO0
) ?
884 SATURN_PCFG_FSI
: 0x0,
885 cp
->regs
+ REG_SATURN_PCFG
);
887 /* load firmware to address 10Mbps auto-negotiation
888 * issue. NOTE: this will need to be changed if the
889 * default firmware gets fixed.
891 if (PHY_NS_DP83065
== cp
->phy_id
) {
892 cas_saturn_firmware_load(cp
);
897 /* advertise capabilities */
898 val
= cas_phy_read(cp
, MII_BMCR
);
899 val
&= ~BMCR_ANENABLE
;
900 cas_phy_write(cp
, MII_BMCR
, val
);
903 cas_phy_write(cp
, MII_ADVERTISE
,
904 cas_phy_read(cp
, MII_ADVERTISE
) |
905 (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
906 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
907 CAS_ADVERTISE_PAUSE
|
908 CAS_ADVERTISE_ASYM_PAUSE
));
910 if (cp
->cas_flags
& CAS_FLAG_1000MB_CAP
) {
911 /* make sure that we don't advertise half
912 * duplex to avoid a chip issue
914 val
= cas_phy_read(cp
, CAS_MII_1000_CTRL
);
915 val
&= ~CAS_ADVERTISE_1000HALF
;
916 val
|= CAS_ADVERTISE_1000FULL
;
917 cas_phy_write(cp
, CAS_MII_1000_CTRL
, val
);
921 /* reset pcs for serdes */
925 writel(PCS_DATAPATH_MODE_SERDES
,
926 cp
->regs
+ REG_PCS_DATAPATH_MODE
);
928 /* enable serdes pins on saturn */
929 if (cp
->cas_flags
& CAS_FLAG_SATURN
)
930 writel(0, cp
->regs
+ REG_SATURN_PCFG
);
932 /* Reset PCS unit. */
933 val
= readl(cp
->regs
+ REG_PCS_MII_CTRL
);
934 val
|= PCS_MII_RESET
;
935 writel(val
, cp
->regs
+ REG_PCS_MII_CTRL
);
938 while (limit
-- > 0) {
940 if ((readl(cp
->regs
+ REG_PCS_MII_CTRL
) &
945 printk(KERN_WARNING
"%s: PCS reset bit would not "
946 "clear [%08x].\n", cp
->dev
->name
,
947 readl(cp
->regs
+ REG_PCS_STATE_MACHINE
));
949 /* Make sure PCS is disabled while changing advertisement
952 writel(0x0, cp
->regs
+ REG_PCS_CFG
);
954 /* Advertise all capabilities except half-duplex. */
955 val
= readl(cp
->regs
+ REG_PCS_MII_ADVERT
);
956 val
&= ~PCS_MII_ADVERT_HD
;
957 val
|= (PCS_MII_ADVERT_FD
| PCS_MII_ADVERT_SYM_PAUSE
|
958 PCS_MII_ADVERT_ASYM_PAUSE
);
959 writel(val
, cp
->regs
+ REG_PCS_MII_ADVERT
);
962 writel(PCS_CFG_EN
, cp
->regs
+ REG_PCS_CFG
);
964 /* pcs workaround: enable sync detect */
965 writel(PCS_SERDES_CTRL_SYNCD_EN
,
966 cp
->regs
+ REG_PCS_SERDES_CTRL
);
971 static int cas_pcs_link_check(struct cas
*cp
)
973 u32 stat
, state_machine
;
976 /* The link status bit latches on zero, so you must
977 * read it twice in such a case to see a transition
978 * to the link being up.
980 stat
= readl(cp
->regs
+ REG_PCS_MII_STATUS
);
981 if ((stat
& PCS_MII_STATUS_LINK_STATUS
) == 0)
982 stat
= readl(cp
->regs
+ REG_PCS_MII_STATUS
);
984 /* The remote-fault indication is only valid
985 * when autoneg has completed.
987 if ((stat
& (PCS_MII_STATUS_AUTONEG_COMP
|
988 PCS_MII_STATUS_REMOTE_FAULT
)) ==
989 (PCS_MII_STATUS_AUTONEG_COMP
| PCS_MII_STATUS_REMOTE_FAULT
)) {
990 if (netif_msg_link(cp
))
991 printk(KERN_INFO
"%s: PCS RemoteFault\n",
995 /* work around link detection issue by querying the PCS state
998 state_machine
= readl(cp
->regs
+ REG_PCS_STATE_MACHINE
);
999 if ((state_machine
& PCS_SM_LINK_STATE_MASK
) != SM_LINK_STATE_UP
) {
1000 stat
&= ~PCS_MII_STATUS_LINK_STATUS
;
1001 } else if (state_machine
& PCS_SM_WORD_SYNC_STATE_MASK
) {
1002 stat
|= PCS_MII_STATUS_LINK_STATUS
;
1005 if (stat
& PCS_MII_STATUS_LINK_STATUS
) {
1006 if (cp
->lstate
!= link_up
) {
1008 cp
->lstate
= link_up
;
1009 cp
->link_transition
= LINK_TRANSITION_LINK_UP
;
1011 cas_set_link_modes(cp
);
1012 netif_carrier_on(cp
->dev
);
1015 } else if (cp
->lstate
== link_up
) {
1016 cp
->lstate
= link_down
;
1017 if (link_transition_timeout
!= 0 &&
1018 cp
->link_transition
!= LINK_TRANSITION_REQUESTED_RESET
&&
1019 !cp
->link_transition_jiffies_valid
) {
1021 * force a reset, as a workaround for the
1022 * link-failure problem. May want to move this to a
1023 * point a bit earlier in the sequence. If we had
1024 * generated a reset a short time ago, we'll wait for
1025 * the link timer to check the status until a
1026 * timer expires (link_transistion_jiffies_valid is
1027 * true when the timer is running.) Instead of using
1028 * a system timer, we just do a check whenever the
1029 * link timer is running - this clears the flag after
1033 cp
->link_transition
= LINK_TRANSITION_REQUESTED_RESET
;
1034 cp
->link_transition_jiffies
= jiffies
;
1035 cp
->link_transition_jiffies_valid
= 1;
1037 cp
->link_transition
= LINK_TRANSITION_ON_FAILURE
;
1039 netif_carrier_off(cp
->dev
);
1040 if (cp
->opened
&& netif_msg_link(cp
)) {
1041 printk(KERN_INFO
"%s: PCS link down.\n",
1045 /* Cassini only: if you force a mode, there can be
1046 * sync problems on link down. to fix that, the following
1047 * things need to be checked:
1048 * 1) read serialink state register
1049 * 2) read pcs status register to verify link down.
1050 * 3) if link down and serial link == 0x03, then you need
1051 * to global reset the chip.
1053 if ((cp
->cas_flags
& CAS_FLAG_REG_PLUS
) == 0) {
1054 /* should check to see if we're in a forced mode */
1055 stat
= readl(cp
->regs
+ REG_PCS_SERDES_STATE
);
1059 } else if (cp
->lstate
== link_down
) {
1060 if (link_transition_timeout
!= 0 &&
1061 cp
->link_transition
!= LINK_TRANSITION_REQUESTED_RESET
&&
1062 !cp
->link_transition_jiffies_valid
) {
1063 /* force a reset, as a workaround for the
1064 * link-failure problem. May want to move
1065 * this to a point a bit earlier in the
1069 cp
->link_transition
= LINK_TRANSITION_REQUESTED_RESET
;
1070 cp
->link_transition_jiffies
= jiffies
;
1071 cp
->link_transition_jiffies_valid
= 1;
1073 cp
->link_transition
= LINK_TRANSITION_STILL_FAILED
;
1080 static int cas_pcs_interrupt(struct net_device
*dev
,
1081 struct cas
*cp
, u32 status
)
1083 u32 stat
= readl(cp
->regs
+ REG_PCS_INTR_STATUS
);
1085 if ((stat
& PCS_INTR_STATUS_LINK_CHANGE
) == 0)
1087 return cas_pcs_link_check(cp
);
1090 static int cas_txmac_interrupt(struct net_device
*dev
,
1091 struct cas
*cp
, u32 status
)
1093 u32 txmac_stat
= readl(cp
->regs
+ REG_MAC_TX_STATUS
);
1098 if (netif_msg_intr(cp
))
1099 printk(KERN_DEBUG
"%s: txmac interrupt, txmac_stat: 0x%x\n",
1100 cp
->dev
->name
, txmac_stat
);
1102 /* Defer timer expiration is quite normal,
1103 * don't even log the event.
1105 if ((txmac_stat
& MAC_TX_DEFER_TIMER
) &&
1106 !(txmac_stat
& ~MAC_TX_DEFER_TIMER
))
1109 spin_lock(&cp
->stat_lock
[0]);
1110 if (txmac_stat
& MAC_TX_UNDERRUN
) {
1111 printk(KERN_ERR
"%s: TX MAC xmit underrun.\n",
1113 cp
->net_stats
[0].tx_fifo_errors
++;
1116 if (txmac_stat
& MAC_TX_MAX_PACKET_ERR
) {
1117 printk(KERN_ERR
"%s: TX MAC max packet size error.\n",
1119 cp
->net_stats
[0].tx_errors
++;
1122 /* The rest are all cases of one of the 16-bit TX
1123 * counters expiring.
1125 if (txmac_stat
& MAC_TX_COLL_NORMAL
)
1126 cp
->net_stats
[0].collisions
+= 0x10000;
1128 if (txmac_stat
& MAC_TX_COLL_EXCESS
) {
1129 cp
->net_stats
[0].tx_aborted_errors
+= 0x10000;
1130 cp
->net_stats
[0].collisions
+= 0x10000;
1133 if (txmac_stat
& MAC_TX_COLL_LATE
) {
1134 cp
->net_stats
[0].tx_aborted_errors
+= 0x10000;
1135 cp
->net_stats
[0].collisions
+= 0x10000;
1137 spin_unlock(&cp
->stat_lock
[0]);
1139 /* We do not keep track of MAC_TX_COLL_FIRST and
1140 * MAC_TX_PEAK_ATTEMPTS events.
1145 static void cas_load_firmware(struct cas
*cp
, cas_hp_inst_t
*firmware
)
1147 cas_hp_inst_t
*inst
;
1152 while ((inst
= firmware
) && inst
->note
) {
1153 writel(i
, cp
->regs
+ REG_HP_INSTR_RAM_ADDR
);
1155 val
= CAS_BASE(HP_INSTR_RAM_HI_VAL
, inst
->val
);
1156 val
|= CAS_BASE(HP_INSTR_RAM_HI_MASK
, inst
->mask
);
1157 writel(val
, cp
->regs
+ REG_HP_INSTR_RAM_DATA_HI
);
1159 val
= CAS_BASE(HP_INSTR_RAM_MID_OUTARG
, inst
->outarg
>> 10);
1160 val
|= CAS_BASE(HP_INSTR_RAM_MID_OUTOP
, inst
->outop
);
1161 val
|= CAS_BASE(HP_INSTR_RAM_MID_FNEXT
, inst
->fnext
);
1162 val
|= CAS_BASE(HP_INSTR_RAM_MID_FOFF
, inst
->foff
);
1163 val
|= CAS_BASE(HP_INSTR_RAM_MID_SNEXT
, inst
->snext
);
1164 val
|= CAS_BASE(HP_INSTR_RAM_MID_SOFF
, inst
->soff
);
1165 val
|= CAS_BASE(HP_INSTR_RAM_MID_OP
, inst
->op
);
1166 writel(val
, cp
->regs
+ REG_HP_INSTR_RAM_DATA_MID
);
1168 val
= CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK
, inst
->outmask
);
1169 val
|= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT
, inst
->outshift
);
1170 val
|= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN
, inst
->outenab
);
1171 val
|= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG
, inst
->outarg
);
1172 writel(val
, cp
->regs
+ REG_HP_INSTR_RAM_DATA_LOW
);
1178 static void cas_init_rx_dma(struct cas
*cp
)
1180 u64 desc_dma
= cp
->block_dvma
;
1184 /* rx free descriptors */
1185 val
= CAS_BASE(RX_CFG_SWIVEL
, RX_SWIVEL_OFF_VAL
);
1186 val
|= CAS_BASE(RX_CFG_DESC_RING
, RX_DESC_RINGN_INDEX(0));
1187 val
|= CAS_BASE(RX_CFG_COMP_RING
, RX_COMP_RINGN_INDEX(0));
1188 if ((N_RX_DESC_RINGS
> 1) &&
1189 (cp
->cas_flags
& CAS_FLAG_REG_PLUS
)) /* do desc 2 */
1190 val
|= CAS_BASE(RX_CFG_DESC_RING1
, RX_DESC_RINGN_INDEX(1));
1191 writel(val
, cp
->regs
+ REG_RX_CFG
);
1193 val
= (unsigned long) cp
->init_rxds
[0] -
1194 (unsigned long) cp
->init_block
;
1195 writel((desc_dma
+ val
) >> 32, cp
->regs
+ REG_RX_DB_HI
);
1196 writel((desc_dma
+ val
) & 0xffffffff, cp
->regs
+ REG_RX_DB_LOW
);
1197 writel(RX_DESC_RINGN_SIZE(0) - 4, cp
->regs
+ REG_RX_KICK
);
1199 if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) {
1200 /* rx desc 2 is for IPSEC packets. however,
1201 * we don't it that for that purpose.
1203 val
= (unsigned long) cp
->init_rxds
[1] -
1204 (unsigned long) cp
->init_block
;
1205 writel((desc_dma
+ val
) >> 32, cp
->regs
+ REG_PLUS_RX_DB1_HI
);
1206 writel((desc_dma
+ val
) & 0xffffffff, cp
->regs
+
1207 REG_PLUS_RX_DB1_LOW
);
1208 writel(RX_DESC_RINGN_SIZE(1) - 4, cp
->regs
+
1212 /* rx completion registers */
1213 val
= (unsigned long) cp
->init_rxcs
[0] -
1214 (unsigned long) cp
->init_block
;
1215 writel((desc_dma
+ val
) >> 32, cp
->regs
+ REG_RX_CB_HI
);
1216 writel((desc_dma
+ val
) & 0xffffffff, cp
->regs
+ REG_RX_CB_LOW
);
1218 if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) {
1220 for (i
= 1; i
< MAX_RX_COMP_RINGS
; i
++) {
1221 val
= (unsigned long) cp
->init_rxcs
[i
] -
1222 (unsigned long) cp
->init_block
;
1223 writel((desc_dma
+ val
) >> 32, cp
->regs
+
1224 REG_PLUS_RX_CBN_HI(i
));
1225 writel((desc_dma
+ val
) & 0xffffffff, cp
->regs
+
1226 REG_PLUS_RX_CBN_LOW(i
));
1230 /* read selective clear regs to prevent spurious interrupts
1231 * on reset because complete == kick.
1232 * selective clear set up to prevent interrupts on resets
1234 readl(cp
->regs
+ REG_INTR_STATUS_ALIAS
);
1235 writel(INTR_RX_DONE
| INTR_RX_BUF_UNAVAIL
, cp
->regs
+ REG_ALIAS_CLEAR
);
1236 if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) {
1237 for (i
= 1; i
< N_RX_COMP_RINGS
; i
++)
1238 readl(cp
->regs
+ REG_PLUS_INTRN_STATUS_ALIAS(i
));
1240 /* 2 is different from 3 and 4 */
1241 if (N_RX_COMP_RINGS
> 1)
1242 writel(INTR_RX_DONE_ALT
| INTR_RX_BUF_UNAVAIL_1
,
1243 cp
->regs
+ REG_PLUS_ALIASN_CLEAR(1));
1245 for (i
= 2; i
< N_RX_COMP_RINGS
; i
++)
1246 writel(INTR_RX_DONE_ALT
,
1247 cp
->regs
+ REG_PLUS_ALIASN_CLEAR(i
));
1250 /* set up pause thresholds */
1251 val
= CAS_BASE(RX_PAUSE_THRESH_OFF
,
1252 cp
->rx_pause_off
/ RX_PAUSE_THRESH_QUANTUM
);
1253 val
|= CAS_BASE(RX_PAUSE_THRESH_ON
,
1254 cp
->rx_pause_on
/ RX_PAUSE_THRESH_QUANTUM
);
1255 writel(val
, cp
->regs
+ REG_RX_PAUSE_THRESH
);
1257 /* zero out dma reassembly buffers */
1258 for (i
= 0; i
< 64; i
++) {
1259 writel(i
, cp
->regs
+ REG_RX_TABLE_ADDR
);
1260 writel(0x0, cp
->regs
+ REG_RX_TABLE_DATA_LOW
);
1261 writel(0x0, cp
->regs
+ REG_RX_TABLE_DATA_MID
);
1262 writel(0x0, cp
->regs
+ REG_RX_TABLE_DATA_HI
);
1265 /* make sure address register is 0 for normal operation */
1266 writel(0x0, cp
->regs
+ REG_RX_CTRL_FIFO_ADDR
);
1267 writel(0x0, cp
->regs
+ REG_RX_IPP_FIFO_ADDR
);
1269 /* interrupt mitigation */
1271 val
= CAS_BASE(RX_BLANK_INTR_TIME
, RX_BLANK_INTR_TIME_VAL
);
1272 val
|= CAS_BASE(RX_BLANK_INTR_PKT
, RX_BLANK_INTR_PKT_VAL
);
1273 writel(val
, cp
->regs
+ REG_RX_BLANK
);
1275 writel(0x0, cp
->regs
+ REG_RX_BLANK
);
1278 /* interrupt generation as a function of low water marks for
1279 * free desc and completion entries. these are used to trigger
1280 * housekeeping for rx descs. we don't use the free interrupt
1281 * as it's not very useful
1283 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1284 val
= CAS_BASE(RX_AE_THRESH_COMP
, RX_AE_COMP_VAL
);
1285 writel(val
, cp
->regs
+ REG_RX_AE_THRESH
);
1286 if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) {
1287 val
= CAS_BASE(RX_AE1_THRESH_FREE
, RX_AE_FREEN_VAL(1));
1288 writel(val
, cp
->regs
+ REG_PLUS_RX_AE1_THRESH
);
1291 /* Random early detect registers. useful for congestion avoidance.
1292 * this should be tunable.
1294 writel(0x0, cp
->regs
+ REG_RX_RED
);
1296 /* receive page sizes. default == 2K (0x800) */
1298 if (cp
->page_size
== 0x1000)
1300 else if (cp
->page_size
== 0x2000)
1302 else if (cp
->page_size
== 0x4000)
1305 /* round mtu + offset. constrain to page size. */
1306 size
= cp
->dev
->mtu
+ 64;
1307 if (size
> cp
->page_size
)
1308 size
= cp
->page_size
;
1312 else if (size
<= 0x800)
1314 else if (size
<= 0x1000)
1319 cp
->mtu_stride
= 1 << (i
+ 10);
1320 val
= CAS_BASE(RX_PAGE_SIZE
, val
);
1321 val
|= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE
, i
);
1322 val
|= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT
, cp
->page_size
>> (i
+ 10));
1323 val
|= CAS_BASE(RX_PAGE_SIZE_MTU_OFF
, 0x1);
1324 writel(val
, cp
->regs
+ REG_RX_PAGE_SIZE
);
1326 /* enable the header parser if desired */
1327 if (CAS_HP_FIRMWARE
== cas_prog_null
)
1330 val
= CAS_BASE(HP_CFG_NUM_CPU
, CAS_NCPUS
> 63 ? 0 : CAS_NCPUS
);
1331 val
|= HP_CFG_PARSE_EN
| HP_CFG_SYN_INC_MASK
;
1332 val
|= CAS_BASE(HP_CFG_TCP_THRESH
, HP_TCP_THRESH_VAL
);
1333 writel(val
, cp
->regs
+ REG_HP_CFG
);
1336 static inline void cas_rxc_init(struct cas_rx_comp
*rxc
)
1338 memset(rxc
, 0, sizeof(*rxc
));
1339 rxc
->word4
= cpu_to_le64(RX_COMP4_ZERO
);
1342 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
1343 * flipping is protected by the fact that the chip will not
1344 * hand back the same page index while it's being processed.
1346 static inline cas_page_t
*cas_page_spare(struct cas
*cp
, const int index
)
1348 cas_page_t
*page
= cp
->rx_pages
[1][index
];
1351 if (page_count(page
->buffer
) == 1)
1354 new = cas_page_dequeue(cp
);
1356 spin_lock(&cp
->rx_inuse_lock
);
1357 list_add(&page
->list
, &cp
->rx_inuse_list
);
1358 spin_unlock(&cp
->rx_inuse_lock
);
1363 /* this needs to be changed if we actually use the ENC RX DESC ring */
1364 static cas_page_t
*cas_page_swap(struct cas
*cp
, const int ring
,
1367 cas_page_t
**page0
= cp
->rx_pages
[0];
1368 cas_page_t
**page1
= cp
->rx_pages
[1];
1370 /* swap if buffer is in use */
1371 if (page_count(page0
[index
]->buffer
) > 1) {
1372 cas_page_t
*new = cas_page_spare(cp
, index
);
1374 page1
[index
] = page0
[index
];
1378 RX_USED_SET(page0
[index
], 0);
1379 return page0
[index
];
1382 static void cas_clean_rxds(struct cas
*cp
)
1384 /* only clean ring 0 as ring 1 is used for spare buffers */
1385 struct cas_rx_desc
*rxd
= cp
->init_rxds
[0];
1388 /* release all rx flows */
1389 for (i
= 0; i
< N_RX_FLOWS
; i
++) {
1390 struct sk_buff
*skb
;
1391 while ((skb
= __skb_dequeue(&cp
->rx_flows
[i
]))) {
1392 cas_skb_release(skb
);
1396 /* initialize descriptors */
1397 size
= RX_DESC_RINGN_SIZE(0);
1398 for (i
= 0; i
< size
; i
++) {
1399 cas_page_t
*page
= cas_page_swap(cp
, 0, i
);
1400 rxd
[i
].buffer
= cpu_to_le64(page
->dma_addr
);
1401 rxd
[i
].index
= cpu_to_le64(CAS_BASE(RX_INDEX_NUM
, i
) |
1402 CAS_BASE(RX_INDEX_RING
, 0));
1405 cp
->rx_old
[0] = RX_DESC_RINGN_SIZE(0) - 4;
1407 cp
->cas_flags
&= ~CAS_FLAG_RXD_POST(0);
1410 static void cas_clean_rxcs(struct cas
*cp
)
1414 /* take ownership of rx comp descriptors */
1415 memset(cp
->rx_cur
, 0, sizeof(*cp
->rx_cur
)*N_RX_COMP_RINGS
);
1416 memset(cp
->rx_new
, 0, sizeof(*cp
->rx_new
)*N_RX_COMP_RINGS
);
1417 for (i
= 0; i
< N_RX_COMP_RINGS
; i
++) {
1418 struct cas_rx_comp
*rxc
= cp
->init_rxcs
[i
];
1419 for (j
= 0; j
< RX_COMP_RINGN_SIZE(i
); j
++) {
1420 cas_rxc_init(rxc
+ j
);
1426 /* When we get a RX fifo overflow, the RX unit is probably hung
1427 * so we do the following.
1429 * If any part of the reset goes wrong, we return 1 and that causes the
1430 * whole chip to be reset.
1432 static int cas_rxmac_reset(struct cas
*cp
)
1434 struct net_device
*dev
= cp
->dev
;
1438 /* First, reset MAC RX. */
1439 writel(cp
->mac_rx_cfg
& ~MAC_RX_CFG_EN
, cp
->regs
+ REG_MAC_RX_CFG
);
1440 for (limit
= 0; limit
< STOP_TRIES
; limit
++) {
1441 if (!(readl(cp
->regs
+ REG_MAC_RX_CFG
) & MAC_RX_CFG_EN
))
1445 if (limit
== STOP_TRIES
) {
1446 printk(KERN_ERR
"%s: RX MAC will not disable, resetting whole "
1447 "chip.\n", dev
->name
);
1451 /* Second, disable RX DMA. */
1452 writel(0, cp
->regs
+ REG_RX_CFG
);
1453 for (limit
= 0; limit
< STOP_TRIES
; limit
++) {
1454 if (!(readl(cp
->regs
+ REG_RX_CFG
) & RX_CFG_DMA_EN
))
1458 if (limit
== STOP_TRIES
) {
1459 printk(KERN_ERR
"%s: RX DMA will not disable, resetting whole "
1460 "chip.\n", dev
->name
);
1466 /* Execute RX reset command. */
1467 writel(SW_RESET_RX
, cp
->regs
+ REG_SW_RESET
);
1468 for (limit
= 0; limit
< STOP_TRIES
; limit
++) {
1469 if (!(readl(cp
->regs
+ REG_SW_RESET
) & SW_RESET_RX
))
1473 if (limit
== STOP_TRIES
) {
1474 printk(KERN_ERR
"%s: RX reset command will not execute, "
1475 "resetting whole chip.\n", dev
->name
);
1479 /* reset driver rx state */
1483 /* Now, reprogram the rest of RX unit. */
1484 cas_init_rx_dma(cp
);
1487 val
= readl(cp
->regs
+ REG_RX_CFG
);
1488 writel(val
| RX_CFG_DMA_EN
, cp
->regs
+ REG_RX_CFG
);
1489 writel(MAC_RX_FRAME_RECV
, cp
->regs
+ REG_MAC_RX_MASK
);
1490 val
= readl(cp
->regs
+ REG_MAC_RX_CFG
);
1491 writel(val
| MAC_RX_CFG_EN
, cp
->regs
+ REG_MAC_RX_CFG
);
1496 static int cas_rxmac_interrupt(struct net_device
*dev
, struct cas
*cp
,
1499 u32 stat
= readl(cp
->regs
+ REG_MAC_RX_STATUS
);
1504 if (netif_msg_intr(cp
))
1505 printk(KERN_DEBUG
"%s: rxmac interrupt, stat: 0x%x\n",
1506 cp
->dev
->name
, stat
);
1508 /* these are all rollovers */
1509 spin_lock(&cp
->stat_lock
[0]);
1510 if (stat
& MAC_RX_ALIGN_ERR
)
1511 cp
->net_stats
[0].rx_frame_errors
+= 0x10000;
1513 if (stat
& MAC_RX_CRC_ERR
)
1514 cp
->net_stats
[0].rx_crc_errors
+= 0x10000;
1516 if (stat
& MAC_RX_LEN_ERR
)
1517 cp
->net_stats
[0].rx_length_errors
+= 0x10000;
1519 if (stat
& MAC_RX_OVERFLOW
) {
1520 cp
->net_stats
[0].rx_over_errors
++;
1521 cp
->net_stats
[0].rx_fifo_errors
++;
1524 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
1527 spin_unlock(&cp
->stat_lock
[0]);
1531 static int cas_mac_interrupt(struct net_device
*dev
, struct cas
*cp
,
1534 u32 stat
= readl(cp
->regs
+ REG_MAC_CTRL_STATUS
);
1539 if (netif_msg_intr(cp
))
1540 printk(KERN_DEBUG
"%s: mac interrupt, stat: 0x%x\n",
1541 cp
->dev
->name
, stat
);
1543 /* This interrupt is just for pause frame and pause
1544 * tracking. It is useful for diagnostics and debug
1545 * but probably by default we will mask these events.
1547 if (stat
& MAC_CTRL_PAUSE_STATE
)
1548 cp
->pause_entered
++;
1550 if (stat
& MAC_CTRL_PAUSE_RECEIVED
)
1551 cp
->pause_last_time_recvd
= (stat
>> 16);
1557 /* Must be invoked under cp->lock. */
1558 static inline int cas_mdio_link_not_up(struct cas
*cp
)
1562 switch (cp
->lstate
) {
1563 case link_force_ret
:
1564 if (netif_msg_link(cp
))
1565 printk(KERN_INFO
"%s: Autoneg failed again, keeping"
1566 " forced mode\n", cp
->dev
->name
);
1567 cas_phy_write(cp
, MII_BMCR
, cp
->link_fcntl
);
1568 cp
->timer_ticks
= 5;
1569 cp
->lstate
= link_force_ok
;
1570 cp
->link_transition
= LINK_TRANSITION_LINK_CONFIG
;
1574 val
= cas_phy_read(cp
, MII_BMCR
);
1576 /* Try forced modes. we try things in the following order:
1577 * 1000 full -> 100 full/half -> 10 half
1579 val
&= ~(BMCR_ANRESTART
| BMCR_ANENABLE
);
1580 val
|= BMCR_FULLDPLX
;
1581 val
|= (cp
->cas_flags
& CAS_FLAG_1000MB_CAP
) ?
1582 CAS_BMCR_SPEED1000
: BMCR_SPEED100
;
1583 cas_phy_write(cp
, MII_BMCR
, val
);
1584 cp
->timer_ticks
= 5;
1585 cp
->lstate
= link_force_try
;
1586 cp
->link_transition
= LINK_TRANSITION_LINK_CONFIG
;
1589 case link_force_try
:
1590 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
1591 val
= cas_phy_read(cp
, MII_BMCR
);
1592 cp
->timer_ticks
= 5;
1593 if (val
& CAS_BMCR_SPEED1000
) { /* gigabit */
1594 val
&= ~CAS_BMCR_SPEED1000
;
1595 val
|= (BMCR_SPEED100
| BMCR_FULLDPLX
);
1596 cas_phy_write(cp
, MII_BMCR
, val
);
1600 if (val
& BMCR_SPEED100
) {
1601 if (val
& BMCR_FULLDPLX
) /* fd failed */
1602 val
&= ~BMCR_FULLDPLX
;
1603 else { /* 100Mbps failed */
1604 val
&= ~BMCR_SPEED100
;
1606 cas_phy_write(cp
, MII_BMCR
, val
);
1616 /* must be invoked with cp->lock held */
1617 static int cas_mii_link_check(struct cas
*cp
, const u16 bmsr
)
1621 if (bmsr
& BMSR_LSTATUS
) {
1622 /* Ok, here we got a link. If we had it due to a forced
1623 * fallback, and we were configured for autoneg, we
1624 * retry a short autoneg pass. If you know your hub is
1625 * broken, use ethtool ;)
1627 if ((cp
->lstate
== link_force_try
) &&
1628 (cp
->link_cntl
& BMCR_ANENABLE
)) {
1629 cp
->lstate
= link_force_ret
;
1630 cp
->link_transition
= LINK_TRANSITION_LINK_CONFIG
;
1631 cas_mif_poll(cp
, 0);
1632 cp
->link_fcntl
= cas_phy_read(cp
, MII_BMCR
);
1633 cp
->timer_ticks
= 5;
1634 if (cp
->opened
&& netif_msg_link(cp
))
1635 printk(KERN_INFO
"%s: Got link after fallback, retrying"
1636 " autoneg once...\n", cp
->dev
->name
);
1637 cas_phy_write(cp
, MII_BMCR
,
1638 cp
->link_fcntl
| BMCR_ANENABLE
|
1640 cas_mif_poll(cp
, 1);
1642 } else if (cp
->lstate
!= link_up
) {
1643 cp
->lstate
= link_up
;
1644 cp
->link_transition
= LINK_TRANSITION_LINK_UP
;
1647 cas_set_link_modes(cp
);
1648 netif_carrier_on(cp
->dev
);
1654 /* link not up. if the link was previously up, we restart the
1658 if (cp
->lstate
== link_up
) {
1659 cp
->lstate
= link_down
;
1660 cp
->link_transition
= LINK_TRANSITION_LINK_DOWN
;
1662 netif_carrier_off(cp
->dev
);
1663 if (cp
->opened
&& netif_msg_link(cp
))
1664 printk(KERN_INFO
"%s: Link down\n",
1668 } else if (++cp
->timer_ticks
> 10)
1669 cas_mdio_link_not_up(cp
);
1674 static int cas_mif_interrupt(struct net_device
*dev
, struct cas
*cp
,
1677 u32 stat
= readl(cp
->regs
+ REG_MIF_STATUS
);
1680 /* check for a link change */
1681 if (CAS_VAL(MIF_STATUS_POLL_STATUS
, stat
) == 0)
1684 bmsr
= CAS_VAL(MIF_STATUS_POLL_DATA
, stat
);
1685 return cas_mii_link_check(cp
, bmsr
);
1688 static int cas_pci_interrupt(struct net_device
*dev
, struct cas
*cp
,
1691 u32 stat
= readl(cp
->regs
+ REG_PCI_ERR_STATUS
);
1696 printk(KERN_ERR
"%s: PCI error [%04x:%04x] ", dev
->name
, stat
,
1697 readl(cp
->regs
+ REG_BIM_DIAG
));
1699 /* cassini+ has this reserved */
1700 if ((stat
& PCI_ERR_BADACK
) &&
1701 ((cp
->cas_flags
& CAS_FLAG_REG_PLUS
) == 0))
1702 printk("<No ACK64# during ABS64 cycle> ");
1704 if (stat
& PCI_ERR_DTRTO
)
1705 printk("<Delayed transaction timeout> ");
1706 if (stat
& PCI_ERR_OTHER
)
1708 if (stat
& PCI_ERR_BIM_DMA_WRITE
)
1709 printk("<BIM DMA 0 write req> ");
1710 if (stat
& PCI_ERR_BIM_DMA_READ
)
1711 printk("<BIM DMA 0 read req> ");
1714 if (stat
& PCI_ERR_OTHER
) {
1717 /* Interrogate PCI config space for the
1720 pci_read_config_word(cp
->pdev
, PCI_STATUS
, &cfg
);
1721 printk(KERN_ERR
"%s: Read PCI cfg space status [%04x]\n",
1723 if (cfg
& PCI_STATUS_PARITY
)
1724 printk(KERN_ERR
"%s: PCI parity error detected.\n",
1726 if (cfg
& PCI_STATUS_SIG_TARGET_ABORT
)
1727 printk(KERN_ERR
"%s: PCI target abort.\n",
1729 if (cfg
& PCI_STATUS_REC_TARGET_ABORT
)
1730 printk(KERN_ERR
"%s: PCI master acks target abort.\n",
1732 if (cfg
& PCI_STATUS_REC_MASTER_ABORT
)
1733 printk(KERN_ERR
"%s: PCI master abort.\n", dev
->name
);
1734 if (cfg
& PCI_STATUS_SIG_SYSTEM_ERROR
)
1735 printk(KERN_ERR
"%s: PCI system error SERR#.\n",
1737 if (cfg
& PCI_STATUS_DETECTED_PARITY
)
1738 printk(KERN_ERR
"%s: PCI parity error.\n",
1741 /* Write the error bits back to clear them. */
1742 cfg
&= (PCI_STATUS_PARITY
|
1743 PCI_STATUS_SIG_TARGET_ABORT
|
1744 PCI_STATUS_REC_TARGET_ABORT
|
1745 PCI_STATUS_REC_MASTER_ABORT
|
1746 PCI_STATUS_SIG_SYSTEM_ERROR
|
1747 PCI_STATUS_DETECTED_PARITY
);
1748 pci_write_config_word(cp
->pdev
, PCI_STATUS
, cfg
);
1751 /* For all PCI errors, we should reset the chip. */
1755 /* All non-normal interrupt conditions get serviced here.
1756 * Returns non-zero if we should just exit the interrupt
1757 * handler right now (ie. if we reset the card which invalidates
1758 * all of the other original irq status bits).
1760 static int cas_abnormal_irq(struct net_device
*dev
, struct cas
*cp
,
1763 if (status
& INTR_RX_TAG_ERROR
) {
1764 /* corrupt RX tag framing */
1765 if (netif_msg_rx_err(cp
))
1766 printk(KERN_DEBUG
"%s: corrupt rx tag framing\n",
1768 spin_lock(&cp
->stat_lock
[0]);
1769 cp
->net_stats
[0].rx_errors
++;
1770 spin_unlock(&cp
->stat_lock
[0]);
1774 if (status
& INTR_RX_LEN_MISMATCH
) {
1775 /* length mismatch. */
1776 if (netif_msg_rx_err(cp
))
1777 printk(KERN_DEBUG
"%s: length mismatch for rx frame\n",
1779 spin_lock(&cp
->stat_lock
[0]);
1780 cp
->net_stats
[0].rx_errors
++;
1781 spin_unlock(&cp
->stat_lock
[0]);
1785 if (status
& INTR_PCS_STATUS
) {
1786 if (cas_pcs_interrupt(dev
, cp
, status
))
1790 if (status
& INTR_TX_MAC_STATUS
) {
1791 if (cas_txmac_interrupt(dev
, cp
, status
))
1795 if (status
& INTR_RX_MAC_STATUS
) {
1796 if (cas_rxmac_interrupt(dev
, cp
, status
))
1800 if (status
& INTR_MAC_CTRL_STATUS
) {
1801 if (cas_mac_interrupt(dev
, cp
, status
))
1805 if (status
& INTR_MIF_STATUS
) {
1806 if (cas_mif_interrupt(dev
, cp
, status
))
1810 if (status
& INTR_PCI_ERROR_STATUS
) {
1811 if (cas_pci_interrupt(dev
, cp
, status
))
1818 atomic_inc(&cp
->reset_task_pending
);
1819 atomic_inc(&cp
->reset_task_pending_all
);
1820 printk(KERN_ERR
"%s:reset called in cas_abnormal_irq [0x%x]\n",
1822 schedule_work(&cp
->reset_task
);
1824 atomic_set(&cp
->reset_task_pending
, CAS_RESET_ALL
);
1825 printk(KERN_ERR
"reset called in cas_abnormal_irq\n");
1826 schedule_work(&cp
->reset_task
);
1831 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
1832 * determining whether to do a netif_stop/wakeup
1834 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
1835 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
1836 static inline int cas_calc_tabort(struct cas
*cp
, const unsigned long addr
,
1839 unsigned long off
= addr
+ len
;
1841 if (CAS_TABORT(cp
) == 1)
1843 if ((CAS_ROUND_PAGE(off
) - off
) > TX_TARGET_ABORT_LEN
)
1845 return TX_TARGET_ABORT_LEN
;
1848 static inline void cas_tx_ringN(struct cas
*cp
, int ring
, int limit
)
1850 struct cas_tx_desc
*txds
;
1851 struct sk_buff
**skbs
;
1852 struct net_device
*dev
= cp
->dev
;
1855 spin_lock(&cp
->tx_lock
[ring
]);
1856 txds
= cp
->init_txds
[ring
];
1857 skbs
= cp
->tx_skbs
[ring
];
1858 entry
= cp
->tx_old
[ring
];
1860 count
= TX_BUFF_COUNT(ring
, entry
, limit
);
1861 while (entry
!= limit
) {
1862 struct sk_buff
*skb
= skbs
[entry
];
1868 /* this should never occur */
1869 entry
= TX_DESC_NEXT(ring
, entry
);
1873 /* however, we might get only a partial skb release. */
1874 count
-= skb_shinfo(skb
)->nr_frags
+
1875 + cp
->tx_tiny_use
[ring
][entry
].nbufs
+ 1;
1879 if (netif_msg_tx_done(cp
))
1880 printk(KERN_DEBUG
"%s: tx[%d] done, slot %d\n",
1881 cp
->dev
->name
, ring
, entry
);
1884 cp
->tx_tiny_use
[ring
][entry
].nbufs
= 0;
1886 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
1887 struct cas_tx_desc
*txd
= txds
+ entry
;
1889 daddr
= le64_to_cpu(txd
->buffer
);
1890 dlen
= CAS_VAL(TX_DESC_BUFLEN
,
1891 le64_to_cpu(txd
->control
));
1892 pci_unmap_page(cp
->pdev
, daddr
, dlen
,
1894 entry
= TX_DESC_NEXT(ring
, entry
);
1896 /* tiny buffer may follow */
1897 if (cp
->tx_tiny_use
[ring
][entry
].used
) {
1898 cp
->tx_tiny_use
[ring
][entry
].used
= 0;
1899 entry
= TX_DESC_NEXT(ring
, entry
);
1903 spin_lock(&cp
->stat_lock
[ring
]);
1904 cp
->net_stats
[ring
].tx_packets
++;
1905 cp
->net_stats
[ring
].tx_bytes
+= skb
->len
;
1906 spin_unlock(&cp
->stat_lock
[ring
]);
1907 dev_kfree_skb_irq(skb
);
1909 cp
->tx_old
[ring
] = entry
;
1911 /* this is wrong for multiple tx rings. the net device needs
1912 * multiple queues for this to do the right thing. we wait
1913 * for 2*packets to be available when using tiny buffers
1915 if (netif_queue_stopped(dev
) &&
1916 (TX_BUFFS_AVAIL(cp
, ring
) > CAS_TABORT(cp
)*(MAX_SKB_FRAGS
+ 1)))
1917 netif_wake_queue(dev
);
1918 spin_unlock(&cp
->tx_lock
[ring
]);
1921 static void cas_tx(struct net_device
*dev
, struct cas
*cp
,
1925 #ifdef USE_TX_COMPWB
1926 u64 compwb
= le64_to_cpu(cp
->init_block
->tx_compwb
);
1928 if (netif_msg_intr(cp
))
1929 printk(KERN_DEBUG
"%s: tx interrupt, status: 0x%x, %lx\n",
1930 cp
->dev
->name
, status
, compwb
);
1931 /* process all the rings */
1932 for (ring
= 0; ring
< N_TX_RINGS
; ring
++) {
1933 #ifdef USE_TX_COMPWB
1934 /* use the completion writeback registers */
1935 limit
= (CAS_VAL(TX_COMPWB_MSB
, compwb
) << 8) |
1936 CAS_VAL(TX_COMPWB_LSB
, compwb
);
1937 compwb
= TX_COMPWB_NEXT(compwb
);
1939 limit
= readl(cp
->regs
+ REG_TX_COMPN(ring
));
1941 if (cp
->tx_old
[ring
] != limit
)
1942 cas_tx_ringN(cp
, ring
, limit
);
1947 static int cas_rx_process_pkt(struct cas
*cp
, struct cas_rx_comp
*rxc
,
1948 int entry
, const u64
*words
,
1949 struct sk_buff
**skbref
)
1951 int dlen
, hlen
, len
, i
, alloclen
;
1952 int off
, swivel
= RX_SWIVEL_OFF_VAL
;
1953 struct cas_page
*page
;
1954 struct sk_buff
*skb
;
1955 void *addr
, *crcaddr
;
1958 hlen
= CAS_VAL(RX_COMP2_HDR_SIZE
, words
[1]);
1959 dlen
= CAS_VAL(RX_COMP1_DATA_SIZE
, words
[0]);
1962 if (RX_COPY_ALWAYS
|| (words
[2] & RX_COMP3_SMALL_PKT
))
1965 alloclen
= max(hlen
, RX_COPY_MIN
);
1967 skb
= dev_alloc_skb(alloclen
+ swivel
+ cp
->crc_size
);
1973 skb_reserve(skb
, swivel
);
1976 addr
= crcaddr
= NULL
;
1977 if (hlen
) { /* always copy header pages */
1978 i
= CAS_VAL(RX_COMP2_HDR_INDEX
, words
[1]);
1979 page
= cp
->rx_pages
[CAS_VAL(RX_INDEX_RING
, i
)][CAS_VAL(RX_INDEX_NUM
, i
)];
1980 off
= CAS_VAL(RX_COMP2_HDR_OFF
, words
[1]) * 0x100 +
1984 if (!dlen
) /* attach FCS */
1986 pci_dma_sync_single_for_cpu(cp
->pdev
, page
->dma_addr
+ off
, i
,
1987 PCI_DMA_FROMDEVICE
);
1988 addr
= cas_page_map(page
->buffer
);
1989 memcpy(p
, addr
+ off
, i
);
1990 pci_dma_sync_single_for_device(cp
->pdev
, page
->dma_addr
+ off
, i
,
1991 PCI_DMA_FROMDEVICE
);
1992 cas_page_unmap(addr
);
1993 RX_USED_ADD(page
, 0x100);
1999 if (alloclen
< (hlen
+ dlen
)) {
2000 skb_frag_t
*frag
= skb_shinfo(skb
)->frags
;
2002 /* normal or jumbo packets. we use frags */
2003 i
= CAS_VAL(RX_COMP1_DATA_INDEX
, words
[0]);
2004 page
= cp
->rx_pages
[CAS_VAL(RX_INDEX_RING
, i
)][CAS_VAL(RX_INDEX_NUM
, i
)];
2005 off
= CAS_VAL(RX_COMP1_DATA_OFF
, words
[0]) + swivel
;
2007 hlen
= min(cp
->page_size
- off
, dlen
);
2009 if (netif_msg_rx_err(cp
)) {
2010 printk(KERN_DEBUG
"%s: rx page overflow: "
2011 "%d\n", cp
->dev
->name
, hlen
);
2013 dev_kfree_skb_irq(skb
);
2017 if (i
== dlen
) /* attach FCS */
2019 pci_dma_sync_single_for_cpu(cp
->pdev
, page
->dma_addr
+ off
, i
,
2020 PCI_DMA_FROMDEVICE
);
2022 /* make sure we always copy a header */
2024 if (p
== (char *) skb
->data
) { /* not split */
2025 addr
= cas_page_map(page
->buffer
);
2026 memcpy(p
, addr
+ off
, RX_COPY_MIN
);
2027 pci_dma_sync_single_for_device(cp
->pdev
, page
->dma_addr
+ off
, i
,
2028 PCI_DMA_FROMDEVICE
);
2029 cas_page_unmap(addr
);
2031 swivel
= RX_COPY_MIN
;
2032 RX_USED_ADD(page
, cp
->mtu_stride
);
2034 RX_USED_ADD(page
, hlen
);
2036 skb_put(skb
, alloclen
);
2038 skb_shinfo(skb
)->nr_frags
++;
2039 skb
->data_len
+= hlen
- swivel
;
2040 skb
->len
+= hlen
- swivel
;
2042 get_page(page
->buffer
);
2043 frag
->page
= page
->buffer
;
2044 frag
->page_offset
= off
;
2045 frag
->size
= hlen
- swivel
;
2047 /* any more data? */
2048 if ((words
[0] & RX_COMP1_SPLIT_PKT
) && ((dlen
-= hlen
) > 0)) {
2052 i
= CAS_VAL(RX_COMP2_NEXT_INDEX
, words
[1]);
2053 page
= cp
->rx_pages
[CAS_VAL(RX_INDEX_RING
, i
)][CAS_VAL(RX_INDEX_NUM
, i
)];
2054 pci_dma_sync_single_for_cpu(cp
->pdev
, page
->dma_addr
,
2055 hlen
+ cp
->crc_size
,
2056 PCI_DMA_FROMDEVICE
);
2057 pci_dma_sync_single_for_device(cp
->pdev
, page
->dma_addr
,
2058 hlen
+ cp
->crc_size
,
2059 PCI_DMA_FROMDEVICE
);
2061 skb_shinfo(skb
)->nr_frags
++;
2062 skb
->data_len
+= hlen
;
2066 get_page(page
->buffer
);
2067 frag
->page
= page
->buffer
;
2068 frag
->page_offset
= 0;
2070 RX_USED_ADD(page
, hlen
+ cp
->crc_size
);
2074 addr
= cas_page_map(page
->buffer
);
2075 crcaddr
= addr
+ off
+ hlen
;
2079 /* copying packet */
2083 i
= CAS_VAL(RX_COMP1_DATA_INDEX
, words
[0]);
2084 page
= cp
->rx_pages
[CAS_VAL(RX_INDEX_RING
, i
)][CAS_VAL(RX_INDEX_NUM
, i
)];
2085 off
= CAS_VAL(RX_COMP1_DATA_OFF
, words
[0]) + swivel
;
2086 hlen
= min(cp
->page_size
- off
, dlen
);
2088 if (netif_msg_rx_err(cp
)) {
2089 printk(KERN_DEBUG
"%s: rx page overflow: "
2090 "%d\n", cp
->dev
->name
, hlen
);
2092 dev_kfree_skb_irq(skb
);
2096 if (i
== dlen
) /* attach FCS */
2098 pci_dma_sync_single_for_cpu(cp
->pdev
, page
->dma_addr
+ off
, i
,
2099 PCI_DMA_FROMDEVICE
);
2100 addr
= cas_page_map(page
->buffer
);
2101 memcpy(p
, addr
+ off
, i
);
2102 pci_dma_sync_single_for_device(cp
->pdev
, page
->dma_addr
+ off
, i
,
2103 PCI_DMA_FROMDEVICE
);
2104 cas_page_unmap(addr
);
2105 if (p
== (char *) skb
->data
) /* not split */
2106 RX_USED_ADD(page
, cp
->mtu_stride
);
2108 RX_USED_ADD(page
, i
);
2110 /* any more data? */
2111 if ((words
[0] & RX_COMP1_SPLIT_PKT
) && ((dlen
-= hlen
) > 0)) {
2113 i
= CAS_VAL(RX_COMP2_NEXT_INDEX
, words
[1]);
2114 page
= cp
->rx_pages
[CAS_VAL(RX_INDEX_RING
, i
)][CAS_VAL(RX_INDEX_NUM
, i
)];
2115 pci_dma_sync_single_for_cpu(cp
->pdev
, page
->dma_addr
,
2116 dlen
+ cp
->crc_size
,
2117 PCI_DMA_FROMDEVICE
);
2118 addr
= cas_page_map(page
->buffer
);
2119 memcpy(p
, addr
, dlen
+ cp
->crc_size
);
2120 pci_dma_sync_single_for_device(cp
->pdev
, page
->dma_addr
,
2121 dlen
+ cp
->crc_size
,
2122 PCI_DMA_FROMDEVICE
);
2123 cas_page_unmap(addr
);
2124 RX_USED_ADD(page
, dlen
+ cp
->crc_size
);
2129 crcaddr
= skb
->data
+ alloclen
;
2131 skb_put(skb
, alloclen
);
2134 i
= CAS_VAL(RX_COMP4_TCP_CSUM
, words
[3]);
2136 /* checksum includes FCS. strip it out. */
2137 i
= csum_fold(csum_partial(crcaddr
, cp
->crc_size
, i
));
2139 cas_page_unmap(addr
);
2141 skb
->csum
= ntohs(i
^ 0xffff);
2142 skb
->ip_summed
= CHECKSUM_HW
;
2143 skb
->protocol
= eth_type_trans(skb
, cp
->dev
);
2148 /* we can handle up to 64 rx flows at a time. we do the same thing
2149 * as nonreassm except that we batch up the buffers.
2150 * NOTE: we currently just treat each flow as a bunch of packets that
2151 * we pass up. a better way would be to coalesce the packets
2152 * into a jumbo packet. to do that, we need to do the following:
2153 * 1) the first packet will have a clean split between header and
2155 * 2) each time the next flow packet comes in, extend the
2156 * data length and merge the checksums.
2157 * 3) on flow release, fix up the header.
2158 * 4) make sure the higher layer doesn't care.
2159 * because packets get coalesced, we shouldn't run into fragment count
2162 static inline void cas_rx_flow_pkt(struct cas
*cp
, const u64
*words
,
2163 struct sk_buff
*skb
)
2165 int flowid
= CAS_VAL(RX_COMP3_FLOWID
, words
[2]) & (N_RX_FLOWS
- 1);
2166 struct sk_buff_head
*flow
= &cp
->rx_flows
[flowid
];
2168 /* this is protected at a higher layer, so no need to
2169 * do any additional locking here. stick the buffer
2172 __skb_insert(skb
, flow
->prev
, (struct sk_buff
*) flow
, flow
);
2173 if (words
[0] & RX_COMP1_RELEASE_FLOW
) {
2174 while ((skb
= __skb_dequeue(flow
))) {
2175 cas_skb_release(skb
);
2180 /* put rx descriptor back on ring. if a buffer is in use by a higher
2181 * layer, this will need to put in a replacement.
2183 static void cas_post_page(struct cas
*cp
, const int ring
, const int index
)
2188 entry
= cp
->rx_old
[ring
];
2190 new = cas_page_swap(cp
, ring
, index
);
2191 cp
->init_rxds
[ring
][entry
].buffer
= cpu_to_le64(new->dma_addr
);
2192 cp
->init_rxds
[ring
][entry
].index
=
2193 cpu_to_le64(CAS_BASE(RX_INDEX_NUM
, index
) |
2194 CAS_BASE(RX_INDEX_RING
, ring
));
2196 entry
= RX_DESC_ENTRY(ring
, entry
+ 1);
2197 cp
->rx_old
[ring
] = entry
;
2203 writel(entry
, cp
->regs
+ REG_RX_KICK
);
2204 else if ((N_RX_DESC_RINGS
> 1) &&
2205 (cp
->cas_flags
& CAS_FLAG_REG_PLUS
))
2206 writel(entry
, cp
->regs
+ REG_PLUS_RX_KICK1
);
2210 /* only when things are bad */
2211 static int cas_post_rxds_ringN(struct cas
*cp
, int ring
, int num
)
2213 unsigned int entry
, last
, count
, released
;
2215 cas_page_t
**page
= cp
->rx_pages
[ring
];
2217 entry
= cp
->rx_old
[ring
];
2219 if (netif_msg_intr(cp
))
2220 printk(KERN_DEBUG
"%s: rxd[%d] interrupt, done: %d\n",
2221 cp
->dev
->name
, ring
, entry
);
2224 count
= entry
& 0x3;
2225 last
= RX_DESC_ENTRY(ring
, num
? entry
+ num
- 4: entry
- 4);
2227 while (entry
!= last
) {
2228 /* make a new buffer if it's still in use */
2229 if (page_count(page
[entry
]->buffer
) > 1) {
2230 cas_page_t
*new = cas_page_dequeue(cp
);
2232 /* let the timer know that we need to
2235 cp
->cas_flags
|= CAS_FLAG_RXD_POST(ring
);
2236 if (!timer_pending(&cp
->link_timer
))
2237 mod_timer(&cp
->link_timer
, jiffies
+
2238 CAS_LINK_FAST_TIMEOUT
);
2239 cp
->rx_old
[ring
] = entry
;
2240 cp
->rx_last
[ring
] = num
? num
- released
: 0;
2243 spin_lock(&cp
->rx_inuse_lock
);
2244 list_add(&page
[entry
]->list
, &cp
->rx_inuse_list
);
2245 spin_unlock(&cp
->rx_inuse_lock
);
2246 cp
->init_rxds
[ring
][entry
].buffer
=
2247 cpu_to_le64(new->dma_addr
);
2257 entry
= RX_DESC_ENTRY(ring
, entry
+ 1);
2259 cp
->rx_old
[ring
] = entry
;
2265 writel(cluster
, cp
->regs
+ REG_RX_KICK
);
2266 else if ((N_RX_DESC_RINGS
> 1) &&
2267 (cp
->cas_flags
& CAS_FLAG_REG_PLUS
))
2268 writel(cluster
, cp
->regs
+ REG_PLUS_RX_KICK1
);
2273 /* process a completion ring. packets are set up in three basic ways:
2274 * small packets: should be copied header + data in single buffer.
2275 * large packets: header and data in a single buffer.
2276 * split packets: header in a separate buffer from data.
2277 * data may be in multiple pages. data may be > 256
2278 * bytes but in a single page.
2280 * NOTE: RX page posting is done in this routine as well. while there's
2281 * the capability of using multiple RX completion rings, it isn't
2282 * really worthwhile due to the fact that the page posting will
2283 * force serialization on the single descriptor ring.
2285 static int cas_rx_ringN(struct cas
*cp
, int ring
, int budget
)
2287 struct cas_rx_comp
*rxcs
= cp
->init_rxcs
[ring
];
2291 if (netif_msg_intr(cp
))
2292 printk(KERN_DEBUG
"%s: rx[%d] interrupt, done: %d/%d\n",
2293 cp
->dev
->name
, ring
,
2294 readl(cp
->regs
+ REG_RX_COMP_HEAD
),
2297 entry
= cp
->rx_new
[ring
];
2300 struct cas_rx_comp
*rxc
= rxcs
+ entry
;
2301 struct sk_buff
*skb
;
2306 words
[0] = le64_to_cpu(rxc
->word1
);
2307 words
[1] = le64_to_cpu(rxc
->word2
);
2308 words
[2] = le64_to_cpu(rxc
->word3
);
2309 words
[3] = le64_to_cpu(rxc
->word4
);
2311 /* don't touch if still owned by hw */
2312 type
= CAS_VAL(RX_COMP1_TYPE
, words
[0]);
2316 /* hw hasn't cleared the zero bit yet */
2317 if (words
[3] & RX_COMP4_ZERO
) {
2321 /* get info on the packet */
2322 if (words
[3] & (RX_COMP4_LEN_MISMATCH
| RX_COMP4_BAD
)) {
2323 spin_lock(&cp
->stat_lock
[ring
]);
2324 cp
->net_stats
[ring
].rx_errors
++;
2325 if (words
[3] & RX_COMP4_LEN_MISMATCH
)
2326 cp
->net_stats
[ring
].rx_length_errors
++;
2327 if (words
[3] & RX_COMP4_BAD
)
2328 cp
->net_stats
[ring
].rx_crc_errors
++;
2329 spin_unlock(&cp
->stat_lock
[ring
]);
2331 /* We'll just return it to Cassini. */
2333 spin_lock(&cp
->stat_lock
[ring
]);
2334 ++cp
->net_stats
[ring
].rx_dropped
;
2335 spin_unlock(&cp
->stat_lock
[ring
]);
2339 len
= cas_rx_process_pkt(cp
, rxc
, entry
, words
, &skb
);
2345 /* see if it's a flow re-assembly or not. the driver
2346 * itself handles release back up.
2348 if (RX_DONT_BATCH
|| (type
== 0x2)) {
2349 /* non-reassm: these always get released */
2350 cas_skb_release(skb
);
2352 cas_rx_flow_pkt(cp
, words
, skb
);
2355 spin_lock(&cp
->stat_lock
[ring
]);
2356 cp
->net_stats
[ring
].rx_packets
++;
2357 cp
->net_stats
[ring
].rx_bytes
+= len
;
2358 spin_unlock(&cp
->stat_lock
[ring
]);
2359 cp
->dev
->last_rx
= jiffies
;
2364 /* should it be released? */
2365 if (words
[0] & RX_COMP1_RELEASE_HDR
) {
2366 i
= CAS_VAL(RX_COMP2_HDR_INDEX
, words
[1]);
2367 dring
= CAS_VAL(RX_INDEX_RING
, i
);
2368 i
= CAS_VAL(RX_INDEX_NUM
, i
);
2369 cas_post_page(cp
, dring
, i
);
2372 if (words
[0] & RX_COMP1_RELEASE_DATA
) {
2373 i
= CAS_VAL(RX_COMP1_DATA_INDEX
, words
[0]);
2374 dring
= CAS_VAL(RX_INDEX_RING
, i
);
2375 i
= CAS_VAL(RX_INDEX_NUM
, i
);
2376 cas_post_page(cp
, dring
, i
);
2379 if (words
[0] & RX_COMP1_RELEASE_NEXT
) {
2380 i
= CAS_VAL(RX_COMP2_NEXT_INDEX
, words
[1]);
2381 dring
= CAS_VAL(RX_INDEX_RING
, i
);
2382 i
= CAS_VAL(RX_INDEX_NUM
, i
);
2383 cas_post_page(cp
, dring
, i
);
2386 /* skip to the next entry */
2387 entry
= RX_COMP_ENTRY(ring
, entry
+ 1 +
2388 CAS_VAL(RX_COMP1_SKIP
, words
[0]));
2390 if (budget
&& (npackets
>= budget
))
2394 cp
->rx_new
[ring
] = entry
;
2397 printk(KERN_INFO
"%s: Memory squeeze, deferring packet.\n",
2403 /* put completion entries back on the ring */
2404 static void cas_post_rxcs_ringN(struct net_device
*dev
,
2405 struct cas
*cp
, int ring
)
2407 struct cas_rx_comp
*rxc
= cp
->init_rxcs
[ring
];
2410 last
= cp
->rx_cur
[ring
];
2411 entry
= cp
->rx_new
[ring
];
2412 if (netif_msg_intr(cp
))
2413 printk(KERN_DEBUG
"%s: rxc[%d] interrupt, done: %d/%d\n",
2414 dev
->name
, ring
, readl(cp
->regs
+ REG_RX_COMP_HEAD
),
2417 /* zero and re-mark descriptors */
2418 while (last
!= entry
) {
2419 cas_rxc_init(rxc
+ last
);
2420 last
= RX_COMP_ENTRY(ring
, last
+ 1);
2422 cp
->rx_cur
[ring
] = last
;
2425 writel(last
, cp
->regs
+ REG_RX_COMP_TAIL
);
2426 else if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
)
2427 writel(last
, cp
->regs
+ REG_PLUS_RX_COMPN_TAIL(ring
));
2432 /* cassini can use all four PCI interrupts for the completion ring.
2433 * rings 3 and 4 are identical
2435 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
2436 static inline void cas_handle_irqN(struct net_device
*dev
,
2437 struct cas
*cp
, const u32 status
,
2440 if (status
& (INTR_RX_COMP_FULL_ALT
| INTR_RX_COMP_AF_ALT
))
2441 cas_post_rxcs_ringN(dev
, cp
, ring
);
2444 static irqreturn_t
cas_interruptN(int irq
, void *dev_id
, struct pt_regs
*regs
)
2446 struct net_device
*dev
= dev_id
;
2447 struct cas
*cp
= netdev_priv(dev
);
2448 unsigned long flags
;
2450 u32 status
= readl(cp
->regs
+ REG_PLUS_INTRN_STATUS(ring
));
2452 /* check for shared irq */
2456 ring
= (irq
== cp
->pci_irq_INTC
) ? 2 : 3;
2457 spin_lock_irqsave(&cp
->lock
, flags
);
2458 if (status
& INTR_RX_DONE_ALT
) { /* handle rx separately */
2461 netif_rx_schedule(dev
);
2463 cas_rx_ringN(cp
, ring
, 0);
2465 status
&= ~INTR_RX_DONE_ALT
;
2469 cas_handle_irqN(dev
, cp
, status
, ring
);
2470 spin_unlock_irqrestore(&cp
->lock
, flags
);
2476 /* everything but rx packets */
2477 static inline void cas_handle_irq1(struct cas
*cp
, const u32 status
)
2479 if (status
& INTR_RX_BUF_UNAVAIL_1
) {
2480 /* Frame arrived, no free RX buffers available.
2481 * NOTE: we can get this on a link transition. */
2482 cas_post_rxds_ringN(cp
, 1, 0);
2483 spin_lock(&cp
->stat_lock
[1]);
2484 cp
->net_stats
[1].rx_dropped
++;
2485 spin_unlock(&cp
->stat_lock
[1]);
2488 if (status
& INTR_RX_BUF_AE_1
)
2489 cas_post_rxds_ringN(cp
, 1, RX_DESC_RINGN_SIZE(1) -
2490 RX_AE_FREEN_VAL(1));
2492 if (status
& (INTR_RX_COMP_AF
| INTR_RX_COMP_FULL
))
2493 cas_post_rxcs_ringN(cp
, 1);
2496 /* ring 2 handles a few more events than 3 and 4 */
2497 static irqreturn_t
cas_interrupt1(int irq
, void *dev_id
, struct pt_regs
*regs
)
2499 struct net_device
*dev
= dev_id
;
2500 struct cas
*cp
= netdev_priv(dev
);
2501 unsigned long flags
;
2502 u32 status
= readl(cp
->regs
+ REG_PLUS_INTRN_STATUS(1));
2504 /* check for shared interrupt */
2508 spin_lock_irqsave(&cp
->lock
, flags
);
2509 if (status
& INTR_RX_DONE_ALT
) { /* handle rx separately */
2512 netif_rx_schedule(dev
);
2514 cas_rx_ringN(cp
, 1, 0);
2516 status
&= ~INTR_RX_DONE_ALT
;
2519 cas_handle_irq1(cp
, status
);
2520 spin_unlock_irqrestore(&cp
->lock
, flags
);
2525 static inline void cas_handle_irq(struct net_device
*dev
,
2526 struct cas
*cp
, const u32 status
)
2528 /* housekeeping interrupts */
2529 if (status
& INTR_ERROR_MASK
)
2530 cas_abnormal_irq(dev
, cp
, status
);
2532 if (status
& INTR_RX_BUF_UNAVAIL
) {
2533 /* Frame arrived, no free RX buffers available.
2534 * NOTE: we can get this on a link transition.
2536 cas_post_rxds_ringN(cp
, 0, 0);
2537 spin_lock(&cp
->stat_lock
[0]);
2538 cp
->net_stats
[0].rx_dropped
++;
2539 spin_unlock(&cp
->stat_lock
[0]);
2540 } else if (status
& INTR_RX_BUF_AE
) {
2541 cas_post_rxds_ringN(cp
, 0, RX_DESC_RINGN_SIZE(0) -
2542 RX_AE_FREEN_VAL(0));
2545 if (status
& (INTR_RX_COMP_AF
| INTR_RX_COMP_FULL
))
2546 cas_post_rxcs_ringN(dev
, cp
, 0);
2549 static irqreturn_t
cas_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2551 struct net_device
*dev
= dev_id
;
2552 struct cas
*cp
= netdev_priv(dev
);
2553 unsigned long flags
;
2554 u32 status
= readl(cp
->regs
+ REG_INTR_STATUS
);
2559 spin_lock_irqsave(&cp
->lock
, flags
);
2560 if (status
& (INTR_TX_ALL
| INTR_TX_INTME
)) {
2561 cas_tx(dev
, cp
, status
);
2562 status
&= ~(INTR_TX_ALL
| INTR_TX_INTME
);
2565 if (status
& INTR_RX_DONE
) {
2568 netif_rx_schedule(dev
);
2570 cas_rx_ringN(cp
, 0, 0);
2572 status
&= ~INTR_RX_DONE
;
2576 cas_handle_irq(dev
, cp
, status
);
2577 spin_unlock_irqrestore(&cp
->lock
, flags
);
2583 static int cas_poll(struct net_device
*dev
, int *budget
)
2585 struct cas
*cp
= netdev_priv(dev
);
2586 int i
, enable_intr
, todo
, credits
;
2587 u32 status
= readl(cp
->regs
+ REG_INTR_STATUS
);
2588 unsigned long flags
;
2590 spin_lock_irqsave(&cp
->lock
, flags
);
2591 cas_tx(dev
, cp
, status
);
2592 spin_unlock_irqrestore(&cp
->lock
, flags
);
2594 /* NAPI rx packets. we spread the credits across all of the
2597 todo
= min(*budget
, dev
->quota
);
2599 /* to make sure we're fair with the work we loop through each
2600 * ring N_RX_COMP_RING times with a request of
2601 * todo / N_RX_COMP_RINGS
2605 for (i
= 0; i
< N_RX_COMP_RINGS
; i
++) {
2607 for (j
= 0; j
< N_RX_COMP_RINGS
; j
++) {
2608 credits
+= cas_rx_ringN(cp
, j
, todo
/ N_RX_COMP_RINGS
);
2609 if (credits
>= todo
) {
2618 dev
->quota
-= credits
;
2620 /* final rx completion */
2621 spin_lock_irqsave(&cp
->lock
, flags
);
2623 cas_handle_irq(dev
, cp
, status
);
2626 if (N_RX_COMP_RINGS
> 1) {
2627 status
= readl(cp
->regs
+ REG_PLUS_INTRN_STATUS(1));
2629 cas_handle_irq1(dev
, cp
, status
);
2634 if (N_RX_COMP_RINGS
> 2) {
2635 status
= readl(cp
->regs
+ REG_PLUS_INTRN_STATUS(2));
2637 cas_handle_irqN(dev
, cp
, status
, 2);
2642 if (N_RX_COMP_RINGS
> 3) {
2643 status
= readl(cp
->regs
+ REG_PLUS_INTRN_STATUS(3));
2645 cas_handle_irqN(dev
, cp
, status
, 3);
2648 spin_unlock_irqrestore(&cp
->lock
, flags
);
2650 netif_rx_complete(dev
);
2651 cas_unmask_intr(cp
);
2658 #ifdef CONFIG_NET_POLL_CONTROLLER
2659 static void cas_netpoll(struct net_device
*dev
)
2661 struct cas
*cp
= netdev_priv(dev
);
2663 cas_disable_irq(cp
, 0);
2664 cas_interrupt(cp
->pdev
->irq
, dev
, NULL
);
2665 cas_enable_irq(cp
, 0);
2668 if (N_RX_COMP_RINGS
> 1) {
2669 /* cas_interrupt1(); */
2673 if (N_RX_COMP_RINGS
> 2) {
2674 /* cas_interruptN(); */
2678 if (N_RX_COMP_RINGS
> 3) {
2679 /* cas_interruptN(); */
2685 static void cas_tx_timeout(struct net_device
*dev
)
2687 struct cas
*cp
= netdev_priv(dev
);
2689 printk(KERN_ERR
"%s: transmit timed out, resetting\n", dev
->name
);
2690 if (!cp
->hw_running
) {
2691 printk("%s: hrm.. hw not running!\n", dev
->name
);
2695 printk(KERN_ERR
"%s: MIF_STATE[%08x]\n",
2696 dev
->name
, readl(cp
->regs
+ REG_MIF_STATE_MACHINE
));
2698 printk(KERN_ERR
"%s: MAC_STATE[%08x]\n",
2699 dev
->name
, readl(cp
->regs
+ REG_MAC_STATE_MACHINE
));
2701 printk(KERN_ERR
"%s: TX_STATE[%08x:%08x:%08x] "
2702 "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
2704 readl(cp
->regs
+ REG_TX_CFG
),
2705 readl(cp
->regs
+ REG_MAC_TX_STATUS
),
2706 readl(cp
->regs
+ REG_MAC_TX_CFG
),
2707 readl(cp
->regs
+ REG_TX_FIFO_PKT_CNT
),
2708 readl(cp
->regs
+ REG_TX_FIFO_WRITE_PTR
),
2709 readl(cp
->regs
+ REG_TX_FIFO_READ_PTR
),
2710 readl(cp
->regs
+ REG_TX_SM_1
),
2711 readl(cp
->regs
+ REG_TX_SM_2
));
2713 printk(KERN_ERR
"%s: RX_STATE[%08x:%08x:%08x]\n",
2715 readl(cp
->regs
+ REG_RX_CFG
),
2716 readl(cp
->regs
+ REG_MAC_RX_STATUS
),
2717 readl(cp
->regs
+ REG_MAC_RX_CFG
));
2719 printk(KERN_ERR
"%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
2721 readl(cp
->regs
+ REG_HP_STATE_MACHINE
),
2722 readl(cp
->regs
+ REG_HP_STATUS0
),
2723 readl(cp
->regs
+ REG_HP_STATUS1
),
2724 readl(cp
->regs
+ REG_HP_STATUS2
));
2727 atomic_inc(&cp
->reset_task_pending
);
2728 atomic_inc(&cp
->reset_task_pending_all
);
2729 schedule_work(&cp
->reset_task
);
2731 atomic_set(&cp
->reset_task_pending
, CAS_RESET_ALL
);
2732 schedule_work(&cp
->reset_task
);
2736 static inline int cas_intme(int ring
, int entry
)
2738 /* Algorithm: IRQ every 1/2 of descriptors. */
2739 if (!(entry
& ((TX_DESC_RINGN_SIZE(ring
) >> 1) - 1)))
2745 static void cas_write_txd(struct cas
*cp
, int ring
, int entry
,
2746 dma_addr_t mapping
, int len
, u64 ctrl
, int last
)
2748 struct cas_tx_desc
*txd
= cp
->init_txds
[ring
] + entry
;
2750 ctrl
|= CAS_BASE(TX_DESC_BUFLEN
, len
);
2751 if (cas_intme(ring
, entry
))
2752 ctrl
|= TX_DESC_INTME
;
2754 ctrl
|= TX_DESC_EOF
;
2755 txd
->control
= cpu_to_le64(ctrl
);
2756 txd
->buffer
= cpu_to_le64(mapping
);
2759 static inline void *tx_tiny_buf(struct cas
*cp
, const int ring
,
2762 return cp
->tx_tiny_bufs
[ring
] + TX_TINY_BUF_LEN
*entry
;
2765 static inline dma_addr_t
tx_tiny_map(struct cas
*cp
, const int ring
,
2766 const int entry
, const int tentry
)
2768 cp
->tx_tiny_use
[ring
][tentry
].nbufs
++;
2769 cp
->tx_tiny_use
[ring
][entry
].used
= 1;
2770 return cp
->tx_tiny_dvma
[ring
] + TX_TINY_BUF_LEN
*entry
;
2773 static inline int cas_xmit_tx_ringN(struct cas
*cp
, int ring
,
2774 struct sk_buff
*skb
)
2776 struct net_device
*dev
= cp
->dev
;
2777 int entry
, nr_frags
, frag
, tabort
, tentry
;
2779 unsigned long flags
;
2783 spin_lock_irqsave(&cp
->tx_lock
[ring
], flags
);
2785 /* This is a hard error, log it. */
2786 if (TX_BUFFS_AVAIL(cp
, ring
) <=
2787 CAS_TABORT(cp
)*(skb_shinfo(skb
)->nr_frags
+ 1)) {
2788 netif_stop_queue(dev
);
2789 spin_unlock_irqrestore(&cp
->tx_lock
[ring
], flags
);
2790 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
2791 "queue awake!\n", dev
->name
);
2796 if (skb
->ip_summed
== CHECKSUM_HW
) {
2797 u64 csum_start_off
, csum_stuff_off
;
2799 csum_start_off
= (u64
) (skb
->h
.raw
- skb
->data
);
2800 csum_stuff_off
= (u64
) ((skb
->h
.raw
+ skb
->csum
) - skb
->data
);
2802 ctrl
= TX_DESC_CSUM_EN
|
2803 CAS_BASE(TX_DESC_CSUM_START
, csum_start_off
) |
2804 CAS_BASE(TX_DESC_CSUM_STUFF
, csum_stuff_off
);
2807 entry
= cp
->tx_new
[ring
];
2808 cp
->tx_skbs
[ring
][entry
] = skb
;
2810 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2811 len
= skb_headlen(skb
);
2812 mapping
= pci_map_page(cp
->pdev
, virt_to_page(skb
->data
),
2813 offset_in_page(skb
->data
), len
,
2817 tabort
= cas_calc_tabort(cp
, (unsigned long) skb
->data
, len
);
2818 if (unlikely(tabort
)) {
2819 /* NOTE: len is always > tabort */
2820 cas_write_txd(cp
, ring
, entry
, mapping
, len
- tabort
,
2821 ctrl
| TX_DESC_SOF
, 0);
2822 entry
= TX_DESC_NEXT(ring
, entry
);
2824 memcpy(tx_tiny_buf(cp
, ring
, entry
), skb
->data
+
2825 len
- tabort
, tabort
);
2826 mapping
= tx_tiny_map(cp
, ring
, entry
, tentry
);
2827 cas_write_txd(cp
, ring
, entry
, mapping
, tabort
, ctrl
,
2830 cas_write_txd(cp
, ring
, entry
, mapping
, len
, ctrl
|
2831 TX_DESC_SOF
, (nr_frags
== 0));
2833 entry
= TX_DESC_NEXT(ring
, entry
);
2835 for (frag
= 0; frag
< nr_frags
; frag
++) {
2836 skb_frag_t
*fragp
= &skb_shinfo(skb
)->frags
[frag
];
2839 mapping
= pci_map_page(cp
->pdev
, fragp
->page
,
2840 fragp
->page_offset
, len
,
2843 tabort
= cas_calc_tabort(cp
, fragp
->page_offset
, len
);
2844 if (unlikely(tabort
)) {
2847 /* NOTE: len is always > tabort */
2848 cas_write_txd(cp
, ring
, entry
, mapping
, len
- tabort
,
2850 entry
= TX_DESC_NEXT(ring
, entry
);
2852 addr
= cas_page_map(fragp
->page
);
2853 memcpy(tx_tiny_buf(cp
, ring
, entry
),
2854 addr
+ fragp
->page_offset
+ len
- tabort
,
2856 cas_page_unmap(addr
);
2857 mapping
= tx_tiny_map(cp
, ring
, entry
, tentry
);
2861 cas_write_txd(cp
, ring
, entry
, mapping
, len
, ctrl
,
2862 (frag
+ 1 == nr_frags
));
2863 entry
= TX_DESC_NEXT(ring
, entry
);
2866 cp
->tx_new
[ring
] = entry
;
2867 if (TX_BUFFS_AVAIL(cp
, ring
) <= CAS_TABORT(cp
)*(MAX_SKB_FRAGS
+ 1))
2868 netif_stop_queue(dev
);
2870 if (netif_msg_tx_queued(cp
))
2871 printk(KERN_DEBUG
"%s: tx[%d] queued, slot %d, skblen %d, "
2873 dev
->name
, ring
, entry
, skb
->len
,
2874 TX_BUFFS_AVAIL(cp
, ring
));
2875 writel(entry
, cp
->regs
+ REG_TX_KICKN(ring
));
2876 spin_unlock_irqrestore(&cp
->tx_lock
[ring
], flags
);
2880 static int cas_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2882 struct cas
*cp
= netdev_priv(dev
);
2884 /* this is only used as a load-balancing hint, so it doesn't
2885 * need to be SMP safe
2889 skb
= skb_padto(skb
, cp
->min_frame_size
);
2893 /* XXX: we need some higher-level QoS hooks to steer packets to
2894 * individual queues.
2896 if (cas_xmit_tx_ringN(cp
, ring
++ & N_TX_RINGS_MASK
, skb
))
2898 dev
->trans_start
= jiffies
;
2902 static void cas_init_tx_dma(struct cas
*cp
)
2904 u64 desc_dma
= cp
->block_dvma
;
2909 /* set up tx completion writeback registers. must be 8-byte aligned */
2910 #ifdef USE_TX_COMPWB
2911 off
= offsetof(struct cas_init_block
, tx_compwb
);
2912 writel((desc_dma
+ off
) >> 32, cp
->regs
+ REG_TX_COMPWB_DB_HI
);
2913 writel((desc_dma
+ off
) & 0xffffffff, cp
->regs
+ REG_TX_COMPWB_DB_LOW
);
2916 /* enable completion writebacks, enable paced mode,
2917 * disable read pipe, and disable pre-interrupt compwbs
2919 val
= TX_CFG_COMPWB_Q1
| TX_CFG_COMPWB_Q2
|
2920 TX_CFG_COMPWB_Q3
| TX_CFG_COMPWB_Q4
|
2921 TX_CFG_DMA_RDPIPE_DIS
| TX_CFG_PACED_MODE
|
2922 TX_CFG_INTR_COMPWB_DIS
;
2924 /* write out tx ring info and tx desc bases */
2925 for (i
= 0; i
< MAX_TX_RINGS
; i
++) {
2926 off
= (unsigned long) cp
->init_txds
[i
] -
2927 (unsigned long) cp
->init_block
;
2929 val
|= CAS_TX_RINGN_BASE(i
);
2930 writel((desc_dma
+ off
) >> 32, cp
->regs
+ REG_TX_DBN_HI(i
));
2931 writel((desc_dma
+ off
) & 0xffffffff, cp
->regs
+
2933 /* don't zero out the kick register here as the system
2937 writel(val
, cp
->regs
+ REG_TX_CFG
);
2939 /* program max burst sizes. these numbers should be different
2943 writel(0x800, cp
->regs
+ REG_TX_MAXBURST_0
);
2944 writel(0x1600, cp
->regs
+ REG_TX_MAXBURST_1
);
2945 writel(0x2400, cp
->regs
+ REG_TX_MAXBURST_2
);
2946 writel(0x4800, cp
->regs
+ REG_TX_MAXBURST_3
);
2948 writel(0x800, cp
->regs
+ REG_TX_MAXBURST_0
);
2949 writel(0x800, cp
->regs
+ REG_TX_MAXBURST_1
);
2950 writel(0x800, cp
->regs
+ REG_TX_MAXBURST_2
);
2951 writel(0x800, cp
->regs
+ REG_TX_MAXBURST_3
);
2955 /* Must be invoked under cp->lock. */
2956 static inline void cas_init_dma(struct cas
*cp
)
2958 cas_init_tx_dma(cp
);
2959 cas_init_rx_dma(cp
);
2962 /* Must be invoked under cp->lock. */
2963 static u32
cas_setup_multicast(struct cas
*cp
)
2968 if (cp
->dev
->flags
& IFF_PROMISC
) {
2969 rxcfg
|= MAC_RX_CFG_PROMISC_EN
;
2971 } else if (cp
->dev
->flags
& IFF_ALLMULTI
) {
2972 for (i
=0; i
< 16; i
++)
2973 writel(0xFFFF, cp
->regs
+ REG_MAC_HASH_TABLEN(i
));
2974 rxcfg
|= MAC_RX_CFG_HASH_FILTER_EN
;
2979 struct dev_mc_list
*dmi
= cp
->dev
->mc_list
;
2982 /* use the alternate mac address registers for the
2983 * first 15 multicast addresses
2985 for (i
= 1; i
<= CAS_MC_EXACT_MATCH_SIZE
; i
++) {
2987 writel(0x0, cp
->regs
+ REG_MAC_ADDRN(i
*3 + 0));
2988 writel(0x0, cp
->regs
+ REG_MAC_ADDRN(i
*3 + 1));
2989 writel(0x0, cp
->regs
+ REG_MAC_ADDRN(i
*3 + 2));
2992 writel((dmi
->dmi_addr
[4] << 8) | dmi
->dmi_addr
[5],
2993 cp
->regs
+ REG_MAC_ADDRN(i
*3 + 0));
2994 writel((dmi
->dmi_addr
[2] << 8) | dmi
->dmi_addr
[3],
2995 cp
->regs
+ REG_MAC_ADDRN(i
*3 + 1));
2996 writel((dmi
->dmi_addr
[0] << 8) | dmi
->dmi_addr
[1],
2997 cp
->regs
+ REG_MAC_ADDRN(i
*3 + 2));
3001 /* use hw hash table for the next series of
3002 * multicast addresses
3004 memset(hash_table
, 0, sizeof(hash_table
));
3006 crc
= ether_crc_le(ETH_ALEN
, dmi
->dmi_addr
);
3008 hash_table
[crc
>> 4] |= 1 << (15 - (crc
& 0xf));
3011 for (i
=0; i
< 16; i
++)
3012 writel(hash_table
[i
], cp
->regs
+
3013 REG_MAC_HASH_TABLEN(i
));
3014 rxcfg
|= MAC_RX_CFG_HASH_FILTER_EN
;
3020 /* must be invoked under cp->stat_lock[N_TX_RINGS] */
3021 static void cas_clear_mac_err(struct cas
*cp
)
3023 writel(0, cp
->regs
+ REG_MAC_COLL_NORMAL
);
3024 writel(0, cp
->regs
+ REG_MAC_COLL_FIRST
);
3025 writel(0, cp
->regs
+ REG_MAC_COLL_EXCESS
);
3026 writel(0, cp
->regs
+ REG_MAC_COLL_LATE
);
3027 writel(0, cp
->regs
+ REG_MAC_TIMER_DEFER
);
3028 writel(0, cp
->regs
+ REG_MAC_ATTEMPTS_PEAK
);
3029 writel(0, cp
->regs
+ REG_MAC_RECV_FRAME
);
3030 writel(0, cp
->regs
+ REG_MAC_LEN_ERR
);
3031 writel(0, cp
->regs
+ REG_MAC_ALIGN_ERR
);
3032 writel(0, cp
->regs
+ REG_MAC_FCS_ERR
);
3033 writel(0, cp
->regs
+ REG_MAC_RX_CODE_ERR
);
3037 static void cas_mac_reset(struct cas
*cp
)
3041 /* do both TX and RX reset */
3042 writel(0x1, cp
->regs
+ REG_MAC_TX_RESET
);
3043 writel(0x1, cp
->regs
+ REG_MAC_RX_RESET
);
3048 if (readl(cp
->regs
+ REG_MAC_TX_RESET
) == 0)
3056 if (readl(cp
->regs
+ REG_MAC_RX_RESET
) == 0)
3061 if (readl(cp
->regs
+ REG_MAC_TX_RESET
) |
3062 readl(cp
->regs
+ REG_MAC_RX_RESET
))
3063 printk(KERN_ERR
"%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
3064 cp
->dev
->name
, readl(cp
->regs
+ REG_MAC_TX_RESET
),
3065 readl(cp
->regs
+ REG_MAC_RX_RESET
),
3066 readl(cp
->regs
+ REG_MAC_STATE_MACHINE
));
3070 /* Must be invoked under cp->lock. */
3071 static void cas_init_mac(struct cas
*cp
)
3073 unsigned char *e
= &cp
->dev
->dev_addr
[0];
3075 #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
3080 /* setup core arbitration weight register */
3081 writel(CAWR_RR_DIS
, cp
->regs
+ REG_CAWR
);
3083 /* XXX Use pci_dma_burst_advice() */
3084 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
3085 /* set the infinite burst register for chips that don't have
3088 if ((cp
->cas_flags
& CAS_FLAG_TARGET_ABORT
) == 0)
3089 writel(INF_BURST_EN
, cp
->regs
+ REG_INF_BURST
);
3092 writel(0x1BF0, cp
->regs
+ REG_MAC_SEND_PAUSE
);
3094 writel(0x00, cp
->regs
+ REG_MAC_IPG0
);
3095 writel(0x08, cp
->regs
+ REG_MAC_IPG1
);
3096 writel(0x04, cp
->regs
+ REG_MAC_IPG2
);
3098 /* change later for 802.3z */
3099 writel(0x40, cp
->regs
+ REG_MAC_SLOT_TIME
);
3101 /* min frame + FCS */
3102 writel(ETH_ZLEN
+ 4, cp
->regs
+ REG_MAC_FRAMESIZE_MIN
);
3104 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
3105 * specify the maximum frame size to prevent RX tag errors on
3108 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST
, 0x2000) |
3109 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME
,
3110 (CAS_MAX_MTU
+ ETH_HLEN
+ 4 + 4)),
3111 cp
->regs
+ REG_MAC_FRAMESIZE_MAX
);
3113 /* NOTE: crc_size is used as a surrogate for half-duplex.
3114 * workaround saturn half-duplex issue by increasing preamble
3117 if ((cp
->cas_flags
& CAS_FLAG_SATURN
) && cp
->crc_size
)
3118 writel(0x41, cp
->regs
+ REG_MAC_PA_SIZE
);
3120 writel(0x07, cp
->regs
+ REG_MAC_PA_SIZE
);
3121 writel(0x04, cp
->regs
+ REG_MAC_JAM_SIZE
);
3122 writel(0x10, cp
->regs
+ REG_MAC_ATTEMPT_LIMIT
);
3123 writel(0x8808, cp
->regs
+ REG_MAC_CTRL_TYPE
);
3125 writel((e
[5] | (e
[4] << 8)) & 0x3ff, cp
->regs
+ REG_MAC_RANDOM_SEED
);
3127 writel(0, cp
->regs
+ REG_MAC_ADDR_FILTER0
);
3128 writel(0, cp
->regs
+ REG_MAC_ADDR_FILTER1
);
3129 writel(0, cp
->regs
+ REG_MAC_ADDR_FILTER2
);
3130 writel(0, cp
->regs
+ REG_MAC_ADDR_FILTER2_1_MASK
);
3131 writel(0, cp
->regs
+ REG_MAC_ADDR_FILTER0_MASK
);
3133 /* setup mac address in perfect filter array */
3134 for (i
= 0; i
< 45; i
++)
3135 writel(0x0, cp
->regs
+ REG_MAC_ADDRN(i
));
3137 writel((e
[4] << 8) | e
[5], cp
->regs
+ REG_MAC_ADDRN(0));
3138 writel((e
[2] << 8) | e
[3], cp
->regs
+ REG_MAC_ADDRN(1));
3139 writel((e
[0] << 8) | e
[1], cp
->regs
+ REG_MAC_ADDRN(2));
3141 writel(0x0001, cp
->regs
+ REG_MAC_ADDRN(42));
3142 writel(0xc200, cp
->regs
+ REG_MAC_ADDRN(43));
3143 writel(0x0180, cp
->regs
+ REG_MAC_ADDRN(44));
3145 #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
3146 cp
->mac_rx_cfg
= cas_setup_multicast(cp
);
3148 /* WTZ: Do what Adrian did in cas_set_multicast. Doing
3149 * a writel does not seem to be necessary because Cassini
3150 * seems to preserve the configuration when we do the reset.
3151 * If the chip is in trouble, though, it is not clear if we
3152 * can really count on this behavior. cas_set_multicast uses
3153 * spin_lock_irqsave, but we are called only in cas_init_hw and
3154 * cas_init_hw is protected by cas_lock_all, which calls
3155 * spin_lock_irq (so it doesn't need to save the flags, and
3156 * we should be OK for the writel, as that is the only
3159 cp
->mac_rx_cfg
= rxcfg
= cas_setup_multicast(cp
);
3160 writel(rxcfg
, cp
->regs
+ REG_MAC_RX_CFG
);
3162 spin_lock(&cp
->stat_lock
[N_TX_RINGS
]);
3163 cas_clear_mac_err(cp
);
3164 spin_unlock(&cp
->stat_lock
[N_TX_RINGS
]);
3166 /* Setup MAC interrupts. We want to get all of the interesting
3167 * counter expiration events, but we do not want to hear about
3168 * normal rx/tx as the DMA engine tells us that.
3170 writel(MAC_TX_FRAME_XMIT
, cp
->regs
+ REG_MAC_TX_MASK
);
3171 writel(MAC_RX_FRAME_RECV
, cp
->regs
+ REG_MAC_RX_MASK
);
3173 /* Don't enable even the PAUSE interrupts for now, we
3174 * make no use of those events other than to record them.
3176 writel(0xffffffff, cp
->regs
+ REG_MAC_CTRL_MASK
);
3179 /* Must be invoked under cp->lock. */
3180 static void cas_init_pause_thresholds(struct cas
*cp
)
3182 /* Calculate pause thresholds. Setting the OFF threshold to the
3183 * full RX fifo size effectively disables PAUSE generation
3185 if (cp
->rx_fifo_size
<= (2 * 1024)) {
3186 cp
->rx_pause_off
= cp
->rx_pause_on
= cp
->rx_fifo_size
;
3188 int max_frame
= (cp
->dev
->mtu
+ ETH_HLEN
+ 4 + 4 + 64) & ~63;
3189 if (max_frame
* 3 > cp
->rx_fifo_size
) {
3190 cp
->rx_pause_off
= 7104;
3191 cp
->rx_pause_on
= 960;
3193 int off
= (cp
->rx_fifo_size
- (max_frame
* 2));
3194 int on
= off
- max_frame
;
3195 cp
->rx_pause_off
= off
;
3196 cp
->rx_pause_on
= on
;
3201 static int cas_vpd_match(const void __iomem
*p
, const char *str
)
3203 int len
= strlen(str
) + 1;
3206 for (i
= 0; i
< len
; i
++) {
3207 if (readb(p
+ i
) != str
[i
])
3214 /* get the mac address by reading the vpd information in the rom.
3215 * also get the phy type and determine if there's an entropy generator.
3216 * NOTE: this is a bit convoluted for the following reasons:
3217 * 1) vpd info has order-dependent mac addresses for multinic cards
3218 * 2) the only way to determine the nic order is to use the slot
3220 * 3) fiber cards don't have bridges, so their slot numbers don't
3222 * 4) we don't actually know we have a fiber card until after
3223 * the mac addresses are parsed.
3225 static int cas_get_vpd_info(struct cas
*cp
, unsigned char *dev_addr
,
3228 void __iomem
*p
= cp
->regs
+ REG_EXPANSION_ROM_RUN_START
;
3229 void __iomem
*base
, *kstart
;
3232 #define VPD_FOUND_MAC 0x01
3233 #define VPD_FOUND_PHY 0x02
3235 int phy_type
= CAS_PHY_MII_MDIO0
; /* default phy type */
3238 /* give us access to the PROM */
3239 writel(BIM_LOCAL_DEV_PROM
| BIM_LOCAL_DEV_PAD
,
3240 cp
->regs
+ REG_BIM_LOCAL_DEV_EN
);
3242 /* check for an expansion rom */
3243 if (readb(p
) != 0x55 || readb(p
+ 1) != 0xaa)
3244 goto use_random_mac_addr
;
3246 /* search for beginning of vpd */
3248 for (i
= 2; i
< EXPANSION_ROM_SIZE
; i
++) {
3249 /* check for PCIR */
3250 if ((readb(p
+ i
+ 0) == 0x50) &&
3251 (readb(p
+ i
+ 1) == 0x43) &&
3252 (readb(p
+ i
+ 2) == 0x49) &&
3253 (readb(p
+ i
+ 3) == 0x52)) {
3254 base
= p
+ (readb(p
+ i
+ 8) |
3255 (readb(p
+ i
+ 9) << 8));
3260 if (!base
|| (readb(base
) != 0x82))
3261 goto use_random_mac_addr
;
3263 i
= (readb(base
+ 1) | (readb(base
+ 2) << 8)) + 3;
3264 while (i
< EXPANSION_ROM_SIZE
) {
3265 if (readb(base
+ i
) != 0x90) /* no vpd found */
3266 goto use_random_mac_addr
;
3268 /* found a vpd field */
3269 len
= readb(base
+ i
+ 1) | (readb(base
+ i
+ 2) << 8);
3271 /* extract keywords */
3272 kstart
= base
+ i
+ 3;
3274 while ((p
- kstart
) < len
) {
3275 int klen
= readb(p
+ 2);
3281 /* look for the following things:
3282 * -- correct length == 29
3283 * 3 (type) + 2 (size) +
3284 * 18 (strlen("local-mac-address") + 1) +
3286 * -- VPD Instance 'I'
3287 * -- VPD Type Bytes 'B'
3288 * -- VPD data length == 6
3289 * -- property string == local-mac-address
3291 * -- correct length == 24
3292 * 3 (type) + 2 (size) +
3293 * 12 (strlen("entropy-dev") + 1) +
3294 * 7 (strlen("vms110") + 1)
3295 * -- VPD Instance 'I'
3296 * -- VPD Type String 'B'
3297 * -- VPD data length == 7
3298 * -- property string == entropy-dev
3300 * -- correct length == 18
3301 * 3 (type) + 2 (size) +
3302 * 9 (strlen("phy-type") + 1) +
3303 * 4 (strlen("pcs") + 1)
3304 * -- VPD Instance 'I'
3305 * -- VPD Type String 'S'
3306 * -- VPD data length == 4
3307 * -- property string == phy-type
3309 * -- correct length == 23
3310 * 3 (type) + 2 (size) +
3311 * 14 (strlen("phy-interface") + 1) +
3312 * 4 (strlen("pcs") + 1)
3313 * -- VPD Instance 'I'
3314 * -- VPD Type String 'S'
3315 * -- VPD data length == 4
3316 * -- property string == phy-interface
3318 if (readb(p
) != 'I')
3321 /* finally, check string and length */
3322 type
= readb(p
+ 3);
3324 if ((klen
== 29) && readb(p
+ 4) == 6 &&
3325 cas_vpd_match(p
+ 5,
3326 "local-mac-address")) {
3327 if (mac_off
++ > offset
)
3330 /* set mac address */
3331 for (j
= 0; j
< 6; j
++)
3341 #ifdef USE_ENTROPY_DEV
3343 cas_vpd_match(p
+ 5, "entropy-dev") &&
3344 cas_vpd_match(p
+ 17, "vms110")) {
3345 cp
->cas_flags
|= CAS_FLAG_ENTROPY_DEV
;
3350 if (found
& VPD_FOUND_PHY
)
3353 if ((klen
== 18) && readb(p
+ 4) == 4 &&
3354 cas_vpd_match(p
+ 5, "phy-type")) {
3355 if (cas_vpd_match(p
+ 14, "pcs")) {
3356 phy_type
= CAS_PHY_SERDES
;
3361 if ((klen
== 23) && readb(p
+ 4) == 4 &&
3362 cas_vpd_match(p
+ 5, "phy-interface")) {
3363 if (cas_vpd_match(p
+ 19, "pcs")) {
3364 phy_type
= CAS_PHY_SERDES
;
3369 found
|= VPD_FOUND_MAC
;
3373 found
|= VPD_FOUND_PHY
;
3381 use_random_mac_addr
:
3382 if (found
& VPD_FOUND_MAC
)
3385 /* Sun MAC prefix then 3 random bytes. */
3386 printk(PFX
"MAC address not found in ROM VPD\n");
3390 get_random_bytes(dev_addr
+ 3, 3);
3393 writel(0, cp
->regs
+ REG_BIM_LOCAL_DEV_EN
);
3397 /* check pci invariants */
3398 static void cas_check_pci_invariants(struct cas
*cp
)
3400 struct pci_dev
*pdev
= cp
->pdev
;
3404 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
3405 if ((pdev
->vendor
== PCI_VENDOR_ID_SUN
) &&
3406 (pdev
->device
== PCI_DEVICE_ID_SUN_CASSINI
)) {
3407 if (rev
>= CAS_ID_REVPLUS
)
3408 cp
->cas_flags
|= CAS_FLAG_REG_PLUS
;
3409 if (rev
< CAS_ID_REVPLUS02u
)
3410 cp
->cas_flags
|= CAS_FLAG_TARGET_ABORT
;
3412 /* Original Cassini supports HW CSUM, but it's not
3413 * enabled by default as it can trigger TX hangs.
3415 if (rev
< CAS_ID_REV2
)
3416 cp
->cas_flags
|= CAS_FLAG_NO_HW_CSUM
;
3418 /* Only sun has original cassini chips. */
3419 cp
->cas_flags
|= CAS_FLAG_REG_PLUS
;
3421 /* We use a flag because the same phy might be externally
3424 if ((pdev
->vendor
== PCI_VENDOR_ID_NS
) &&
3425 (pdev
->device
== PCI_DEVICE_ID_NS_SATURN
))
3426 cp
->cas_flags
|= CAS_FLAG_SATURN
;
3431 static int cas_check_invariants(struct cas
*cp
)
3433 struct pci_dev
*pdev
= cp
->pdev
;
3437 /* get page size for rx buffers. */
3439 #ifdef USE_PAGE_ORDER
3440 if (PAGE_SHIFT
< CAS_JUMBO_PAGE_SHIFT
) {
3441 /* see if we can allocate larger pages */
3442 struct page
*page
= alloc_pages(GFP_ATOMIC
,
3443 CAS_JUMBO_PAGE_SHIFT
-
3446 __free_pages(page
, CAS_JUMBO_PAGE_SHIFT
- PAGE_SHIFT
);
3447 cp
->page_order
= CAS_JUMBO_PAGE_SHIFT
- PAGE_SHIFT
;
3449 printk(PFX
"MTU limited to %d bytes\n", CAS_MAX_MTU
);
3453 cp
->page_size
= (PAGE_SIZE
<< cp
->page_order
);
3455 /* Fetch the FIFO configurations. */
3456 cp
->tx_fifo_size
= readl(cp
->regs
+ REG_TX_FIFO_SIZE
) * 64;
3457 cp
->rx_fifo_size
= RX_FIFO_SIZE
;
3459 /* finish phy determination. MDIO1 takes precedence over MDIO0 if
3460 * they're both connected.
3462 cp
->phy_type
= cas_get_vpd_info(cp
, cp
->dev
->dev_addr
,
3463 PCI_SLOT(pdev
->devfn
));
3464 if (cp
->phy_type
& CAS_PHY_SERDES
) {
3465 cp
->cas_flags
|= CAS_FLAG_1000MB_CAP
;
3466 return 0; /* no more checking needed */
3470 cfg
= readl(cp
->regs
+ REG_MIF_CFG
);
3471 if (cfg
& MIF_CFG_MDIO_1
) {
3472 cp
->phy_type
= CAS_PHY_MII_MDIO1
;
3473 } else if (cfg
& MIF_CFG_MDIO_0
) {
3474 cp
->phy_type
= CAS_PHY_MII_MDIO0
;
3477 cas_mif_poll(cp
, 0);
3478 writel(PCS_DATAPATH_MODE_MII
, cp
->regs
+ REG_PCS_DATAPATH_MODE
);
3480 for (i
= 0; i
< 32; i
++) {
3484 for (j
= 0; j
< 3; j
++) {
3486 phy_id
= cas_phy_read(cp
, MII_PHYSID1
) << 16;
3487 phy_id
|= cas_phy_read(cp
, MII_PHYSID2
);
3488 if (phy_id
&& (phy_id
!= 0xFFFFFFFF)) {
3489 cp
->phy_id
= phy_id
;
3494 printk(KERN_ERR PFX
"MII phy did not respond [%08x]\n",
3495 readl(cp
->regs
+ REG_MIF_STATE_MACHINE
));
3499 /* see if we can do gigabit */
3500 cfg
= cas_phy_read(cp
, MII_BMSR
);
3501 if ((cfg
& CAS_BMSR_1000_EXTEND
) &&
3502 cas_phy_read(cp
, CAS_MII_1000_EXTEND
))
3503 cp
->cas_flags
|= CAS_FLAG_1000MB_CAP
;
3507 /* Must be invoked under cp->lock. */
3508 static inline void cas_start_dma(struct cas
*cp
)
3515 val
= readl(cp
->regs
+ REG_TX_CFG
) | TX_CFG_DMA_EN
;
3516 writel(val
, cp
->regs
+ REG_TX_CFG
);
3517 val
= readl(cp
->regs
+ REG_RX_CFG
) | RX_CFG_DMA_EN
;
3518 writel(val
, cp
->regs
+ REG_RX_CFG
);
3520 /* enable the mac */
3521 val
= readl(cp
->regs
+ REG_MAC_TX_CFG
) | MAC_TX_CFG_EN
;
3522 writel(val
, cp
->regs
+ REG_MAC_TX_CFG
);
3523 val
= readl(cp
->regs
+ REG_MAC_RX_CFG
) | MAC_RX_CFG_EN
;
3524 writel(val
, cp
->regs
+ REG_MAC_RX_CFG
);
3528 val
= readl(cp
->regs
+ REG_MAC_TX_CFG
);
3529 if ((val
& MAC_TX_CFG_EN
))
3533 if (i
< 0) txfailed
= 1;
3536 val
= readl(cp
->regs
+ REG_MAC_RX_CFG
);
3537 if ((val
& MAC_RX_CFG_EN
)) {
3540 "%s: enabling mac failed [tx:%08x:%08x].\n",
3542 readl(cp
->regs
+ REG_MIF_STATE_MACHINE
),
3543 readl(cp
->regs
+ REG_MAC_STATE_MACHINE
));
3545 goto enable_rx_done
;
3549 printk(KERN_ERR
"%s: enabling mac failed [%s:%08x:%08x].\n",
3551 (txfailed
? "tx,rx":"rx"),
3552 readl(cp
->regs
+ REG_MIF_STATE_MACHINE
),
3553 readl(cp
->regs
+ REG_MAC_STATE_MACHINE
));
3556 cas_unmask_intr(cp
); /* enable interrupts */
3557 writel(RX_DESC_RINGN_SIZE(0) - 4, cp
->regs
+ REG_RX_KICK
);
3558 writel(0, cp
->regs
+ REG_RX_COMP_TAIL
);
3560 if (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) {
3561 if (N_RX_DESC_RINGS
> 1)
3562 writel(RX_DESC_RINGN_SIZE(1) - 4,
3563 cp
->regs
+ REG_PLUS_RX_KICK1
);
3565 for (i
= 1; i
< N_RX_COMP_RINGS
; i
++)
3566 writel(0, cp
->regs
+ REG_PLUS_RX_COMPN_TAIL(i
));
3570 /* Must be invoked under cp->lock. */
3571 static void cas_read_pcs_link_mode(struct cas
*cp
, int *fd
, int *spd
,
3574 u32 val
= readl(cp
->regs
+ REG_PCS_MII_LPA
);
3575 *fd
= (val
& PCS_MII_LPA_FD
) ? 1 : 0;
3576 *pause
= (val
& PCS_MII_LPA_SYM_PAUSE
) ? 0x01 : 0x00;
3577 if (val
& PCS_MII_LPA_ASYM_PAUSE
)
3582 /* Must be invoked under cp->lock. */
3583 static void cas_read_mii_link_mode(struct cas
*cp
, int *fd
, int *spd
,
3592 /* use GMII registers */
3593 val
= cas_phy_read(cp
, MII_LPA
);
3594 if (val
& CAS_LPA_PAUSE
)
3597 if (val
& CAS_LPA_ASYM_PAUSE
)
3600 if (val
& LPA_DUPLEX
)
3605 if (cp
->cas_flags
& CAS_FLAG_1000MB_CAP
) {
3606 val
= cas_phy_read(cp
, CAS_MII_1000_STATUS
);
3607 if (val
& (CAS_LPA_1000FULL
| CAS_LPA_1000HALF
))
3609 if (val
& CAS_LPA_1000FULL
)
3614 /* A link-up condition has occurred, initialize and enable the
3617 * Must be invoked under cp->lock.
3619 static void cas_set_link_modes(struct cas
*cp
)
3622 int full_duplex
, speed
, pause
;
3628 if (CAS_PHY_MII(cp
->phy_type
)) {
3629 cas_mif_poll(cp
, 0);
3630 val
= cas_phy_read(cp
, MII_BMCR
);
3631 if (val
& BMCR_ANENABLE
) {
3632 cas_read_mii_link_mode(cp
, &full_duplex
, &speed
,
3635 if (val
& BMCR_FULLDPLX
)
3638 if (val
& BMCR_SPEED100
)
3640 else if (val
& CAS_BMCR_SPEED1000
)
3641 speed
= (cp
->cas_flags
& CAS_FLAG_1000MB_CAP
) ?
3644 cas_mif_poll(cp
, 1);
3647 val
= readl(cp
->regs
+ REG_PCS_MII_CTRL
);
3648 cas_read_pcs_link_mode(cp
, &full_duplex
, &speed
, &pause
);
3649 if ((val
& PCS_MII_AUTONEG_EN
) == 0) {
3650 if (val
& PCS_MII_CTRL_DUPLEX
)
3655 if (netif_msg_link(cp
))
3656 printk(KERN_INFO
"%s: Link up at %d Mbps, %s-duplex.\n",
3657 cp
->dev
->name
, speed
, (full_duplex
? "full" : "half"));
3659 val
= MAC_XIF_TX_MII_OUTPUT_EN
| MAC_XIF_LINK_LED
;
3660 if (CAS_PHY_MII(cp
->phy_type
)) {
3661 val
|= MAC_XIF_MII_BUFFER_OUTPUT_EN
;
3663 val
|= MAC_XIF_DISABLE_ECHO
;
3666 val
|= MAC_XIF_FDPLX_LED
;
3668 val
|= MAC_XIF_GMII_MODE
;
3669 writel(val
, cp
->regs
+ REG_MAC_XIF_CFG
);
3671 /* deal with carrier and collision detect. */
3672 val
= MAC_TX_CFG_IPG_EN
;
3674 val
|= MAC_TX_CFG_IGNORE_CARRIER
;
3675 val
|= MAC_TX_CFG_IGNORE_COLL
;
3677 #ifndef USE_CSMA_CD_PROTO
3678 val
|= MAC_TX_CFG_NEVER_GIVE_UP_EN
;
3679 val
|= MAC_TX_CFG_NEVER_GIVE_UP_LIM
;
3682 /* val now set up for REG_MAC_TX_CFG */
3684 /* If gigabit and half-duplex, enable carrier extension
3685 * mode. increase slot time to 512 bytes as well.
3686 * else, disable it and make sure slot time is 64 bytes.
3687 * also activate checksum bug workaround
3689 if ((speed
== 1000) && !full_duplex
) {
3690 writel(val
| MAC_TX_CFG_CARRIER_EXTEND
,
3691 cp
->regs
+ REG_MAC_TX_CFG
);
3693 val
= readl(cp
->regs
+ REG_MAC_RX_CFG
);
3694 val
&= ~MAC_RX_CFG_STRIP_FCS
; /* checksum workaround */
3695 writel(val
| MAC_RX_CFG_CARRIER_EXTEND
,
3696 cp
->regs
+ REG_MAC_RX_CFG
);
3698 writel(0x200, cp
->regs
+ REG_MAC_SLOT_TIME
);
3701 /* minimum size gigabit frame at half duplex */
3702 cp
->min_frame_size
= CAS_1000MB_MIN_FRAME
;
3705 writel(val
, cp
->regs
+ REG_MAC_TX_CFG
);
3707 /* checksum bug workaround. don't strip FCS when in
3710 val
= readl(cp
->regs
+ REG_MAC_RX_CFG
);
3712 val
|= MAC_RX_CFG_STRIP_FCS
;
3714 cp
->min_frame_size
= CAS_MIN_MTU
;
3716 val
&= ~MAC_RX_CFG_STRIP_FCS
;
3718 cp
->min_frame_size
= CAS_MIN_FRAME
;
3720 writel(val
& ~MAC_RX_CFG_CARRIER_EXTEND
,
3721 cp
->regs
+ REG_MAC_RX_CFG
);
3722 writel(0x40, cp
->regs
+ REG_MAC_SLOT_TIME
);
3725 if (netif_msg_link(cp
)) {
3727 printk(KERN_INFO
"%s: Pause is enabled "
3728 "(rxfifo: %d off: %d on: %d)\n",
3733 } else if (pause
& 0x10) {
3734 printk(KERN_INFO
"%s: TX pause enabled\n",
3737 printk(KERN_INFO
"%s: Pause is disabled\n",
3742 val
= readl(cp
->regs
+ REG_MAC_CTRL_CFG
);
3743 val
&= ~(MAC_CTRL_CFG_SEND_PAUSE_EN
| MAC_CTRL_CFG_RECV_PAUSE_EN
);
3744 if (pause
) { /* symmetric or asymmetric pause */
3745 val
|= MAC_CTRL_CFG_SEND_PAUSE_EN
;
3746 if (pause
& 0x01) { /* symmetric pause */
3747 val
|= MAC_CTRL_CFG_RECV_PAUSE_EN
;
3750 writel(val
, cp
->regs
+ REG_MAC_CTRL_CFG
);
3754 /* Must be invoked under cp->lock. */
3755 static void cas_init_hw(struct cas
*cp
, int restart_link
)
3760 cas_init_pause_thresholds(cp
);
3765 /* Default aneg parameters */
3766 cp
->timer_ticks
= 0;
3767 cas_begin_auto_negotiation(cp
, NULL
);
3768 } else if (cp
->lstate
== link_up
) {
3769 cas_set_link_modes(cp
);
3770 netif_carrier_on(cp
->dev
);
3774 /* Must be invoked under cp->lock. on earlier cassini boards,
3775 * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
3776 * let it settle out, and then restore pci state.
3778 static void cas_hard_reset(struct cas
*cp
)
3780 writel(BIM_LOCAL_DEV_SOFT_0
, cp
->regs
+ REG_BIM_LOCAL_DEV_EN
);
3782 pci_restore_state(cp
->pdev
);
3786 static void cas_global_reset(struct cas
*cp
, int blkflag
)
3790 /* issue a global reset. don't use RSTOUT. */
3791 if (blkflag
&& !CAS_PHY_MII(cp
->phy_type
)) {
3792 /* For PCS, when the blkflag is set, we should set the
3793 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
3794 * the last autonegotiation from being cleared. We'll
3795 * need some special handling if the chip is set into a
3798 writel((SW_RESET_TX
| SW_RESET_RX
| SW_RESET_BLOCK_PCS_SLINK
),
3799 cp
->regs
+ REG_SW_RESET
);
3801 writel(SW_RESET_TX
| SW_RESET_RX
, cp
->regs
+ REG_SW_RESET
);
3804 /* need to wait at least 3ms before polling register */
3808 while (limit
-- > 0) {
3809 u32 val
= readl(cp
->regs
+ REG_SW_RESET
);
3810 if ((val
& (SW_RESET_TX
| SW_RESET_RX
)) == 0)
3814 printk(KERN_ERR
"%s: sw reset failed.\n", cp
->dev
->name
);
3817 /* enable various BIM interrupts */
3818 writel(BIM_CFG_DPAR_INTR_ENABLE
| BIM_CFG_RMA_INTR_ENABLE
|
3819 BIM_CFG_RTA_INTR_ENABLE
, cp
->regs
+ REG_BIM_CFG
);
3821 /* clear out pci error status mask for handled errors.
3822 * we don't deal with DMA counter overflows as they happen
3825 writel(0xFFFFFFFFU
& ~(PCI_ERR_BADACK
| PCI_ERR_DTRTO
|
3826 PCI_ERR_OTHER
| PCI_ERR_BIM_DMA_WRITE
|
3827 PCI_ERR_BIM_DMA_READ
), cp
->regs
+
3828 REG_PCI_ERR_STATUS_MASK
);
3830 /* set up for MII by default to address mac rx reset timeout
3833 writel(PCS_DATAPATH_MODE_MII
, cp
->regs
+ REG_PCS_DATAPATH_MODE
);
3836 static void cas_reset(struct cas
*cp
, int blkflag
)
3841 cas_global_reset(cp
, blkflag
);
3843 cas_entropy_reset(cp
);
3845 /* disable dma engines. */
3846 val
= readl(cp
->regs
+ REG_TX_CFG
);
3847 val
&= ~TX_CFG_DMA_EN
;
3848 writel(val
, cp
->regs
+ REG_TX_CFG
);
3850 val
= readl(cp
->regs
+ REG_RX_CFG
);
3851 val
&= ~RX_CFG_DMA_EN
;
3852 writel(val
, cp
->regs
+ REG_RX_CFG
);
3854 /* program header parser */
3855 if ((cp
->cas_flags
& CAS_FLAG_TARGET_ABORT
) ||
3856 (CAS_HP_ALT_FIRMWARE
== cas_prog_null
)) {
3857 cas_load_firmware(cp
, CAS_HP_FIRMWARE
);
3859 cas_load_firmware(cp
, CAS_HP_ALT_FIRMWARE
);
3862 /* clear out error registers */
3863 spin_lock(&cp
->stat_lock
[N_TX_RINGS
]);
3864 cas_clear_mac_err(cp
);
3865 spin_unlock(&cp
->stat_lock
[N_TX_RINGS
]);
3868 /* Shut down the chip, must be called with pm_sem held. */
3869 static void cas_shutdown(struct cas
*cp
)
3871 unsigned long flags
;
3873 /* Make us not-running to avoid timers respawning */
3876 del_timer_sync(&cp
->link_timer
);
3878 /* Stop the reset task */
3880 while (atomic_read(&cp
->reset_task_pending_mtu
) ||
3881 atomic_read(&cp
->reset_task_pending_spare
) ||
3882 atomic_read(&cp
->reset_task_pending_all
))
3886 while (atomic_read(&cp
->reset_task_pending
))
3889 /* Actually stop the chip */
3890 cas_lock_all_save(cp
, flags
);
3892 if (cp
->cas_flags
& CAS_FLAG_SATURN
)
3893 cas_phy_powerdown(cp
);
3894 cas_unlock_all_restore(cp
, flags
);
3897 static int cas_change_mtu(struct net_device
*dev
, int new_mtu
)
3899 struct cas
*cp
= netdev_priv(dev
);
3901 if (new_mtu
< CAS_MIN_MTU
|| new_mtu
> CAS_MAX_MTU
)
3905 if (!netif_running(dev
) || !netif_device_present(dev
))
3908 /* let the reset task handle it */
3910 atomic_inc(&cp
->reset_task_pending
);
3911 if ((cp
->phy_type
& CAS_PHY_SERDES
)) {
3912 atomic_inc(&cp
->reset_task_pending_all
);
3914 atomic_inc(&cp
->reset_task_pending_mtu
);
3916 schedule_work(&cp
->reset_task
);
3918 atomic_set(&cp
->reset_task_pending
, (cp
->phy_type
& CAS_PHY_SERDES
) ?
3919 CAS_RESET_ALL
: CAS_RESET_MTU
);
3920 printk(KERN_ERR
"reset called in cas_change_mtu\n");
3921 schedule_work(&cp
->reset_task
);
3924 flush_scheduled_work();
3928 static void cas_clean_txd(struct cas
*cp
, int ring
)
3930 struct cas_tx_desc
*txd
= cp
->init_txds
[ring
];
3931 struct sk_buff
*skb
, **skbs
= cp
->tx_skbs
[ring
];
3935 size
= TX_DESC_RINGN_SIZE(ring
);
3936 for (i
= 0; i
< size
; i
++) {
3939 if (skbs
[i
] == NULL
)
3945 for (frag
= 0; frag
<= skb_shinfo(skb
)->nr_frags
; frag
++) {
3946 int ent
= i
& (size
- 1);
3948 /* first buffer is never a tiny buffer and so
3949 * needs to be unmapped.
3951 daddr
= le64_to_cpu(txd
[ent
].buffer
);
3952 dlen
= CAS_VAL(TX_DESC_BUFLEN
,
3953 le64_to_cpu(txd
[ent
].control
));
3954 pci_unmap_page(cp
->pdev
, daddr
, dlen
,
3957 if (frag
!= skb_shinfo(skb
)->nr_frags
) {
3960 /* next buffer might by a tiny buffer.
3963 ent
= i
& (size
- 1);
3964 if (cp
->tx_tiny_use
[ring
][ent
].used
)
3968 dev_kfree_skb_any(skb
);
3971 /* zero out tiny buf usage */
3972 memset(cp
->tx_tiny_use
[ring
], 0, size
*sizeof(*cp
->tx_tiny_use
[ring
]));
3975 /* freed on close */
3976 static inline void cas_free_rx_desc(struct cas
*cp
, int ring
)
3978 cas_page_t
**page
= cp
->rx_pages
[ring
];
3981 size
= RX_DESC_RINGN_SIZE(ring
);
3982 for (i
= 0; i
< size
; i
++) {
3984 cas_page_free(cp
, page
[i
]);
3990 static void cas_free_rxds(struct cas
*cp
)
3994 for (i
= 0; i
< N_RX_DESC_RINGS
; i
++)
3995 cas_free_rx_desc(cp
, i
);
3998 /* Must be invoked under cp->lock. */
3999 static void cas_clean_rings(struct cas
*cp
)
4003 /* need to clean all tx rings */
4004 memset(cp
->tx_old
, 0, sizeof(*cp
->tx_old
)*N_TX_RINGS
);
4005 memset(cp
->tx_new
, 0, sizeof(*cp
->tx_new
)*N_TX_RINGS
);
4006 for (i
= 0; i
< N_TX_RINGS
; i
++)
4007 cas_clean_txd(cp
, i
);
4009 /* zero out init block */
4010 memset(cp
->init_block
, 0, sizeof(struct cas_init_block
));
4015 /* allocated on open */
4016 static inline int cas_alloc_rx_desc(struct cas
*cp
, int ring
)
4018 cas_page_t
**page
= cp
->rx_pages
[ring
];
4021 size
= RX_DESC_RINGN_SIZE(ring
);
4022 for (i
= 0; i
< size
; i
++) {
4023 if ((page
[i
] = cas_page_alloc(cp
, GFP_KERNEL
)) == NULL
)
4029 static int cas_alloc_rxds(struct cas
*cp
)
4033 for (i
= 0; i
< N_RX_DESC_RINGS
; i
++) {
4034 if (cas_alloc_rx_desc(cp
, i
) < 0) {
4042 static void cas_reset_task(void *data
)
4044 struct cas
*cp
= (struct cas
*) data
;
4046 int pending
= atomic_read(&cp
->reset_task_pending
);
4048 int pending_all
= atomic_read(&cp
->reset_task_pending_all
);
4049 int pending_spare
= atomic_read(&cp
->reset_task_pending_spare
);
4050 int pending_mtu
= atomic_read(&cp
->reset_task_pending_mtu
);
4052 if (pending_all
== 0 && pending_spare
== 0 && pending_mtu
== 0) {
4053 /* We can have more tasks scheduled than actually
4056 atomic_dec(&cp
->reset_task_pending
);
4060 /* The link went down, we reset the ring, but keep
4061 * DMA stopped. Use this function for reset
4064 if (cp
->hw_running
) {
4065 unsigned long flags
;
4067 /* Make sure we don't get interrupts or tx packets */
4068 netif_device_detach(cp
->dev
);
4069 cas_lock_all_save(cp
, flags
);
4072 /* We call cas_spare_recover when we call cas_open.
4073 * but we do not initialize the lists cas_spare_recover
4074 * uses until cas_open is called.
4076 cas_spare_recover(cp
, GFP_ATOMIC
);
4079 /* test => only pending_spare set */
4080 if (!pending_all
&& !pending_mtu
)
4083 if (pending
== CAS_RESET_SPARE
)
4086 /* when pending == CAS_RESET_ALL, the following
4087 * call to cas_init_hw will restart auto negotiation.
4088 * Setting the second argument of cas_reset to
4089 * !(pending == CAS_RESET_ALL) will set this argument
4090 * to 1 (avoiding reinitializing the PHY for the normal
4091 * PCS case) when auto negotiation is not restarted.
4094 cas_reset(cp
, !(pending_all
> 0));
4096 cas_clean_rings(cp
);
4097 cas_init_hw(cp
, (pending_all
> 0));
4099 cas_reset(cp
, !(pending
== CAS_RESET_ALL
));
4101 cas_clean_rings(cp
);
4102 cas_init_hw(cp
, pending
== CAS_RESET_ALL
);
4106 cas_unlock_all_restore(cp
, flags
);
4107 netif_device_attach(cp
->dev
);
4110 atomic_sub(pending_all
, &cp
->reset_task_pending_all
);
4111 atomic_sub(pending_spare
, &cp
->reset_task_pending_spare
);
4112 atomic_sub(pending_mtu
, &cp
->reset_task_pending_mtu
);
4113 atomic_dec(&cp
->reset_task_pending
);
4115 atomic_set(&cp
->reset_task_pending
, 0);
4119 static void cas_link_timer(unsigned long data
)
4121 struct cas
*cp
= (struct cas
*) data
;
4122 int mask
, pending
= 0, reset
= 0;
4123 unsigned long flags
;
4125 if (link_transition_timeout
!= 0 &&
4126 cp
->link_transition_jiffies_valid
&&
4127 ((jiffies
- cp
->link_transition_jiffies
) >
4128 (link_transition_timeout
))) {
4129 /* One-second counter so link-down workaround doesn't
4130 * cause resets to occur so fast as to fool the switch
4131 * into thinking the link is down.
4133 cp
->link_transition_jiffies_valid
= 0;
4136 if (!cp
->hw_running
)
4139 spin_lock_irqsave(&cp
->lock
, flags
);
4141 cas_entropy_gather(cp
);
4143 /* If the link task is still pending, we just
4144 * reschedule the link timer
4147 if (atomic_read(&cp
->reset_task_pending_all
) ||
4148 atomic_read(&cp
->reset_task_pending_spare
) ||
4149 atomic_read(&cp
->reset_task_pending_mtu
))
4152 if (atomic_read(&cp
->reset_task_pending
))
4156 /* check for rx cleaning */
4157 if ((mask
= (cp
->cas_flags
& CAS_FLAG_RXD_POST_MASK
))) {
4160 for (i
= 0; i
< MAX_RX_DESC_RINGS
; i
++) {
4161 rmask
= CAS_FLAG_RXD_POST(i
);
4162 if ((mask
& rmask
) == 0)
4165 /* post_rxds will do a mod_timer */
4166 if (cas_post_rxds_ringN(cp
, i
, cp
->rx_last
[i
]) < 0) {
4170 cp
->cas_flags
&= ~rmask
;
4174 if (CAS_PHY_MII(cp
->phy_type
)) {
4176 cas_mif_poll(cp
, 0);
4177 bmsr
= cas_phy_read(cp
, MII_BMSR
);
4178 /* WTZ: Solaris driver reads this twice, but that
4179 * may be due to the PCS case and the use of a
4180 * common implementation. Read it twice here to be
4183 bmsr
= cas_phy_read(cp
, MII_BMSR
);
4184 cas_mif_poll(cp
, 1);
4185 readl(cp
->regs
+ REG_MIF_STATUS
); /* avoid dups */
4186 reset
= cas_mii_link_check(cp
, bmsr
);
4188 reset
= cas_pcs_link_check(cp
);
4194 /* check for tx state machine confusion */
4195 if ((readl(cp
->regs
+ REG_MAC_TX_STATUS
) & MAC_TX_FRAME_XMIT
) == 0) {
4196 u32 val
= readl(cp
->regs
+ REG_MAC_STATE_MACHINE
);
4198 int tlm
= CAS_VAL(MAC_SM_TLM
, val
);
4200 if (((tlm
== 0x5) || (tlm
== 0x3)) &&
4201 (CAS_VAL(MAC_SM_ENCAP_SM
, val
) == 0)) {
4202 if (netif_msg_tx_err(cp
))
4203 printk(KERN_DEBUG
"%s: tx err: "
4204 "MAC_STATE[%08x]\n",
4205 cp
->dev
->name
, val
);
4210 val
= readl(cp
->regs
+ REG_TX_FIFO_PKT_CNT
);
4211 wptr
= readl(cp
->regs
+ REG_TX_FIFO_WRITE_PTR
);
4212 rptr
= readl(cp
->regs
+ REG_TX_FIFO_READ_PTR
);
4213 if ((val
== 0) && (wptr
!= rptr
)) {
4214 if (netif_msg_tx_err(cp
))
4215 printk(KERN_DEBUG
"%s: tx err: "
4216 "TX_FIFO[%08x:%08x:%08x]\n",
4217 cp
->dev
->name
, val
, wptr
, rptr
);
4228 atomic_inc(&cp
->reset_task_pending
);
4229 atomic_inc(&cp
->reset_task_pending_all
);
4230 schedule_work(&cp
->reset_task
);
4232 atomic_set(&cp
->reset_task_pending
, CAS_RESET_ALL
);
4233 printk(KERN_ERR
"reset called in cas_link_timer\n");
4234 schedule_work(&cp
->reset_task
);
4239 mod_timer(&cp
->link_timer
, jiffies
+ CAS_LINK_TIMEOUT
);
4241 spin_unlock_irqrestore(&cp
->lock
, flags
);
4244 /* tiny buffers are used to avoid target abort issues with
4247 static void cas_tx_tiny_free(struct cas
*cp
)
4249 struct pci_dev
*pdev
= cp
->pdev
;
4252 for (i
= 0; i
< N_TX_RINGS
; i
++) {
4253 if (!cp
->tx_tiny_bufs
[i
])
4256 pci_free_consistent(pdev
, TX_TINY_BUF_BLOCK
,
4257 cp
->tx_tiny_bufs
[i
],
4258 cp
->tx_tiny_dvma
[i
]);
4259 cp
->tx_tiny_bufs
[i
] = NULL
;
4263 static int cas_tx_tiny_alloc(struct cas
*cp
)
4265 struct pci_dev
*pdev
= cp
->pdev
;
4268 for (i
= 0; i
< N_TX_RINGS
; i
++) {
4269 cp
->tx_tiny_bufs
[i
] =
4270 pci_alloc_consistent(pdev
, TX_TINY_BUF_BLOCK
,
4271 &cp
->tx_tiny_dvma
[i
]);
4272 if (!cp
->tx_tiny_bufs
[i
]) {
4273 cas_tx_tiny_free(cp
);
4281 static int cas_open(struct net_device
*dev
)
4283 struct cas
*cp
= netdev_priv(dev
);
4285 unsigned long flags
;
4289 hw_was_up
= cp
->hw_running
;
4291 /* The power-management semaphore protects the hw_running
4292 * etc. state so it is safe to do this bit without cp->lock
4294 if (!cp
->hw_running
) {
4295 /* Reset the chip */
4296 cas_lock_all_save(cp
, flags
);
4297 /* We set the second arg to cas_reset to zero
4298 * because cas_init_hw below will have its second
4299 * argument set to non-zero, which will force
4300 * autonegotiation to start.
4304 cas_unlock_all_restore(cp
, flags
);
4307 if (cas_tx_tiny_alloc(cp
) < 0)
4310 /* alloc rx descriptors */
4312 if (cas_alloc_rxds(cp
) < 0)
4315 /* allocate spares */
4317 cas_spare_recover(cp
, GFP_KERNEL
);
4319 /* We can now request the interrupt as we know it's masked
4320 * on the controller. cassini+ has up to 4 interrupts
4321 * that can be used, but you need to do explicit pci interrupt
4322 * mapping to expose them
4324 if (request_irq(cp
->pdev
->irq
, cas_interrupt
,
4325 SA_SHIRQ
, dev
->name
, (void *) dev
)) {
4326 printk(KERN_ERR
"%s: failed to request irq !\n",
4333 cas_lock_all_save(cp
, flags
);
4334 cas_clean_rings(cp
);
4335 cas_init_hw(cp
, !hw_was_up
);
4337 cas_unlock_all_restore(cp
, flags
);
4339 netif_start_queue(dev
);
4347 cas_tx_tiny_free(cp
);
4352 static int cas_close(struct net_device
*dev
)
4354 unsigned long flags
;
4355 struct cas
*cp
= netdev_priv(dev
);
4357 /* Make sure we don't get distracted by suspend/resume */
4360 netif_stop_queue(dev
);
4362 /* Stop traffic, mark us closed */
4363 cas_lock_all_save(cp
, flags
);
4367 cas_begin_auto_negotiation(cp
, NULL
);
4368 cas_clean_rings(cp
);
4369 cas_unlock_all_restore(cp
, flags
);
4371 free_irq(cp
->pdev
->irq
, (void *) dev
);
4374 cas_tx_tiny_free(cp
);
4380 const char name
[ETH_GSTRING_LEN
];
4381 } ethtool_cassini_statnames
[] = {
4388 {"rx_frame_errors"},
4389 {"rx_length_errors"},
4392 {"tx_aborted_errors"},
4399 #define CAS_NUM_STAT_KEYS (sizeof(ethtool_cassini_statnames)/ETH_GSTRING_LEN)
4402 const int offsets
; /* neg. values for 2nd arg to cas_read_phy */
4403 } ethtool_register_table
[] = {
4418 {REG_PCS_MII_STATUS
},
4419 {REG_PCS_STATE_MACHINE
},
4420 {REG_MAC_COLL_EXCESS
},
4423 #define CAS_REG_LEN (sizeof(ethtool_register_table)/sizeof(int))
4424 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
4426 static u8
*cas_get_regs(struct cas
*cp
)
4428 u8
*ptr
= kmalloc(CAS_MAX_REGS
, GFP_KERNEL
);
4431 unsigned long flags
;
4436 spin_lock_irqsave(&cp
->lock
, flags
);
4437 for (i
= 0, p
= ptr
; i
< CAS_REG_LEN
; i
++, p
+= sizeof(u32
)) {
4440 if (ethtool_register_table
[i
].offsets
< 0) {
4441 hval
= cas_phy_read(cp
,
4442 -ethtool_register_table
[i
].offsets
);
4445 val
= readl(cp
->regs
+ethtool_register_table
[i
].offsets
);
4447 memcpy(p
, (u8
*)&val
, sizeof(u32
));
4449 spin_unlock_irqrestore(&cp
->lock
, flags
);
4454 static struct net_device_stats
*cas_get_stats(struct net_device
*dev
)
4456 struct cas
*cp
= netdev_priv(dev
);
4457 struct net_device_stats
*stats
= cp
->net_stats
;
4458 unsigned long flags
;
4462 /* we collate all of the stats into net_stats[N_TX_RING] */
4463 if (!cp
->hw_running
)
4464 return stats
+ N_TX_RINGS
;
4466 /* collect outstanding stats */
4467 /* WTZ: the Cassini spec gives these as 16 bit counters but
4468 * stored in 32-bit words. Added a mask of 0xffff to be safe,
4469 * in case the chip somehow puts any garbage in the other bits.
4470 * Also, counter usage didn't seem to mach what Adrian did
4471 * in the parts of the code that set these quantities. Made
4474 spin_lock_irqsave(&cp
->stat_lock
[N_TX_RINGS
], flags
);
4475 stats
[N_TX_RINGS
].rx_crc_errors
+=
4476 readl(cp
->regs
+ REG_MAC_FCS_ERR
) & 0xffff;
4477 stats
[N_TX_RINGS
].rx_frame_errors
+=
4478 readl(cp
->regs
+ REG_MAC_ALIGN_ERR
) &0xffff;
4479 stats
[N_TX_RINGS
].rx_length_errors
+=
4480 readl(cp
->regs
+ REG_MAC_LEN_ERR
) & 0xffff;
4482 tmp
= (readl(cp
->regs
+ REG_MAC_COLL_EXCESS
) & 0xffff) +
4483 (readl(cp
->regs
+ REG_MAC_COLL_LATE
) & 0xffff);
4484 stats
[N_TX_RINGS
].tx_aborted_errors
+= tmp
;
4485 stats
[N_TX_RINGS
].collisions
+=
4486 tmp
+ (readl(cp
->regs
+ REG_MAC_COLL_NORMAL
) & 0xffff);
4488 stats
[N_TX_RINGS
].tx_aborted_errors
+=
4489 readl(cp
->regs
+ REG_MAC_COLL_EXCESS
);
4490 stats
[N_TX_RINGS
].collisions
+= readl(cp
->regs
+ REG_MAC_COLL_EXCESS
) +
4491 readl(cp
->regs
+ REG_MAC_COLL_LATE
);
4493 cas_clear_mac_err(cp
);
4495 /* saved bits that are unique to ring 0 */
4496 spin_lock(&cp
->stat_lock
[0]);
4497 stats
[N_TX_RINGS
].collisions
+= stats
[0].collisions
;
4498 stats
[N_TX_RINGS
].rx_over_errors
+= stats
[0].rx_over_errors
;
4499 stats
[N_TX_RINGS
].rx_frame_errors
+= stats
[0].rx_frame_errors
;
4500 stats
[N_TX_RINGS
].rx_fifo_errors
+= stats
[0].rx_fifo_errors
;
4501 stats
[N_TX_RINGS
].tx_aborted_errors
+= stats
[0].tx_aborted_errors
;
4502 stats
[N_TX_RINGS
].tx_fifo_errors
+= stats
[0].tx_fifo_errors
;
4503 spin_unlock(&cp
->stat_lock
[0]);
4505 for (i
= 0; i
< N_TX_RINGS
; i
++) {
4506 spin_lock(&cp
->stat_lock
[i
]);
4507 stats
[N_TX_RINGS
].rx_length_errors
+=
4508 stats
[i
].rx_length_errors
;
4509 stats
[N_TX_RINGS
].rx_crc_errors
+= stats
[i
].rx_crc_errors
;
4510 stats
[N_TX_RINGS
].rx_packets
+= stats
[i
].rx_packets
;
4511 stats
[N_TX_RINGS
].tx_packets
+= stats
[i
].tx_packets
;
4512 stats
[N_TX_RINGS
].rx_bytes
+= stats
[i
].rx_bytes
;
4513 stats
[N_TX_RINGS
].tx_bytes
+= stats
[i
].tx_bytes
;
4514 stats
[N_TX_RINGS
].rx_errors
+= stats
[i
].rx_errors
;
4515 stats
[N_TX_RINGS
].tx_errors
+= stats
[i
].tx_errors
;
4516 stats
[N_TX_RINGS
].rx_dropped
+= stats
[i
].rx_dropped
;
4517 stats
[N_TX_RINGS
].tx_dropped
+= stats
[i
].tx_dropped
;
4518 memset(stats
+ i
, 0, sizeof(struct net_device_stats
));
4519 spin_unlock(&cp
->stat_lock
[i
]);
4521 spin_unlock_irqrestore(&cp
->stat_lock
[N_TX_RINGS
], flags
);
4522 return stats
+ N_TX_RINGS
;
4526 static void cas_set_multicast(struct net_device
*dev
)
4528 struct cas
*cp
= netdev_priv(dev
);
4529 u32 rxcfg
, rxcfg_new
;
4530 unsigned long flags
;
4531 int limit
= STOP_TRIES
;
4533 if (!cp
->hw_running
)
4536 spin_lock_irqsave(&cp
->lock
, flags
);
4537 rxcfg
= readl(cp
->regs
+ REG_MAC_RX_CFG
);
4539 /* disable RX MAC and wait for completion */
4540 writel(rxcfg
& ~MAC_RX_CFG_EN
, cp
->regs
+ REG_MAC_RX_CFG
);
4541 while (readl(cp
->regs
+ REG_MAC_RX_CFG
) & MAC_RX_CFG_EN
) {
4547 /* disable hash filter and wait for completion */
4549 rxcfg
&= ~(MAC_RX_CFG_PROMISC_EN
| MAC_RX_CFG_HASH_FILTER_EN
);
4550 writel(rxcfg
& ~MAC_RX_CFG_EN
, cp
->regs
+ REG_MAC_RX_CFG
);
4551 while (readl(cp
->regs
+ REG_MAC_RX_CFG
) & MAC_RX_CFG_HASH_FILTER_EN
) {
4557 /* program hash filters */
4558 cp
->mac_rx_cfg
= rxcfg_new
= cas_setup_multicast(cp
);
4560 writel(rxcfg
, cp
->regs
+ REG_MAC_RX_CFG
);
4561 spin_unlock_irqrestore(&cp
->lock
, flags
);
4564 /* Eventually add support for changing the advertisement
4567 static int cas_ethtool_ioctl(struct net_device
*dev
, void __user
*ep_user
)
4569 struct cas
*cp
= netdev_priv(dev
);
4571 int full_duplex
, speed
, pause
;
4572 struct ethtool_cmd ecmd
;
4573 unsigned long flags
;
4574 enum link_state linkstate
= link_up
;
4576 if (copy_from_user(&ecmd
, ep_user
, sizeof(ecmd
)))
4580 case ETHTOOL_GDRVINFO
: {
4581 struct ethtool_drvinfo info
= { .cmd
= ETHTOOL_GDRVINFO
};
4583 strncpy(info
.driver
, DRV_MODULE_NAME
,
4584 ETHTOOL_BUSINFO_LEN
);
4585 strncpy(info
.version
, DRV_MODULE_VERSION
,
4586 ETHTOOL_BUSINFO_LEN
);
4587 info
.fw_version
[0] = '\0';
4588 strncpy(info
.bus_info
, pci_name(cp
->pdev
),
4589 ETHTOOL_BUSINFO_LEN
);
4590 info
.regdump_len
= cp
->casreg_len
< CAS_MAX_REGS
?
4591 cp
->casreg_len
: CAS_MAX_REGS
;
4592 info
.n_stats
= CAS_NUM_STAT_KEYS
;
4593 if (copy_to_user(ep_user
, &info
, sizeof(info
)))
4600 ecmd
.advertising
= 0;
4601 ecmd
.supported
= SUPPORTED_Autoneg
;
4602 if (cp
->cas_flags
& CAS_FLAG_1000MB_CAP
) {
4603 ecmd
.supported
|= SUPPORTED_1000baseT_Full
;
4604 ecmd
.advertising
|= ADVERTISED_1000baseT_Full
;
4607 /* Record PHY settings if HW is on. */
4608 spin_lock_irqsave(&cp
->lock
, flags
);
4610 linkstate
= cp
->lstate
;
4611 if (CAS_PHY_MII(cp
->phy_type
)) {
4612 ecmd
.port
= PORT_MII
;
4613 ecmd
.transceiver
= (cp
->cas_flags
& CAS_FLAG_SATURN
) ?
4614 XCVR_INTERNAL
: XCVR_EXTERNAL
;
4615 ecmd
.phy_address
= cp
->phy_addr
;
4616 ecmd
.advertising
|= ADVERTISED_TP
| ADVERTISED_MII
|
4617 ADVERTISED_10baseT_Half
|
4618 ADVERTISED_10baseT_Full
|
4619 ADVERTISED_100baseT_Half
|
4620 ADVERTISED_100baseT_Full
;
4623 (SUPPORTED_10baseT_Half
|
4624 SUPPORTED_10baseT_Full
|
4625 SUPPORTED_100baseT_Half
|
4626 SUPPORTED_100baseT_Full
|
4627 SUPPORTED_TP
| SUPPORTED_MII
);
4629 if (cp
->hw_running
) {
4630 cas_mif_poll(cp
, 0);
4631 bmcr
= cas_phy_read(cp
, MII_BMCR
);
4632 cas_read_mii_link_mode(cp
, &full_duplex
,
4634 cas_mif_poll(cp
, 1);
4638 ecmd
.port
= PORT_FIBRE
;
4639 ecmd
.transceiver
= XCVR_INTERNAL
;
4640 ecmd
.phy_address
= 0;
4641 ecmd
.supported
|= SUPPORTED_FIBRE
;
4642 ecmd
.advertising
|= ADVERTISED_FIBRE
;
4644 if (cp
->hw_running
) {
4645 /* pcs uses the same bits as mii */
4646 bmcr
= readl(cp
->regs
+ REG_PCS_MII_CTRL
);
4647 cas_read_pcs_link_mode(cp
, &full_duplex
,
4651 spin_unlock_irqrestore(&cp
->lock
, flags
);
4653 if (bmcr
& BMCR_ANENABLE
) {
4654 ecmd
.advertising
|= ADVERTISED_Autoneg
;
4655 ecmd
.autoneg
= AUTONEG_ENABLE
;
4656 ecmd
.speed
= ((speed
== 10) ?
4659 SPEED_1000
: SPEED_100
));
4660 ecmd
.duplex
= full_duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
4662 ecmd
.autoneg
= AUTONEG_DISABLE
;
4664 (bmcr
& CAS_BMCR_SPEED1000
) ?
4666 ((bmcr
& BMCR_SPEED100
) ? SPEED_100
:
4669 (bmcr
& BMCR_FULLDPLX
) ?
4670 DUPLEX_FULL
: DUPLEX_HALF
;
4672 if (linkstate
!= link_up
) {
4673 /* Force these to "unknown" if the link is not up and
4674 * autonogotiation in enabled. We can set the link
4675 * speed to 0, but not ecmd.duplex,
4676 * because its legal values are 0 and 1. Ethtool will
4677 * print the value reported in parentheses after the
4678 * word "Unknown" for unrecognized values.
4680 * If in forced mode, we report the speed and duplex
4681 * settings that we configured.
4683 if (cp
->link_cntl
& BMCR_ANENABLE
) {
4687 ecmd
.speed
= SPEED_10
;
4688 if (cp
->link_cntl
& BMCR_SPEED100
) {
4689 ecmd
.speed
= SPEED_100
;
4690 } else if (cp
->link_cntl
& CAS_BMCR_SPEED1000
) {
4691 ecmd
.speed
= SPEED_1000
;
4693 ecmd
.duplex
= (cp
->link_cntl
& BMCR_FULLDPLX
)?
4694 DUPLEX_FULL
: DUPLEX_HALF
;
4697 if (copy_to_user(ep_user
, &ecmd
, sizeof(ecmd
)))
4702 if (!capable(CAP_NET_ADMIN
))
4705 /* Verify the settings we care about. */
4706 if (ecmd
.autoneg
!= AUTONEG_ENABLE
&&
4707 ecmd
.autoneg
!= AUTONEG_DISABLE
)
4710 if (ecmd
.autoneg
== AUTONEG_DISABLE
&&
4711 ((ecmd
.speed
!= SPEED_1000
&&
4712 ecmd
.speed
!= SPEED_100
&&
4713 ecmd
.speed
!= SPEED_10
) ||
4714 (ecmd
.duplex
!= DUPLEX_HALF
&&
4715 ecmd
.duplex
!= DUPLEX_FULL
)))
4718 /* Apply settings and restart link process. */
4719 spin_lock_irqsave(&cp
->lock
, flags
);
4720 cas_begin_auto_negotiation(cp
, &ecmd
);
4721 spin_unlock_irqrestore(&cp
->lock
, flags
);
4724 case ETHTOOL_NWAY_RST
:
4725 if ((cp
->link_cntl
& BMCR_ANENABLE
) == 0)
4728 /* Restart link process. */
4729 spin_lock_irqsave(&cp
->lock
, flags
);
4730 cas_begin_auto_negotiation(cp
, NULL
);
4731 spin_unlock_irqrestore(&cp
->lock
, flags
);
4737 break; /* doesn't exist */
4739 /* get link status */
4740 case ETHTOOL_GLINK
: {
4741 struct ethtool_value edata
= { .cmd
= ETHTOOL_GLINK
};
4743 edata
.data
= (cp
->lstate
== link_up
);
4744 if (copy_to_user(ep_user
, &edata
, sizeof(edata
)))
4749 /* get message-level */
4750 case ETHTOOL_GMSGLVL
: {
4751 struct ethtool_value edata
= { .cmd
= ETHTOOL_GMSGLVL
};
4753 edata
.data
= cp
->msg_enable
;
4754 if (copy_to_user(ep_user
, &edata
, sizeof(edata
)))
4759 /* set message-level */
4760 case ETHTOOL_SMSGLVL
: {
4761 struct ethtool_value edata
;
4763 if (!capable(CAP_NET_ADMIN
)) {
4766 if (copy_from_user(&edata
, ep_user
, sizeof(edata
)))
4768 cp
->msg_enable
= edata
.data
;
4772 case ETHTOOL_GREGS
: {
4773 struct ethtool_regs edata
;
4775 int len
= cp
->casreg_len
< CAS_MAX_REGS
?
4776 cp
->casreg_len
: CAS_MAX_REGS
;
4778 if (copy_from_user(&edata
, ep_user
, sizeof (edata
)))
4781 if (edata
.len
> len
)
4784 if (copy_to_user (ep_user
, &edata
, sizeof(edata
)))
4787 /* cas_get_regs handles locks (cp->lock). */
4788 ptr
= cas_get_regs(cp
);
4791 if (copy_to_user(ep_user
+ sizeof (edata
), ptr
, edata
.len
))
4797 case ETHTOOL_GSTRINGS
: {
4798 struct ethtool_gstrings edata
;
4801 if (copy_from_user(&edata
, ep_user
, sizeof(edata
)))
4805 switch(edata
.string_set
) {
4807 edata
.len
= (len
< CAS_NUM_STAT_KEYS
) ?
4808 len
: CAS_NUM_STAT_KEYS
;
4809 if (copy_to_user(ep_user
, &edata
, sizeof(edata
)))
4812 if (copy_to_user(ep_user
+ sizeof(edata
),
4813 ðtool_cassini_statnames
,
4814 (edata
.len
* ETH_GSTRING_LEN
)))
4821 case ETHTOOL_GSTATS
: {
4824 struct ethtool_stats edata
;
4825 struct net_device_stats
*stats
;
4828 if (copy_from_user(&edata
, ep_user
, sizeof(edata
)))
4831 len
= edata
.n_stats
;
4832 stats
= cas_get_stats(cp
->dev
);
4833 edata
.cmd
= ETHTOOL_GSTATS
;
4834 edata
.n_stats
= (len
< CAS_NUM_STAT_KEYS
) ?
4835 len
: CAS_NUM_STAT_KEYS
;
4836 if (copy_to_user(ep_user
, &edata
, sizeof (edata
)))
4839 tmp
= kmalloc(sizeof(u64
)*CAS_NUM_STAT_KEYS
, GFP_KERNEL
);
4841 tmp
[i
++] = stats
->collisions
;
4842 tmp
[i
++] = stats
->rx_bytes
;
4843 tmp
[i
++] = stats
->rx_crc_errors
;
4844 tmp
[i
++] = stats
->rx_dropped
;
4845 tmp
[i
++] = stats
->rx_errors
;
4846 tmp
[i
++] = stats
->rx_fifo_errors
;
4847 tmp
[i
++] = stats
->rx_frame_errors
;
4848 tmp
[i
++] = stats
->rx_length_errors
;
4849 tmp
[i
++] = stats
->rx_over_errors
;
4850 tmp
[i
++] = stats
->rx_packets
;
4851 tmp
[i
++] = stats
->tx_aborted_errors
;
4852 tmp
[i
++] = stats
->tx_bytes
;
4853 tmp
[i
++] = stats
->tx_dropped
;
4854 tmp
[i
++] = stats
->tx_errors
;
4855 tmp
[i
++] = stats
->tx_fifo_errors
;
4856 tmp
[i
++] = stats
->tx_packets
;
4857 BUG_ON(i
!= CAS_NUM_STAT_KEYS
);
4859 i
= copy_to_user(ep_user
+ sizeof(edata
),
4860 tmp
, sizeof(u64
)*edata
.n_stats
);
4874 static int cas_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4876 struct cas
*cp
= netdev_priv(dev
);
4877 struct mii_ioctl_data
*data
= if_mii(ifr
);
4878 unsigned long flags
;
4879 int rc
= -EOPNOTSUPP
;
4881 /* Hold the PM semaphore while doing ioctl's or we may collide
4882 * with open/close and power management and oops.
4887 rc
= cas_ethtool_ioctl(dev
, ifr
->ifr_data
);
4890 case SIOCGMIIPHY
: /* Get address of MII PHY in use. */
4891 data
->phy_id
= cp
->phy_addr
;
4892 /* Fallthrough... */
4894 case SIOCGMIIREG
: /* Read MII PHY register. */
4895 spin_lock_irqsave(&cp
->lock
, flags
);
4896 cas_mif_poll(cp
, 0);
4897 data
->val_out
= cas_phy_read(cp
, data
->reg_num
& 0x1f);
4898 cas_mif_poll(cp
, 1);
4899 spin_unlock_irqrestore(&cp
->lock
, flags
);
4903 case SIOCSMIIREG
: /* Write MII PHY register. */
4904 if (!capable(CAP_NET_ADMIN
)) {
4908 spin_lock_irqsave(&cp
->lock
, flags
);
4909 cas_mif_poll(cp
, 0);
4910 rc
= cas_phy_write(cp
, data
->reg_num
& 0x1f, data
->val_in
);
4911 cas_mif_poll(cp
, 1);
4912 spin_unlock_irqrestore(&cp
->lock
, flags
);
4922 static int __devinit
cas_init_one(struct pci_dev
*pdev
,
4923 const struct pci_device_id
*ent
)
4925 static int cas_version_printed
= 0;
4926 unsigned long casreg_base
, casreg_len
;
4927 struct net_device
*dev
;
4929 int i
, err
, pci_using_dac
;
4931 u8 orig_cacheline_size
= 0, cas_cacheline_size
= 0;
4933 if (cas_version_printed
++ == 0)
4934 printk(KERN_INFO
"%s", version
);
4936 err
= pci_enable_device(pdev
);
4938 printk(KERN_ERR PFX
"Cannot enable PCI device, "
4943 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
4944 printk(KERN_ERR PFX
"Cannot find proper PCI device "
4945 "base address, aborting.\n");
4947 goto err_out_disable_pdev
;
4950 dev
= alloc_etherdev(sizeof(*cp
));
4952 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
4954 goto err_out_disable_pdev
;
4956 SET_MODULE_OWNER(dev
);
4957 SET_NETDEV_DEV(dev
, &pdev
->dev
);
4959 err
= pci_request_regions(pdev
, dev
->name
);
4961 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
4963 goto err_out_free_netdev
;
4965 pci_set_master(pdev
);
4967 /* we must always turn on parity response or else parity
4968 * doesn't get generated properly. disable SERR/PERR as well.
4969 * in addition, we want to turn MWI on.
4971 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4972 pci_cmd
&= ~PCI_COMMAND_SERR
;
4973 pci_cmd
|= PCI_COMMAND_PARITY
;
4974 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4977 * On some architectures, the default cache line size set
4978 * by pci_set_mwi reduces perforamnce. We have to increase
4979 * it for this case. To start, we'll print some configuration
4983 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
,
4984 &orig_cacheline_size
);
4985 if (orig_cacheline_size
< CAS_PREF_CACHELINE_SIZE
) {
4986 cas_cacheline_size
=
4987 (CAS_PREF_CACHELINE_SIZE
< SMP_CACHE_BYTES
) ?
4988 CAS_PREF_CACHELINE_SIZE
: SMP_CACHE_BYTES
;
4989 if (pci_write_config_byte(pdev
,
4990 PCI_CACHE_LINE_SIZE
,
4991 cas_cacheline_size
)) {
4992 printk(KERN_ERR PFX
"Could not set PCI cache "
4994 goto err_write_cacheline
;
5000 /* Configure DMA attributes. */
5001 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
5003 err
= pci_set_consistent_dma_mask(pdev
,
5006 printk(KERN_ERR PFX
"Unable to obtain 64-bit DMA "
5007 "for consistent allocations\n");
5008 goto err_out_free_res
;
5012 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
5014 printk(KERN_ERR PFX
"No usable DMA configuration, "
5016 goto err_out_free_res
;
5021 casreg_base
= pci_resource_start(pdev
, 0);
5022 casreg_len
= pci_resource_len(pdev
, 0);
5024 cp
= netdev_priv(dev
);
5027 /* A value of 0 indicates we never explicitly set it */
5028 cp
->orig_cacheline_size
= cas_cacheline_size
? orig_cacheline_size
: 0;
5031 cp
->msg_enable
= (cassini_debug
< 0) ? CAS_DEF_MSG_ENABLE
:
5034 cp
->link_transition
= LINK_TRANSITION_UNKNOWN
;
5035 cp
->link_transition_jiffies_valid
= 0;
5037 spin_lock_init(&cp
->lock
);
5038 spin_lock_init(&cp
->rx_inuse_lock
);
5039 spin_lock_init(&cp
->rx_spare_lock
);
5040 for (i
= 0; i
< N_TX_RINGS
; i
++) {
5041 spin_lock_init(&cp
->stat_lock
[i
]);
5042 spin_lock_init(&cp
->tx_lock
[i
]);
5044 spin_lock_init(&cp
->stat_lock
[N_TX_RINGS
]);
5045 init_MUTEX(&cp
->pm_sem
);
5047 init_timer(&cp
->link_timer
);
5048 cp
->link_timer
.function
= cas_link_timer
;
5049 cp
->link_timer
.data
= (unsigned long) cp
;
5052 /* Just in case the implementation of atomic operations
5053 * change so that an explicit initialization is necessary.
5055 atomic_set(&cp
->reset_task_pending
, 0);
5056 atomic_set(&cp
->reset_task_pending_all
, 0);
5057 atomic_set(&cp
->reset_task_pending_spare
, 0);
5058 atomic_set(&cp
->reset_task_pending_mtu
, 0);
5060 INIT_WORK(&cp
->reset_task
, cas_reset_task
, cp
);
5062 /* Default link parameters */
5063 if (link_mode
>= 0 && link_mode
<= 6)
5064 cp
->link_cntl
= link_modes
[link_mode
];
5066 cp
->link_cntl
= BMCR_ANENABLE
;
5067 cp
->lstate
= link_down
;
5068 cp
->link_transition
= LINK_TRANSITION_LINK_DOWN
;
5069 netif_carrier_off(cp
->dev
);
5070 cp
->timer_ticks
= 0;
5072 /* give us access to cassini registers */
5073 cp
->regs
= ioremap(casreg_base
, casreg_len
);
5074 if (cp
->regs
== 0UL) {
5075 printk(KERN_ERR PFX
"Cannot map device registers, "
5077 goto err_out_free_res
;
5079 cp
->casreg_len
= casreg_len
;
5081 pci_save_state(pdev
);
5082 cas_check_pci_invariants(cp
);
5085 if (cas_check_invariants(cp
))
5086 goto err_out_iounmap
;
5088 cp
->init_block
= (struct cas_init_block
*)
5089 pci_alloc_consistent(pdev
, sizeof(struct cas_init_block
),
5091 if (!cp
->init_block
) {
5092 printk(KERN_ERR PFX
"Cannot allocate init block, "
5094 goto err_out_iounmap
;
5097 for (i
= 0; i
< N_TX_RINGS
; i
++)
5098 cp
->init_txds
[i
] = cp
->init_block
->txds
[i
];
5100 for (i
= 0; i
< N_RX_DESC_RINGS
; i
++)
5101 cp
->init_rxds
[i
] = cp
->init_block
->rxds
[i
];
5103 for (i
= 0; i
< N_RX_COMP_RINGS
; i
++)
5104 cp
->init_rxcs
[i
] = cp
->init_block
->rxcs
[i
];
5106 for (i
= 0; i
< N_RX_FLOWS
; i
++)
5107 skb_queue_head_init(&cp
->rx_flows
[i
]);
5109 dev
->open
= cas_open
;
5110 dev
->stop
= cas_close
;
5111 dev
->hard_start_xmit
= cas_start_xmit
;
5112 dev
->get_stats
= cas_get_stats
;
5113 dev
->set_multicast_list
= cas_set_multicast
;
5114 dev
->do_ioctl
= cas_ioctl
;
5115 dev
->tx_timeout
= cas_tx_timeout
;
5116 dev
->watchdog_timeo
= CAS_TX_TIMEOUT
;
5117 dev
->change_mtu
= cas_change_mtu
;
5119 dev
->poll
= cas_poll
;
5122 #ifdef CONFIG_NET_POLL_CONTROLLER
5123 dev
->poll_controller
= cas_netpoll
;
5125 dev
->irq
= pdev
->irq
;
5128 /* Cassini features. */
5129 if ((cp
->cas_flags
& CAS_FLAG_NO_HW_CSUM
) == 0)
5130 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
5133 dev
->features
|= NETIF_F_HIGHDMA
;
5135 if (register_netdev(dev
)) {
5136 printk(KERN_ERR PFX
"Cannot register net device, "
5138 goto err_out_free_consistent
;
5141 i
= readl(cp
->regs
+ REG_BIM_CFG
);
5142 printk(KERN_INFO
"%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
5143 "Ethernet[%d] ", dev
->name
,
5144 (cp
->cas_flags
& CAS_FLAG_REG_PLUS
) ? "+" : "",
5145 (i
& BIM_CFG_32BIT
) ? "32" : "64",
5146 (i
& BIM_CFG_66MHZ
) ? "66" : "33",
5147 (cp
->phy_type
== CAS_PHY_SERDES
) ? "Fi" : "Cu", pdev
->irq
);
5149 for (i
= 0; i
< 6; i
++)
5150 printk("%2.2x%c", dev
->dev_addr
[i
],
5151 i
== 5 ? ' ' : ':');
5154 pci_set_drvdata(pdev
, dev
);
5156 cas_entropy_reset(cp
);
5158 cas_begin_auto_negotiation(cp
, NULL
);
5161 err_out_free_consistent
:
5162 pci_free_consistent(pdev
, sizeof(struct cas_init_block
),
5163 cp
->init_block
, cp
->block_dvma
);
5175 pci_release_regions(pdev
);
5177 err_write_cacheline
:
5178 /* Try to restore it in case the error occured after we
5181 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, orig_cacheline_size
);
5183 err_out_free_netdev
:
5186 err_out_disable_pdev
:
5187 pci_disable_device(pdev
);
5188 pci_set_drvdata(pdev
, NULL
);
5192 static void __devexit
cas_remove_one(struct pci_dev
*pdev
)
5194 struct net_device
*dev
= pci_get_drvdata(pdev
);
5199 cp
= netdev_priv(dev
);
5200 unregister_netdev(dev
);
5203 flush_scheduled_work();
5209 if (cp
->orig_cacheline_size
) {
5210 /* Restore the cache line size if we had modified
5213 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
,
5214 cp
->orig_cacheline_size
);
5217 pci_free_consistent(pdev
, sizeof(struct cas_init_block
),
5218 cp
->init_block
, cp
->block_dvma
);
5221 pci_release_regions(pdev
);
5222 pci_disable_device(pdev
);
5223 pci_set_drvdata(pdev
, NULL
);
5227 static int cas_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5229 struct net_device
*dev
= pci_get_drvdata(pdev
);
5230 struct cas
*cp
= netdev_priv(dev
);
5231 unsigned long flags
;
5233 /* We hold the PM semaphore during entire driver
5238 /* If the driver is opened, we stop the DMA */
5240 netif_device_detach(dev
);
5242 cas_lock_all_save(cp
, flags
);
5244 /* We can set the second arg of cas_reset to 0
5245 * because on resume, we'll call cas_init_hw with
5246 * its second arg set so that autonegotiation is
5250 cas_clean_rings(cp
);
5251 cas_unlock_all_restore(cp
, flags
);
5260 static int cas_resume(struct pci_dev
*pdev
)
5262 struct net_device
*dev
= pci_get_drvdata(pdev
);
5263 struct cas
*cp
= netdev_priv(dev
);
5265 printk(KERN_INFO
"%s: resuming\n", dev
->name
);
5269 unsigned long flags
;
5270 cas_lock_all_save(cp
, flags
);
5273 cas_clean_rings(cp
);
5275 cas_unlock_all_restore(cp
, flags
);
5277 netif_device_attach(dev
);
5282 #endif /* CONFIG_PM */
5284 static struct pci_driver cas_driver
= {
5285 .name
= DRV_MODULE_NAME
,
5286 .id_table
= cas_pci_tbl
,
5287 .probe
= cas_init_one
,
5288 .remove
= __devexit_p(cas_remove_one
),
5290 .suspend
= cas_suspend
,
5291 .resume
= cas_resume
5295 static int __init
cas_init(void)
5297 if (linkdown_timeout
> 0)
5298 link_transition_timeout
= linkdown_timeout
* HZ
;
5300 link_transition_timeout
= 0;
5302 return pci_module_init(&cas_driver
);
5305 static void __exit
cas_cleanup(void)
5307 pci_unregister_driver(&cas_driver
);
5310 module_init(cas_init
);
5311 module_exit(cas_cleanup
);