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cnic: Call cm_connect_complete() immediately on error
[deliverable/linux.git] / drivers / net / cnic.c
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define BCM_VLAN 1
32 #endif
33 #include <net/ip.h>
34 #include <net/tcp.h>
35 #include <net/route.h>
36 #include <net/ipv6.h>
37 #include <net/ip6_route.h>
38 #include <net/ip6_checksum.h>
39 #include <scsi/iscsi_if.h>
40
41 #include "cnic_if.h"
42 #include "bnx2.h"
43 #include "bnx2x/bnx2x_reg.h"
44 #include "bnx2x/bnx2x_fw_defs.h"
45 #include "bnx2x/bnx2x_hsi.h"
46 #include "../scsi/bnx2i/57xx_iscsi_constants.h"
47 #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
48 #include "cnic.h"
49 #include "cnic_defs.h"
50
51 #define DRV_MODULE_NAME "cnic"
52
53 static char version[] __devinitdata =
54 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
55
56 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
57 "Chen (zongxi@broadcom.com");
58 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
59 MODULE_LICENSE("GPL");
60 MODULE_VERSION(CNIC_MODULE_VERSION);
61
62 /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
63 static LIST_HEAD(cnic_dev_list);
64 static LIST_HEAD(cnic_udev_list);
65 static DEFINE_RWLOCK(cnic_dev_lock);
66 static DEFINE_MUTEX(cnic_lock);
67
68 static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
69
70 static int cnic_service_bnx2(void *, void *);
71 static int cnic_service_bnx2x(void *, void *);
72 static int cnic_ctl(void *, struct cnic_ctl_info *);
73
74 static struct cnic_ops cnic_bnx2_ops = {
75 .cnic_owner = THIS_MODULE,
76 .cnic_handler = cnic_service_bnx2,
77 .cnic_ctl = cnic_ctl,
78 };
79
80 static struct cnic_ops cnic_bnx2x_ops = {
81 .cnic_owner = THIS_MODULE,
82 .cnic_handler = cnic_service_bnx2x,
83 .cnic_ctl = cnic_ctl,
84 };
85
86 static struct workqueue_struct *cnic_wq;
87
88 static void cnic_shutdown_rings(struct cnic_dev *);
89 static void cnic_init_rings(struct cnic_dev *);
90 static int cnic_cm_set_pg(struct cnic_sock *);
91
92 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
93 {
94 struct cnic_uio_dev *udev = uinfo->priv;
95 struct cnic_dev *dev;
96
97 if (!capable(CAP_NET_ADMIN))
98 return -EPERM;
99
100 if (udev->uio_dev != -1)
101 return -EBUSY;
102
103 rtnl_lock();
104 dev = udev->dev;
105
106 if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
107 rtnl_unlock();
108 return -ENODEV;
109 }
110
111 udev->uio_dev = iminor(inode);
112
113 cnic_shutdown_rings(dev);
114 cnic_init_rings(dev);
115 rtnl_unlock();
116
117 return 0;
118 }
119
120 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
121 {
122 struct cnic_uio_dev *udev = uinfo->priv;
123
124 udev->uio_dev = -1;
125 return 0;
126 }
127
128 static inline void cnic_hold(struct cnic_dev *dev)
129 {
130 atomic_inc(&dev->ref_count);
131 }
132
133 static inline void cnic_put(struct cnic_dev *dev)
134 {
135 atomic_dec(&dev->ref_count);
136 }
137
138 static inline void csk_hold(struct cnic_sock *csk)
139 {
140 atomic_inc(&csk->ref_count);
141 }
142
143 static inline void csk_put(struct cnic_sock *csk)
144 {
145 atomic_dec(&csk->ref_count);
146 }
147
148 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
149 {
150 struct cnic_dev *cdev;
151
152 read_lock(&cnic_dev_lock);
153 list_for_each_entry(cdev, &cnic_dev_list, list) {
154 if (netdev == cdev->netdev) {
155 cnic_hold(cdev);
156 read_unlock(&cnic_dev_lock);
157 return cdev;
158 }
159 }
160 read_unlock(&cnic_dev_lock);
161 return NULL;
162 }
163
164 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
165 {
166 atomic_inc(&ulp_ops->ref_count);
167 }
168
169 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
170 {
171 atomic_dec(&ulp_ops->ref_count);
172 }
173
174 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
175 {
176 struct cnic_local *cp = dev->cnic_priv;
177 struct cnic_eth_dev *ethdev = cp->ethdev;
178 struct drv_ctl_info info;
179 struct drv_ctl_io *io = &info.data.io;
180
181 info.cmd = DRV_CTL_CTX_WR_CMD;
182 io->cid_addr = cid_addr;
183 io->offset = off;
184 io->data = val;
185 ethdev->drv_ctl(dev->netdev, &info);
186 }
187
188 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
189 {
190 struct cnic_local *cp = dev->cnic_priv;
191 struct cnic_eth_dev *ethdev = cp->ethdev;
192 struct drv_ctl_info info;
193 struct drv_ctl_io *io = &info.data.io;
194
195 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
196 io->offset = off;
197 io->dma_addr = addr;
198 ethdev->drv_ctl(dev->netdev, &info);
199 }
200
201 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
202 {
203 struct cnic_local *cp = dev->cnic_priv;
204 struct cnic_eth_dev *ethdev = cp->ethdev;
205 struct drv_ctl_info info;
206 struct drv_ctl_l2_ring *ring = &info.data.ring;
207
208 if (start)
209 info.cmd = DRV_CTL_START_L2_CMD;
210 else
211 info.cmd = DRV_CTL_STOP_L2_CMD;
212
213 ring->cid = cid;
214 ring->client_id = cl_id;
215 ethdev->drv_ctl(dev->netdev, &info);
216 }
217
218 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
219 {
220 struct cnic_local *cp = dev->cnic_priv;
221 struct cnic_eth_dev *ethdev = cp->ethdev;
222 struct drv_ctl_info info;
223 struct drv_ctl_io *io = &info.data.io;
224
225 info.cmd = DRV_CTL_IO_WR_CMD;
226 io->offset = off;
227 io->data = val;
228 ethdev->drv_ctl(dev->netdev, &info);
229 }
230
231 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
232 {
233 struct cnic_local *cp = dev->cnic_priv;
234 struct cnic_eth_dev *ethdev = cp->ethdev;
235 struct drv_ctl_info info;
236 struct drv_ctl_io *io = &info.data.io;
237
238 info.cmd = DRV_CTL_IO_RD_CMD;
239 io->offset = off;
240 ethdev->drv_ctl(dev->netdev, &info);
241 return io->data;
242 }
243
244 static int cnic_in_use(struct cnic_sock *csk)
245 {
246 return test_bit(SK_F_INUSE, &csk->flags);
247 }
248
249 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
250 {
251 struct cnic_local *cp = dev->cnic_priv;
252 struct cnic_eth_dev *ethdev = cp->ethdev;
253 struct drv_ctl_info info;
254
255 info.cmd = cmd;
256 info.data.credit.credit_count = count;
257 ethdev->drv_ctl(dev->netdev, &info);
258 }
259
260 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
261 {
262 u32 i;
263
264 for (i = 0; i < cp->max_cid_space; i++) {
265 if (cp->ctx_tbl[i].cid == cid) {
266 *l5_cid = i;
267 return 0;
268 }
269 }
270 return -EINVAL;
271 }
272
273 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
274 struct cnic_sock *csk)
275 {
276 struct iscsi_path path_req;
277 char *buf = NULL;
278 u16 len = 0;
279 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
280 struct cnic_ulp_ops *ulp_ops;
281 struct cnic_uio_dev *udev = cp->udev;
282 int rc = 0, retry = 0;
283
284 if (!udev || udev->uio_dev == -1)
285 return -ENODEV;
286
287 if (csk) {
288 len = sizeof(path_req);
289 buf = (char *) &path_req;
290 memset(&path_req, 0, len);
291
292 msg_type = ISCSI_KEVENT_PATH_REQ;
293 path_req.handle = (u64) csk->l5_cid;
294 if (test_bit(SK_F_IPV6, &csk->flags)) {
295 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
296 sizeof(struct in6_addr));
297 path_req.ip_addr_len = 16;
298 } else {
299 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
300 sizeof(struct in_addr));
301 path_req.ip_addr_len = 4;
302 }
303 path_req.vlan_id = csk->vlan_id;
304 path_req.pmtu = csk->mtu;
305 }
306
307 while (retry < 3) {
308 rc = 0;
309 rcu_read_lock();
310 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
311 if (ulp_ops)
312 rc = ulp_ops->iscsi_nl_send_msg(
313 cp->ulp_handle[CNIC_ULP_ISCSI],
314 msg_type, buf, len);
315 rcu_read_unlock();
316 if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
317 break;
318
319 msleep(100);
320 retry++;
321 }
322 return 0;
323 }
324
325 static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
326
327 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
328 char *buf, u16 len)
329 {
330 int rc = -EINVAL;
331
332 switch (msg_type) {
333 case ISCSI_UEVENT_PATH_UPDATE: {
334 struct cnic_local *cp;
335 u32 l5_cid;
336 struct cnic_sock *csk;
337 struct iscsi_path *path_resp;
338
339 if (len < sizeof(*path_resp))
340 break;
341
342 path_resp = (struct iscsi_path *) buf;
343 cp = dev->cnic_priv;
344 l5_cid = (u32) path_resp->handle;
345 if (l5_cid >= MAX_CM_SK_TBL_SZ)
346 break;
347
348 rcu_read_lock();
349 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
350 rc = -ENODEV;
351 rcu_read_unlock();
352 break;
353 }
354 csk = &cp->csk_tbl[l5_cid];
355 csk_hold(csk);
356 if (cnic_in_use(csk) &&
357 test_bit(SK_F_CONNECT_START, &csk->flags)) {
358
359 memcpy(csk->ha, path_resp->mac_addr, 6);
360 if (test_bit(SK_F_IPV6, &csk->flags))
361 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
362 sizeof(struct in6_addr));
363 else
364 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
365 sizeof(struct in_addr));
366
367 if (is_valid_ether_addr(csk->ha)) {
368 cnic_cm_set_pg(csk);
369 } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
370 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
371
372 cnic_cm_upcall(cp, csk,
373 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
374 clear_bit(SK_F_CONNECT_START, &csk->flags);
375 }
376 }
377 csk_put(csk);
378 rcu_read_unlock();
379 rc = 0;
380 }
381 }
382
383 return rc;
384 }
385
386 static int cnic_offld_prep(struct cnic_sock *csk)
387 {
388 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
389 return 0;
390
391 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
392 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
393 return 0;
394 }
395
396 return 1;
397 }
398
399 static int cnic_close_prep(struct cnic_sock *csk)
400 {
401 clear_bit(SK_F_CONNECT_START, &csk->flags);
402 smp_mb__after_clear_bit();
403
404 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
405 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
406 msleep(1);
407
408 return 1;
409 }
410 return 0;
411 }
412
413 static int cnic_abort_prep(struct cnic_sock *csk)
414 {
415 clear_bit(SK_F_CONNECT_START, &csk->flags);
416 smp_mb__after_clear_bit();
417
418 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
419 msleep(1);
420
421 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
422 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
423 return 1;
424 }
425
426 return 0;
427 }
428
429 static void cnic_uio_stop(void)
430 {
431 struct cnic_dev *dev;
432
433 read_lock(&cnic_dev_lock);
434 list_for_each_entry(dev, &cnic_dev_list, list) {
435 struct cnic_local *cp = dev->cnic_priv;
436
437 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
438 }
439 read_unlock(&cnic_dev_lock);
440 }
441
442 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
443 {
444 struct cnic_dev *dev;
445
446 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
447 pr_err("%s: Bad type %d\n", __func__, ulp_type);
448 return -EINVAL;
449 }
450 mutex_lock(&cnic_lock);
451 if (cnic_ulp_tbl[ulp_type]) {
452 pr_err("%s: Type %d has already been registered\n",
453 __func__, ulp_type);
454 mutex_unlock(&cnic_lock);
455 return -EBUSY;
456 }
457
458 read_lock(&cnic_dev_lock);
459 list_for_each_entry(dev, &cnic_dev_list, list) {
460 struct cnic_local *cp = dev->cnic_priv;
461
462 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
463 }
464 read_unlock(&cnic_dev_lock);
465
466 atomic_set(&ulp_ops->ref_count, 0);
467 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
468 mutex_unlock(&cnic_lock);
469
470 /* Prevent race conditions with netdev_event */
471 rtnl_lock();
472 list_for_each_entry(dev, &cnic_dev_list, list) {
473 struct cnic_local *cp = dev->cnic_priv;
474
475 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
476 ulp_ops->cnic_init(dev);
477 }
478 rtnl_unlock();
479
480 return 0;
481 }
482
483 int cnic_unregister_driver(int ulp_type)
484 {
485 struct cnic_dev *dev;
486 struct cnic_ulp_ops *ulp_ops;
487 int i = 0;
488
489 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
490 pr_err("%s: Bad type %d\n", __func__, ulp_type);
491 return -EINVAL;
492 }
493 mutex_lock(&cnic_lock);
494 ulp_ops = cnic_ulp_tbl[ulp_type];
495 if (!ulp_ops) {
496 pr_err("%s: Type %d has not been registered\n",
497 __func__, ulp_type);
498 goto out_unlock;
499 }
500 read_lock(&cnic_dev_lock);
501 list_for_each_entry(dev, &cnic_dev_list, list) {
502 struct cnic_local *cp = dev->cnic_priv;
503
504 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
505 pr_err("%s: Type %d still has devices registered\n",
506 __func__, ulp_type);
507 read_unlock(&cnic_dev_lock);
508 goto out_unlock;
509 }
510 }
511 read_unlock(&cnic_dev_lock);
512
513 if (ulp_type == CNIC_ULP_ISCSI)
514 cnic_uio_stop();
515
516 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
517
518 mutex_unlock(&cnic_lock);
519 synchronize_rcu();
520 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
521 msleep(100);
522 i++;
523 }
524
525 if (atomic_read(&ulp_ops->ref_count) != 0)
526 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
527 return 0;
528
529 out_unlock:
530 mutex_unlock(&cnic_lock);
531 return -EINVAL;
532 }
533
534 static int cnic_start_hw(struct cnic_dev *);
535 static void cnic_stop_hw(struct cnic_dev *);
536
537 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
538 void *ulp_ctx)
539 {
540 struct cnic_local *cp = dev->cnic_priv;
541 struct cnic_ulp_ops *ulp_ops;
542
543 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
544 pr_err("%s: Bad type %d\n", __func__, ulp_type);
545 return -EINVAL;
546 }
547 mutex_lock(&cnic_lock);
548 if (cnic_ulp_tbl[ulp_type] == NULL) {
549 pr_err("%s: Driver with type %d has not been registered\n",
550 __func__, ulp_type);
551 mutex_unlock(&cnic_lock);
552 return -EAGAIN;
553 }
554 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
555 pr_err("%s: Type %d has already been registered to this device\n",
556 __func__, ulp_type);
557 mutex_unlock(&cnic_lock);
558 return -EBUSY;
559 }
560
561 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
562 cp->ulp_handle[ulp_type] = ulp_ctx;
563 ulp_ops = cnic_ulp_tbl[ulp_type];
564 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
565 cnic_hold(dev);
566
567 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
568 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
569 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
570
571 mutex_unlock(&cnic_lock);
572
573 return 0;
574
575 }
576 EXPORT_SYMBOL(cnic_register_driver);
577
578 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
579 {
580 struct cnic_local *cp = dev->cnic_priv;
581 int i = 0;
582
583 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
584 pr_err("%s: Bad type %d\n", __func__, ulp_type);
585 return -EINVAL;
586 }
587 mutex_lock(&cnic_lock);
588 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
589 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
590 cnic_put(dev);
591 } else {
592 pr_err("%s: device not registered to this ulp type %d\n",
593 __func__, ulp_type);
594 mutex_unlock(&cnic_lock);
595 return -EINVAL;
596 }
597 mutex_unlock(&cnic_lock);
598
599 synchronize_rcu();
600
601 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
602 i < 20) {
603 msleep(100);
604 i++;
605 }
606 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
607 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
608
609 return 0;
610 }
611 EXPORT_SYMBOL(cnic_unregister_driver);
612
613 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
614 {
615 id_tbl->start = start_id;
616 id_tbl->max = size;
617 id_tbl->next = 0;
618 spin_lock_init(&id_tbl->lock);
619 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
620 if (!id_tbl->table)
621 return -ENOMEM;
622
623 return 0;
624 }
625
626 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
627 {
628 kfree(id_tbl->table);
629 id_tbl->table = NULL;
630 }
631
632 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
633 {
634 int ret = -1;
635
636 id -= id_tbl->start;
637 if (id >= id_tbl->max)
638 return ret;
639
640 spin_lock(&id_tbl->lock);
641 if (!test_bit(id, id_tbl->table)) {
642 set_bit(id, id_tbl->table);
643 ret = 0;
644 }
645 spin_unlock(&id_tbl->lock);
646 return ret;
647 }
648
649 /* Returns -1 if not successful */
650 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
651 {
652 u32 id;
653
654 spin_lock(&id_tbl->lock);
655 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
656 if (id >= id_tbl->max) {
657 id = -1;
658 if (id_tbl->next != 0) {
659 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
660 if (id >= id_tbl->next)
661 id = -1;
662 }
663 }
664
665 if (id < id_tbl->max) {
666 set_bit(id, id_tbl->table);
667 id_tbl->next = (id + 1) & (id_tbl->max - 1);
668 id += id_tbl->start;
669 }
670
671 spin_unlock(&id_tbl->lock);
672
673 return id;
674 }
675
676 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
677 {
678 if (id == -1)
679 return;
680
681 id -= id_tbl->start;
682 if (id >= id_tbl->max)
683 return;
684
685 clear_bit(id, id_tbl->table);
686 }
687
688 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
689 {
690 int i;
691
692 if (!dma->pg_arr)
693 return;
694
695 for (i = 0; i < dma->num_pages; i++) {
696 if (dma->pg_arr[i]) {
697 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
698 dma->pg_arr[i], dma->pg_map_arr[i]);
699 dma->pg_arr[i] = NULL;
700 }
701 }
702 if (dma->pgtbl) {
703 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
704 dma->pgtbl, dma->pgtbl_map);
705 dma->pgtbl = NULL;
706 }
707 kfree(dma->pg_arr);
708 dma->pg_arr = NULL;
709 dma->num_pages = 0;
710 }
711
712 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
713 {
714 int i;
715 u32 *page_table = dma->pgtbl;
716
717 for (i = 0; i < dma->num_pages; i++) {
718 /* Each entry needs to be in big endian format. */
719 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
720 page_table++;
721 *page_table = (u32) dma->pg_map_arr[i];
722 page_table++;
723 }
724 }
725
726 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
727 {
728 int i;
729 u32 *page_table = dma->pgtbl;
730
731 for (i = 0; i < dma->num_pages; i++) {
732 /* Each entry needs to be in little endian format. */
733 *page_table = dma->pg_map_arr[i] & 0xffffffff;
734 page_table++;
735 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
736 page_table++;
737 }
738 }
739
740 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
741 int pages, int use_pg_tbl)
742 {
743 int i, size;
744 struct cnic_local *cp = dev->cnic_priv;
745
746 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
747 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
748 if (dma->pg_arr == NULL)
749 return -ENOMEM;
750
751 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
752 dma->num_pages = pages;
753
754 for (i = 0; i < pages; i++) {
755 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
756 BCM_PAGE_SIZE,
757 &dma->pg_map_arr[i],
758 GFP_ATOMIC);
759 if (dma->pg_arr[i] == NULL)
760 goto error;
761 }
762 if (!use_pg_tbl)
763 return 0;
764
765 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
766 ~(BCM_PAGE_SIZE - 1);
767 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
768 &dma->pgtbl_map, GFP_ATOMIC);
769 if (dma->pgtbl == NULL)
770 goto error;
771
772 cp->setup_pgtbl(dev, dma);
773
774 return 0;
775
776 error:
777 cnic_free_dma(dev, dma);
778 return -ENOMEM;
779 }
780
781 static void cnic_free_context(struct cnic_dev *dev)
782 {
783 struct cnic_local *cp = dev->cnic_priv;
784 int i;
785
786 for (i = 0; i < cp->ctx_blks; i++) {
787 if (cp->ctx_arr[i].ctx) {
788 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
789 cp->ctx_arr[i].ctx,
790 cp->ctx_arr[i].mapping);
791 cp->ctx_arr[i].ctx = NULL;
792 }
793 }
794 }
795
796 static void __cnic_free_uio(struct cnic_uio_dev *udev)
797 {
798 uio_unregister_device(&udev->cnic_uinfo);
799
800 if (udev->l2_buf) {
801 dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
802 udev->l2_buf, udev->l2_buf_map);
803 udev->l2_buf = NULL;
804 }
805
806 if (udev->l2_ring) {
807 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
808 udev->l2_ring, udev->l2_ring_map);
809 udev->l2_ring = NULL;
810 }
811
812 pci_dev_put(udev->pdev);
813 kfree(udev);
814 }
815
816 static void cnic_free_uio(struct cnic_uio_dev *udev)
817 {
818 if (!udev)
819 return;
820
821 write_lock(&cnic_dev_lock);
822 list_del_init(&udev->list);
823 write_unlock(&cnic_dev_lock);
824 __cnic_free_uio(udev);
825 }
826
827 static void cnic_free_resc(struct cnic_dev *dev)
828 {
829 struct cnic_local *cp = dev->cnic_priv;
830 struct cnic_uio_dev *udev = cp->udev;
831
832 if (udev) {
833 udev->dev = NULL;
834 cp->udev = NULL;
835 }
836
837 cnic_free_context(dev);
838 kfree(cp->ctx_arr);
839 cp->ctx_arr = NULL;
840 cp->ctx_blks = 0;
841
842 cnic_free_dma(dev, &cp->gbl_buf_info);
843 cnic_free_dma(dev, &cp->conn_buf_info);
844 cnic_free_dma(dev, &cp->kwq_info);
845 cnic_free_dma(dev, &cp->kwq_16_data_info);
846 cnic_free_dma(dev, &cp->kcq1.dma);
847 kfree(cp->iscsi_tbl);
848 cp->iscsi_tbl = NULL;
849 kfree(cp->ctx_tbl);
850 cp->ctx_tbl = NULL;
851
852 cnic_free_id_tbl(&cp->cid_tbl);
853 }
854
855 static int cnic_alloc_context(struct cnic_dev *dev)
856 {
857 struct cnic_local *cp = dev->cnic_priv;
858
859 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
860 int i, k, arr_size;
861
862 cp->ctx_blk_size = BCM_PAGE_SIZE;
863 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
864 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
865 sizeof(struct cnic_ctx);
866 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
867 if (cp->ctx_arr == NULL)
868 return -ENOMEM;
869
870 k = 0;
871 for (i = 0; i < 2; i++) {
872 u32 j, reg, off, lo, hi;
873
874 if (i == 0)
875 off = BNX2_PG_CTX_MAP;
876 else
877 off = BNX2_ISCSI_CTX_MAP;
878
879 reg = cnic_reg_rd_ind(dev, off);
880 lo = reg >> 16;
881 hi = reg & 0xffff;
882 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
883 cp->ctx_arr[k].cid = j;
884 }
885
886 cp->ctx_blks = k;
887 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
888 cp->ctx_blks = 0;
889 return -ENOMEM;
890 }
891
892 for (i = 0; i < cp->ctx_blks; i++) {
893 cp->ctx_arr[i].ctx =
894 dma_alloc_coherent(&dev->pcidev->dev,
895 BCM_PAGE_SIZE,
896 &cp->ctx_arr[i].mapping,
897 GFP_KERNEL);
898 if (cp->ctx_arr[i].ctx == NULL)
899 return -ENOMEM;
900 }
901 }
902 return 0;
903 }
904
905 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
906 {
907 int err, i, is_bnx2 = 0;
908 struct kcqe **kcq;
909
910 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
911 is_bnx2 = 1;
912
913 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
914 if (err)
915 return err;
916
917 kcq = (struct kcqe **) info->dma.pg_arr;
918 info->kcq = kcq;
919
920 if (is_bnx2)
921 return 0;
922
923 for (i = 0; i < KCQ_PAGE_CNT; i++) {
924 struct bnx2x_bd_chain_next *next =
925 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
926 int j = i + 1;
927
928 if (j >= KCQ_PAGE_CNT)
929 j = 0;
930 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
931 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
932 }
933 return 0;
934 }
935
936 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
937 {
938 struct cnic_local *cp = dev->cnic_priv;
939 struct cnic_uio_dev *udev;
940
941 read_lock(&cnic_dev_lock);
942 list_for_each_entry(udev, &cnic_udev_list, list) {
943 if (udev->pdev == dev->pcidev) {
944 udev->dev = dev;
945 cp->udev = udev;
946 read_unlock(&cnic_dev_lock);
947 return 0;
948 }
949 }
950 read_unlock(&cnic_dev_lock);
951
952 udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
953 if (!udev)
954 return -ENOMEM;
955
956 udev->uio_dev = -1;
957
958 udev->dev = dev;
959 udev->pdev = dev->pcidev;
960 udev->l2_ring_size = pages * BCM_PAGE_SIZE;
961 udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
962 &udev->l2_ring_map,
963 GFP_KERNEL | __GFP_COMP);
964 if (!udev->l2_ring)
965 return -ENOMEM;
966
967 udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
968 udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
969 udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
970 &udev->l2_buf_map,
971 GFP_KERNEL | __GFP_COMP);
972 if (!udev->l2_buf)
973 return -ENOMEM;
974
975 write_lock(&cnic_dev_lock);
976 list_add(&udev->list, &cnic_udev_list);
977 write_unlock(&cnic_dev_lock);
978
979 pci_dev_get(udev->pdev);
980
981 cp->udev = udev;
982
983 return 0;
984 }
985
986 static int cnic_init_uio(struct cnic_dev *dev)
987 {
988 struct cnic_local *cp = dev->cnic_priv;
989 struct cnic_uio_dev *udev = cp->udev;
990 struct uio_info *uinfo;
991 int ret = 0;
992
993 if (!udev)
994 return -ENOMEM;
995
996 uinfo = &udev->cnic_uinfo;
997
998 uinfo->mem[0].addr = dev->netdev->base_addr;
999 uinfo->mem[0].internal_addr = dev->regview;
1000 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
1001 uinfo->mem[0].memtype = UIO_MEM_PHYS;
1002
1003 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
1004 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
1005 PAGE_MASK;
1006 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
1007 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
1008 else
1009 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
1010
1011 uinfo->name = "bnx2_cnic";
1012 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
1013 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
1014 PAGE_MASK;
1015 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
1016
1017 uinfo->name = "bnx2x_cnic";
1018 }
1019
1020 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
1021
1022 uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
1023 uinfo->mem[2].size = udev->l2_ring_size;
1024 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
1025
1026 uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
1027 uinfo->mem[3].size = udev->l2_buf_size;
1028 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
1029
1030 uinfo->version = CNIC_MODULE_VERSION;
1031 uinfo->irq = UIO_IRQ_CUSTOM;
1032
1033 uinfo->open = cnic_uio_open;
1034 uinfo->release = cnic_uio_close;
1035
1036 if (udev->uio_dev == -1) {
1037 if (!uinfo->priv) {
1038 uinfo->priv = udev;
1039
1040 ret = uio_register_device(&udev->pdev->dev, uinfo);
1041 }
1042 } else {
1043 cnic_init_rings(dev);
1044 }
1045
1046 return ret;
1047 }
1048
1049 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1050 {
1051 struct cnic_local *cp = dev->cnic_priv;
1052 int ret;
1053
1054 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1055 if (ret)
1056 goto error;
1057 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1058
1059 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1060 if (ret)
1061 goto error;
1062
1063 ret = cnic_alloc_context(dev);
1064 if (ret)
1065 goto error;
1066
1067 ret = cnic_alloc_uio_rings(dev, 2);
1068 if (ret)
1069 goto error;
1070
1071 ret = cnic_init_uio(dev);
1072 if (ret)
1073 goto error;
1074
1075 return 0;
1076
1077 error:
1078 cnic_free_resc(dev);
1079 return ret;
1080 }
1081
1082 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1083 {
1084 struct cnic_local *cp = dev->cnic_priv;
1085 int ctx_blk_size = cp->ethdev->ctx_blk_size;
1086 int total_mem, blks, i;
1087
1088 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1089 blks = total_mem / ctx_blk_size;
1090 if (total_mem % ctx_blk_size)
1091 blks++;
1092
1093 if (blks > cp->ethdev->ctx_tbl_len)
1094 return -ENOMEM;
1095
1096 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1097 if (cp->ctx_arr == NULL)
1098 return -ENOMEM;
1099
1100 cp->ctx_blks = blks;
1101 cp->ctx_blk_size = ctx_blk_size;
1102 if (!BNX2X_CHIP_IS_57710(cp->chip_id))
1103 cp->ctx_align = 0;
1104 else
1105 cp->ctx_align = ctx_blk_size;
1106
1107 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1108
1109 for (i = 0; i < blks; i++) {
1110 cp->ctx_arr[i].ctx =
1111 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1112 &cp->ctx_arr[i].mapping,
1113 GFP_KERNEL);
1114 if (cp->ctx_arr[i].ctx == NULL)
1115 return -ENOMEM;
1116
1117 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1118 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1119 cnic_free_context(dev);
1120 cp->ctx_blk_size += cp->ctx_align;
1121 i = -1;
1122 continue;
1123 }
1124 }
1125 }
1126 return 0;
1127 }
1128
1129 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1130 {
1131 struct cnic_local *cp = dev->cnic_priv;
1132 struct cnic_eth_dev *ethdev = cp->ethdev;
1133 u32 start_cid = ethdev->starting_cid;
1134 int i, j, n, ret, pages;
1135 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1136
1137 cp->iro_arr = ethdev->iro_arr;
1138
1139 cp->max_cid_space = MAX_ISCSI_TBL_SZ;
1140 cp->iscsi_start_cid = start_cid;
1141 if (start_cid < BNX2X_ISCSI_START_CID) {
1142 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1143
1144 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1145 cp->max_cid_space += delta;
1146 }
1147
1148 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1149 GFP_KERNEL);
1150 if (!cp->iscsi_tbl)
1151 goto error;
1152
1153 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1154 cp->max_cid_space, GFP_KERNEL);
1155 if (!cp->ctx_tbl)
1156 goto error;
1157
1158 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1159 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1160 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1161 }
1162
1163 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1164 PAGE_SIZE;
1165
1166 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1167 if (ret)
1168 return -ENOMEM;
1169
1170 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1171 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1172 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1173
1174 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1175 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1176 off;
1177
1178 if ((i % n) == (n - 1))
1179 j++;
1180 }
1181
1182 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1183 if (ret)
1184 goto error;
1185
1186 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1187 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1188 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1189 if (ret)
1190 goto error;
1191
1192 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1193 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1194 if (ret)
1195 goto error;
1196
1197 ret = cnic_alloc_bnx2x_context(dev);
1198 if (ret)
1199 goto error;
1200
1201 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1202
1203 cp->l2_rx_ring_size = 15;
1204
1205 ret = cnic_alloc_uio_rings(dev, 4);
1206 if (ret)
1207 goto error;
1208
1209 ret = cnic_init_uio(dev);
1210 if (ret)
1211 goto error;
1212
1213 return 0;
1214
1215 error:
1216 cnic_free_resc(dev);
1217 return -ENOMEM;
1218 }
1219
1220 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1221 {
1222 return cp->max_kwq_idx -
1223 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1224 }
1225
1226 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1227 u32 num_wqes)
1228 {
1229 struct cnic_local *cp = dev->cnic_priv;
1230 struct kwqe *prod_qe;
1231 u16 prod, sw_prod, i;
1232
1233 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1234 return -EAGAIN; /* bnx2 is down */
1235
1236 spin_lock_bh(&cp->cnic_ulp_lock);
1237 if (num_wqes > cnic_kwq_avail(cp) &&
1238 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1239 spin_unlock_bh(&cp->cnic_ulp_lock);
1240 return -EAGAIN;
1241 }
1242
1243 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1244
1245 prod = cp->kwq_prod_idx;
1246 sw_prod = prod & MAX_KWQ_IDX;
1247 for (i = 0; i < num_wqes; i++) {
1248 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1249 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1250 prod++;
1251 sw_prod = prod & MAX_KWQ_IDX;
1252 }
1253 cp->kwq_prod_idx = prod;
1254
1255 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1256
1257 spin_unlock_bh(&cp->cnic_ulp_lock);
1258 return 0;
1259 }
1260
1261 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1262 union l5cm_specific_data *l5_data)
1263 {
1264 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1265 dma_addr_t map;
1266
1267 map = ctx->kwqe_data_mapping;
1268 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1269 l5_data->phy_address.hi = (u64) map >> 32;
1270 return ctx->kwqe_data;
1271 }
1272
1273 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1274 u32 type, union l5cm_specific_data *l5_data)
1275 {
1276 struct cnic_local *cp = dev->cnic_priv;
1277 struct l5cm_spe kwqe;
1278 struct kwqe_16 *kwq[1];
1279 int ret;
1280
1281 kwqe.hdr.conn_and_cmd_data =
1282 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1283 BNX2X_HW_CID(cp, cid)));
1284 kwqe.hdr.type = cpu_to_le16(type);
1285 kwqe.hdr.reserved1 = 0;
1286 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1287 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1288
1289 kwq[0] = (struct kwqe_16 *) &kwqe;
1290
1291 spin_lock_bh(&cp->cnic_ulp_lock);
1292 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1293 spin_unlock_bh(&cp->cnic_ulp_lock);
1294
1295 if (ret == 1)
1296 return 0;
1297
1298 return -EBUSY;
1299 }
1300
1301 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1302 struct kcqe *cqes[], u32 num_cqes)
1303 {
1304 struct cnic_local *cp = dev->cnic_priv;
1305 struct cnic_ulp_ops *ulp_ops;
1306
1307 rcu_read_lock();
1308 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1309 if (likely(ulp_ops)) {
1310 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1311 cqes, num_cqes);
1312 }
1313 rcu_read_unlock();
1314 }
1315
1316 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1317 {
1318 struct cnic_local *cp = dev->cnic_priv;
1319 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1320 int hq_bds, pages;
1321 u32 pfid = cp->pfid;
1322
1323 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1324 cp->num_ccells = req1->num_ccells_per_conn;
1325 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1326 cp->num_iscsi_tasks;
1327 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1328 BNX2X_ISCSI_R2TQE_SIZE;
1329 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1330 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1331 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1332 cp->num_cqs = req1->num_cqs;
1333
1334 if (!dev->max_iscsi_conn)
1335 return 0;
1336
1337 /* init Tstorm RAM */
1338 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1339 req1->rq_num_wqes);
1340 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1341 PAGE_SIZE);
1342 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1343 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1344 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1345 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1346 req1->num_tasks_per_conn);
1347
1348 /* init Ustorm RAM */
1349 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1350 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1351 req1->rq_buffer_size);
1352 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1353 PAGE_SIZE);
1354 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1355 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1356 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1357 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1358 req1->num_tasks_per_conn);
1359 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1360 req1->rq_num_wqes);
1361 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1362 req1->cq_num_wqes);
1363 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1364 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1365
1366 /* init Xstorm RAM */
1367 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1368 PAGE_SIZE);
1369 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1370 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1371 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1372 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1373 req1->num_tasks_per_conn);
1374 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1375 hq_bds);
1376 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1377 req1->num_tasks_per_conn);
1378 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1379 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1380
1381 /* init Cstorm RAM */
1382 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1383 PAGE_SIZE);
1384 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1385 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1386 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1387 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1388 req1->num_tasks_per_conn);
1389 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1390 req1->cq_num_wqes);
1391 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1392 hq_bds);
1393
1394 return 0;
1395 }
1396
1397 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1398 {
1399 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1400 struct cnic_local *cp = dev->cnic_priv;
1401 u32 pfid = cp->pfid;
1402 struct iscsi_kcqe kcqe;
1403 struct kcqe *cqes[1];
1404
1405 memset(&kcqe, 0, sizeof(kcqe));
1406 if (!dev->max_iscsi_conn) {
1407 kcqe.completion_status =
1408 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1409 goto done;
1410 }
1411
1412 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1413 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1414 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1415 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1416 req2->error_bit_map[1]);
1417
1418 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1419 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1420 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1421 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1422 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1423 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1424 req2->error_bit_map[1]);
1425
1426 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1427 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1428
1429 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1430
1431 done:
1432 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1433 cqes[0] = (struct kcqe *) &kcqe;
1434 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1435
1436 return 0;
1437 }
1438
1439 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1440 {
1441 struct cnic_local *cp = dev->cnic_priv;
1442 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1443
1444 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1445 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1446
1447 cnic_free_dma(dev, &iscsi->hq_info);
1448 cnic_free_dma(dev, &iscsi->r2tq_info);
1449 cnic_free_dma(dev, &iscsi->task_array_info);
1450 }
1451 cnic_free_id(&cp->cid_tbl, ctx->cid);
1452 ctx->cid = 0;
1453 }
1454
1455 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1456 {
1457 u32 cid;
1458 int ret, pages;
1459 struct cnic_local *cp = dev->cnic_priv;
1460 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1461 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1462
1463 cid = cnic_alloc_new_id(&cp->cid_tbl);
1464 if (cid == -1) {
1465 ret = -ENOMEM;
1466 goto error;
1467 }
1468
1469 ctx->cid = cid;
1470 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1471
1472 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1473 if (ret)
1474 goto error;
1475
1476 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1477 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1478 if (ret)
1479 goto error;
1480
1481 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1482 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1483 if (ret)
1484 goto error;
1485
1486 return 0;
1487
1488 error:
1489 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1490 return ret;
1491 }
1492
1493 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1494 struct regpair *ctx_addr)
1495 {
1496 struct cnic_local *cp = dev->cnic_priv;
1497 struct cnic_eth_dev *ethdev = cp->ethdev;
1498 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1499 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1500 unsigned long align_off = 0;
1501 dma_addr_t ctx_map;
1502 void *ctx;
1503
1504 if (cp->ctx_align) {
1505 unsigned long mask = cp->ctx_align - 1;
1506
1507 if (cp->ctx_arr[blk].mapping & mask)
1508 align_off = cp->ctx_align -
1509 (cp->ctx_arr[blk].mapping & mask);
1510 }
1511 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1512 (off * BNX2X_CONTEXT_MEM_SIZE);
1513 ctx = cp->ctx_arr[blk].ctx + align_off +
1514 (off * BNX2X_CONTEXT_MEM_SIZE);
1515 if (init)
1516 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1517
1518 ctx_addr->lo = ctx_map & 0xffffffff;
1519 ctx_addr->hi = (u64) ctx_map >> 32;
1520 return ctx;
1521 }
1522
1523 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1524 u32 num)
1525 {
1526 struct cnic_local *cp = dev->cnic_priv;
1527 struct iscsi_kwqe_conn_offload1 *req1 =
1528 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1529 struct iscsi_kwqe_conn_offload2 *req2 =
1530 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1531 struct iscsi_kwqe_conn_offload3 *req3;
1532 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1533 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1534 u32 cid = ctx->cid;
1535 u32 hw_cid = BNX2X_HW_CID(cp, cid);
1536 struct iscsi_context *ictx;
1537 struct regpair context_addr;
1538 int i, j, n = 2, n_max;
1539
1540 ctx->ctx_flags = 0;
1541 if (!req2->num_additional_wqes)
1542 return -EINVAL;
1543
1544 n_max = req2->num_additional_wqes + 2;
1545
1546 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1547 if (ictx == NULL)
1548 return -ENOMEM;
1549
1550 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1551
1552 ictx->xstorm_ag_context.hq_prod = 1;
1553
1554 ictx->xstorm_st_context.iscsi.first_burst_length =
1555 ISCSI_DEF_FIRST_BURST_LEN;
1556 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1557 ISCSI_DEF_MAX_RECV_SEG_LEN;
1558 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1559 req1->sq_page_table_addr_lo;
1560 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1561 req1->sq_page_table_addr_hi;
1562 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1563 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1564 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1565 iscsi->hq_info.pgtbl_map & 0xffffffff;
1566 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1567 (u64) iscsi->hq_info.pgtbl_map >> 32;
1568 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1569 iscsi->hq_info.pgtbl[0];
1570 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1571 iscsi->hq_info.pgtbl[1];
1572 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1573 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1574 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1575 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1576 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1577 iscsi->r2tq_info.pgtbl[0];
1578 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1579 iscsi->r2tq_info.pgtbl[1];
1580 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1581 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1582 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1583 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1584 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1585 BNX2X_ISCSI_PBL_NOT_CACHED;
1586 ictx->xstorm_st_context.iscsi.flags.flags |=
1587 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1588 ictx->xstorm_st_context.iscsi.flags.flags |=
1589 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1590
1591 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1592 /* TSTORM requires the base address of RQ DB & not PTE */
1593 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1594 req2->rq_page_table_addr_lo & PAGE_MASK;
1595 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1596 req2->rq_page_table_addr_hi;
1597 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1598 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1599 ictx->tstorm_st_context.tcp.flags2 |=
1600 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1601 ictx->tstorm_st_context.tcp.ooo_support_mode =
1602 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1603
1604 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1605
1606 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1607 req2->rq_page_table_addr_lo;
1608 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1609 req2->rq_page_table_addr_hi;
1610 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1611 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1612 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1613 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1614 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1615 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1616 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1617 iscsi->r2tq_info.pgtbl[0];
1618 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1619 iscsi->r2tq_info.pgtbl[1];
1620 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1621 req1->cq_page_table_addr_lo;
1622 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1623 req1->cq_page_table_addr_hi;
1624 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1625 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1626 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1627 ictx->ustorm_st_context.task_pbe_cache_index =
1628 BNX2X_ISCSI_PBL_NOT_CACHED;
1629 ictx->ustorm_st_context.task_pdu_cache_index =
1630 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1631
1632 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1633 if (j == 3) {
1634 if (n >= n_max)
1635 break;
1636 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1637 j = 0;
1638 }
1639 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1640 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1641 req3->qp_first_pte[j].hi;
1642 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1643 req3->qp_first_pte[j].lo;
1644 }
1645
1646 ictx->ustorm_st_context.task_pbl_base.lo =
1647 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1648 ictx->ustorm_st_context.task_pbl_base.hi =
1649 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1650 ictx->ustorm_st_context.tce_phy_addr.lo =
1651 iscsi->task_array_info.pgtbl[0];
1652 ictx->ustorm_st_context.tce_phy_addr.hi =
1653 iscsi->task_array_info.pgtbl[1];
1654 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1655 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1656 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1657 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1658 ISCSI_DEF_MAX_BURST_LEN;
1659 ictx->ustorm_st_context.negotiated_rx |=
1660 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1661 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1662
1663 ictx->cstorm_st_context.hq_pbl_base.lo =
1664 iscsi->hq_info.pgtbl_map & 0xffffffff;
1665 ictx->cstorm_st_context.hq_pbl_base.hi =
1666 (u64) iscsi->hq_info.pgtbl_map >> 32;
1667 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1668 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1669 ictx->cstorm_st_context.task_pbl_base.lo =
1670 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1671 ictx->cstorm_st_context.task_pbl_base.hi =
1672 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1673 /* CSTORM and USTORM initialization is different, CSTORM requires
1674 * CQ DB base & not PTE addr */
1675 ictx->cstorm_st_context.cq_db_base.lo =
1676 req1->cq_page_table_addr_lo & PAGE_MASK;
1677 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1678 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1679 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1680 for (i = 0; i < cp->num_cqs; i++) {
1681 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1682 ISCSI_INITIAL_SN;
1683 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1684 ISCSI_INITIAL_SN;
1685 }
1686
1687 ictx->xstorm_ag_context.cdu_reserved =
1688 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1689 ISCSI_CONNECTION_TYPE);
1690 ictx->ustorm_ag_context.cdu_usage =
1691 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1692 ISCSI_CONNECTION_TYPE);
1693 return 0;
1694
1695 }
1696
1697 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1698 u32 num, int *work)
1699 {
1700 struct iscsi_kwqe_conn_offload1 *req1;
1701 struct iscsi_kwqe_conn_offload2 *req2;
1702 struct cnic_local *cp = dev->cnic_priv;
1703 struct cnic_context *ctx;
1704 struct iscsi_kcqe kcqe;
1705 struct kcqe *cqes[1];
1706 u32 l5_cid;
1707 int ret = 0;
1708
1709 if (num < 2) {
1710 *work = num;
1711 return -EINVAL;
1712 }
1713
1714 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1715 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1716 if ((num - 2) < req2->num_additional_wqes) {
1717 *work = num;
1718 return -EINVAL;
1719 }
1720 *work = 2 + req2->num_additional_wqes;
1721
1722 l5_cid = req1->iscsi_conn_id;
1723 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1724 return -EINVAL;
1725
1726 memset(&kcqe, 0, sizeof(kcqe));
1727 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1728 kcqe.iscsi_conn_id = l5_cid;
1729 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1730
1731 ctx = &cp->ctx_tbl[l5_cid];
1732 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1733 kcqe.completion_status =
1734 ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1735 goto done;
1736 }
1737
1738 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1739 atomic_dec(&cp->iscsi_conn);
1740 goto done;
1741 }
1742 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1743 if (ret) {
1744 atomic_dec(&cp->iscsi_conn);
1745 ret = 0;
1746 goto done;
1747 }
1748 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1749 if (ret < 0) {
1750 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1751 atomic_dec(&cp->iscsi_conn);
1752 goto done;
1753 }
1754
1755 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1756 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
1757
1758 done:
1759 cqes[0] = (struct kcqe *) &kcqe;
1760 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1761 return ret;
1762 }
1763
1764
1765 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1766 {
1767 struct cnic_local *cp = dev->cnic_priv;
1768 struct iscsi_kwqe_conn_update *req =
1769 (struct iscsi_kwqe_conn_update *) kwqe;
1770 void *data;
1771 union l5cm_specific_data l5_data;
1772 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1773 int ret;
1774
1775 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1776 return -EINVAL;
1777
1778 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1779 if (!data)
1780 return -ENOMEM;
1781
1782 memcpy(data, kwqe, sizeof(struct kwqe));
1783
1784 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1785 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1786 return ret;
1787 }
1788
1789 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1790 {
1791 struct cnic_local *cp = dev->cnic_priv;
1792 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1793 union l5cm_specific_data l5_data;
1794 int ret;
1795 u32 hw_cid, type;
1796
1797 init_waitqueue_head(&ctx->waitq);
1798 ctx->wait_cond = 0;
1799 memset(&l5_data, 0, sizeof(l5_data));
1800 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1801 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
1802 & SPE_HDR_CONN_TYPE;
1803 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1804 SPE_HDR_FUNCTION_ID);
1805
1806 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1807 hw_cid, type, &l5_data);
1808
1809 if (ret == 0)
1810 wait_event(ctx->waitq, ctx->wait_cond);
1811
1812 return ret;
1813 }
1814
1815 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1816 {
1817 struct cnic_local *cp = dev->cnic_priv;
1818 struct iscsi_kwqe_conn_destroy *req =
1819 (struct iscsi_kwqe_conn_destroy *) kwqe;
1820 u32 l5_cid = req->reserved0;
1821 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1822 int ret = 0;
1823 struct iscsi_kcqe kcqe;
1824 struct kcqe *cqes[1];
1825
1826 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
1827 goto skip_cfc_delete;
1828
1829 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
1830 unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
1831
1832 if (delta > (2 * HZ))
1833 delta = 0;
1834
1835 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
1836 queue_delayed_work(cnic_wq, &cp->delete_task, delta);
1837 goto destroy_reply;
1838 }
1839
1840 ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
1841
1842 skip_cfc_delete:
1843 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1844
1845 atomic_dec(&cp->iscsi_conn);
1846 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
1847
1848 destroy_reply:
1849 memset(&kcqe, 0, sizeof(kcqe));
1850 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1851 kcqe.iscsi_conn_id = l5_cid;
1852 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1853 kcqe.iscsi_conn_context_id = req->context_id;
1854
1855 cqes[0] = (struct kcqe *) &kcqe;
1856 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1857
1858 return ret;
1859 }
1860
1861 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1862 struct l4_kwq_connect_req1 *kwqe1,
1863 struct l4_kwq_connect_req3 *kwqe3,
1864 struct l5cm_active_conn_buffer *conn_buf)
1865 {
1866 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1867 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1868 &conn_buf->xstorm_conn_buffer;
1869 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1870 &conn_buf->tstorm_conn_buffer;
1871 struct regpair context_addr;
1872 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1873 struct in6_addr src_ip, dst_ip;
1874 int i;
1875 u32 *addrp;
1876
1877 addrp = (u32 *) &conn_addr->local_ip_addr;
1878 for (i = 0; i < 4; i++, addrp++)
1879 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1880
1881 addrp = (u32 *) &conn_addr->remote_ip_addr;
1882 for (i = 0; i < 4; i++, addrp++)
1883 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1884
1885 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1886
1887 xstorm_buf->context_addr.hi = context_addr.hi;
1888 xstorm_buf->context_addr.lo = context_addr.lo;
1889 xstorm_buf->mss = 0xffff;
1890 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1891 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1892 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1893 xstorm_buf->pseudo_header_checksum =
1894 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1895
1896 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1897 tstorm_buf->params |=
1898 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1899 if (kwqe3->ka_timeout) {
1900 tstorm_buf->ka_enable = 1;
1901 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1902 tstorm_buf->ka_interval = kwqe3->ka_interval;
1903 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1904 }
1905 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1906 tstorm_buf->snd_buf = kwqe3->snd_buf;
1907 tstorm_buf->max_rt_time = 0xffffffff;
1908 }
1909
1910 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1911 {
1912 struct cnic_local *cp = dev->cnic_priv;
1913 u32 pfid = cp->pfid;
1914 u8 *mac = dev->mac_addr;
1915
1916 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1917 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
1918 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1919 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
1920 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1921 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
1922 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1923 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
1924 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1925 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
1926 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1927 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
1928
1929 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1930 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
1931 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1932 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1933 mac[4]);
1934 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1935 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
1936 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1937 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1938 mac[2]);
1939 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1940 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
1941 mac[1]);
1942 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1943 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
1944 mac[0]);
1945 }
1946
1947 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1948 {
1949 struct cnic_local *cp = dev->cnic_priv;
1950 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1951 u16 tstorm_flags = 0;
1952
1953 if (tcp_ts) {
1954 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1955 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1956 }
1957
1958 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1959 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
1960
1961 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1962 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
1963 }
1964
1965 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
1966 u32 num, int *work)
1967 {
1968 struct cnic_local *cp = dev->cnic_priv;
1969 struct l4_kwq_connect_req1 *kwqe1 =
1970 (struct l4_kwq_connect_req1 *) wqes[0];
1971 struct l4_kwq_connect_req3 *kwqe3;
1972 struct l5cm_active_conn_buffer *conn_buf;
1973 struct l5cm_conn_addr_params *conn_addr;
1974 union l5cm_specific_data l5_data;
1975 u32 l5_cid = kwqe1->pg_cid;
1976 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
1977 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1978 int ret;
1979
1980 if (num < 2) {
1981 *work = num;
1982 return -EINVAL;
1983 }
1984
1985 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
1986 *work = 3;
1987 else
1988 *work = 2;
1989
1990 if (num < *work) {
1991 *work = num;
1992 return -EINVAL;
1993 }
1994
1995 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
1996 netdev_err(dev->netdev, "conn_buf size too big\n");
1997 return -ENOMEM;
1998 }
1999 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2000 if (!conn_buf)
2001 return -ENOMEM;
2002
2003 memset(conn_buf, 0, sizeof(*conn_buf));
2004
2005 conn_addr = &conn_buf->conn_addr_buf;
2006 conn_addr->remote_addr_0 = csk->ha[0];
2007 conn_addr->remote_addr_1 = csk->ha[1];
2008 conn_addr->remote_addr_2 = csk->ha[2];
2009 conn_addr->remote_addr_3 = csk->ha[3];
2010 conn_addr->remote_addr_4 = csk->ha[4];
2011 conn_addr->remote_addr_5 = csk->ha[5];
2012
2013 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
2014 struct l4_kwq_connect_req2 *kwqe2 =
2015 (struct l4_kwq_connect_req2 *) wqes[1];
2016
2017 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
2018 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
2019 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
2020
2021 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
2022 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
2023 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
2024 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
2025 }
2026 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
2027
2028 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
2029 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
2030 conn_addr->local_tcp_port = kwqe1->src_port;
2031 conn_addr->remote_tcp_port = kwqe1->dst_port;
2032
2033 conn_addr->pmtu = kwqe3->pmtu;
2034 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
2035
2036 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
2037 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
2038
2039 cnic_bnx2x_set_tcp_timestamp(dev,
2040 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
2041
2042 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2043 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2044 if (!ret)
2045 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2046
2047 return ret;
2048 }
2049
2050 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2051 {
2052 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2053 union l5cm_specific_data l5_data;
2054 int ret;
2055
2056 memset(&l5_data, 0, sizeof(l5_data));
2057 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2058 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2059 return ret;
2060 }
2061
2062 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2063 {
2064 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2065 union l5cm_specific_data l5_data;
2066 int ret;
2067
2068 memset(&l5_data, 0, sizeof(l5_data));
2069 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2070 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2071 return ret;
2072 }
2073 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2074 {
2075 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2076 struct l4_kcq kcqe;
2077 struct kcqe *cqes[1];
2078
2079 memset(&kcqe, 0, sizeof(kcqe));
2080 kcqe.pg_host_opaque = req->host_opaque;
2081 kcqe.pg_cid = req->host_opaque;
2082 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2083 cqes[0] = (struct kcqe *) &kcqe;
2084 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2085 return 0;
2086 }
2087
2088 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2089 {
2090 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2091 struct l4_kcq kcqe;
2092 struct kcqe *cqes[1];
2093
2094 memset(&kcqe, 0, sizeof(kcqe));
2095 kcqe.pg_host_opaque = req->pg_host_opaque;
2096 kcqe.pg_cid = req->pg_cid;
2097 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2098 cqes[0] = (struct kcqe *) &kcqe;
2099 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2100 return 0;
2101 }
2102
2103 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2104 u32 num_wqes)
2105 {
2106 int i, work, ret;
2107 u32 opcode;
2108 struct kwqe *kwqe;
2109
2110 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2111 return -EAGAIN; /* bnx2 is down */
2112
2113 for (i = 0; i < num_wqes; ) {
2114 kwqe = wqes[i];
2115 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2116 work = 1;
2117
2118 switch (opcode) {
2119 case ISCSI_KWQE_OPCODE_INIT1:
2120 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2121 break;
2122 case ISCSI_KWQE_OPCODE_INIT2:
2123 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2124 break;
2125 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2126 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2127 num_wqes - i, &work);
2128 break;
2129 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2130 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2131 break;
2132 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2133 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2134 break;
2135 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2136 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2137 &work);
2138 break;
2139 case L4_KWQE_OPCODE_VALUE_CLOSE:
2140 ret = cnic_bnx2x_close(dev, kwqe);
2141 break;
2142 case L4_KWQE_OPCODE_VALUE_RESET:
2143 ret = cnic_bnx2x_reset(dev, kwqe);
2144 break;
2145 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2146 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2147 break;
2148 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2149 ret = cnic_bnx2x_update_pg(dev, kwqe);
2150 break;
2151 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2152 ret = 0;
2153 break;
2154 default:
2155 ret = 0;
2156 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2157 opcode);
2158 break;
2159 }
2160 if (ret < 0)
2161 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2162 opcode);
2163 i += work;
2164 }
2165 return 0;
2166 }
2167
2168 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2169 {
2170 struct cnic_local *cp = dev->cnic_priv;
2171 int i, j, comp = 0;
2172
2173 i = 0;
2174 j = 1;
2175 while (num_cqes) {
2176 struct cnic_ulp_ops *ulp_ops;
2177 int ulp_type;
2178 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2179 u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
2180
2181 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2182 comp++;
2183
2184 while (j < num_cqes) {
2185 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2186
2187 if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
2188 break;
2189
2190 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2191 comp++;
2192 j++;
2193 }
2194
2195 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2196 ulp_type = CNIC_ULP_RDMA;
2197 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2198 ulp_type = CNIC_ULP_ISCSI;
2199 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2200 ulp_type = CNIC_ULP_L4;
2201 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2202 goto end;
2203 else {
2204 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2205 kcqe_op_flag);
2206 goto end;
2207 }
2208
2209 rcu_read_lock();
2210 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2211 if (likely(ulp_ops)) {
2212 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2213 cp->completed_kcq + i, j);
2214 }
2215 rcu_read_unlock();
2216 end:
2217 num_cqes -= j;
2218 i += j;
2219 j = 1;
2220 }
2221 if (unlikely(comp))
2222 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2223 }
2224
2225 static u16 cnic_bnx2_next_idx(u16 idx)
2226 {
2227 return idx + 1;
2228 }
2229
2230 static u16 cnic_bnx2_hw_idx(u16 idx)
2231 {
2232 return idx;
2233 }
2234
2235 static u16 cnic_bnx2x_next_idx(u16 idx)
2236 {
2237 idx++;
2238 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2239 idx++;
2240
2241 return idx;
2242 }
2243
2244 static u16 cnic_bnx2x_hw_idx(u16 idx)
2245 {
2246 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2247 idx++;
2248 return idx;
2249 }
2250
2251 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2252 {
2253 struct cnic_local *cp = dev->cnic_priv;
2254 u16 i, ri, hw_prod, last;
2255 struct kcqe *kcqe;
2256 int kcqe_cnt = 0, last_cnt = 0;
2257
2258 i = ri = last = info->sw_prod_idx;
2259 ri &= MAX_KCQ_IDX;
2260 hw_prod = *info->hw_prod_idx_ptr;
2261 hw_prod = cp->hw_idx(hw_prod);
2262
2263 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2264 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2265 cp->completed_kcq[kcqe_cnt++] = kcqe;
2266 i = cp->next_idx(i);
2267 ri = i & MAX_KCQ_IDX;
2268 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2269 last_cnt = kcqe_cnt;
2270 last = i;
2271 }
2272 }
2273
2274 info->sw_prod_idx = last;
2275 return last_cnt;
2276 }
2277
2278 static int cnic_l2_completion(struct cnic_local *cp)
2279 {
2280 u16 hw_cons, sw_cons;
2281 struct cnic_uio_dev *udev = cp->udev;
2282 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2283 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
2284 u32 cmd;
2285 int comp = 0;
2286
2287 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2288 return 0;
2289
2290 hw_cons = *cp->rx_cons_ptr;
2291 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2292 hw_cons++;
2293
2294 sw_cons = cp->rx_cons;
2295 while (sw_cons != hw_cons) {
2296 u8 cqe_fp_flags;
2297
2298 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2299 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2300 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2301 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2302 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2303 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2304 cmd == RAMROD_CMD_ID_ETH_HALT)
2305 comp++;
2306 }
2307 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2308 }
2309 return comp;
2310 }
2311
2312 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2313 {
2314 u16 rx_cons, tx_cons;
2315 int comp = 0;
2316
2317 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2318 return;
2319
2320 rx_cons = *cp->rx_cons_ptr;
2321 tx_cons = *cp->tx_cons_ptr;
2322 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2323 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2324 comp = cnic_l2_completion(cp);
2325
2326 cp->tx_cons = tx_cons;
2327 cp->rx_cons = rx_cons;
2328
2329 if (cp->udev)
2330 uio_event_notify(&cp->udev->cnic_uinfo);
2331 }
2332 if (comp)
2333 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2334 }
2335
2336 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2337 {
2338 struct cnic_local *cp = dev->cnic_priv;
2339 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2340 int kcqe_cnt;
2341
2342 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2343
2344 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2345
2346 service_kcqes(dev, kcqe_cnt);
2347
2348 /* Tell compiler that status_blk fields can change. */
2349 barrier();
2350 if (status_idx != *cp->kcq1.status_idx_ptr) {
2351 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2352 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2353 } else
2354 break;
2355 }
2356
2357 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2358
2359 cnic_chk_pkt_rings(cp);
2360
2361 return status_idx;
2362 }
2363
2364 static int cnic_service_bnx2(void *data, void *status_blk)
2365 {
2366 struct cnic_dev *dev = data;
2367
2368 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2369 struct status_block *sblk = status_blk;
2370
2371 return sblk->status_idx;
2372 }
2373
2374 return cnic_service_bnx2_queues(dev);
2375 }
2376
2377 static void cnic_service_bnx2_msix(unsigned long data)
2378 {
2379 struct cnic_dev *dev = (struct cnic_dev *) data;
2380 struct cnic_local *cp = dev->cnic_priv;
2381
2382 cp->last_status_idx = cnic_service_bnx2_queues(dev);
2383
2384 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2385 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2386 }
2387
2388 static void cnic_doirq(struct cnic_dev *dev)
2389 {
2390 struct cnic_local *cp = dev->cnic_priv;
2391
2392 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2393 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
2394
2395 prefetch(cp->status_blk.gen);
2396 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2397
2398 tasklet_schedule(&cp->cnic_irq_task);
2399 }
2400 }
2401
2402 static irqreturn_t cnic_irq(int irq, void *dev_instance)
2403 {
2404 struct cnic_dev *dev = dev_instance;
2405 struct cnic_local *cp = dev->cnic_priv;
2406
2407 if (cp->ack_int)
2408 cp->ack_int(dev);
2409
2410 cnic_doirq(dev);
2411
2412 return IRQ_HANDLED;
2413 }
2414
2415 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2416 u16 index, u8 op, u8 update)
2417 {
2418 struct cnic_local *cp = dev->cnic_priv;
2419 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2420 COMMAND_REG_INT_ACK);
2421 struct igu_ack_register igu_ack;
2422
2423 igu_ack.status_block_index = index;
2424 igu_ack.sb_id_and_flags =
2425 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2426 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2427 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2428 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2429
2430 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2431 }
2432
2433 static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
2434 u16 index, u8 op, u8 update)
2435 {
2436 struct igu_regular cmd_data;
2437 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
2438
2439 cmd_data.sb_id_and_flags =
2440 (index << IGU_REGULAR_SB_INDEX_SHIFT) |
2441 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2442 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2443 (op << IGU_REGULAR_ENABLE_INT_SHIFT);
2444
2445
2446 CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
2447 }
2448
2449 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2450 {
2451 struct cnic_local *cp = dev->cnic_priv;
2452
2453 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
2454 IGU_INT_DISABLE, 0);
2455 }
2456
2457 static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
2458 {
2459 struct cnic_local *cp = dev->cnic_priv;
2460
2461 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
2462 IGU_INT_DISABLE, 0);
2463 }
2464
2465 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
2466 {
2467 u32 last_status = *info->status_idx_ptr;
2468 int kcqe_cnt;
2469
2470 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
2471
2472 service_kcqes(dev, kcqe_cnt);
2473
2474 /* Tell compiler that sblk fields can change. */
2475 barrier();
2476 if (last_status == *info->status_idx_ptr)
2477 break;
2478
2479 last_status = *info->status_idx_ptr;
2480 }
2481 return last_status;
2482 }
2483
2484 static void cnic_service_bnx2x_bh(unsigned long data)
2485 {
2486 struct cnic_dev *dev = (struct cnic_dev *) data;
2487 struct cnic_local *cp = dev->cnic_priv;
2488 u32 status_idx;
2489
2490 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2491 return;
2492
2493 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
2494
2495 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
2496 if (BNX2X_CHIP_IS_E2(cp->chip_id))
2497 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
2498 status_idx, IGU_INT_ENABLE, 1);
2499 else
2500 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
2501 status_idx, IGU_INT_ENABLE, 1);
2502 }
2503
2504 static int cnic_service_bnx2x(void *data, void *status_blk)
2505 {
2506 struct cnic_dev *dev = data;
2507 struct cnic_local *cp = dev->cnic_priv;
2508
2509 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
2510 cnic_doirq(dev);
2511
2512 cnic_chk_pkt_rings(cp);
2513
2514 return 0;
2515 }
2516
2517 static void cnic_ulp_stop(struct cnic_dev *dev)
2518 {
2519 struct cnic_local *cp = dev->cnic_priv;
2520 int if_type;
2521
2522 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2523
2524 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2525 struct cnic_ulp_ops *ulp_ops;
2526
2527 mutex_lock(&cnic_lock);
2528 ulp_ops = cp->ulp_ops[if_type];
2529 if (!ulp_ops) {
2530 mutex_unlock(&cnic_lock);
2531 continue;
2532 }
2533 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2534 mutex_unlock(&cnic_lock);
2535
2536 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2537 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
2538
2539 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2540 }
2541 }
2542
2543 static void cnic_ulp_start(struct cnic_dev *dev)
2544 {
2545 struct cnic_local *cp = dev->cnic_priv;
2546 int if_type;
2547
2548 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2549 struct cnic_ulp_ops *ulp_ops;
2550
2551 mutex_lock(&cnic_lock);
2552 ulp_ops = cp->ulp_ops[if_type];
2553 if (!ulp_ops || !ulp_ops->cnic_start) {
2554 mutex_unlock(&cnic_lock);
2555 continue;
2556 }
2557 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2558 mutex_unlock(&cnic_lock);
2559
2560 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2561 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
2562
2563 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2564 }
2565 }
2566
2567 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
2568 {
2569 struct cnic_dev *dev = data;
2570
2571 switch (info->cmd) {
2572 case CNIC_CTL_STOP_CMD:
2573 cnic_hold(dev);
2574
2575 cnic_ulp_stop(dev);
2576 cnic_stop_hw(dev);
2577
2578 cnic_put(dev);
2579 break;
2580 case CNIC_CTL_START_CMD:
2581 cnic_hold(dev);
2582
2583 if (!cnic_start_hw(dev))
2584 cnic_ulp_start(dev);
2585
2586 cnic_put(dev);
2587 break;
2588 case CNIC_CTL_COMPLETION_CMD: {
2589 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
2590 u32 l5_cid;
2591 struct cnic_local *cp = dev->cnic_priv;
2592
2593 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
2594 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2595
2596 ctx->wait_cond = 1;
2597 wake_up(&ctx->waitq);
2598 }
2599 break;
2600 }
2601 default:
2602 return -EINVAL;
2603 }
2604 return 0;
2605 }
2606
2607 static void cnic_ulp_init(struct cnic_dev *dev)
2608 {
2609 int i;
2610 struct cnic_local *cp = dev->cnic_priv;
2611
2612 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2613 struct cnic_ulp_ops *ulp_ops;
2614
2615 mutex_lock(&cnic_lock);
2616 ulp_ops = cnic_ulp_tbl[i];
2617 if (!ulp_ops || !ulp_ops->cnic_init) {
2618 mutex_unlock(&cnic_lock);
2619 continue;
2620 }
2621 ulp_get(ulp_ops);
2622 mutex_unlock(&cnic_lock);
2623
2624 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2625 ulp_ops->cnic_init(dev);
2626
2627 ulp_put(ulp_ops);
2628 }
2629 }
2630
2631 static void cnic_ulp_exit(struct cnic_dev *dev)
2632 {
2633 int i;
2634 struct cnic_local *cp = dev->cnic_priv;
2635
2636 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
2637 struct cnic_ulp_ops *ulp_ops;
2638
2639 mutex_lock(&cnic_lock);
2640 ulp_ops = cnic_ulp_tbl[i];
2641 if (!ulp_ops || !ulp_ops->cnic_exit) {
2642 mutex_unlock(&cnic_lock);
2643 continue;
2644 }
2645 ulp_get(ulp_ops);
2646 mutex_unlock(&cnic_lock);
2647
2648 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
2649 ulp_ops->cnic_exit(dev);
2650
2651 ulp_put(ulp_ops);
2652 }
2653 }
2654
2655 static int cnic_cm_offload_pg(struct cnic_sock *csk)
2656 {
2657 struct cnic_dev *dev = csk->dev;
2658 struct l4_kwq_offload_pg *l4kwqe;
2659 struct kwqe *wqes[1];
2660
2661 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
2662 memset(l4kwqe, 0, sizeof(*l4kwqe));
2663 wqes[0] = (struct kwqe *) l4kwqe;
2664
2665 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
2666 l4kwqe->flags =
2667 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
2668 l4kwqe->l2hdr_nbytes = ETH_HLEN;
2669
2670 l4kwqe->da0 = csk->ha[0];
2671 l4kwqe->da1 = csk->ha[1];
2672 l4kwqe->da2 = csk->ha[2];
2673 l4kwqe->da3 = csk->ha[3];
2674 l4kwqe->da4 = csk->ha[4];
2675 l4kwqe->da5 = csk->ha[5];
2676
2677 l4kwqe->sa0 = dev->mac_addr[0];
2678 l4kwqe->sa1 = dev->mac_addr[1];
2679 l4kwqe->sa2 = dev->mac_addr[2];
2680 l4kwqe->sa3 = dev->mac_addr[3];
2681 l4kwqe->sa4 = dev->mac_addr[4];
2682 l4kwqe->sa5 = dev->mac_addr[5];
2683
2684 l4kwqe->etype = ETH_P_IP;
2685 l4kwqe->ipid_start = DEF_IPID_START;
2686 l4kwqe->host_opaque = csk->l5_cid;
2687
2688 if (csk->vlan_id) {
2689 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
2690 l4kwqe->vlan_tag = csk->vlan_id;
2691 l4kwqe->l2hdr_nbytes += 4;
2692 }
2693
2694 return dev->submit_kwqes(dev, wqes, 1);
2695 }
2696
2697 static int cnic_cm_update_pg(struct cnic_sock *csk)
2698 {
2699 struct cnic_dev *dev = csk->dev;
2700 struct l4_kwq_update_pg *l4kwqe;
2701 struct kwqe *wqes[1];
2702
2703 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
2704 memset(l4kwqe, 0, sizeof(*l4kwqe));
2705 wqes[0] = (struct kwqe *) l4kwqe;
2706
2707 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
2708 l4kwqe->flags =
2709 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
2710 l4kwqe->pg_cid = csk->pg_cid;
2711
2712 l4kwqe->da0 = csk->ha[0];
2713 l4kwqe->da1 = csk->ha[1];
2714 l4kwqe->da2 = csk->ha[2];
2715 l4kwqe->da3 = csk->ha[3];
2716 l4kwqe->da4 = csk->ha[4];
2717 l4kwqe->da5 = csk->ha[5];
2718
2719 l4kwqe->pg_host_opaque = csk->l5_cid;
2720 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
2721
2722 return dev->submit_kwqes(dev, wqes, 1);
2723 }
2724
2725 static int cnic_cm_upload_pg(struct cnic_sock *csk)
2726 {
2727 struct cnic_dev *dev = csk->dev;
2728 struct l4_kwq_upload *l4kwqe;
2729 struct kwqe *wqes[1];
2730
2731 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
2732 memset(l4kwqe, 0, sizeof(*l4kwqe));
2733 wqes[0] = (struct kwqe *) l4kwqe;
2734
2735 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
2736 l4kwqe->flags =
2737 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
2738 l4kwqe->cid = csk->pg_cid;
2739
2740 return dev->submit_kwqes(dev, wqes, 1);
2741 }
2742
2743 static int cnic_cm_conn_req(struct cnic_sock *csk)
2744 {
2745 struct cnic_dev *dev = csk->dev;
2746 struct l4_kwq_connect_req1 *l4kwqe1;
2747 struct l4_kwq_connect_req2 *l4kwqe2;
2748 struct l4_kwq_connect_req3 *l4kwqe3;
2749 struct kwqe *wqes[3];
2750 u8 tcp_flags = 0;
2751 int num_wqes = 2;
2752
2753 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
2754 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
2755 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
2756 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
2757 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
2758 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
2759
2760 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
2761 l4kwqe3->flags =
2762 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
2763 l4kwqe3->ka_timeout = csk->ka_timeout;
2764 l4kwqe3->ka_interval = csk->ka_interval;
2765 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
2766 l4kwqe3->tos = csk->tos;
2767 l4kwqe3->ttl = csk->ttl;
2768 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
2769 l4kwqe3->pmtu = csk->mtu;
2770 l4kwqe3->rcv_buf = csk->rcv_buf;
2771 l4kwqe3->snd_buf = csk->snd_buf;
2772 l4kwqe3->seed = csk->seed;
2773
2774 wqes[0] = (struct kwqe *) l4kwqe1;
2775 if (test_bit(SK_F_IPV6, &csk->flags)) {
2776 wqes[1] = (struct kwqe *) l4kwqe2;
2777 wqes[2] = (struct kwqe *) l4kwqe3;
2778 num_wqes = 3;
2779
2780 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
2781 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
2782 l4kwqe2->flags =
2783 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
2784 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
2785 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
2786 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
2787 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
2788 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
2789 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
2790 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
2791 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
2792 sizeof(struct tcphdr);
2793 } else {
2794 wqes[1] = (struct kwqe *) l4kwqe3;
2795 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
2796 sizeof(struct tcphdr);
2797 }
2798
2799 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
2800 l4kwqe1->flags =
2801 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
2802 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
2803 l4kwqe1->cid = csk->cid;
2804 l4kwqe1->pg_cid = csk->pg_cid;
2805 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
2806 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
2807 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
2808 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
2809 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
2810 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
2811 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
2812 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
2813 if (csk->tcp_flags & SK_TCP_NAGLE)
2814 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
2815 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
2816 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
2817 if (csk->tcp_flags & SK_TCP_SACK)
2818 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
2819 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
2820 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
2821
2822 l4kwqe1->tcp_flags = tcp_flags;
2823
2824 return dev->submit_kwqes(dev, wqes, num_wqes);
2825 }
2826
2827 static int cnic_cm_close_req(struct cnic_sock *csk)
2828 {
2829 struct cnic_dev *dev = csk->dev;
2830 struct l4_kwq_close_req *l4kwqe;
2831 struct kwqe *wqes[1];
2832
2833 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
2834 memset(l4kwqe, 0, sizeof(*l4kwqe));
2835 wqes[0] = (struct kwqe *) l4kwqe;
2836
2837 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
2838 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
2839 l4kwqe->cid = csk->cid;
2840
2841 return dev->submit_kwqes(dev, wqes, 1);
2842 }
2843
2844 static int cnic_cm_abort_req(struct cnic_sock *csk)
2845 {
2846 struct cnic_dev *dev = csk->dev;
2847 struct l4_kwq_reset_req *l4kwqe;
2848 struct kwqe *wqes[1];
2849
2850 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
2851 memset(l4kwqe, 0, sizeof(*l4kwqe));
2852 wqes[0] = (struct kwqe *) l4kwqe;
2853
2854 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
2855 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
2856 l4kwqe->cid = csk->cid;
2857
2858 return dev->submit_kwqes(dev, wqes, 1);
2859 }
2860
2861 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
2862 u32 l5_cid, struct cnic_sock **csk, void *context)
2863 {
2864 struct cnic_local *cp = dev->cnic_priv;
2865 struct cnic_sock *csk1;
2866
2867 if (l5_cid >= MAX_CM_SK_TBL_SZ)
2868 return -EINVAL;
2869
2870 if (cp->ctx_tbl) {
2871 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2872
2873 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2874 return -EAGAIN;
2875 }
2876
2877 csk1 = &cp->csk_tbl[l5_cid];
2878 if (atomic_read(&csk1->ref_count))
2879 return -EAGAIN;
2880
2881 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
2882 return -EBUSY;
2883
2884 csk1->dev = dev;
2885 csk1->cid = cid;
2886 csk1->l5_cid = l5_cid;
2887 csk1->ulp_type = ulp_type;
2888 csk1->context = context;
2889
2890 csk1->ka_timeout = DEF_KA_TIMEOUT;
2891 csk1->ka_interval = DEF_KA_INTERVAL;
2892 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
2893 csk1->tos = DEF_TOS;
2894 csk1->ttl = DEF_TTL;
2895 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
2896 csk1->rcv_buf = DEF_RCV_BUF;
2897 csk1->snd_buf = DEF_SND_BUF;
2898 csk1->seed = DEF_SEED;
2899
2900 *csk = csk1;
2901 return 0;
2902 }
2903
2904 static void cnic_cm_cleanup(struct cnic_sock *csk)
2905 {
2906 if (csk->src_port) {
2907 struct cnic_dev *dev = csk->dev;
2908 struct cnic_local *cp = dev->cnic_priv;
2909
2910 cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
2911 csk->src_port = 0;
2912 }
2913 }
2914
2915 static void cnic_close_conn(struct cnic_sock *csk)
2916 {
2917 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
2918 cnic_cm_upload_pg(csk);
2919 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
2920 }
2921 cnic_cm_cleanup(csk);
2922 }
2923
2924 static int cnic_cm_destroy(struct cnic_sock *csk)
2925 {
2926 if (!cnic_in_use(csk))
2927 return -EINVAL;
2928
2929 csk_hold(csk);
2930 clear_bit(SK_F_INUSE, &csk->flags);
2931 smp_mb__after_clear_bit();
2932 while (atomic_read(&csk->ref_count) != 1)
2933 msleep(1);
2934 cnic_cm_cleanup(csk);
2935
2936 csk->flags = 0;
2937 csk_put(csk);
2938 return 0;
2939 }
2940
2941 static inline u16 cnic_get_vlan(struct net_device *dev,
2942 struct net_device **vlan_dev)
2943 {
2944 if (dev->priv_flags & IFF_802_1Q_VLAN) {
2945 *vlan_dev = vlan_dev_real_dev(dev);
2946 return vlan_dev_vlan_id(dev);
2947 }
2948 *vlan_dev = dev;
2949 return 0;
2950 }
2951
2952 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
2953 struct dst_entry **dst)
2954 {
2955 #if defined(CONFIG_INET)
2956 struct flowi fl;
2957 int err;
2958 struct rtable *rt;
2959
2960 memset(&fl, 0, sizeof(fl));
2961 fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
2962
2963 err = ip_route_output_key(&init_net, &rt, &fl);
2964 if (!err)
2965 *dst = &rt->dst;
2966 return err;
2967 #else
2968 return -ENETUNREACH;
2969 #endif
2970 }
2971
2972 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
2973 struct dst_entry **dst)
2974 {
2975 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
2976 struct flowi fl;
2977
2978 memset(&fl, 0, sizeof(fl));
2979 ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
2980 if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
2981 fl.oif = dst_addr->sin6_scope_id;
2982
2983 *dst = ip6_route_output(&init_net, NULL, &fl);
2984 if (*dst)
2985 return 0;
2986 #endif
2987
2988 return -ENETUNREACH;
2989 }
2990
2991 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
2992 int ulp_type)
2993 {
2994 struct cnic_dev *dev = NULL;
2995 struct dst_entry *dst;
2996 struct net_device *netdev = NULL;
2997 int err = -ENETUNREACH;
2998
2999 if (dst_addr->sin_family == AF_INET)
3000 err = cnic_get_v4_route(dst_addr, &dst);
3001 else if (dst_addr->sin_family == AF_INET6) {
3002 struct sockaddr_in6 *dst_addr6 =
3003 (struct sockaddr_in6 *) dst_addr;
3004
3005 err = cnic_get_v6_route(dst_addr6, &dst);
3006 } else
3007 return NULL;
3008
3009 if (err)
3010 return NULL;
3011
3012 if (!dst->dev)
3013 goto done;
3014
3015 cnic_get_vlan(dst->dev, &netdev);
3016
3017 dev = cnic_from_netdev(netdev);
3018
3019 done:
3020 dst_release(dst);
3021 if (dev)
3022 cnic_put(dev);
3023 return dev;
3024 }
3025
3026 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3027 {
3028 struct cnic_dev *dev = csk->dev;
3029 struct cnic_local *cp = dev->cnic_priv;
3030
3031 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
3032 }
3033
3034 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3035 {
3036 struct cnic_dev *dev = csk->dev;
3037 struct cnic_local *cp = dev->cnic_priv;
3038 int is_v6, rc = 0;
3039 struct dst_entry *dst = NULL;
3040 struct net_device *realdev;
3041 __be16 local_port;
3042 u32 port_id;
3043
3044 if (saddr->local.v6.sin6_family == AF_INET6 &&
3045 saddr->remote.v6.sin6_family == AF_INET6)
3046 is_v6 = 1;
3047 else if (saddr->local.v4.sin_family == AF_INET &&
3048 saddr->remote.v4.sin_family == AF_INET)
3049 is_v6 = 0;
3050 else
3051 return -EINVAL;
3052
3053 clear_bit(SK_F_IPV6, &csk->flags);
3054
3055 if (is_v6) {
3056 set_bit(SK_F_IPV6, &csk->flags);
3057 cnic_get_v6_route(&saddr->remote.v6, &dst);
3058
3059 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
3060 sizeof(struct in6_addr));
3061 csk->dst_port = saddr->remote.v6.sin6_port;
3062 local_port = saddr->local.v6.sin6_port;
3063
3064 } else {
3065 cnic_get_v4_route(&saddr->remote.v4, &dst);
3066
3067 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
3068 csk->dst_port = saddr->remote.v4.sin_port;
3069 local_port = saddr->local.v4.sin_port;
3070 }
3071
3072 csk->vlan_id = 0;
3073 csk->mtu = dev->netdev->mtu;
3074 if (dst && dst->dev) {
3075 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3076 if (realdev == dev->netdev) {
3077 csk->vlan_id = vlan;
3078 csk->mtu = dst_mtu(dst);
3079 }
3080 }
3081
3082 port_id = be16_to_cpu(local_port);
3083 if (port_id >= CNIC_LOCAL_PORT_MIN &&
3084 port_id < CNIC_LOCAL_PORT_MAX) {
3085 if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
3086 port_id = 0;
3087 } else
3088 port_id = 0;
3089
3090 if (!port_id) {
3091 port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
3092 if (port_id == -1) {
3093 rc = -ENOMEM;
3094 goto err_out;
3095 }
3096 local_port = cpu_to_be16(port_id);
3097 }
3098 csk->src_port = local_port;
3099
3100 err_out:
3101 dst_release(dst);
3102 return rc;
3103 }
3104
3105 static void cnic_init_csk_state(struct cnic_sock *csk)
3106 {
3107 csk->state = 0;
3108 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3109 clear_bit(SK_F_CLOSING, &csk->flags);
3110 }
3111
3112 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3113 {
3114 int err = 0;
3115
3116 if (!cnic_in_use(csk))
3117 return -EINVAL;
3118
3119 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3120 return -EINVAL;
3121
3122 cnic_init_csk_state(csk);
3123
3124 err = cnic_get_route(csk, saddr);
3125 if (err)
3126 goto err_out;
3127
3128 err = cnic_resolve_addr(csk, saddr);
3129 if (!err)
3130 return 0;
3131
3132 err_out:
3133 clear_bit(SK_F_CONNECT_START, &csk->flags);
3134 return err;
3135 }
3136
3137 static int cnic_cm_abort(struct cnic_sock *csk)
3138 {
3139 struct cnic_local *cp = csk->dev->cnic_priv;
3140 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3141
3142 if (!cnic_in_use(csk))
3143 return -EINVAL;
3144
3145 if (cnic_abort_prep(csk))
3146 return cnic_cm_abort_req(csk);
3147
3148 /* Getting here means that we haven't started connect, or
3149 * connect was not successful.
3150 */
3151
3152 cp->close_conn(csk, opcode);
3153 if (csk->state != opcode)
3154 return -EALREADY;
3155
3156 return 0;
3157 }
3158
3159 static int cnic_cm_close(struct cnic_sock *csk)
3160 {
3161 if (!cnic_in_use(csk))
3162 return -EINVAL;
3163
3164 if (cnic_close_prep(csk)) {
3165 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3166 return cnic_cm_close_req(csk);
3167 } else {
3168 return -EALREADY;
3169 }
3170 return 0;
3171 }
3172
3173 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3174 u8 opcode)
3175 {
3176 struct cnic_ulp_ops *ulp_ops;
3177 int ulp_type = csk->ulp_type;
3178
3179 rcu_read_lock();
3180 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3181 if (ulp_ops) {
3182 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3183 ulp_ops->cm_connect_complete(csk);
3184 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3185 ulp_ops->cm_close_complete(csk);
3186 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3187 ulp_ops->cm_remote_abort(csk);
3188 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3189 ulp_ops->cm_abort_complete(csk);
3190 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3191 ulp_ops->cm_remote_close(csk);
3192 }
3193 rcu_read_unlock();
3194 }
3195
3196 static int cnic_cm_set_pg(struct cnic_sock *csk)
3197 {
3198 if (cnic_offld_prep(csk)) {
3199 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3200 cnic_cm_update_pg(csk);
3201 else
3202 cnic_cm_offload_pg(csk);
3203 }
3204 return 0;
3205 }
3206
3207 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3208 {
3209 struct cnic_local *cp = dev->cnic_priv;
3210 u32 l5_cid = kcqe->pg_host_opaque;
3211 u8 opcode = kcqe->op_code;
3212 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3213
3214 csk_hold(csk);
3215 if (!cnic_in_use(csk))
3216 goto done;
3217
3218 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3219 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3220 goto done;
3221 }
3222 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3223 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3224 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3225 cnic_cm_upcall(cp, csk,
3226 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3227 goto done;
3228 }
3229
3230 csk->pg_cid = kcqe->pg_cid;
3231 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3232 cnic_cm_conn_req(csk);
3233
3234 done:
3235 csk_put(csk);
3236 }
3237
3238 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3239 {
3240 struct cnic_local *cp = dev->cnic_priv;
3241 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3242 u8 opcode = l4kcqe->op_code;
3243 u32 l5_cid;
3244 struct cnic_sock *csk;
3245
3246 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3247 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3248 cnic_cm_process_offld_pg(dev, l4kcqe);
3249 return;
3250 }
3251
3252 l5_cid = l4kcqe->conn_id;
3253 if (opcode & 0x80)
3254 l5_cid = l4kcqe->cid;
3255 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3256 return;
3257
3258 csk = &cp->csk_tbl[l5_cid];
3259 csk_hold(csk);
3260
3261 if (!cnic_in_use(csk)) {
3262 csk_put(csk);
3263 return;
3264 }
3265
3266 switch (opcode) {
3267 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3268 if (l4kcqe->status != 0) {
3269 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3270 cnic_cm_upcall(cp, csk,
3271 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3272 }
3273 break;
3274 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3275 if (l4kcqe->status == 0)
3276 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3277
3278 smp_mb__before_clear_bit();
3279 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3280 cnic_cm_upcall(cp, csk, opcode);
3281 break;
3282
3283 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3284 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3285 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3286 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3287 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3288 cp->close_conn(csk, opcode);
3289 break;
3290
3291 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3292 cnic_cm_upcall(cp, csk, opcode);
3293 break;
3294 }
3295 csk_put(csk);
3296 }
3297
3298 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3299 {
3300 struct cnic_dev *dev = data;
3301 int i;
3302
3303 for (i = 0; i < num; i++)
3304 cnic_cm_process_kcqe(dev, kcqe[i]);
3305 }
3306
3307 static struct cnic_ulp_ops cm_ulp_ops = {
3308 .indicate_kcqes = cnic_cm_indicate_kcqe,
3309 };
3310
3311 static void cnic_cm_free_mem(struct cnic_dev *dev)
3312 {
3313 struct cnic_local *cp = dev->cnic_priv;
3314
3315 kfree(cp->csk_tbl);
3316 cp->csk_tbl = NULL;
3317 cnic_free_id_tbl(&cp->csk_port_tbl);
3318 }
3319
3320 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3321 {
3322 struct cnic_local *cp = dev->cnic_priv;
3323
3324 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3325 GFP_KERNEL);
3326 if (!cp->csk_tbl)
3327 return -ENOMEM;
3328
3329 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3330 CNIC_LOCAL_PORT_MIN)) {
3331 cnic_cm_free_mem(dev);
3332 return -ENOMEM;
3333 }
3334 return 0;
3335 }
3336
3337 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3338 {
3339 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
3340 /* Unsolicited RESET_COMP or RESET_RECEIVED */
3341 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3342 csk->state = opcode;
3343 }
3344
3345 /* 1. If event opcode matches the expected event in csk->state
3346 * 2. If the expected event is CLOSE_COMP, we accept any event
3347 * 3. If the expected event is 0, meaning the connection was never
3348 * never established, we accept the opcode from cm_abort.
3349 */
3350 if (opcode == csk->state || csk->state == 0 ||
3351 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
3352 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3353 if (csk->state == 0)
3354 csk->state = opcode;
3355 return 1;
3356 }
3357 }
3358 return 0;
3359 }
3360
3361 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3362 {
3363 struct cnic_dev *dev = csk->dev;
3364 struct cnic_local *cp = dev->cnic_priv;
3365
3366 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
3367 cnic_cm_upcall(cp, csk, opcode);
3368 return;
3369 }
3370
3371 clear_bit(SK_F_CONNECT_START, &csk->flags);
3372 cnic_close_conn(csk);
3373 csk->state = opcode;
3374 cnic_cm_upcall(cp, csk, opcode);
3375 }
3376
3377 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3378 {
3379 }
3380
3381 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3382 {
3383 u32 seed;
3384
3385 get_random_bytes(&seed, 4);
3386 cnic_ctx_wr(dev, 45, 0, seed);
3387 return 0;
3388 }
3389
3390 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3391 {
3392 struct cnic_dev *dev = csk->dev;
3393 struct cnic_local *cp = dev->cnic_priv;
3394 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3395 union l5cm_specific_data l5_data;
3396 u32 cmd = 0;
3397 int close_complete = 0;
3398
3399 switch (opcode) {
3400 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3401 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3402 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3403 if (cnic_ready_to_close(csk, opcode)) {
3404 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3405 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3406 else
3407 close_complete = 1;
3408 }
3409 break;
3410 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3411 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3412 break;
3413 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3414 close_complete = 1;
3415 break;
3416 }
3417 if (cmd) {
3418 memset(&l5_data, 0, sizeof(l5_data));
3419
3420 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3421 &l5_data);
3422 } else if (close_complete) {
3423 ctx->timestamp = jiffies;
3424 cnic_close_conn(csk);
3425 cnic_cm_upcall(cp, csk, csk->state);
3426 }
3427 }
3428
3429 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3430 {
3431 struct cnic_local *cp = dev->cnic_priv;
3432 int i;
3433
3434 if (!cp->ctx_tbl)
3435 return;
3436
3437 if (!netif_running(dev->netdev))
3438 return;
3439
3440 for (i = 0; i < cp->max_cid_space; i++) {
3441 struct cnic_context *ctx = &cp->ctx_tbl[i];
3442
3443 while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3444 msleep(10);
3445
3446 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3447 netdev_warn(dev->netdev, "CID %x not deleted\n",
3448 ctx->cid);
3449 }
3450
3451 cancel_delayed_work(&cp->delete_task);
3452 flush_workqueue(cnic_wq);
3453
3454 if (atomic_read(&cp->iscsi_conn) != 0)
3455 netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
3456 atomic_read(&cp->iscsi_conn));
3457 }
3458
3459 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3460 {
3461 struct cnic_local *cp = dev->cnic_priv;
3462 u32 pfid = cp->pfid;
3463 u32 port = CNIC_PORT(cp);
3464
3465 cnic_init_bnx2x_mac(dev);
3466 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3467
3468 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3469 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
3470
3471 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3472 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
3473 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3474 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
3475 DEF_MAX_DA_COUNT);
3476
3477 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3478 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
3479 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3480 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
3481 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3482 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
3483 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3484 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
3485
3486 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
3487 DEF_MAX_CWND);
3488 return 0;
3489 }
3490
3491 static void cnic_delete_task(struct work_struct *work)
3492 {
3493 struct cnic_local *cp;
3494 struct cnic_dev *dev;
3495 u32 i;
3496 int need_resched = 0;
3497
3498 cp = container_of(work, struct cnic_local, delete_task.work);
3499 dev = cp->dev;
3500
3501 for (i = 0; i < cp->max_cid_space; i++) {
3502 struct cnic_context *ctx = &cp->ctx_tbl[i];
3503
3504 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
3505 !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3506 continue;
3507
3508 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
3509 need_resched = 1;
3510 continue;
3511 }
3512
3513 if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3514 continue;
3515
3516 cnic_bnx2x_destroy_ramrod(dev, i);
3517
3518 cnic_free_bnx2x_conn_resc(dev, i);
3519 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
3520 atomic_dec(&cp->iscsi_conn);
3521
3522 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
3523 }
3524
3525 if (need_resched)
3526 queue_delayed_work(cnic_wq, &cp->delete_task,
3527 msecs_to_jiffies(10));
3528
3529 }
3530
3531 static int cnic_cm_open(struct cnic_dev *dev)
3532 {
3533 struct cnic_local *cp = dev->cnic_priv;
3534 int err;
3535
3536 err = cnic_cm_alloc_mem(dev);
3537 if (err)
3538 return err;
3539
3540 err = cp->start_cm(dev);
3541
3542 if (err)
3543 goto err_out;
3544
3545 INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
3546
3547 dev->cm_create = cnic_cm_create;
3548 dev->cm_destroy = cnic_cm_destroy;
3549 dev->cm_connect = cnic_cm_connect;
3550 dev->cm_abort = cnic_cm_abort;
3551 dev->cm_close = cnic_cm_close;
3552 dev->cm_select_dev = cnic_cm_select_dev;
3553
3554 cp->ulp_handle[CNIC_ULP_L4] = dev;
3555 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
3556 return 0;
3557
3558 err_out:
3559 cnic_cm_free_mem(dev);
3560 return err;
3561 }
3562
3563 static int cnic_cm_shutdown(struct cnic_dev *dev)
3564 {
3565 struct cnic_local *cp = dev->cnic_priv;
3566 int i;
3567
3568 cp->stop_cm(dev);
3569
3570 if (!cp->csk_tbl)
3571 return 0;
3572
3573 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
3574 struct cnic_sock *csk = &cp->csk_tbl[i];
3575
3576 clear_bit(SK_F_INUSE, &csk->flags);
3577 cnic_cm_cleanup(csk);
3578 }
3579 cnic_cm_free_mem(dev);
3580
3581 return 0;
3582 }
3583
3584 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
3585 {
3586 u32 cid_addr;
3587 int i;
3588
3589 cid_addr = GET_CID_ADDR(cid);
3590
3591 for (i = 0; i < CTX_SIZE; i += 4)
3592 cnic_ctx_wr(dev, cid_addr, i, 0);
3593 }
3594
3595 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
3596 {
3597 struct cnic_local *cp = dev->cnic_priv;
3598 int ret = 0, i;
3599 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
3600
3601 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3602 return 0;
3603
3604 for (i = 0; i < cp->ctx_blks; i++) {
3605 int j;
3606 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
3607 u32 val;
3608
3609 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
3610
3611 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
3612 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
3613 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
3614 (u64) cp->ctx_arr[i].mapping >> 32);
3615 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
3616 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3617 for (j = 0; j < 10; j++) {
3618
3619 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
3620 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
3621 break;
3622 udelay(5);
3623 }
3624 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
3625 ret = -EBUSY;
3626 break;
3627 }
3628 }
3629 return ret;
3630 }
3631
3632 static void cnic_free_irq(struct cnic_dev *dev)
3633 {
3634 struct cnic_local *cp = dev->cnic_priv;
3635 struct cnic_eth_dev *ethdev = cp->ethdev;
3636
3637 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3638 cp->disable_int_sync(dev);
3639 tasklet_kill(&cp->cnic_irq_task);
3640 free_irq(ethdev->irq_arr[0].vector, dev);
3641 }
3642 }
3643
3644 static int cnic_request_irq(struct cnic_dev *dev)
3645 {
3646 struct cnic_local *cp = dev->cnic_priv;
3647 struct cnic_eth_dev *ethdev = cp->ethdev;
3648 int err;
3649
3650 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
3651 if (err)
3652 tasklet_disable(&cp->cnic_irq_task);
3653
3654 return err;
3655 }
3656
3657 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
3658 {
3659 struct cnic_local *cp = dev->cnic_priv;
3660 struct cnic_eth_dev *ethdev = cp->ethdev;
3661
3662 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3663 int err, i = 0;
3664 int sblk_num = cp->status_blk_num;
3665 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
3666 BNX2_HC_SB_CONFIG_1;
3667
3668 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
3669
3670 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
3671 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
3672 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
3673
3674 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
3675 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
3676 (unsigned long) dev);
3677 err = cnic_request_irq(dev);
3678 if (err)
3679 return err;
3680
3681 while (cp->status_blk.bnx2->status_completion_producer_index &&
3682 i < 10) {
3683 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
3684 1 << (11 + sblk_num));
3685 udelay(10);
3686 i++;
3687 barrier();
3688 }
3689 if (cp->status_blk.bnx2->status_completion_producer_index) {
3690 cnic_free_irq(dev);
3691 goto failed;
3692 }
3693
3694 } else {
3695 struct status_block *sblk = cp->status_blk.gen;
3696 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
3697 int i = 0;
3698
3699 while (sblk->status_completion_producer_index && i < 10) {
3700 CNIC_WR(dev, BNX2_HC_COMMAND,
3701 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3702 udelay(10);
3703 i++;
3704 barrier();
3705 }
3706 if (sblk->status_completion_producer_index)
3707 goto failed;
3708
3709 }
3710 return 0;
3711
3712 failed:
3713 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
3714 return -EBUSY;
3715 }
3716
3717 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
3718 {
3719 struct cnic_local *cp = dev->cnic_priv;
3720 struct cnic_eth_dev *ethdev = cp->ethdev;
3721
3722 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3723 return;
3724
3725 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3726 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
3727 }
3728
3729 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
3730 {
3731 struct cnic_local *cp = dev->cnic_priv;
3732 struct cnic_eth_dev *ethdev = cp->ethdev;
3733
3734 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3735 return;
3736
3737 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3738 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3739 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
3740 synchronize_irq(ethdev->irq_arr[0].vector);
3741 }
3742
3743 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
3744 {
3745 struct cnic_local *cp = dev->cnic_priv;
3746 struct cnic_eth_dev *ethdev = cp->ethdev;
3747 struct cnic_uio_dev *udev = cp->udev;
3748 u32 cid_addr, tx_cid, sb_id;
3749 u32 val, offset0, offset1, offset2, offset3;
3750 int i;
3751 struct tx_bd *txbd;
3752 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
3753 struct status_block *s_blk = cp->status_blk.gen;
3754
3755 sb_id = cp->status_blk_num;
3756 tx_cid = 20;
3757 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
3758 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3759 struct status_block_msix *sblk = cp->status_blk.bnx2;
3760
3761 tx_cid = TX_TSS_CID + sb_id - 1;
3762 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
3763 (TX_TSS_CID << 7));
3764 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
3765 }
3766 cp->tx_cons = *cp->tx_cons_ptr;
3767
3768 cid_addr = GET_CID_ADDR(tx_cid);
3769 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
3770 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
3771
3772 for (i = 0; i < PHY_CTX_SIZE; i += 4)
3773 cnic_ctx_wr(dev, cid_addr2, i, 0);
3774
3775 offset0 = BNX2_L2CTX_TYPE_XI;
3776 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
3777 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
3778 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
3779 } else {
3780 cnic_init_context(dev, tx_cid);
3781 cnic_init_context(dev, tx_cid + 1);
3782
3783 offset0 = BNX2_L2CTX_TYPE;
3784 offset1 = BNX2_L2CTX_CMD_TYPE;
3785 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
3786 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
3787 }
3788 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
3789 cnic_ctx_wr(dev, cid_addr, offset0, val);
3790
3791 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3792 cnic_ctx_wr(dev, cid_addr, offset1, val);
3793
3794 txbd = (struct tx_bd *) udev->l2_ring;
3795
3796 buf_map = udev->l2_buf_map;
3797 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
3798 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
3799 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3800 }
3801 val = (u64) ring_map >> 32;
3802 cnic_ctx_wr(dev, cid_addr, offset2, val);
3803 txbd->tx_bd_haddr_hi = val;
3804
3805 val = (u64) ring_map & 0xffffffff;
3806 cnic_ctx_wr(dev, cid_addr, offset3, val);
3807 txbd->tx_bd_haddr_lo = val;
3808 }
3809
3810 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
3811 {
3812 struct cnic_local *cp = dev->cnic_priv;
3813 struct cnic_eth_dev *ethdev = cp->ethdev;
3814 struct cnic_uio_dev *udev = cp->udev;
3815 u32 cid_addr, sb_id, val, coal_reg, coal_val;
3816 int i;
3817 struct rx_bd *rxbd;
3818 struct status_block *s_blk = cp->status_blk.gen;
3819 dma_addr_t ring_map = udev->l2_ring_map;
3820
3821 sb_id = cp->status_blk_num;
3822 cnic_init_context(dev, 2);
3823 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
3824 coal_reg = BNX2_HC_COMMAND;
3825 coal_val = CNIC_RD(dev, coal_reg);
3826 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
3827 struct status_block_msix *sblk = cp->status_blk.bnx2;
3828
3829 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
3830 coal_reg = BNX2_HC_COALESCE_NOW;
3831 coal_val = 1 << (11 + sb_id);
3832 }
3833 i = 0;
3834 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
3835 CNIC_WR(dev, coal_reg, coal_val);
3836 udelay(10);
3837 i++;
3838 barrier();
3839 }
3840 cp->rx_cons = *cp->rx_cons_ptr;
3841
3842 cid_addr = GET_CID_ADDR(2);
3843 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3844 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3845 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
3846
3847 if (sb_id == 0)
3848 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
3849 else
3850 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
3851 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
3852
3853 rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
3854 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3855 dma_addr_t buf_map;
3856 int n = (i % cp->l2_rx_ring_size) + 1;
3857
3858 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
3859 rxbd->rx_bd_len = cp->l2_single_buf_size;
3860 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3861 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
3862 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
3863 }
3864 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
3865 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
3866 rxbd->rx_bd_haddr_hi = val;
3867
3868 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
3869 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
3870 rxbd->rx_bd_haddr_lo = val;
3871
3872 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
3873 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
3874 }
3875
3876 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
3877 {
3878 struct kwqe *wqes[1], l2kwqe;
3879
3880 memset(&l2kwqe, 0, sizeof(l2kwqe));
3881 wqes[0] = &l2kwqe;
3882 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
3883 (L2_KWQE_OPCODE_VALUE_FLUSH <<
3884 KWQE_OPCODE_SHIFT) | 2;
3885 dev->submit_kwqes(dev, wqes, 1);
3886 }
3887
3888 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
3889 {
3890 struct cnic_local *cp = dev->cnic_priv;
3891 u32 val;
3892
3893 val = cp->func << 2;
3894
3895 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
3896
3897 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3898 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
3899 dev->mac_addr[0] = (u8) (val >> 8);
3900 dev->mac_addr[1] = (u8) val;
3901
3902 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
3903
3904 val = cnic_reg_rd_ind(dev, cp->shmem_base +
3905 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
3906 dev->mac_addr[2] = (u8) (val >> 24);
3907 dev->mac_addr[3] = (u8) (val >> 16);
3908 dev->mac_addr[4] = (u8) (val >> 8);
3909 dev->mac_addr[5] = (u8) val;
3910
3911 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
3912
3913 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
3914 if (CHIP_NUM(cp) != CHIP_NUM_5709)
3915 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
3916
3917 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
3918 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
3919 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
3920 }
3921
3922 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
3923 {
3924 struct cnic_local *cp = dev->cnic_priv;
3925 struct cnic_eth_dev *ethdev = cp->ethdev;
3926 struct status_block *sblk = cp->status_blk.gen;
3927 u32 val, kcq_cid_addr, kwq_cid_addr;
3928 int err;
3929
3930 cnic_set_bnx2_mac(dev);
3931
3932 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
3933 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3934 if (BCM_PAGE_BITS > 12)
3935 val |= (12 - 8) << 4;
3936 else
3937 val |= (BCM_PAGE_BITS - 8) << 4;
3938
3939 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
3940
3941 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
3942 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
3943 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
3944
3945 err = cnic_setup_5709_context(dev, 1);
3946 if (err)
3947 return err;
3948
3949 cnic_init_context(dev, KWQ_CID);
3950 cnic_init_context(dev, KCQ_CID);
3951
3952 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
3953 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
3954
3955 cp->max_kwq_idx = MAX_KWQ_IDX;
3956 cp->kwq_prod_idx = 0;
3957 cp->kwq_con_idx = 0;
3958 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
3959
3960 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
3961 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
3962 else
3963 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
3964
3965 /* Initialize the kernel work queue context. */
3966 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3967 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3968 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
3969
3970 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
3971 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3972
3973 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
3974 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
3975
3976 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
3977 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
3978
3979 val = (u32) cp->kwq_info.pgtbl_map;
3980 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
3981
3982 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
3983 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
3984
3985 cp->kcq1.sw_prod_idx = 0;
3986 cp->kcq1.hw_prod_idx_ptr =
3987 (u16 *) &sblk->status_completion_producer_index;
3988
3989 cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
3990
3991 /* Initialize the kernel complete queue context. */
3992 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
3993 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
3994 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
3995
3996 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
3997 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
3998
3999 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
4000 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4001
4002 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
4003 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4004
4005 val = (u32) cp->kcq1.dma.pgtbl_map;
4006 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4007
4008 cp->int_num = 0;
4009 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4010 struct status_block_msix *msblk = cp->status_blk.bnx2;
4011 u32 sb_id = cp->status_blk_num;
4012 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
4013
4014 cp->kcq1.hw_prod_idx_ptr =
4015 (u16 *) &msblk->status_completion_producer_index;
4016 cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
4017 cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
4018 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
4019 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4020 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4021 }
4022
4023 /* Enable Commnad Scheduler notification when we write to the
4024 * host producer index of the kernel contexts. */
4025 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
4026
4027 /* Enable Command Scheduler notification when we write to either
4028 * the Send Queue or Receive Queue producer indexes of the kernel
4029 * bypass contexts. */
4030 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
4031 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
4032
4033 /* Notify COM when the driver post an application buffer. */
4034 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
4035
4036 /* Set the CP and COM doorbells. These two processors polls the
4037 * doorbell for a non zero value before running. This must be done
4038 * after setting up the kernel queue contexts. */
4039 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
4040 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
4041
4042 cnic_init_bnx2_tx_ring(dev);
4043 cnic_init_bnx2_rx_ring(dev);
4044
4045 err = cnic_init_bnx2_irq(dev);
4046 if (err) {
4047 netdev_err(dev->netdev, "cnic_init_irq failed\n");
4048 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4049 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4050 return err;
4051 }
4052
4053 return 0;
4054 }
4055
4056 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
4057 {
4058 struct cnic_local *cp = dev->cnic_priv;
4059 struct cnic_eth_dev *ethdev = cp->ethdev;
4060 u32 start_offset = ethdev->ctx_tbl_offset;
4061 int i;
4062
4063 for (i = 0; i < cp->ctx_blks; i++) {
4064 struct cnic_ctx *ctx = &cp->ctx_arr[i];
4065 dma_addr_t map = ctx->mapping;
4066
4067 if (cp->ctx_align) {
4068 unsigned long mask = cp->ctx_align - 1;
4069
4070 map = (map + mask) & ~mask;
4071 }
4072
4073 cnic_ctx_tbl_wr(dev, start_offset + i, map);
4074 }
4075 }
4076
4077 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4078 {
4079 struct cnic_local *cp = dev->cnic_priv;
4080 struct cnic_eth_dev *ethdev = cp->ethdev;
4081 int err = 0;
4082
4083 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
4084 (unsigned long) dev);
4085 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4086 err = cnic_request_irq(dev);
4087
4088 return err;
4089 }
4090
4091 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4092 u16 sb_id, u8 sb_index,
4093 u8 disable)
4094 {
4095
4096 u32 addr = BAR_CSTRORM_INTMEM +
4097 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4098 offsetof(struct hc_status_block_data_e1x, index_data) +
4099 sizeof(struct hc_index_data)*sb_index +
4100 offsetof(struct hc_index_data, flags);
4101 u16 flags = CNIC_RD16(dev, addr);
4102 /* clear and set */
4103 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4104 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4105 HC_INDEX_DATA_HC_ENABLED);
4106 CNIC_WR16(dev, addr, flags);
4107 }
4108
4109 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4110 {
4111 struct cnic_local *cp = dev->cnic_priv;
4112 u8 sb_id = cp->status_blk_num;
4113
4114 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4115 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4116 offsetof(struct hc_status_block_data_e1x, index_data) +
4117 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4118 offsetof(struct hc_index_data, timeout), 64 / 12);
4119 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4120 }
4121
4122 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4123 {
4124 }
4125
4126 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4127 struct client_init_ramrod_data *data)
4128 {
4129 struct cnic_local *cp = dev->cnic_priv;
4130 struct cnic_uio_dev *udev = cp->udev;
4131 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4132 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4133 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4134 int port = CNIC_PORT(cp);
4135 int i;
4136 u32 cli = cp->ethdev->iscsi_l2_client_id;
4137 u32 val;
4138
4139 memset(txbd, 0, BCM_PAGE_SIZE);
4140
4141 buf_map = udev->l2_buf_map;
4142 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4143 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4144 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4145
4146 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4147 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4148 reg_bd->addr_hi = start_bd->addr_hi;
4149 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4150 start_bd->nbytes = cpu_to_le16(0x10);
4151 start_bd->nbd = cpu_to_le16(3);
4152 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4153 start_bd->general_data = (UNICAST_ADDRESS <<
4154 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
4155 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4156
4157 }
4158
4159 val = (u64) ring_map >> 32;
4160 txbd->next_bd.addr_hi = cpu_to_le32(val);
4161
4162 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4163
4164 val = (u64) ring_map & 0xffffffff;
4165 txbd->next_bd.addr_lo = cpu_to_le32(val);
4166
4167 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4168
4169 /* Other ramrod params */
4170 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4171 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4172
4173 /* reset xstorm per client statistics */
4174 if (cli < MAX_STAT_COUNTER_ID) {
4175 val = BAR_XSTRORM_INTMEM +
4176 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4177 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
4178 CNIC_WR(dev, val + i * 4, 0);
4179 }
4180
4181 cp->tx_cons_ptr =
4182 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4183 }
4184
4185 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4186 struct client_init_ramrod_data *data)
4187 {
4188 struct cnic_local *cp = dev->cnic_priv;
4189 struct cnic_uio_dev *udev = cp->udev;
4190 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4191 BCM_PAGE_SIZE);
4192 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4193 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
4194 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4195 int i;
4196 int port = CNIC_PORT(cp);
4197 u32 cli = cp->ethdev->iscsi_l2_client_id;
4198 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4199 u32 val;
4200 dma_addr_t ring_map = udev->l2_ring_map;
4201
4202 /* General data */
4203 data->general.client_id = cli;
4204 data->general.statistics_en_flg = 1;
4205 data->general.statistics_counter_id = cli;
4206 data->general.activate_flg = 1;
4207 data->general.sp_client_id = cli;
4208
4209 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
4210 dma_addr_t buf_map;
4211 int n = (i % cp->l2_rx_ring_size) + 1;
4212
4213 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4214 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4215 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4216 }
4217
4218 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4219 rxbd->addr_hi = cpu_to_le32(val);
4220 data->rx.bd_page_base.hi = cpu_to_le32(val);
4221
4222 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4223 rxbd->addr_lo = cpu_to_le32(val);
4224 data->rx.bd_page_base.lo = cpu_to_le32(val);
4225
4226 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
4227 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
4228 rxcqe->addr_hi = cpu_to_le32(val);
4229 data->rx.cqe_page_base.hi = cpu_to_le32(val);
4230
4231 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
4232 rxcqe->addr_lo = cpu_to_le32(val);
4233 data->rx.cqe_page_base.lo = cpu_to_le32(val);
4234
4235 /* Other ramrod params */
4236 data->rx.client_qzone_id = cl_qzone_id;
4237 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
4238 data->rx.status_block_id = BNX2X_DEF_SB_ID;
4239
4240 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
4241 data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
4242
4243 data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4244 data->rx.outer_vlan_removal_enable_flg = 1;
4245
4246 /* reset tstorm and ustorm per client statistics */
4247 if (cli < MAX_STAT_COUNTER_ID) {
4248 val = BAR_TSTRORM_INTMEM +
4249 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4250 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
4251 CNIC_WR(dev, val + i * 4, 0);
4252
4253 val = BAR_USTRORM_INTMEM +
4254 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4255 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4256 CNIC_WR(dev, val + i * 4, 0);
4257 }
4258
4259 cp->rx_cons_ptr =
4260 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
4261 cp->rx_cons = *cp->rx_cons_ptr;
4262 }
4263
4264 static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr,
4265 u32 lower_addr)
4266 {
4267 u32 val;
4268 u8 mac[6];
4269
4270 val = CNIC_RD(dev, upper_addr);
4271
4272 mac[0] = (u8) (val >> 8);
4273 mac[1] = (u8) val;
4274
4275 val = CNIC_RD(dev, lower_addr);
4276
4277 mac[2] = (u8) (val >> 24);
4278 mac[3] = (u8) (val >> 16);
4279 mac[4] = (u8) (val >> 8);
4280 mac[5] = (u8) val;
4281
4282 if (is_valid_ether_addr(mac)) {
4283 memcpy(dev->mac_addr, mac, 6);
4284 return 0;
4285 } else {
4286 return -EINVAL;
4287 }
4288 }
4289
4290 static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4291 {
4292 struct cnic_local *cp = dev->cnic_priv;
4293 u32 base, base2, addr, addr1, val;
4294 int port = CNIC_PORT(cp);
4295
4296 dev->max_iscsi_conn = 0;
4297 base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
4298 if (base == 0)
4299 return;
4300
4301 base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
4302 MISC_REG_GENERIC_CR_0));
4303 addr = BNX2X_SHMEM_ADDR(base,
4304 dev_info.port_hw_config[port].iscsi_mac_upper);
4305
4306 addr1 = BNX2X_SHMEM_ADDR(base,
4307 dev_info.port_hw_config[port].iscsi_mac_lower);
4308
4309 cnic_read_bnx2x_iscsi_mac(dev, addr, addr1);
4310
4311 addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
4312 val = CNIC_RD(dev, addr);
4313
4314 if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
4315 u16 val16;
4316
4317 addr = BNX2X_SHMEM_ADDR(base,
4318 drv_lic_key[port].max_iscsi_init_conn);
4319 val16 = CNIC_RD16(dev, addr);
4320
4321 if (val16)
4322 val16 ^= 0x1e1e;
4323 dev->max_iscsi_conn = val16;
4324 }
4325 if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
4326 int func = CNIC_FUNC(cp);
4327 u32 mf_cfg_addr;
4328
4329 if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
4330 mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
4331 mf_cfg_addr));
4332 else
4333 mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
4334
4335 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4336 /* Must determine if the MF is SD vs SI mode */
4337 addr = BNX2X_SHMEM_ADDR(base,
4338 dev_info.shared_feature_config.config);
4339 val = CNIC_RD(dev, addr);
4340 if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) ==
4341 SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) {
4342 int rc;
4343
4344 /* MULTI_FUNCTION_SI mode */
4345 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4346 func_ext_config[func].func_cfg);
4347 val = CNIC_RD(dev, addr);
4348 if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
4349 dev->max_iscsi_conn = 0;
4350
4351 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4352 func_ext_config[func].
4353 iscsi_mac_addr_upper);
4354 addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4355 func_ext_config[func].
4356 iscsi_mac_addr_lower);
4357 rc = cnic_read_bnx2x_iscsi_mac(dev, addr,
4358 addr1);
4359 if (rc && func > 1)
4360 dev->max_iscsi_conn = 0;
4361
4362 return;
4363 }
4364 }
4365
4366 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4367 func_mf_config[func].e1hov_tag);
4368
4369 val = CNIC_RD(dev, addr);
4370 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
4371 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
4372 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4373 func_mf_config[func].config);
4374 val = CNIC_RD(dev, addr);
4375 val &= FUNC_MF_CFG_PROTOCOL_MASK;
4376 if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
4377 dev->max_iscsi_conn = 0;
4378 }
4379 }
4380 if (!is_valid_ether_addr(dev->mac_addr))
4381 dev->max_iscsi_conn = 0;
4382 }
4383
4384 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4385 {
4386 struct cnic_local *cp = dev->cnic_priv;
4387 struct cnic_eth_dev *ethdev = cp->ethdev;
4388 int func = CNIC_FUNC(cp), ret, i;
4389 u32 pfid;
4390
4391 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4392 u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
4393
4394 if (!(val & 1))
4395 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
4396 else
4397 val = (val >> 1) & 1;
4398
4399 if (val)
4400 cp->pfid = func >> 1;
4401 else
4402 cp->pfid = func & 0x6;
4403 } else {
4404 cp->pfid = func;
4405 }
4406 pfid = cp->pfid;
4407
4408 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4409 cp->iscsi_start_cid);
4410
4411 if (ret)
4412 return -ENOMEM;
4413
4414 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4415
4416 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
4417 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
4418 cp->kcq1.sw_prod_idx = 0;
4419
4420 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4421 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4422
4423 cp->kcq1.hw_prod_idx_ptr =
4424 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4425 cp->kcq1.status_idx_ptr =
4426 &sb->sb.running_index[SM_RX_ID];
4427 } else {
4428 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
4429
4430 cp->kcq1.hw_prod_idx_ptr =
4431 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4432 cp->kcq1.status_idx_ptr =
4433 &sb->sb.running_index[SM_RX_ID];
4434 }
4435
4436 cnic_get_bnx2x_iscsi_info(dev);
4437
4438 /* Only 1 EQ */
4439 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
4440 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4441 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
4442 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4443 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
4444 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
4445 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4446 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
4447 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
4448 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4449 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
4450 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
4451 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4452 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
4453 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
4454 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4455 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
4456 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4457 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
4458 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4459 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
4460 HC_INDEX_ISCSI_EQ_CONS);
4461
4462 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4463 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4464 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
4465 cp->conn_buf_info.pgtbl[2 * i]);
4466 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4467 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
4468 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4469 }
4470
4471 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4472 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
4473 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4474 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4475 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
4476 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4477
4478 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4479 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
4480
4481 cnic_setup_bnx2x_context(dev);
4482
4483 ret = cnic_init_bnx2x_irq(dev);
4484 if (ret)
4485 return ret;
4486
4487 return 0;
4488 }
4489
4490 static void cnic_init_rings(struct cnic_dev *dev)
4491 {
4492 struct cnic_local *cp = dev->cnic_priv;
4493 struct cnic_uio_dev *udev = cp->udev;
4494
4495 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4496 return;
4497
4498 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4499 cnic_init_bnx2_tx_ring(dev);
4500 cnic_init_bnx2_rx_ring(dev);
4501 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4502 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4503 u32 cli = cp->ethdev->iscsi_l2_client_id;
4504 u32 cid = cp->ethdev->iscsi_l2_cid;
4505 u32 cl_qzone_id, type;
4506 struct client_init_ramrod_data *data;
4507 union l5cm_specific_data l5_data;
4508 struct ustorm_eth_rx_producers rx_prods = {0};
4509 u32 off, i;
4510
4511 rx_prods.bd_prod = 0;
4512 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4513 barrier();
4514
4515 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4516
4517 off = BAR_USTRORM_INTMEM +
4518 (BNX2X_CHIP_IS_E2(cp->chip_id) ?
4519 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
4520 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
4521
4522 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4523 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
4524
4525 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4526
4527 data = udev->l2_buf;
4528
4529 memset(data, 0, sizeof(*data));
4530
4531 cnic_init_bnx2x_tx_ring(dev, data);
4532 cnic_init_bnx2x_rx_ring(dev, data);
4533
4534 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
4535 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
4536
4537 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
4538 & SPE_HDR_CONN_TYPE;
4539 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
4540 SPE_HDR_FUNCTION_ID);
4541
4542 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4543
4544 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4545 cid, type, &l5_data);
4546
4547 i = 0;
4548 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4549 ++i < 10)
4550 msleep(1);
4551
4552 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4553 netdev_err(dev->netdev,
4554 "iSCSI CLIENT_SETUP did not complete\n");
4555 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4556 cnic_ring_ctl(dev, cid, cli, 1);
4557 }
4558 }
4559
4560 static void cnic_shutdown_rings(struct cnic_dev *dev)
4561 {
4562 struct cnic_local *cp = dev->cnic_priv;
4563
4564 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4565 return;
4566
4567 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4568 cnic_shutdown_bnx2_rx_ring(dev);
4569 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4570 struct cnic_local *cp = dev->cnic_priv;
4571 u32 cli = cp->ethdev->iscsi_l2_client_id;
4572 u32 cid = cp->ethdev->iscsi_l2_cid;
4573 union l5cm_specific_data l5_data;
4574 int i;
4575 u32 type;
4576
4577 cnic_ring_ctl(dev, cid, cli, 0);
4578
4579 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4580
4581 l5_data.phy_address.lo = cli;
4582 l5_data.phy_address.hi = 0;
4583 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4584 cid, ETH_CONNECTION_TYPE, &l5_data);
4585 i = 0;
4586 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4587 ++i < 10)
4588 msleep(1);
4589
4590 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4591 netdev_err(dev->netdev,
4592 "iSCSI CLIENT_HALT did not complete\n");
4593 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4594
4595 memset(&l5_data, 0, sizeof(l5_data));
4596 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
4597 & SPE_HDR_CONN_TYPE;
4598 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
4599 SPE_HDR_FUNCTION_ID);
4600 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
4601 cid, type, &l5_data);
4602 msleep(10);
4603 }
4604 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4605 }
4606
4607 static int cnic_register_netdev(struct cnic_dev *dev)
4608 {
4609 struct cnic_local *cp = dev->cnic_priv;
4610 struct cnic_eth_dev *ethdev = cp->ethdev;
4611 int err;
4612
4613 if (!ethdev)
4614 return -ENODEV;
4615
4616 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
4617 return 0;
4618
4619 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
4620 if (err)
4621 netdev_err(dev->netdev, "register_cnic failed\n");
4622
4623 return err;
4624 }
4625
4626 static void cnic_unregister_netdev(struct cnic_dev *dev)
4627 {
4628 struct cnic_local *cp = dev->cnic_priv;
4629 struct cnic_eth_dev *ethdev = cp->ethdev;
4630
4631 if (!ethdev)
4632 return;
4633
4634 ethdev->drv_unregister_cnic(dev->netdev);
4635 }
4636
4637 static int cnic_start_hw(struct cnic_dev *dev)
4638 {
4639 struct cnic_local *cp = dev->cnic_priv;
4640 struct cnic_eth_dev *ethdev = cp->ethdev;
4641 int err;
4642
4643 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
4644 return -EALREADY;
4645
4646 dev->regview = ethdev->io_base;
4647 pci_dev_get(dev->pcidev);
4648 cp->func = PCI_FUNC(dev->pcidev->devfn);
4649 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
4650 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
4651
4652 err = cp->alloc_resc(dev);
4653 if (err) {
4654 netdev_err(dev->netdev, "allocate resource failure\n");
4655 goto err1;
4656 }
4657
4658 err = cp->start_hw(dev);
4659 if (err)
4660 goto err1;
4661
4662 err = cnic_cm_open(dev);
4663 if (err)
4664 goto err1;
4665
4666 set_bit(CNIC_F_CNIC_UP, &dev->flags);
4667
4668 cp->enable_int(dev);
4669
4670 return 0;
4671
4672 err1:
4673 cp->free_resc(dev);
4674 pci_dev_put(dev->pcidev);
4675 return err;
4676 }
4677
4678 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
4679 {
4680 cnic_disable_bnx2_int_sync(dev);
4681
4682 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4683 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4684
4685 cnic_init_context(dev, KWQ_CID);
4686 cnic_init_context(dev, KCQ_CID);
4687
4688 cnic_setup_5709_context(dev, 0);
4689 cnic_free_irq(dev);
4690
4691 cnic_free_resc(dev);
4692 }
4693
4694
4695 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
4696 {
4697 struct cnic_local *cp = dev->cnic_priv;
4698
4699 cnic_free_irq(dev);
4700 *cp->kcq1.hw_prod_idx_ptr = 0;
4701 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4702 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
4703 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
4704 cnic_free_resc(dev);
4705 }
4706
4707 static void cnic_stop_hw(struct cnic_dev *dev)
4708 {
4709 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
4710 struct cnic_local *cp = dev->cnic_priv;
4711 int i = 0;
4712
4713 /* Need to wait for the ring shutdown event to complete
4714 * before clearing the CNIC_UP flag.
4715 */
4716 while (cp->udev->uio_dev != -1 && i < 15) {
4717 msleep(100);
4718 i++;
4719 }
4720 cnic_shutdown_rings(dev);
4721 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
4722 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
4723 synchronize_rcu();
4724 cnic_cm_shutdown(dev);
4725 cp->stop_hw(dev);
4726 pci_dev_put(dev->pcidev);
4727 }
4728 }
4729
4730 static void cnic_free_dev(struct cnic_dev *dev)
4731 {
4732 int i = 0;
4733
4734 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
4735 msleep(100);
4736 i++;
4737 }
4738 if (atomic_read(&dev->ref_count) != 0)
4739 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
4740
4741 netdev_info(dev->netdev, "Removed CNIC device\n");
4742 dev_put(dev->netdev);
4743 kfree(dev);
4744 }
4745
4746 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
4747 struct pci_dev *pdev)
4748 {
4749 struct cnic_dev *cdev;
4750 struct cnic_local *cp;
4751 int alloc_size;
4752
4753 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
4754
4755 cdev = kzalloc(alloc_size , GFP_KERNEL);
4756 if (cdev == NULL) {
4757 netdev_err(dev, "allocate dev struct failure\n");
4758 return NULL;
4759 }
4760
4761 cdev->netdev = dev;
4762 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
4763 cdev->register_device = cnic_register_device;
4764 cdev->unregister_device = cnic_unregister_device;
4765 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
4766
4767 cp = cdev->cnic_priv;
4768 cp->dev = cdev;
4769 cp->l2_single_buf_size = 0x400;
4770 cp->l2_rx_ring_size = 3;
4771
4772 spin_lock_init(&cp->cnic_ulp_lock);
4773
4774 netdev_info(dev, "Added CNIC device\n");
4775
4776 return cdev;
4777 }
4778
4779 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
4780 {
4781 struct pci_dev *pdev;
4782 struct cnic_dev *cdev;
4783 struct cnic_local *cp;
4784 struct cnic_eth_dev *ethdev = NULL;
4785 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4786
4787 probe = symbol_get(bnx2_cnic_probe);
4788 if (probe) {
4789 ethdev = (*probe)(dev);
4790 symbol_put(bnx2_cnic_probe);
4791 }
4792 if (!ethdev)
4793 return NULL;
4794
4795 pdev = ethdev->pdev;
4796 if (!pdev)
4797 return NULL;
4798
4799 dev_hold(dev);
4800 pci_dev_get(pdev);
4801 if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
4802 pdev->device == PCI_DEVICE_ID_NX2_5709S) {
4803 u8 rev;
4804
4805 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
4806 if (rev < 0x10) {
4807 pci_dev_put(pdev);
4808 goto cnic_err;
4809 }
4810 }
4811 pci_dev_put(pdev);
4812
4813 cdev = cnic_alloc_dev(dev, pdev);
4814 if (cdev == NULL)
4815 goto cnic_err;
4816
4817 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
4818 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
4819
4820 cp = cdev->cnic_priv;
4821 cp->ethdev = ethdev;
4822 cdev->pcidev = pdev;
4823 cp->chip_id = ethdev->chip_id;
4824
4825 cp->cnic_ops = &cnic_bnx2_ops;
4826 cp->start_hw = cnic_start_bnx2_hw;
4827 cp->stop_hw = cnic_stop_bnx2_hw;
4828 cp->setup_pgtbl = cnic_setup_page_tbl;
4829 cp->alloc_resc = cnic_alloc_bnx2_resc;
4830 cp->free_resc = cnic_free_resc;
4831 cp->start_cm = cnic_cm_init_bnx2_hw;
4832 cp->stop_cm = cnic_cm_stop_bnx2_hw;
4833 cp->enable_int = cnic_enable_bnx2_int;
4834 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
4835 cp->close_conn = cnic_close_bnx2_conn;
4836 cp->next_idx = cnic_bnx2_next_idx;
4837 cp->hw_idx = cnic_bnx2_hw_idx;
4838 return cdev;
4839
4840 cnic_err:
4841 dev_put(dev);
4842 return NULL;
4843 }
4844
4845 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
4846 {
4847 struct pci_dev *pdev;
4848 struct cnic_dev *cdev;
4849 struct cnic_local *cp;
4850 struct cnic_eth_dev *ethdev = NULL;
4851 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
4852
4853 probe = symbol_get(bnx2x_cnic_probe);
4854 if (probe) {
4855 ethdev = (*probe)(dev);
4856 symbol_put(bnx2x_cnic_probe);
4857 }
4858 if (!ethdev)
4859 return NULL;
4860
4861 pdev = ethdev->pdev;
4862 if (!pdev)
4863 return NULL;
4864
4865 dev_hold(dev);
4866 cdev = cnic_alloc_dev(dev, pdev);
4867 if (cdev == NULL) {
4868 dev_put(dev);
4869 return NULL;
4870 }
4871
4872 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
4873 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
4874
4875 cp = cdev->cnic_priv;
4876 cp->ethdev = ethdev;
4877 cdev->pcidev = pdev;
4878 cp->chip_id = ethdev->chip_id;
4879
4880 cp->cnic_ops = &cnic_bnx2x_ops;
4881 cp->start_hw = cnic_start_bnx2x_hw;
4882 cp->stop_hw = cnic_stop_bnx2x_hw;
4883 cp->setup_pgtbl = cnic_setup_page_tbl_le;
4884 cp->alloc_resc = cnic_alloc_bnx2x_resc;
4885 cp->free_resc = cnic_free_resc;
4886 cp->start_cm = cnic_cm_init_bnx2x_hw;
4887 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
4888 cp->enable_int = cnic_enable_bnx2x_int;
4889 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
4890 if (BNX2X_CHIP_IS_E2(cp->chip_id))
4891 cp->ack_int = cnic_ack_bnx2x_e2_msix;
4892 else
4893 cp->ack_int = cnic_ack_bnx2x_msix;
4894 cp->close_conn = cnic_close_bnx2x_conn;
4895 cp->next_idx = cnic_bnx2x_next_idx;
4896 cp->hw_idx = cnic_bnx2x_hw_idx;
4897 return cdev;
4898 }
4899
4900 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
4901 {
4902 struct ethtool_drvinfo drvinfo;
4903 struct cnic_dev *cdev = NULL;
4904
4905 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
4906 memset(&drvinfo, 0, sizeof(drvinfo));
4907 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
4908
4909 if (!strcmp(drvinfo.driver, "bnx2"))
4910 cdev = init_bnx2_cnic(dev);
4911 if (!strcmp(drvinfo.driver, "bnx2x"))
4912 cdev = init_bnx2x_cnic(dev);
4913 if (cdev) {
4914 write_lock(&cnic_dev_lock);
4915 list_add(&cdev->list, &cnic_dev_list);
4916 write_unlock(&cnic_dev_lock);
4917 }
4918 }
4919 return cdev;
4920 }
4921
4922 /**
4923 * netdev event handler
4924 */
4925 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
4926 void *ptr)
4927 {
4928 struct net_device *netdev = ptr;
4929 struct cnic_dev *dev;
4930 int if_type;
4931 int new_dev = 0;
4932
4933 dev = cnic_from_netdev(netdev);
4934
4935 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
4936 /* Check for the hot-plug device */
4937 dev = is_cnic_dev(netdev);
4938 if (dev) {
4939 new_dev = 1;
4940 cnic_hold(dev);
4941 }
4942 }
4943 if (dev) {
4944 struct cnic_local *cp = dev->cnic_priv;
4945
4946 if (new_dev)
4947 cnic_ulp_init(dev);
4948 else if (event == NETDEV_UNREGISTER)
4949 cnic_ulp_exit(dev);
4950
4951 if (event == NETDEV_UP) {
4952 if (cnic_register_netdev(dev) != 0) {
4953 cnic_put(dev);
4954 goto done;
4955 }
4956 if (!cnic_start_hw(dev))
4957 cnic_ulp_start(dev);
4958 }
4959
4960 rcu_read_lock();
4961 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
4962 struct cnic_ulp_ops *ulp_ops;
4963 void *ctx;
4964
4965 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
4966 if (!ulp_ops || !ulp_ops->indicate_netevent)
4967 continue;
4968
4969 ctx = cp->ulp_handle[if_type];
4970
4971 ulp_ops->indicate_netevent(ctx, event);
4972 }
4973 rcu_read_unlock();
4974
4975 if (event == NETDEV_GOING_DOWN) {
4976 cnic_ulp_stop(dev);
4977 cnic_stop_hw(dev);
4978 cnic_unregister_netdev(dev);
4979 } else if (event == NETDEV_UNREGISTER) {
4980 write_lock(&cnic_dev_lock);
4981 list_del_init(&dev->list);
4982 write_unlock(&cnic_dev_lock);
4983
4984 cnic_put(dev);
4985 cnic_free_dev(dev);
4986 goto done;
4987 }
4988 cnic_put(dev);
4989 }
4990 done:
4991 return NOTIFY_DONE;
4992 }
4993
4994 static struct notifier_block cnic_netdev_notifier = {
4995 .notifier_call = cnic_netdev_event
4996 };
4997
4998 static void cnic_release(void)
4999 {
5000 struct cnic_dev *dev;
5001 struct cnic_uio_dev *udev;
5002
5003 while (!list_empty(&cnic_dev_list)) {
5004 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
5005 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5006 cnic_ulp_stop(dev);
5007 cnic_stop_hw(dev);
5008 }
5009
5010 cnic_ulp_exit(dev);
5011 cnic_unregister_netdev(dev);
5012 list_del_init(&dev->list);
5013 cnic_free_dev(dev);
5014 }
5015 while (!list_empty(&cnic_udev_list)) {
5016 udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
5017 list);
5018 cnic_free_uio(udev);
5019 }
5020 }
5021
5022 static int __init cnic_init(void)
5023 {
5024 int rc = 0;
5025
5026 pr_info("%s", version);
5027
5028 rc = register_netdevice_notifier(&cnic_netdev_notifier);
5029 if (rc) {
5030 cnic_release();
5031 return rc;
5032 }
5033
5034 cnic_wq = create_singlethread_workqueue("cnic_wq");
5035 if (!cnic_wq) {
5036 cnic_release();
5037 unregister_netdevice_notifier(&cnic_netdev_notifier);
5038 return -ENOMEM;
5039 }
5040
5041 return 0;
5042 }
5043
5044 static void __exit cnic_exit(void)
5045 {
5046 unregister_netdevice_notifier(&cnic_netdev_notifier);
5047 cnic_release();
5048 destroy_workqueue(cnic_wq);
5049 }
5050
5051 module_init(cnic_init);
5052 module_exit(cnic_exit);
Linux kernel - Deliverables
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