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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / net / cnic.c
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define BCM_VLAN 1
32 #endif
33 #include <net/ip.h>
34 #include <net/tcp.h>
35 #include <net/route.h>
36 #include <net/ipv6.h>
37 #include <net/ip6_route.h>
38 #include <net/ip6_checksum.h>
39 #include <scsi/iscsi_if.h>
40
41 #include "cnic_if.h"
42 #include "bnx2.h"
43 #include "bnx2x/bnx2x_reg.h"
44 #include "bnx2x/bnx2x_fw_defs.h"
45 #include "bnx2x/bnx2x_hsi.h"
46 #include "../scsi/bnx2i/57xx_iscsi_constants.h"
47 #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
48 #include "cnic.h"
49 #include "cnic_defs.h"
50
51 #define DRV_MODULE_NAME "cnic"
52
53 static char version[] __devinitdata =
54 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
55
56 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
57 "Chen (zongxi@broadcom.com");
58 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
59 MODULE_LICENSE("GPL");
60 MODULE_VERSION(CNIC_MODULE_VERSION);
61
62 /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
63 static LIST_HEAD(cnic_dev_list);
64 static LIST_HEAD(cnic_udev_list);
65 static DEFINE_RWLOCK(cnic_dev_lock);
66 static DEFINE_MUTEX(cnic_lock);
67
68 static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
69
70 static int cnic_service_bnx2(void *, void *);
71 static int cnic_service_bnx2x(void *, void *);
72 static int cnic_ctl(void *, struct cnic_ctl_info *);
73
74 static struct cnic_ops cnic_bnx2_ops = {
75 .cnic_owner = THIS_MODULE,
76 .cnic_handler = cnic_service_bnx2,
77 .cnic_ctl = cnic_ctl,
78 };
79
80 static struct cnic_ops cnic_bnx2x_ops = {
81 .cnic_owner = THIS_MODULE,
82 .cnic_handler = cnic_service_bnx2x,
83 .cnic_ctl = cnic_ctl,
84 };
85
86 static struct workqueue_struct *cnic_wq;
87
88 static void cnic_shutdown_rings(struct cnic_dev *);
89 static void cnic_init_rings(struct cnic_dev *);
90 static int cnic_cm_set_pg(struct cnic_sock *);
91
92 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
93 {
94 struct cnic_uio_dev *udev = uinfo->priv;
95 struct cnic_dev *dev;
96
97 if (!capable(CAP_NET_ADMIN))
98 return -EPERM;
99
100 if (udev->uio_dev != -1)
101 return -EBUSY;
102
103 rtnl_lock();
104 dev = udev->dev;
105
106 if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
107 rtnl_unlock();
108 return -ENODEV;
109 }
110
111 udev->uio_dev = iminor(inode);
112
113 cnic_shutdown_rings(dev);
114 cnic_init_rings(dev);
115 rtnl_unlock();
116
117 return 0;
118 }
119
120 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
121 {
122 struct cnic_uio_dev *udev = uinfo->priv;
123
124 udev->uio_dev = -1;
125 return 0;
126 }
127
128 static inline void cnic_hold(struct cnic_dev *dev)
129 {
130 atomic_inc(&dev->ref_count);
131 }
132
133 static inline void cnic_put(struct cnic_dev *dev)
134 {
135 atomic_dec(&dev->ref_count);
136 }
137
138 static inline void csk_hold(struct cnic_sock *csk)
139 {
140 atomic_inc(&csk->ref_count);
141 }
142
143 static inline void csk_put(struct cnic_sock *csk)
144 {
145 atomic_dec(&csk->ref_count);
146 }
147
148 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
149 {
150 struct cnic_dev *cdev;
151
152 read_lock(&cnic_dev_lock);
153 list_for_each_entry(cdev, &cnic_dev_list, list) {
154 if (netdev == cdev->netdev) {
155 cnic_hold(cdev);
156 read_unlock(&cnic_dev_lock);
157 return cdev;
158 }
159 }
160 read_unlock(&cnic_dev_lock);
161 return NULL;
162 }
163
164 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
165 {
166 atomic_inc(&ulp_ops->ref_count);
167 }
168
169 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
170 {
171 atomic_dec(&ulp_ops->ref_count);
172 }
173
174 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
175 {
176 struct cnic_local *cp = dev->cnic_priv;
177 struct cnic_eth_dev *ethdev = cp->ethdev;
178 struct drv_ctl_info info;
179 struct drv_ctl_io *io = &info.data.io;
180
181 info.cmd = DRV_CTL_CTX_WR_CMD;
182 io->cid_addr = cid_addr;
183 io->offset = off;
184 io->data = val;
185 ethdev->drv_ctl(dev->netdev, &info);
186 }
187
188 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
189 {
190 struct cnic_local *cp = dev->cnic_priv;
191 struct cnic_eth_dev *ethdev = cp->ethdev;
192 struct drv_ctl_info info;
193 struct drv_ctl_io *io = &info.data.io;
194
195 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
196 io->offset = off;
197 io->dma_addr = addr;
198 ethdev->drv_ctl(dev->netdev, &info);
199 }
200
201 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
202 {
203 struct cnic_local *cp = dev->cnic_priv;
204 struct cnic_eth_dev *ethdev = cp->ethdev;
205 struct drv_ctl_info info;
206 struct drv_ctl_l2_ring *ring = &info.data.ring;
207
208 if (start)
209 info.cmd = DRV_CTL_START_L2_CMD;
210 else
211 info.cmd = DRV_CTL_STOP_L2_CMD;
212
213 ring->cid = cid;
214 ring->client_id = cl_id;
215 ethdev->drv_ctl(dev->netdev, &info);
216 }
217
218 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
219 {
220 struct cnic_local *cp = dev->cnic_priv;
221 struct cnic_eth_dev *ethdev = cp->ethdev;
222 struct drv_ctl_info info;
223 struct drv_ctl_io *io = &info.data.io;
224
225 info.cmd = DRV_CTL_IO_WR_CMD;
226 io->offset = off;
227 io->data = val;
228 ethdev->drv_ctl(dev->netdev, &info);
229 }
230
231 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
232 {
233 struct cnic_local *cp = dev->cnic_priv;
234 struct cnic_eth_dev *ethdev = cp->ethdev;
235 struct drv_ctl_info info;
236 struct drv_ctl_io *io = &info.data.io;
237
238 info.cmd = DRV_CTL_IO_RD_CMD;
239 io->offset = off;
240 ethdev->drv_ctl(dev->netdev, &info);
241 return io->data;
242 }
243
244 static int cnic_in_use(struct cnic_sock *csk)
245 {
246 return test_bit(SK_F_INUSE, &csk->flags);
247 }
248
249 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
250 {
251 struct cnic_local *cp = dev->cnic_priv;
252 struct cnic_eth_dev *ethdev = cp->ethdev;
253 struct drv_ctl_info info;
254
255 info.cmd = cmd;
256 info.data.credit.credit_count = count;
257 ethdev->drv_ctl(dev->netdev, &info);
258 }
259
260 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
261 {
262 u32 i;
263
264 for (i = 0; i < cp->max_cid_space; i++) {
265 if (cp->ctx_tbl[i].cid == cid) {
266 *l5_cid = i;
267 return 0;
268 }
269 }
270 return -EINVAL;
271 }
272
273 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
274 struct cnic_sock *csk)
275 {
276 struct iscsi_path path_req;
277 char *buf = NULL;
278 u16 len = 0;
279 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
280 struct cnic_ulp_ops *ulp_ops;
281 struct cnic_uio_dev *udev = cp->udev;
282 int rc = 0, retry = 0;
283
284 if (!udev || udev->uio_dev == -1)
285 return -ENODEV;
286
287 if (csk) {
288 len = sizeof(path_req);
289 buf = (char *) &path_req;
290 memset(&path_req, 0, len);
291
292 msg_type = ISCSI_KEVENT_PATH_REQ;
293 path_req.handle = (u64) csk->l5_cid;
294 if (test_bit(SK_F_IPV6, &csk->flags)) {
295 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
296 sizeof(struct in6_addr));
297 path_req.ip_addr_len = 16;
298 } else {
299 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
300 sizeof(struct in_addr));
301 path_req.ip_addr_len = 4;
302 }
303 path_req.vlan_id = csk->vlan_id;
304 path_req.pmtu = csk->mtu;
305 }
306
307 while (retry < 3) {
308 rc = 0;
309 rcu_read_lock();
310 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
311 if (ulp_ops)
312 rc = ulp_ops->iscsi_nl_send_msg(
313 cp->ulp_handle[CNIC_ULP_ISCSI],
314 msg_type, buf, len);
315 rcu_read_unlock();
316 if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
317 break;
318
319 msleep(100);
320 retry++;
321 }
322 return 0;
323 }
324
325 static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
326
327 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
328 char *buf, u16 len)
329 {
330 int rc = -EINVAL;
331
332 switch (msg_type) {
333 case ISCSI_UEVENT_PATH_UPDATE: {
334 struct cnic_local *cp;
335 u32 l5_cid;
336 struct cnic_sock *csk;
337 struct iscsi_path *path_resp;
338
339 if (len < sizeof(*path_resp))
340 break;
341
342 path_resp = (struct iscsi_path *) buf;
343 cp = dev->cnic_priv;
344 l5_cid = (u32) path_resp->handle;
345 if (l5_cid >= MAX_CM_SK_TBL_SZ)
346 break;
347
348 rcu_read_lock();
349 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
350 rc = -ENODEV;
351 rcu_read_unlock();
352 break;
353 }
354 csk = &cp->csk_tbl[l5_cid];
355 csk_hold(csk);
356 if (cnic_in_use(csk) &&
357 test_bit(SK_F_CONNECT_START, &csk->flags)) {
358
359 memcpy(csk->ha, path_resp->mac_addr, 6);
360 if (test_bit(SK_F_IPV6, &csk->flags))
361 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
362 sizeof(struct in6_addr));
363 else
364 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
365 sizeof(struct in_addr));
366
367 if (is_valid_ether_addr(csk->ha)) {
368 cnic_cm_set_pg(csk);
369 } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
370 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
371
372 cnic_cm_upcall(cp, csk,
373 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
374 clear_bit(SK_F_CONNECT_START, &csk->flags);
375 }
376 }
377 csk_put(csk);
378 rcu_read_unlock();
379 rc = 0;
380 }
381 }
382
383 return rc;
384 }
385
386 static int cnic_offld_prep(struct cnic_sock *csk)
387 {
388 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
389 return 0;
390
391 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
392 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
393 return 0;
394 }
395
396 return 1;
397 }
398
399 static int cnic_close_prep(struct cnic_sock *csk)
400 {
401 clear_bit(SK_F_CONNECT_START, &csk->flags);
402 smp_mb__after_clear_bit();
403
404 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
405 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
406 msleep(1);
407
408 return 1;
409 }
410 return 0;
411 }
412
413 static int cnic_abort_prep(struct cnic_sock *csk)
414 {
415 clear_bit(SK_F_CONNECT_START, &csk->flags);
416 smp_mb__after_clear_bit();
417
418 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
419 msleep(1);
420
421 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
422 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
423 return 1;
424 }
425
426 return 0;
427 }
428
429 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
430 {
431 struct cnic_dev *dev;
432
433 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
434 pr_err("%s: Bad type %d\n", __func__, ulp_type);
435 return -EINVAL;
436 }
437 mutex_lock(&cnic_lock);
438 if (cnic_ulp_tbl[ulp_type]) {
439 pr_err("%s: Type %d has already been registered\n",
440 __func__, ulp_type);
441 mutex_unlock(&cnic_lock);
442 return -EBUSY;
443 }
444
445 read_lock(&cnic_dev_lock);
446 list_for_each_entry(dev, &cnic_dev_list, list) {
447 struct cnic_local *cp = dev->cnic_priv;
448
449 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
450 }
451 read_unlock(&cnic_dev_lock);
452
453 atomic_set(&ulp_ops->ref_count, 0);
454 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
455 mutex_unlock(&cnic_lock);
456
457 /* Prevent race conditions with netdev_event */
458 rtnl_lock();
459 list_for_each_entry(dev, &cnic_dev_list, list) {
460 struct cnic_local *cp = dev->cnic_priv;
461
462 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
463 ulp_ops->cnic_init(dev);
464 }
465 rtnl_unlock();
466
467 return 0;
468 }
469
470 int cnic_unregister_driver(int ulp_type)
471 {
472 struct cnic_dev *dev;
473 struct cnic_ulp_ops *ulp_ops;
474 int i = 0;
475
476 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
477 pr_err("%s: Bad type %d\n", __func__, ulp_type);
478 return -EINVAL;
479 }
480 mutex_lock(&cnic_lock);
481 ulp_ops = cnic_ulp_tbl[ulp_type];
482 if (!ulp_ops) {
483 pr_err("%s: Type %d has not been registered\n",
484 __func__, ulp_type);
485 goto out_unlock;
486 }
487 read_lock(&cnic_dev_lock);
488 list_for_each_entry(dev, &cnic_dev_list, list) {
489 struct cnic_local *cp = dev->cnic_priv;
490
491 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
492 pr_err("%s: Type %d still has devices registered\n",
493 __func__, ulp_type);
494 read_unlock(&cnic_dev_lock);
495 goto out_unlock;
496 }
497 }
498 read_unlock(&cnic_dev_lock);
499
500 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
501
502 mutex_unlock(&cnic_lock);
503 synchronize_rcu();
504 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
505 msleep(100);
506 i++;
507 }
508
509 if (atomic_read(&ulp_ops->ref_count) != 0)
510 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
511 return 0;
512
513 out_unlock:
514 mutex_unlock(&cnic_lock);
515 return -EINVAL;
516 }
517
518 static int cnic_start_hw(struct cnic_dev *);
519 static void cnic_stop_hw(struct cnic_dev *);
520
521 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
522 void *ulp_ctx)
523 {
524 struct cnic_local *cp = dev->cnic_priv;
525 struct cnic_ulp_ops *ulp_ops;
526
527 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
528 pr_err("%s: Bad type %d\n", __func__, ulp_type);
529 return -EINVAL;
530 }
531 mutex_lock(&cnic_lock);
532 if (cnic_ulp_tbl[ulp_type] == NULL) {
533 pr_err("%s: Driver with type %d has not been registered\n",
534 __func__, ulp_type);
535 mutex_unlock(&cnic_lock);
536 return -EAGAIN;
537 }
538 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
539 pr_err("%s: Type %d has already been registered to this device\n",
540 __func__, ulp_type);
541 mutex_unlock(&cnic_lock);
542 return -EBUSY;
543 }
544
545 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
546 cp->ulp_handle[ulp_type] = ulp_ctx;
547 ulp_ops = cnic_ulp_tbl[ulp_type];
548 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
549 cnic_hold(dev);
550
551 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
552 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
553 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
554
555 mutex_unlock(&cnic_lock);
556
557 return 0;
558
559 }
560 EXPORT_SYMBOL(cnic_register_driver);
561
562 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
563 {
564 struct cnic_local *cp = dev->cnic_priv;
565 int i = 0;
566
567 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
568 pr_err("%s: Bad type %d\n", __func__, ulp_type);
569 return -EINVAL;
570 }
571 mutex_lock(&cnic_lock);
572 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
573 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
574 cnic_put(dev);
575 } else {
576 pr_err("%s: device not registered to this ulp type %d\n",
577 __func__, ulp_type);
578 mutex_unlock(&cnic_lock);
579 return -EINVAL;
580 }
581 mutex_unlock(&cnic_lock);
582
583 if (ulp_type == CNIC_ULP_ISCSI)
584 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
585
586 synchronize_rcu();
587
588 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
589 i < 20) {
590 msleep(100);
591 i++;
592 }
593 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
594 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
595
596 return 0;
597 }
598 EXPORT_SYMBOL(cnic_unregister_driver);
599
600 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
601 {
602 id_tbl->start = start_id;
603 id_tbl->max = size;
604 id_tbl->next = 0;
605 spin_lock_init(&id_tbl->lock);
606 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
607 if (!id_tbl->table)
608 return -ENOMEM;
609
610 return 0;
611 }
612
613 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
614 {
615 kfree(id_tbl->table);
616 id_tbl->table = NULL;
617 }
618
619 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
620 {
621 int ret = -1;
622
623 id -= id_tbl->start;
624 if (id >= id_tbl->max)
625 return ret;
626
627 spin_lock(&id_tbl->lock);
628 if (!test_bit(id, id_tbl->table)) {
629 set_bit(id, id_tbl->table);
630 ret = 0;
631 }
632 spin_unlock(&id_tbl->lock);
633 return ret;
634 }
635
636 /* Returns -1 if not successful */
637 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
638 {
639 u32 id;
640
641 spin_lock(&id_tbl->lock);
642 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
643 if (id >= id_tbl->max) {
644 id = -1;
645 if (id_tbl->next != 0) {
646 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
647 if (id >= id_tbl->next)
648 id = -1;
649 }
650 }
651
652 if (id < id_tbl->max) {
653 set_bit(id, id_tbl->table);
654 id_tbl->next = (id + 1) & (id_tbl->max - 1);
655 id += id_tbl->start;
656 }
657
658 spin_unlock(&id_tbl->lock);
659
660 return id;
661 }
662
663 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
664 {
665 if (id == -1)
666 return;
667
668 id -= id_tbl->start;
669 if (id >= id_tbl->max)
670 return;
671
672 clear_bit(id, id_tbl->table);
673 }
674
675 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
676 {
677 int i;
678
679 if (!dma->pg_arr)
680 return;
681
682 for (i = 0; i < dma->num_pages; i++) {
683 if (dma->pg_arr[i]) {
684 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
685 dma->pg_arr[i], dma->pg_map_arr[i]);
686 dma->pg_arr[i] = NULL;
687 }
688 }
689 if (dma->pgtbl) {
690 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
691 dma->pgtbl, dma->pgtbl_map);
692 dma->pgtbl = NULL;
693 }
694 kfree(dma->pg_arr);
695 dma->pg_arr = NULL;
696 dma->num_pages = 0;
697 }
698
699 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
700 {
701 int i;
702 u32 *page_table = dma->pgtbl;
703
704 for (i = 0; i < dma->num_pages; i++) {
705 /* Each entry needs to be in big endian format. */
706 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
707 page_table++;
708 *page_table = (u32) dma->pg_map_arr[i];
709 page_table++;
710 }
711 }
712
713 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
714 {
715 int i;
716 u32 *page_table = dma->pgtbl;
717
718 for (i = 0; i < dma->num_pages; i++) {
719 /* Each entry needs to be in little endian format. */
720 *page_table = dma->pg_map_arr[i] & 0xffffffff;
721 page_table++;
722 *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
723 page_table++;
724 }
725 }
726
727 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
728 int pages, int use_pg_tbl)
729 {
730 int i, size;
731 struct cnic_local *cp = dev->cnic_priv;
732
733 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
734 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
735 if (dma->pg_arr == NULL)
736 return -ENOMEM;
737
738 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
739 dma->num_pages = pages;
740
741 for (i = 0; i < pages; i++) {
742 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
743 BCM_PAGE_SIZE,
744 &dma->pg_map_arr[i],
745 GFP_ATOMIC);
746 if (dma->pg_arr[i] == NULL)
747 goto error;
748 }
749 if (!use_pg_tbl)
750 return 0;
751
752 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
753 ~(BCM_PAGE_SIZE - 1);
754 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
755 &dma->pgtbl_map, GFP_ATOMIC);
756 if (dma->pgtbl == NULL)
757 goto error;
758
759 cp->setup_pgtbl(dev, dma);
760
761 return 0;
762
763 error:
764 cnic_free_dma(dev, dma);
765 return -ENOMEM;
766 }
767
768 static void cnic_free_context(struct cnic_dev *dev)
769 {
770 struct cnic_local *cp = dev->cnic_priv;
771 int i;
772
773 for (i = 0; i < cp->ctx_blks; i++) {
774 if (cp->ctx_arr[i].ctx) {
775 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
776 cp->ctx_arr[i].ctx,
777 cp->ctx_arr[i].mapping);
778 cp->ctx_arr[i].ctx = NULL;
779 }
780 }
781 }
782
783 static void __cnic_free_uio(struct cnic_uio_dev *udev)
784 {
785 uio_unregister_device(&udev->cnic_uinfo);
786
787 if (udev->l2_buf) {
788 dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
789 udev->l2_buf, udev->l2_buf_map);
790 udev->l2_buf = NULL;
791 }
792
793 if (udev->l2_ring) {
794 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
795 udev->l2_ring, udev->l2_ring_map);
796 udev->l2_ring = NULL;
797 }
798
799 pci_dev_put(udev->pdev);
800 kfree(udev);
801 }
802
803 static void cnic_free_uio(struct cnic_uio_dev *udev)
804 {
805 if (!udev)
806 return;
807
808 write_lock(&cnic_dev_lock);
809 list_del_init(&udev->list);
810 write_unlock(&cnic_dev_lock);
811 __cnic_free_uio(udev);
812 }
813
814 static void cnic_free_resc(struct cnic_dev *dev)
815 {
816 struct cnic_local *cp = dev->cnic_priv;
817 struct cnic_uio_dev *udev = cp->udev;
818
819 if (udev) {
820 udev->dev = NULL;
821 cp->udev = NULL;
822 }
823
824 cnic_free_context(dev);
825 kfree(cp->ctx_arr);
826 cp->ctx_arr = NULL;
827 cp->ctx_blks = 0;
828
829 cnic_free_dma(dev, &cp->gbl_buf_info);
830 cnic_free_dma(dev, &cp->conn_buf_info);
831 cnic_free_dma(dev, &cp->kwq_info);
832 cnic_free_dma(dev, &cp->kwq_16_data_info);
833 cnic_free_dma(dev, &cp->kcq2.dma);
834 cnic_free_dma(dev, &cp->kcq1.dma);
835 kfree(cp->iscsi_tbl);
836 cp->iscsi_tbl = NULL;
837 kfree(cp->ctx_tbl);
838 cp->ctx_tbl = NULL;
839
840 cnic_free_id_tbl(&cp->fcoe_cid_tbl);
841 cnic_free_id_tbl(&cp->cid_tbl);
842 }
843
844 static int cnic_alloc_context(struct cnic_dev *dev)
845 {
846 struct cnic_local *cp = dev->cnic_priv;
847
848 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
849 int i, k, arr_size;
850
851 cp->ctx_blk_size = BCM_PAGE_SIZE;
852 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
853 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
854 sizeof(struct cnic_ctx);
855 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
856 if (cp->ctx_arr == NULL)
857 return -ENOMEM;
858
859 k = 0;
860 for (i = 0; i < 2; i++) {
861 u32 j, reg, off, lo, hi;
862
863 if (i == 0)
864 off = BNX2_PG_CTX_MAP;
865 else
866 off = BNX2_ISCSI_CTX_MAP;
867
868 reg = cnic_reg_rd_ind(dev, off);
869 lo = reg >> 16;
870 hi = reg & 0xffff;
871 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
872 cp->ctx_arr[k].cid = j;
873 }
874
875 cp->ctx_blks = k;
876 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
877 cp->ctx_blks = 0;
878 return -ENOMEM;
879 }
880
881 for (i = 0; i < cp->ctx_blks; i++) {
882 cp->ctx_arr[i].ctx =
883 dma_alloc_coherent(&dev->pcidev->dev,
884 BCM_PAGE_SIZE,
885 &cp->ctx_arr[i].mapping,
886 GFP_KERNEL);
887 if (cp->ctx_arr[i].ctx == NULL)
888 return -ENOMEM;
889 }
890 }
891 return 0;
892 }
893
894 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
895 {
896 int err, i, is_bnx2 = 0;
897 struct kcqe **kcq;
898
899 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
900 is_bnx2 = 1;
901
902 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
903 if (err)
904 return err;
905
906 kcq = (struct kcqe **) info->dma.pg_arr;
907 info->kcq = kcq;
908
909 if (is_bnx2)
910 return 0;
911
912 for (i = 0; i < KCQ_PAGE_CNT; i++) {
913 struct bnx2x_bd_chain_next *next =
914 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
915 int j = i + 1;
916
917 if (j >= KCQ_PAGE_CNT)
918 j = 0;
919 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
920 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
921 }
922 return 0;
923 }
924
925 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
926 {
927 struct cnic_local *cp = dev->cnic_priv;
928 struct cnic_uio_dev *udev;
929
930 read_lock(&cnic_dev_lock);
931 list_for_each_entry(udev, &cnic_udev_list, list) {
932 if (udev->pdev == dev->pcidev) {
933 udev->dev = dev;
934 cp->udev = udev;
935 read_unlock(&cnic_dev_lock);
936 return 0;
937 }
938 }
939 read_unlock(&cnic_dev_lock);
940
941 udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
942 if (!udev)
943 return -ENOMEM;
944
945 udev->uio_dev = -1;
946
947 udev->dev = dev;
948 udev->pdev = dev->pcidev;
949 udev->l2_ring_size = pages * BCM_PAGE_SIZE;
950 udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
951 &udev->l2_ring_map,
952 GFP_KERNEL | __GFP_COMP);
953 if (!udev->l2_ring)
954 goto err_udev;
955
956 udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
957 udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
958 udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
959 &udev->l2_buf_map,
960 GFP_KERNEL | __GFP_COMP);
961 if (!udev->l2_buf)
962 goto err_dma;
963
964 write_lock(&cnic_dev_lock);
965 list_add(&udev->list, &cnic_udev_list);
966 write_unlock(&cnic_dev_lock);
967
968 pci_dev_get(udev->pdev);
969
970 cp->udev = udev;
971
972 return 0;
973 err_dma:
974 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
975 udev->l2_ring, udev->l2_ring_map);
976 err_udev:
977 kfree(udev);
978 return -ENOMEM;
979 }
980
981 static int cnic_init_uio(struct cnic_dev *dev)
982 {
983 struct cnic_local *cp = dev->cnic_priv;
984 struct cnic_uio_dev *udev = cp->udev;
985 struct uio_info *uinfo;
986 int ret = 0;
987
988 if (!udev)
989 return -ENOMEM;
990
991 uinfo = &udev->cnic_uinfo;
992
993 uinfo->mem[0].addr = dev->netdev->base_addr;
994 uinfo->mem[0].internal_addr = dev->regview;
995 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
996 uinfo->mem[0].memtype = UIO_MEM_PHYS;
997
998 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
999 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
1000 PAGE_MASK;
1001 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
1002 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
1003 else
1004 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
1005
1006 uinfo->name = "bnx2_cnic";
1007 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
1008 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
1009 PAGE_MASK;
1010 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
1011
1012 uinfo->name = "bnx2x_cnic";
1013 }
1014
1015 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
1016
1017 uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
1018 uinfo->mem[2].size = udev->l2_ring_size;
1019 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
1020
1021 uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
1022 uinfo->mem[3].size = udev->l2_buf_size;
1023 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
1024
1025 uinfo->version = CNIC_MODULE_VERSION;
1026 uinfo->irq = UIO_IRQ_CUSTOM;
1027
1028 uinfo->open = cnic_uio_open;
1029 uinfo->release = cnic_uio_close;
1030
1031 if (udev->uio_dev == -1) {
1032 if (!uinfo->priv) {
1033 uinfo->priv = udev;
1034
1035 ret = uio_register_device(&udev->pdev->dev, uinfo);
1036 }
1037 } else {
1038 cnic_init_rings(dev);
1039 }
1040
1041 return ret;
1042 }
1043
1044 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1045 {
1046 struct cnic_local *cp = dev->cnic_priv;
1047 int ret;
1048
1049 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1050 if (ret)
1051 goto error;
1052 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1053
1054 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1055 if (ret)
1056 goto error;
1057
1058 ret = cnic_alloc_context(dev);
1059 if (ret)
1060 goto error;
1061
1062 ret = cnic_alloc_uio_rings(dev, 2);
1063 if (ret)
1064 goto error;
1065
1066 ret = cnic_init_uio(dev);
1067 if (ret)
1068 goto error;
1069
1070 return 0;
1071
1072 error:
1073 cnic_free_resc(dev);
1074 return ret;
1075 }
1076
1077 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1078 {
1079 struct cnic_local *cp = dev->cnic_priv;
1080 int ctx_blk_size = cp->ethdev->ctx_blk_size;
1081 int total_mem, blks, i;
1082
1083 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1084 blks = total_mem / ctx_blk_size;
1085 if (total_mem % ctx_blk_size)
1086 blks++;
1087
1088 if (blks > cp->ethdev->ctx_tbl_len)
1089 return -ENOMEM;
1090
1091 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1092 if (cp->ctx_arr == NULL)
1093 return -ENOMEM;
1094
1095 cp->ctx_blks = blks;
1096 cp->ctx_blk_size = ctx_blk_size;
1097 if (!BNX2X_CHIP_IS_57710(cp->chip_id))
1098 cp->ctx_align = 0;
1099 else
1100 cp->ctx_align = ctx_blk_size;
1101
1102 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1103
1104 for (i = 0; i < blks; i++) {
1105 cp->ctx_arr[i].ctx =
1106 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1107 &cp->ctx_arr[i].mapping,
1108 GFP_KERNEL);
1109 if (cp->ctx_arr[i].ctx == NULL)
1110 return -ENOMEM;
1111
1112 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1113 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1114 cnic_free_context(dev);
1115 cp->ctx_blk_size += cp->ctx_align;
1116 i = -1;
1117 continue;
1118 }
1119 }
1120 }
1121 return 0;
1122 }
1123
1124 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1125 {
1126 struct cnic_local *cp = dev->cnic_priv;
1127 struct cnic_eth_dev *ethdev = cp->ethdev;
1128 u32 start_cid = ethdev->starting_cid;
1129 int i, j, n, ret, pages;
1130 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1131
1132 cp->iro_arr = ethdev->iro_arr;
1133
1134 cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
1135 cp->iscsi_start_cid = start_cid;
1136 cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
1137
1138 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
1139 cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
1140 cp->fcoe_init_cid = ethdev->fcoe_init_cid;
1141 if (!cp->fcoe_init_cid)
1142 cp->fcoe_init_cid = 0x10;
1143 }
1144
1145 if (start_cid < BNX2X_ISCSI_START_CID) {
1146 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1147
1148 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1149 cp->fcoe_start_cid += delta;
1150 cp->max_cid_space += delta;
1151 }
1152
1153 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1154 GFP_KERNEL);
1155 if (!cp->iscsi_tbl)
1156 goto error;
1157
1158 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1159 cp->max_cid_space, GFP_KERNEL);
1160 if (!cp->ctx_tbl)
1161 goto error;
1162
1163 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1164 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1165 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1166 }
1167
1168 for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
1169 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
1170
1171 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1172 PAGE_SIZE;
1173
1174 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1175 if (ret)
1176 return -ENOMEM;
1177
1178 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1179 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1180 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1181
1182 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1183 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1184 off;
1185
1186 if ((i % n) == (n - 1))
1187 j++;
1188 }
1189
1190 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1191 if (ret)
1192 goto error;
1193
1194 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
1195 ret = cnic_alloc_kcq(dev, &cp->kcq2);
1196 if (ret)
1197 goto error;
1198 }
1199
1200 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1201 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1202 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1203 if (ret)
1204 goto error;
1205
1206 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1207 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1208 if (ret)
1209 goto error;
1210
1211 ret = cnic_alloc_bnx2x_context(dev);
1212 if (ret)
1213 goto error;
1214
1215 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1216
1217 cp->l2_rx_ring_size = 15;
1218
1219 ret = cnic_alloc_uio_rings(dev, 4);
1220 if (ret)
1221 goto error;
1222
1223 ret = cnic_init_uio(dev);
1224 if (ret)
1225 goto error;
1226
1227 return 0;
1228
1229 error:
1230 cnic_free_resc(dev);
1231 return -ENOMEM;
1232 }
1233
1234 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1235 {
1236 return cp->max_kwq_idx -
1237 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1238 }
1239
1240 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1241 u32 num_wqes)
1242 {
1243 struct cnic_local *cp = dev->cnic_priv;
1244 struct kwqe *prod_qe;
1245 u16 prod, sw_prod, i;
1246
1247 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1248 return -EAGAIN; /* bnx2 is down */
1249
1250 spin_lock_bh(&cp->cnic_ulp_lock);
1251 if (num_wqes > cnic_kwq_avail(cp) &&
1252 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1253 spin_unlock_bh(&cp->cnic_ulp_lock);
1254 return -EAGAIN;
1255 }
1256
1257 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1258
1259 prod = cp->kwq_prod_idx;
1260 sw_prod = prod & MAX_KWQ_IDX;
1261 for (i = 0; i < num_wqes; i++) {
1262 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1263 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1264 prod++;
1265 sw_prod = prod & MAX_KWQ_IDX;
1266 }
1267 cp->kwq_prod_idx = prod;
1268
1269 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1270
1271 spin_unlock_bh(&cp->cnic_ulp_lock);
1272 return 0;
1273 }
1274
1275 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1276 union l5cm_specific_data *l5_data)
1277 {
1278 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1279 dma_addr_t map;
1280
1281 map = ctx->kwqe_data_mapping;
1282 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1283 l5_data->phy_address.hi = (u64) map >> 32;
1284 return ctx->kwqe_data;
1285 }
1286
1287 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1288 u32 type, union l5cm_specific_data *l5_data)
1289 {
1290 struct cnic_local *cp = dev->cnic_priv;
1291 struct l5cm_spe kwqe;
1292 struct kwqe_16 *kwq[1];
1293 int ret;
1294
1295 kwqe.hdr.conn_and_cmd_data =
1296 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1297 BNX2X_HW_CID(cp, cid)));
1298 kwqe.hdr.type = cpu_to_le16(type);
1299 kwqe.hdr.reserved1 = 0;
1300 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1301 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1302
1303 kwq[0] = (struct kwqe_16 *) &kwqe;
1304
1305 spin_lock_bh(&cp->cnic_ulp_lock);
1306 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1307 spin_unlock_bh(&cp->cnic_ulp_lock);
1308
1309 if (ret == 1)
1310 return 0;
1311
1312 return -EBUSY;
1313 }
1314
1315 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1316 struct kcqe *cqes[], u32 num_cqes)
1317 {
1318 struct cnic_local *cp = dev->cnic_priv;
1319 struct cnic_ulp_ops *ulp_ops;
1320
1321 rcu_read_lock();
1322 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1323 if (likely(ulp_ops)) {
1324 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1325 cqes, num_cqes);
1326 }
1327 rcu_read_unlock();
1328 }
1329
1330 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1331 {
1332 struct cnic_local *cp = dev->cnic_priv;
1333 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1334 int hq_bds, pages;
1335 u32 pfid = cp->pfid;
1336
1337 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1338 cp->num_ccells = req1->num_ccells_per_conn;
1339 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1340 cp->num_iscsi_tasks;
1341 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1342 BNX2X_ISCSI_R2TQE_SIZE;
1343 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1344 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1345 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1346 cp->num_cqs = req1->num_cqs;
1347
1348 if (!dev->max_iscsi_conn)
1349 return 0;
1350
1351 /* init Tstorm RAM */
1352 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1353 req1->rq_num_wqes);
1354 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1355 PAGE_SIZE);
1356 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1357 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1358 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1359 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1360 req1->num_tasks_per_conn);
1361
1362 /* init Ustorm RAM */
1363 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1364 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1365 req1->rq_buffer_size);
1366 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1367 PAGE_SIZE);
1368 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1369 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1370 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1371 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1372 req1->num_tasks_per_conn);
1373 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1374 req1->rq_num_wqes);
1375 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1376 req1->cq_num_wqes);
1377 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1378 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1379
1380 /* init Xstorm RAM */
1381 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1382 PAGE_SIZE);
1383 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1384 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1385 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1386 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1387 req1->num_tasks_per_conn);
1388 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1389 hq_bds);
1390 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1391 req1->num_tasks_per_conn);
1392 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1393 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1394
1395 /* init Cstorm RAM */
1396 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1397 PAGE_SIZE);
1398 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1399 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1400 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1401 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1402 req1->num_tasks_per_conn);
1403 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1404 req1->cq_num_wqes);
1405 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1406 hq_bds);
1407
1408 return 0;
1409 }
1410
1411 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1412 {
1413 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1414 struct cnic_local *cp = dev->cnic_priv;
1415 u32 pfid = cp->pfid;
1416 struct iscsi_kcqe kcqe;
1417 struct kcqe *cqes[1];
1418
1419 memset(&kcqe, 0, sizeof(kcqe));
1420 if (!dev->max_iscsi_conn) {
1421 kcqe.completion_status =
1422 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1423 goto done;
1424 }
1425
1426 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1427 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1428 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1429 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1430 req2->error_bit_map[1]);
1431
1432 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1433 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1434 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1435 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1436 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1437 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1438 req2->error_bit_map[1]);
1439
1440 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1441 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1442
1443 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1444
1445 done:
1446 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1447 cqes[0] = (struct kcqe *) &kcqe;
1448 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1449
1450 return 0;
1451 }
1452
1453 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1454 {
1455 struct cnic_local *cp = dev->cnic_priv;
1456 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1457
1458 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1459 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1460
1461 cnic_free_dma(dev, &iscsi->hq_info);
1462 cnic_free_dma(dev, &iscsi->r2tq_info);
1463 cnic_free_dma(dev, &iscsi->task_array_info);
1464 cnic_free_id(&cp->cid_tbl, ctx->cid);
1465 } else {
1466 cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
1467 }
1468
1469 ctx->cid = 0;
1470 }
1471
1472 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1473 {
1474 u32 cid;
1475 int ret, pages;
1476 struct cnic_local *cp = dev->cnic_priv;
1477 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1478 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1479
1480 if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
1481 cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
1482 if (cid == -1) {
1483 ret = -ENOMEM;
1484 goto error;
1485 }
1486 ctx->cid = cid;
1487 return 0;
1488 }
1489
1490 cid = cnic_alloc_new_id(&cp->cid_tbl);
1491 if (cid == -1) {
1492 ret = -ENOMEM;
1493 goto error;
1494 }
1495
1496 ctx->cid = cid;
1497 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1498
1499 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1500 if (ret)
1501 goto error;
1502
1503 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1504 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1505 if (ret)
1506 goto error;
1507
1508 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1509 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1510 if (ret)
1511 goto error;
1512
1513 return 0;
1514
1515 error:
1516 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1517 return ret;
1518 }
1519
1520 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1521 struct regpair *ctx_addr)
1522 {
1523 struct cnic_local *cp = dev->cnic_priv;
1524 struct cnic_eth_dev *ethdev = cp->ethdev;
1525 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1526 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1527 unsigned long align_off = 0;
1528 dma_addr_t ctx_map;
1529 void *ctx;
1530
1531 if (cp->ctx_align) {
1532 unsigned long mask = cp->ctx_align - 1;
1533
1534 if (cp->ctx_arr[blk].mapping & mask)
1535 align_off = cp->ctx_align -
1536 (cp->ctx_arr[blk].mapping & mask);
1537 }
1538 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1539 (off * BNX2X_CONTEXT_MEM_SIZE);
1540 ctx = cp->ctx_arr[blk].ctx + align_off +
1541 (off * BNX2X_CONTEXT_MEM_SIZE);
1542 if (init)
1543 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1544
1545 ctx_addr->lo = ctx_map & 0xffffffff;
1546 ctx_addr->hi = (u64) ctx_map >> 32;
1547 return ctx;
1548 }
1549
1550 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1551 u32 num)
1552 {
1553 struct cnic_local *cp = dev->cnic_priv;
1554 struct iscsi_kwqe_conn_offload1 *req1 =
1555 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1556 struct iscsi_kwqe_conn_offload2 *req2 =
1557 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1558 struct iscsi_kwqe_conn_offload3 *req3;
1559 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1560 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1561 u32 cid = ctx->cid;
1562 u32 hw_cid = BNX2X_HW_CID(cp, cid);
1563 struct iscsi_context *ictx;
1564 struct regpair context_addr;
1565 int i, j, n = 2, n_max;
1566
1567 ctx->ctx_flags = 0;
1568 if (!req2->num_additional_wqes)
1569 return -EINVAL;
1570
1571 n_max = req2->num_additional_wqes + 2;
1572
1573 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1574 if (ictx == NULL)
1575 return -ENOMEM;
1576
1577 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1578
1579 ictx->xstorm_ag_context.hq_prod = 1;
1580
1581 ictx->xstorm_st_context.iscsi.first_burst_length =
1582 ISCSI_DEF_FIRST_BURST_LEN;
1583 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1584 ISCSI_DEF_MAX_RECV_SEG_LEN;
1585 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1586 req1->sq_page_table_addr_lo;
1587 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1588 req1->sq_page_table_addr_hi;
1589 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1590 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1591 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1592 iscsi->hq_info.pgtbl_map & 0xffffffff;
1593 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1594 (u64) iscsi->hq_info.pgtbl_map >> 32;
1595 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1596 iscsi->hq_info.pgtbl[0];
1597 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1598 iscsi->hq_info.pgtbl[1];
1599 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1600 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1601 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1602 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1603 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1604 iscsi->r2tq_info.pgtbl[0];
1605 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1606 iscsi->r2tq_info.pgtbl[1];
1607 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1608 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1609 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1610 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1611 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1612 BNX2X_ISCSI_PBL_NOT_CACHED;
1613 ictx->xstorm_st_context.iscsi.flags.flags |=
1614 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1615 ictx->xstorm_st_context.iscsi.flags.flags |=
1616 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1617
1618 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1619 /* TSTORM requires the base address of RQ DB & not PTE */
1620 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1621 req2->rq_page_table_addr_lo & PAGE_MASK;
1622 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1623 req2->rq_page_table_addr_hi;
1624 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1625 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1626 ictx->tstorm_st_context.tcp.flags2 |=
1627 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1628 ictx->tstorm_st_context.tcp.ooo_support_mode =
1629 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1630
1631 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1632
1633 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1634 req2->rq_page_table_addr_lo;
1635 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1636 req2->rq_page_table_addr_hi;
1637 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1638 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1639 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1640 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1641 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1642 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1643 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1644 iscsi->r2tq_info.pgtbl[0];
1645 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1646 iscsi->r2tq_info.pgtbl[1];
1647 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1648 req1->cq_page_table_addr_lo;
1649 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1650 req1->cq_page_table_addr_hi;
1651 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1652 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1653 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1654 ictx->ustorm_st_context.task_pbe_cache_index =
1655 BNX2X_ISCSI_PBL_NOT_CACHED;
1656 ictx->ustorm_st_context.task_pdu_cache_index =
1657 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1658
1659 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1660 if (j == 3) {
1661 if (n >= n_max)
1662 break;
1663 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1664 j = 0;
1665 }
1666 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1667 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1668 req3->qp_first_pte[j].hi;
1669 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1670 req3->qp_first_pte[j].lo;
1671 }
1672
1673 ictx->ustorm_st_context.task_pbl_base.lo =
1674 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1675 ictx->ustorm_st_context.task_pbl_base.hi =
1676 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1677 ictx->ustorm_st_context.tce_phy_addr.lo =
1678 iscsi->task_array_info.pgtbl[0];
1679 ictx->ustorm_st_context.tce_phy_addr.hi =
1680 iscsi->task_array_info.pgtbl[1];
1681 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1682 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1683 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1684 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1685 ISCSI_DEF_MAX_BURST_LEN;
1686 ictx->ustorm_st_context.negotiated_rx |=
1687 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1688 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1689
1690 ictx->cstorm_st_context.hq_pbl_base.lo =
1691 iscsi->hq_info.pgtbl_map & 0xffffffff;
1692 ictx->cstorm_st_context.hq_pbl_base.hi =
1693 (u64) iscsi->hq_info.pgtbl_map >> 32;
1694 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1695 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1696 ictx->cstorm_st_context.task_pbl_base.lo =
1697 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1698 ictx->cstorm_st_context.task_pbl_base.hi =
1699 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1700 /* CSTORM and USTORM initialization is different, CSTORM requires
1701 * CQ DB base & not PTE addr */
1702 ictx->cstorm_st_context.cq_db_base.lo =
1703 req1->cq_page_table_addr_lo & PAGE_MASK;
1704 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1705 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1706 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1707 for (i = 0; i < cp->num_cqs; i++) {
1708 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1709 ISCSI_INITIAL_SN;
1710 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1711 ISCSI_INITIAL_SN;
1712 }
1713
1714 ictx->xstorm_ag_context.cdu_reserved =
1715 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1716 ISCSI_CONNECTION_TYPE);
1717 ictx->ustorm_ag_context.cdu_usage =
1718 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1719 ISCSI_CONNECTION_TYPE);
1720 return 0;
1721
1722 }
1723
1724 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1725 u32 num, int *work)
1726 {
1727 struct iscsi_kwqe_conn_offload1 *req1;
1728 struct iscsi_kwqe_conn_offload2 *req2;
1729 struct cnic_local *cp = dev->cnic_priv;
1730 struct cnic_context *ctx;
1731 struct iscsi_kcqe kcqe;
1732 struct kcqe *cqes[1];
1733 u32 l5_cid;
1734 int ret = 0;
1735
1736 if (num < 2) {
1737 *work = num;
1738 return -EINVAL;
1739 }
1740
1741 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1742 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1743 if ((num - 2) < req2->num_additional_wqes) {
1744 *work = num;
1745 return -EINVAL;
1746 }
1747 *work = 2 + req2->num_additional_wqes;
1748
1749 l5_cid = req1->iscsi_conn_id;
1750 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1751 return -EINVAL;
1752
1753 memset(&kcqe, 0, sizeof(kcqe));
1754 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1755 kcqe.iscsi_conn_id = l5_cid;
1756 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1757
1758 ctx = &cp->ctx_tbl[l5_cid];
1759 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1760 kcqe.completion_status =
1761 ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1762 goto done;
1763 }
1764
1765 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1766 atomic_dec(&cp->iscsi_conn);
1767 goto done;
1768 }
1769 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1770 if (ret) {
1771 atomic_dec(&cp->iscsi_conn);
1772 ret = 0;
1773 goto done;
1774 }
1775 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1776 if (ret < 0) {
1777 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1778 atomic_dec(&cp->iscsi_conn);
1779 goto done;
1780 }
1781
1782 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1783 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
1784
1785 done:
1786 cqes[0] = (struct kcqe *) &kcqe;
1787 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1788 return ret;
1789 }
1790
1791
1792 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1793 {
1794 struct cnic_local *cp = dev->cnic_priv;
1795 struct iscsi_kwqe_conn_update *req =
1796 (struct iscsi_kwqe_conn_update *) kwqe;
1797 void *data;
1798 union l5cm_specific_data l5_data;
1799 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1800 int ret;
1801
1802 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1803 return -EINVAL;
1804
1805 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1806 if (!data)
1807 return -ENOMEM;
1808
1809 memcpy(data, kwqe, sizeof(struct kwqe));
1810
1811 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1812 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1813 return ret;
1814 }
1815
1816 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1817 {
1818 struct cnic_local *cp = dev->cnic_priv;
1819 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1820 union l5cm_specific_data l5_data;
1821 int ret;
1822 u32 hw_cid, type;
1823
1824 init_waitqueue_head(&ctx->waitq);
1825 ctx->wait_cond = 0;
1826 memset(&l5_data, 0, sizeof(l5_data));
1827 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1828 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
1829 & SPE_HDR_CONN_TYPE;
1830 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1831 SPE_HDR_FUNCTION_ID);
1832
1833 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1834 hw_cid, type, &l5_data);
1835
1836 if (ret == 0)
1837 wait_event(ctx->waitq, ctx->wait_cond);
1838
1839 return ret;
1840 }
1841
1842 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1843 {
1844 struct cnic_local *cp = dev->cnic_priv;
1845 struct iscsi_kwqe_conn_destroy *req =
1846 (struct iscsi_kwqe_conn_destroy *) kwqe;
1847 u32 l5_cid = req->reserved0;
1848 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1849 int ret = 0;
1850 struct iscsi_kcqe kcqe;
1851 struct kcqe *cqes[1];
1852
1853 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
1854 goto skip_cfc_delete;
1855
1856 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
1857 unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
1858
1859 if (delta > (2 * HZ))
1860 delta = 0;
1861
1862 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
1863 queue_delayed_work(cnic_wq, &cp->delete_task, delta);
1864 goto destroy_reply;
1865 }
1866
1867 ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
1868
1869 skip_cfc_delete:
1870 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1871
1872 atomic_dec(&cp->iscsi_conn);
1873 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
1874
1875 destroy_reply:
1876 memset(&kcqe, 0, sizeof(kcqe));
1877 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1878 kcqe.iscsi_conn_id = l5_cid;
1879 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1880 kcqe.iscsi_conn_context_id = req->context_id;
1881
1882 cqes[0] = (struct kcqe *) &kcqe;
1883 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1884
1885 return ret;
1886 }
1887
1888 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1889 struct l4_kwq_connect_req1 *kwqe1,
1890 struct l4_kwq_connect_req3 *kwqe3,
1891 struct l5cm_active_conn_buffer *conn_buf)
1892 {
1893 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1894 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1895 &conn_buf->xstorm_conn_buffer;
1896 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1897 &conn_buf->tstorm_conn_buffer;
1898 struct regpair context_addr;
1899 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1900 struct in6_addr src_ip, dst_ip;
1901 int i;
1902 u32 *addrp;
1903
1904 addrp = (u32 *) &conn_addr->local_ip_addr;
1905 for (i = 0; i < 4; i++, addrp++)
1906 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1907
1908 addrp = (u32 *) &conn_addr->remote_ip_addr;
1909 for (i = 0; i < 4; i++, addrp++)
1910 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1911
1912 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1913
1914 xstorm_buf->context_addr.hi = context_addr.hi;
1915 xstorm_buf->context_addr.lo = context_addr.lo;
1916 xstorm_buf->mss = 0xffff;
1917 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1918 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1919 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1920 xstorm_buf->pseudo_header_checksum =
1921 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1922
1923 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1924 tstorm_buf->params |=
1925 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1926 if (kwqe3->ka_timeout) {
1927 tstorm_buf->ka_enable = 1;
1928 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1929 tstorm_buf->ka_interval = kwqe3->ka_interval;
1930 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1931 }
1932 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1933 tstorm_buf->snd_buf = kwqe3->snd_buf;
1934 tstorm_buf->max_rt_time = 0xffffffff;
1935 }
1936
1937 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1938 {
1939 struct cnic_local *cp = dev->cnic_priv;
1940 u32 pfid = cp->pfid;
1941 u8 *mac = dev->mac_addr;
1942
1943 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1944 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
1945 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1946 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
1947 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1948 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
1949 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1950 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
1951 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1952 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
1953 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1954 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
1955
1956 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1957 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
1958 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1959 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1960 mac[4]);
1961 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1962 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
1963 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1964 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1965 mac[2]);
1966 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1967 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
1968 mac[1]);
1969 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1970 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
1971 mac[0]);
1972 }
1973
1974 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1975 {
1976 struct cnic_local *cp = dev->cnic_priv;
1977 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1978 u16 tstorm_flags = 0;
1979
1980 if (tcp_ts) {
1981 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1982 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1983 }
1984
1985 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1986 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
1987
1988 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1989 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
1990 }
1991
1992 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
1993 u32 num, int *work)
1994 {
1995 struct cnic_local *cp = dev->cnic_priv;
1996 struct l4_kwq_connect_req1 *kwqe1 =
1997 (struct l4_kwq_connect_req1 *) wqes[0];
1998 struct l4_kwq_connect_req3 *kwqe3;
1999 struct l5cm_active_conn_buffer *conn_buf;
2000 struct l5cm_conn_addr_params *conn_addr;
2001 union l5cm_specific_data l5_data;
2002 u32 l5_cid = kwqe1->pg_cid;
2003 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
2004 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2005 int ret;
2006
2007 if (num < 2) {
2008 *work = num;
2009 return -EINVAL;
2010 }
2011
2012 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
2013 *work = 3;
2014 else
2015 *work = 2;
2016
2017 if (num < *work) {
2018 *work = num;
2019 return -EINVAL;
2020 }
2021
2022 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
2023 netdev_err(dev->netdev, "conn_buf size too big\n");
2024 return -ENOMEM;
2025 }
2026 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2027 if (!conn_buf)
2028 return -ENOMEM;
2029
2030 memset(conn_buf, 0, sizeof(*conn_buf));
2031
2032 conn_addr = &conn_buf->conn_addr_buf;
2033 conn_addr->remote_addr_0 = csk->ha[0];
2034 conn_addr->remote_addr_1 = csk->ha[1];
2035 conn_addr->remote_addr_2 = csk->ha[2];
2036 conn_addr->remote_addr_3 = csk->ha[3];
2037 conn_addr->remote_addr_4 = csk->ha[4];
2038 conn_addr->remote_addr_5 = csk->ha[5];
2039
2040 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
2041 struct l4_kwq_connect_req2 *kwqe2 =
2042 (struct l4_kwq_connect_req2 *) wqes[1];
2043
2044 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
2045 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
2046 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
2047
2048 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
2049 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
2050 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
2051 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
2052 }
2053 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
2054
2055 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
2056 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
2057 conn_addr->local_tcp_port = kwqe1->src_port;
2058 conn_addr->remote_tcp_port = kwqe1->dst_port;
2059
2060 conn_addr->pmtu = kwqe3->pmtu;
2061 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
2062
2063 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
2064 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
2065
2066 cnic_bnx2x_set_tcp_timestamp(dev,
2067 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
2068
2069 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2070 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2071 if (!ret)
2072 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2073
2074 return ret;
2075 }
2076
2077 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2078 {
2079 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2080 union l5cm_specific_data l5_data;
2081 int ret;
2082
2083 memset(&l5_data, 0, sizeof(l5_data));
2084 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2085 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2086 return ret;
2087 }
2088
2089 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2090 {
2091 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2092 union l5cm_specific_data l5_data;
2093 int ret;
2094
2095 memset(&l5_data, 0, sizeof(l5_data));
2096 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2097 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2098 return ret;
2099 }
2100 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2101 {
2102 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2103 struct l4_kcq kcqe;
2104 struct kcqe *cqes[1];
2105
2106 memset(&kcqe, 0, sizeof(kcqe));
2107 kcqe.pg_host_opaque = req->host_opaque;
2108 kcqe.pg_cid = req->host_opaque;
2109 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2110 cqes[0] = (struct kcqe *) &kcqe;
2111 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2112 return 0;
2113 }
2114
2115 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2116 {
2117 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2118 struct l4_kcq kcqe;
2119 struct kcqe *cqes[1];
2120
2121 memset(&kcqe, 0, sizeof(kcqe));
2122 kcqe.pg_host_opaque = req->pg_host_opaque;
2123 kcqe.pg_cid = req->pg_cid;
2124 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2125 cqes[0] = (struct kcqe *) &kcqe;
2126 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2127 return 0;
2128 }
2129
2130 static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
2131 {
2132 struct fcoe_kwqe_stat *req;
2133 struct fcoe_stat_ramrod_params *fcoe_stat;
2134 union l5cm_specific_data l5_data;
2135 struct cnic_local *cp = dev->cnic_priv;
2136 int ret;
2137 u32 cid;
2138
2139 req = (struct fcoe_kwqe_stat *) kwqe;
2140 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2141
2142 fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2143 if (!fcoe_stat)
2144 return -ENOMEM;
2145
2146 memset(fcoe_stat, 0, sizeof(*fcoe_stat));
2147 memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
2148
2149 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
2150 FCOE_CONNECTION_TYPE, &l5_data);
2151 return ret;
2152 }
2153
2154 static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
2155 u32 num, int *work)
2156 {
2157 int ret;
2158 struct cnic_local *cp = dev->cnic_priv;
2159 u32 cid;
2160 struct fcoe_init_ramrod_params *fcoe_init;
2161 struct fcoe_kwqe_init1 *req1;
2162 struct fcoe_kwqe_init2 *req2;
2163 struct fcoe_kwqe_init3 *req3;
2164 union l5cm_specific_data l5_data;
2165
2166 if (num < 3) {
2167 *work = num;
2168 return -EINVAL;
2169 }
2170 req1 = (struct fcoe_kwqe_init1 *) wqes[0];
2171 req2 = (struct fcoe_kwqe_init2 *) wqes[1];
2172 req3 = (struct fcoe_kwqe_init3 *) wqes[2];
2173 if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
2174 *work = 1;
2175 return -EINVAL;
2176 }
2177 if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
2178 *work = 2;
2179 return -EINVAL;
2180 }
2181
2182 if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
2183 netdev_err(dev->netdev, "fcoe_init size too big\n");
2184 return -ENOMEM;
2185 }
2186 fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2187 if (!fcoe_init)
2188 return -ENOMEM;
2189
2190 memset(fcoe_init, 0, sizeof(*fcoe_init));
2191 memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
2192 memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
2193 memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
2194 fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
2195 fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
2196 fcoe_init->eq_next_page_addr.lo =
2197 cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
2198 fcoe_init->eq_next_page_addr.hi =
2199 (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
2200
2201 fcoe_init->sb_num = cp->status_blk_num;
2202 fcoe_init->eq_prod = MAX_KCQ_IDX;
2203 fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
2204 cp->kcq2.sw_prod_idx = 0;
2205
2206 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2207 printk(KERN_ERR "bdbg: submitting INIT RAMROD \n");
2208 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
2209 FCOE_CONNECTION_TYPE, &l5_data);
2210 *work = 3;
2211 return ret;
2212 }
2213
2214 static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
2215 u32 num, int *work)
2216 {
2217 int ret = 0;
2218 u32 cid = -1, l5_cid;
2219 struct cnic_local *cp = dev->cnic_priv;
2220 struct fcoe_kwqe_conn_offload1 *req1;
2221 struct fcoe_kwqe_conn_offload2 *req2;
2222 struct fcoe_kwqe_conn_offload3 *req3;
2223 struct fcoe_kwqe_conn_offload4 *req4;
2224 struct fcoe_conn_offload_ramrod_params *fcoe_offload;
2225 struct cnic_context *ctx;
2226 struct fcoe_context *fctx;
2227 struct regpair ctx_addr;
2228 union l5cm_specific_data l5_data;
2229 struct fcoe_kcqe kcqe;
2230 struct kcqe *cqes[1];
2231
2232 if (num < 4) {
2233 *work = num;
2234 return -EINVAL;
2235 }
2236 req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
2237 req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
2238 req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
2239 req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
2240
2241 *work = 4;
2242
2243 l5_cid = req1->fcoe_conn_id;
2244 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2245 goto err_reply;
2246
2247 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2248
2249 ctx = &cp->ctx_tbl[l5_cid];
2250 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2251 goto err_reply;
2252
2253 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
2254 if (ret) {
2255 ret = 0;
2256 goto err_reply;
2257 }
2258 cid = ctx->cid;
2259
2260 fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
2261 if (fctx) {
2262 u32 hw_cid = BNX2X_HW_CID(cp, cid);
2263 u32 val;
2264
2265 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
2266 FCOE_CONNECTION_TYPE);
2267 fctx->xstorm_ag_context.cdu_reserved = val;
2268 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
2269 FCOE_CONNECTION_TYPE);
2270 fctx->ustorm_ag_context.cdu_usage = val;
2271 }
2272 if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
2273 netdev_err(dev->netdev, "fcoe_offload size too big\n");
2274 goto err_reply;
2275 }
2276 fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2277 if (!fcoe_offload)
2278 goto err_reply;
2279
2280 memset(fcoe_offload, 0, sizeof(*fcoe_offload));
2281 memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
2282 memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
2283 memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
2284 memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
2285
2286 cid = BNX2X_HW_CID(cp, cid);
2287 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
2288 FCOE_CONNECTION_TYPE, &l5_data);
2289 if (!ret)
2290 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2291
2292 return ret;
2293
2294 err_reply:
2295 if (cid != -1)
2296 cnic_free_bnx2x_conn_resc(dev, l5_cid);
2297
2298 memset(&kcqe, 0, sizeof(kcqe));
2299 kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
2300 kcqe.fcoe_conn_id = req1->fcoe_conn_id;
2301 kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
2302
2303 cqes[0] = (struct kcqe *) &kcqe;
2304 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2305 return ret;
2306 }
2307
2308 static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
2309 {
2310 struct fcoe_kwqe_conn_enable_disable *req;
2311 struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
2312 union l5cm_specific_data l5_data;
2313 int ret;
2314 u32 cid, l5_cid;
2315 struct cnic_local *cp = dev->cnic_priv;
2316
2317 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2318 cid = req->context_id;
2319 l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
2320
2321 if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
2322 netdev_err(dev->netdev, "fcoe_enable size too big\n");
2323 return -ENOMEM;
2324 }
2325 fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2326 if (!fcoe_enable)
2327 return -ENOMEM;
2328
2329 memset(fcoe_enable, 0, sizeof(*fcoe_enable));
2330 memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
2331 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
2332 FCOE_CONNECTION_TYPE, &l5_data);
2333 return ret;
2334 }
2335
2336 static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
2337 {
2338 struct fcoe_kwqe_conn_enable_disable *req;
2339 struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
2340 union l5cm_specific_data l5_data;
2341 int ret;
2342 u32 cid, l5_cid;
2343 struct cnic_local *cp = dev->cnic_priv;
2344
2345 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2346 cid = req->context_id;
2347 l5_cid = req->conn_id;
2348 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2349 return -EINVAL;
2350
2351 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2352
2353 if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
2354 netdev_err(dev->netdev, "fcoe_disable size too big\n");
2355 return -ENOMEM;
2356 }
2357 fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2358 if (!fcoe_disable)
2359 return -ENOMEM;
2360
2361 memset(fcoe_disable, 0, sizeof(*fcoe_disable));
2362 memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
2363 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
2364 FCOE_CONNECTION_TYPE, &l5_data);
2365 return ret;
2366 }
2367
2368 static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2369 {
2370 struct fcoe_kwqe_conn_destroy *req;
2371 union l5cm_specific_data l5_data;
2372 int ret;
2373 u32 cid, l5_cid;
2374 struct cnic_local *cp = dev->cnic_priv;
2375 struct cnic_context *ctx;
2376 struct fcoe_kcqe kcqe;
2377 struct kcqe *cqes[1];
2378
2379 req = (struct fcoe_kwqe_conn_destroy *) kwqe;
2380 cid = req->context_id;
2381 l5_cid = req->conn_id;
2382 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2383 return -EINVAL;
2384
2385 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2386
2387 ctx = &cp->ctx_tbl[l5_cid];
2388
2389 init_waitqueue_head(&ctx->waitq);
2390 ctx->wait_cond = 0;
2391
2392 memset(&l5_data, 0, sizeof(l5_data));
2393 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
2394 FCOE_CONNECTION_TYPE, &l5_data);
2395 if (ret == 0) {
2396 wait_event(ctx->waitq, ctx->wait_cond);
2397 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2398 queue_delayed_work(cnic_wq, &cp->delete_task,
2399 msecs_to_jiffies(2000));
2400 }
2401
2402 memset(&kcqe, 0, sizeof(kcqe));
2403 kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
2404 kcqe.fcoe_conn_id = req->conn_id;
2405 kcqe.fcoe_conn_context_id = cid;
2406
2407 cqes[0] = (struct kcqe *) &kcqe;
2408 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2409 return ret;
2410 }
2411
2412 static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2413 {
2414 struct fcoe_kwqe_destroy *req;
2415 union l5cm_specific_data l5_data;
2416 struct cnic_local *cp = dev->cnic_priv;
2417 int ret;
2418 u32 cid;
2419
2420 req = (struct fcoe_kwqe_destroy *) kwqe;
2421 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2422
2423 memset(&l5_data, 0, sizeof(l5_data));
2424 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
2425 FCOE_CONNECTION_TYPE, &l5_data);
2426 return ret;
2427 }
2428
2429 static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
2430 struct kwqe *wqes[], u32 num_wqes)
2431 {
2432 int i, work, ret;
2433 u32 opcode;
2434 struct kwqe *kwqe;
2435
2436 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2437 return -EAGAIN; /* bnx2 is down */
2438
2439 for (i = 0; i < num_wqes; ) {
2440 kwqe = wqes[i];
2441 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2442 work = 1;
2443
2444 switch (opcode) {
2445 case ISCSI_KWQE_OPCODE_INIT1:
2446 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2447 break;
2448 case ISCSI_KWQE_OPCODE_INIT2:
2449 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2450 break;
2451 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2452 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2453 num_wqes - i, &work);
2454 break;
2455 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2456 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2457 break;
2458 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2459 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2460 break;
2461 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2462 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2463 &work);
2464 break;
2465 case L4_KWQE_OPCODE_VALUE_CLOSE:
2466 ret = cnic_bnx2x_close(dev, kwqe);
2467 break;
2468 case L4_KWQE_OPCODE_VALUE_RESET:
2469 ret = cnic_bnx2x_reset(dev, kwqe);
2470 break;
2471 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2472 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2473 break;
2474 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2475 ret = cnic_bnx2x_update_pg(dev, kwqe);
2476 break;
2477 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2478 ret = 0;
2479 break;
2480 default:
2481 ret = 0;
2482 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2483 opcode);
2484 break;
2485 }
2486 if (ret < 0)
2487 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2488 opcode);
2489 i += work;
2490 }
2491 return 0;
2492 }
2493
2494 static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
2495 struct kwqe *wqes[], u32 num_wqes)
2496 {
2497 struct cnic_local *cp = dev->cnic_priv;
2498 int i, work, ret;
2499 u32 opcode;
2500 struct kwqe *kwqe;
2501
2502 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2503 return -EAGAIN; /* bnx2 is down */
2504
2505 if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
2506 return -EINVAL;
2507
2508 for (i = 0; i < num_wqes; ) {
2509 kwqe = wqes[i];
2510 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2511 work = 1;
2512
2513 switch (opcode) {
2514 case FCOE_KWQE_OPCODE_INIT1:
2515 ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
2516 num_wqes - i, &work);
2517 break;
2518 case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
2519 ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
2520 num_wqes - i, &work);
2521 break;
2522 case FCOE_KWQE_OPCODE_ENABLE_CONN:
2523 ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
2524 break;
2525 case FCOE_KWQE_OPCODE_DISABLE_CONN:
2526 ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
2527 break;
2528 case FCOE_KWQE_OPCODE_DESTROY_CONN:
2529 ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
2530 break;
2531 case FCOE_KWQE_OPCODE_DESTROY:
2532 ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
2533 break;
2534 case FCOE_KWQE_OPCODE_STAT:
2535 ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
2536 break;
2537 default:
2538 ret = 0;
2539 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2540 opcode);
2541 break;
2542 }
2543 if (ret < 0)
2544 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2545 opcode);
2546 i += work;
2547 }
2548 return 0;
2549 }
2550
2551 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2552 u32 num_wqes)
2553 {
2554 int ret = -EINVAL;
2555 u32 layer_code;
2556
2557 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2558 return -EAGAIN; /* bnx2x is down */
2559
2560 if (!num_wqes)
2561 return 0;
2562
2563 layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
2564 switch (layer_code) {
2565 case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
2566 case KWQE_FLAGS_LAYER_MASK_L4:
2567 case KWQE_FLAGS_LAYER_MASK_L2:
2568 ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
2569 break;
2570
2571 case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
2572 ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
2573 break;
2574 }
2575 return ret;
2576 }
2577
2578 static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
2579 {
2580 if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
2581 return KCQE_FLAGS_LAYER_MASK_L4;
2582
2583 return opflag & KCQE_FLAGS_LAYER_MASK;
2584 }
2585
2586 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2587 {
2588 struct cnic_local *cp = dev->cnic_priv;
2589 int i, j, comp = 0;
2590
2591 i = 0;
2592 j = 1;
2593 while (num_cqes) {
2594 struct cnic_ulp_ops *ulp_ops;
2595 int ulp_type;
2596 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2597 u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
2598
2599 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2600 comp++;
2601
2602 while (j < num_cqes) {
2603 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2604
2605 if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
2606 break;
2607
2608 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2609 comp++;
2610 j++;
2611 }
2612
2613 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2614 ulp_type = CNIC_ULP_RDMA;
2615 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2616 ulp_type = CNIC_ULP_ISCSI;
2617 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
2618 ulp_type = CNIC_ULP_FCOE;
2619 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2620 ulp_type = CNIC_ULP_L4;
2621 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2622 goto end;
2623 else {
2624 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2625 kcqe_op_flag);
2626 goto end;
2627 }
2628
2629 rcu_read_lock();
2630 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2631 if (likely(ulp_ops)) {
2632 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2633 cp->completed_kcq + i, j);
2634 }
2635 rcu_read_unlock();
2636 end:
2637 num_cqes -= j;
2638 i += j;
2639 j = 1;
2640 }
2641 if (unlikely(comp))
2642 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2643 }
2644
2645 static u16 cnic_bnx2_next_idx(u16 idx)
2646 {
2647 return idx + 1;
2648 }
2649
2650 static u16 cnic_bnx2_hw_idx(u16 idx)
2651 {
2652 return idx;
2653 }
2654
2655 static u16 cnic_bnx2x_next_idx(u16 idx)
2656 {
2657 idx++;
2658 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2659 idx++;
2660
2661 return idx;
2662 }
2663
2664 static u16 cnic_bnx2x_hw_idx(u16 idx)
2665 {
2666 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2667 idx++;
2668 return idx;
2669 }
2670
2671 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2672 {
2673 struct cnic_local *cp = dev->cnic_priv;
2674 u16 i, ri, hw_prod, last;
2675 struct kcqe *kcqe;
2676 int kcqe_cnt = 0, last_cnt = 0;
2677
2678 i = ri = last = info->sw_prod_idx;
2679 ri &= MAX_KCQ_IDX;
2680 hw_prod = *info->hw_prod_idx_ptr;
2681 hw_prod = cp->hw_idx(hw_prod);
2682
2683 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2684 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2685 cp->completed_kcq[kcqe_cnt++] = kcqe;
2686 i = cp->next_idx(i);
2687 ri = i & MAX_KCQ_IDX;
2688 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2689 last_cnt = kcqe_cnt;
2690 last = i;
2691 }
2692 }
2693
2694 info->sw_prod_idx = last;
2695 return last_cnt;
2696 }
2697
2698 static int cnic_l2_completion(struct cnic_local *cp)
2699 {
2700 u16 hw_cons, sw_cons;
2701 struct cnic_uio_dev *udev = cp->udev;
2702 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2703 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
2704 u32 cmd;
2705 int comp = 0;
2706
2707 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2708 return 0;
2709
2710 hw_cons = *cp->rx_cons_ptr;
2711 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2712 hw_cons++;
2713
2714 sw_cons = cp->rx_cons;
2715 while (sw_cons != hw_cons) {
2716 u8 cqe_fp_flags;
2717
2718 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2719 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2720 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2721 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2722 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2723 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2724 cmd == RAMROD_CMD_ID_ETH_HALT)
2725 comp++;
2726 }
2727 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2728 }
2729 return comp;
2730 }
2731
2732 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2733 {
2734 u16 rx_cons, tx_cons;
2735 int comp = 0;
2736
2737 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2738 return;
2739
2740 rx_cons = *cp->rx_cons_ptr;
2741 tx_cons = *cp->tx_cons_ptr;
2742 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2743 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2744 comp = cnic_l2_completion(cp);
2745
2746 cp->tx_cons = tx_cons;
2747 cp->rx_cons = rx_cons;
2748
2749 if (cp->udev)
2750 uio_event_notify(&cp->udev->cnic_uinfo);
2751 }
2752 if (comp)
2753 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2754 }
2755
2756 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2757 {
2758 struct cnic_local *cp = dev->cnic_priv;
2759 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2760 int kcqe_cnt;
2761
2762 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2763
2764 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2765
2766 service_kcqes(dev, kcqe_cnt);
2767
2768 /* Tell compiler that status_blk fields can change. */
2769 barrier();
2770 if (status_idx != *cp->kcq1.status_idx_ptr) {
2771 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2772 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2773 } else
2774 break;
2775 }
2776
2777 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2778
2779 cnic_chk_pkt_rings(cp);
2780
2781 return status_idx;
2782 }
2783
2784 static int cnic_service_bnx2(void *data, void *status_blk)
2785 {
2786 struct cnic_dev *dev = data;
2787
2788 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2789 struct status_block *sblk = status_blk;
2790
2791 return sblk->status_idx;
2792 }
2793
2794 return cnic_service_bnx2_queues(dev);
2795 }
2796
2797 static void cnic_service_bnx2_msix(unsigned long data)
2798 {
2799 struct cnic_dev *dev = (struct cnic_dev *) data;
2800 struct cnic_local *cp = dev->cnic_priv;
2801
2802 cp->last_status_idx = cnic_service_bnx2_queues(dev);
2803
2804 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2805 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2806 }
2807
2808 static void cnic_doirq(struct cnic_dev *dev)
2809 {
2810 struct cnic_local *cp = dev->cnic_priv;
2811
2812 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2813 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
2814
2815 prefetch(cp->status_blk.gen);
2816 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2817
2818 tasklet_schedule(&cp->cnic_irq_task);
2819 }
2820 }
2821
2822 static irqreturn_t cnic_irq(int irq, void *dev_instance)
2823 {
2824 struct cnic_dev *dev = dev_instance;
2825 struct cnic_local *cp = dev->cnic_priv;
2826
2827 if (cp->ack_int)
2828 cp->ack_int(dev);
2829
2830 cnic_doirq(dev);
2831
2832 return IRQ_HANDLED;
2833 }
2834
2835 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2836 u16 index, u8 op, u8 update)
2837 {
2838 struct cnic_local *cp = dev->cnic_priv;
2839 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2840 COMMAND_REG_INT_ACK);
2841 struct igu_ack_register igu_ack;
2842
2843 igu_ack.status_block_index = index;
2844 igu_ack.sb_id_and_flags =
2845 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2846 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2847 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2848 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2849
2850 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2851 }
2852
2853 static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
2854 u16 index, u8 op, u8 update)
2855 {
2856 struct igu_regular cmd_data;
2857 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
2858
2859 cmd_data.sb_id_and_flags =
2860 (index << IGU_REGULAR_SB_INDEX_SHIFT) |
2861 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2862 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2863 (op << IGU_REGULAR_ENABLE_INT_SHIFT);
2864
2865
2866 CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
2867 }
2868
2869 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2870 {
2871 struct cnic_local *cp = dev->cnic_priv;
2872
2873 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
2874 IGU_INT_DISABLE, 0);
2875 }
2876
2877 static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
2878 {
2879 struct cnic_local *cp = dev->cnic_priv;
2880
2881 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
2882 IGU_INT_DISABLE, 0);
2883 }
2884
2885 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
2886 {
2887 u32 last_status = *info->status_idx_ptr;
2888 int kcqe_cnt;
2889
2890 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
2891
2892 service_kcqes(dev, kcqe_cnt);
2893
2894 /* Tell compiler that sblk fields can change. */
2895 barrier();
2896 if (last_status == *info->status_idx_ptr)
2897 break;
2898
2899 last_status = *info->status_idx_ptr;
2900 }
2901 return last_status;
2902 }
2903
2904 static void cnic_service_bnx2x_bh(unsigned long data)
2905 {
2906 struct cnic_dev *dev = (struct cnic_dev *) data;
2907 struct cnic_local *cp = dev->cnic_priv;
2908 u32 status_idx;
2909
2910 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2911 return;
2912
2913 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
2914
2915 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
2916
2917 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
2918 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
2919
2920 CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
2921 MAX_KCQ_IDX);
2922
2923 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
2924 status_idx, IGU_INT_ENABLE, 1);
2925 } else {
2926 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
2927 status_idx, IGU_INT_ENABLE, 1);
2928 }
2929 }
2930
2931 static int cnic_service_bnx2x(void *data, void *status_blk)
2932 {
2933 struct cnic_dev *dev = data;
2934 struct cnic_local *cp = dev->cnic_priv;
2935
2936 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
2937 cnic_doirq(dev);
2938
2939 cnic_chk_pkt_rings(cp);
2940
2941 return 0;
2942 }
2943
2944 static void cnic_ulp_stop(struct cnic_dev *dev)
2945 {
2946 struct cnic_local *cp = dev->cnic_priv;
2947 int if_type;
2948
2949 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2950
2951 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2952 struct cnic_ulp_ops *ulp_ops;
2953
2954 mutex_lock(&cnic_lock);
2955 ulp_ops = cp->ulp_ops[if_type];
2956 if (!ulp_ops) {
2957 mutex_unlock(&cnic_lock);
2958 continue;
2959 }
2960 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2961 mutex_unlock(&cnic_lock);
2962
2963 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2964 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
2965
2966 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2967 }
2968 }
2969
2970 static void cnic_ulp_start(struct cnic_dev *dev)
2971 {
2972 struct cnic_local *cp = dev->cnic_priv;
2973 int if_type;
2974
2975 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2976 struct cnic_ulp_ops *ulp_ops;
2977
2978 mutex_lock(&cnic_lock);
2979 ulp_ops = cp->ulp_ops[if_type];
2980 if (!ulp_ops || !ulp_ops->cnic_start) {
2981 mutex_unlock(&cnic_lock);
2982 continue;
2983 }
2984 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2985 mutex_unlock(&cnic_lock);
2986
2987 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2988 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
2989
2990 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2991 }
2992 }
2993
2994 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
2995 {
2996 struct cnic_dev *dev = data;
2997
2998 switch (info->cmd) {
2999 case CNIC_CTL_STOP_CMD:
3000 cnic_hold(dev);
3001
3002 cnic_ulp_stop(dev);
3003 cnic_stop_hw(dev);
3004
3005 cnic_put(dev);
3006 break;
3007 case CNIC_CTL_START_CMD:
3008 cnic_hold(dev);
3009
3010 if (!cnic_start_hw(dev))
3011 cnic_ulp_start(dev);
3012
3013 cnic_put(dev);
3014 break;
3015 case CNIC_CTL_COMPLETION_CMD: {
3016 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
3017 u32 l5_cid;
3018 struct cnic_local *cp = dev->cnic_priv;
3019
3020 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
3021 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3022
3023 ctx->wait_cond = 1;
3024 wake_up(&ctx->waitq);
3025 }
3026 break;
3027 }
3028 default:
3029 return -EINVAL;
3030 }
3031 return 0;
3032 }
3033
3034 static void cnic_ulp_init(struct cnic_dev *dev)
3035 {
3036 int i;
3037 struct cnic_local *cp = dev->cnic_priv;
3038
3039 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3040 struct cnic_ulp_ops *ulp_ops;
3041
3042 mutex_lock(&cnic_lock);
3043 ulp_ops = cnic_ulp_tbl[i];
3044 if (!ulp_ops || !ulp_ops->cnic_init) {
3045 mutex_unlock(&cnic_lock);
3046 continue;
3047 }
3048 ulp_get(ulp_ops);
3049 mutex_unlock(&cnic_lock);
3050
3051 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3052 ulp_ops->cnic_init(dev);
3053
3054 ulp_put(ulp_ops);
3055 }
3056 }
3057
3058 static void cnic_ulp_exit(struct cnic_dev *dev)
3059 {
3060 int i;
3061 struct cnic_local *cp = dev->cnic_priv;
3062
3063 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3064 struct cnic_ulp_ops *ulp_ops;
3065
3066 mutex_lock(&cnic_lock);
3067 ulp_ops = cnic_ulp_tbl[i];
3068 if (!ulp_ops || !ulp_ops->cnic_exit) {
3069 mutex_unlock(&cnic_lock);
3070 continue;
3071 }
3072 ulp_get(ulp_ops);
3073 mutex_unlock(&cnic_lock);
3074
3075 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3076 ulp_ops->cnic_exit(dev);
3077
3078 ulp_put(ulp_ops);
3079 }
3080 }
3081
3082 static int cnic_cm_offload_pg(struct cnic_sock *csk)
3083 {
3084 struct cnic_dev *dev = csk->dev;
3085 struct l4_kwq_offload_pg *l4kwqe;
3086 struct kwqe *wqes[1];
3087
3088 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
3089 memset(l4kwqe, 0, sizeof(*l4kwqe));
3090 wqes[0] = (struct kwqe *) l4kwqe;
3091
3092 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
3093 l4kwqe->flags =
3094 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
3095 l4kwqe->l2hdr_nbytes = ETH_HLEN;
3096
3097 l4kwqe->da0 = csk->ha[0];
3098 l4kwqe->da1 = csk->ha[1];
3099 l4kwqe->da2 = csk->ha[2];
3100 l4kwqe->da3 = csk->ha[3];
3101 l4kwqe->da4 = csk->ha[4];
3102 l4kwqe->da5 = csk->ha[5];
3103
3104 l4kwqe->sa0 = dev->mac_addr[0];
3105 l4kwqe->sa1 = dev->mac_addr[1];
3106 l4kwqe->sa2 = dev->mac_addr[2];
3107 l4kwqe->sa3 = dev->mac_addr[3];
3108 l4kwqe->sa4 = dev->mac_addr[4];
3109 l4kwqe->sa5 = dev->mac_addr[5];
3110
3111 l4kwqe->etype = ETH_P_IP;
3112 l4kwqe->ipid_start = DEF_IPID_START;
3113 l4kwqe->host_opaque = csk->l5_cid;
3114
3115 if (csk->vlan_id) {
3116 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
3117 l4kwqe->vlan_tag = csk->vlan_id;
3118 l4kwqe->l2hdr_nbytes += 4;
3119 }
3120
3121 return dev->submit_kwqes(dev, wqes, 1);
3122 }
3123
3124 static int cnic_cm_update_pg(struct cnic_sock *csk)
3125 {
3126 struct cnic_dev *dev = csk->dev;
3127 struct l4_kwq_update_pg *l4kwqe;
3128 struct kwqe *wqes[1];
3129
3130 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
3131 memset(l4kwqe, 0, sizeof(*l4kwqe));
3132 wqes[0] = (struct kwqe *) l4kwqe;
3133
3134 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
3135 l4kwqe->flags =
3136 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
3137 l4kwqe->pg_cid = csk->pg_cid;
3138
3139 l4kwqe->da0 = csk->ha[0];
3140 l4kwqe->da1 = csk->ha[1];
3141 l4kwqe->da2 = csk->ha[2];
3142 l4kwqe->da3 = csk->ha[3];
3143 l4kwqe->da4 = csk->ha[4];
3144 l4kwqe->da5 = csk->ha[5];
3145
3146 l4kwqe->pg_host_opaque = csk->l5_cid;
3147 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
3148
3149 return dev->submit_kwqes(dev, wqes, 1);
3150 }
3151
3152 static int cnic_cm_upload_pg(struct cnic_sock *csk)
3153 {
3154 struct cnic_dev *dev = csk->dev;
3155 struct l4_kwq_upload *l4kwqe;
3156 struct kwqe *wqes[1];
3157
3158 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
3159 memset(l4kwqe, 0, sizeof(*l4kwqe));
3160 wqes[0] = (struct kwqe *) l4kwqe;
3161
3162 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
3163 l4kwqe->flags =
3164 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
3165 l4kwqe->cid = csk->pg_cid;
3166
3167 return dev->submit_kwqes(dev, wqes, 1);
3168 }
3169
3170 static int cnic_cm_conn_req(struct cnic_sock *csk)
3171 {
3172 struct cnic_dev *dev = csk->dev;
3173 struct l4_kwq_connect_req1 *l4kwqe1;
3174 struct l4_kwq_connect_req2 *l4kwqe2;
3175 struct l4_kwq_connect_req3 *l4kwqe3;
3176 struct kwqe *wqes[3];
3177 u8 tcp_flags = 0;
3178 int num_wqes = 2;
3179
3180 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
3181 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
3182 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
3183 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
3184 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
3185 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
3186
3187 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
3188 l4kwqe3->flags =
3189 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
3190 l4kwqe3->ka_timeout = csk->ka_timeout;
3191 l4kwqe3->ka_interval = csk->ka_interval;
3192 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
3193 l4kwqe3->tos = csk->tos;
3194 l4kwqe3->ttl = csk->ttl;
3195 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
3196 l4kwqe3->pmtu = csk->mtu;
3197 l4kwqe3->rcv_buf = csk->rcv_buf;
3198 l4kwqe3->snd_buf = csk->snd_buf;
3199 l4kwqe3->seed = csk->seed;
3200
3201 wqes[0] = (struct kwqe *) l4kwqe1;
3202 if (test_bit(SK_F_IPV6, &csk->flags)) {
3203 wqes[1] = (struct kwqe *) l4kwqe2;
3204 wqes[2] = (struct kwqe *) l4kwqe3;
3205 num_wqes = 3;
3206
3207 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
3208 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
3209 l4kwqe2->flags =
3210 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
3211 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
3212 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
3213 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
3214 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
3215 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
3216 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
3217 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
3218 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
3219 sizeof(struct tcphdr);
3220 } else {
3221 wqes[1] = (struct kwqe *) l4kwqe3;
3222 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
3223 sizeof(struct tcphdr);
3224 }
3225
3226 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
3227 l4kwqe1->flags =
3228 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
3229 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
3230 l4kwqe1->cid = csk->cid;
3231 l4kwqe1->pg_cid = csk->pg_cid;
3232 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
3233 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
3234 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
3235 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
3236 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
3237 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
3238 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
3239 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
3240 if (csk->tcp_flags & SK_TCP_NAGLE)
3241 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
3242 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
3243 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
3244 if (csk->tcp_flags & SK_TCP_SACK)
3245 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
3246 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
3247 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
3248
3249 l4kwqe1->tcp_flags = tcp_flags;
3250
3251 return dev->submit_kwqes(dev, wqes, num_wqes);
3252 }
3253
3254 static int cnic_cm_close_req(struct cnic_sock *csk)
3255 {
3256 struct cnic_dev *dev = csk->dev;
3257 struct l4_kwq_close_req *l4kwqe;
3258 struct kwqe *wqes[1];
3259
3260 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
3261 memset(l4kwqe, 0, sizeof(*l4kwqe));
3262 wqes[0] = (struct kwqe *) l4kwqe;
3263
3264 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
3265 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
3266 l4kwqe->cid = csk->cid;
3267
3268 return dev->submit_kwqes(dev, wqes, 1);
3269 }
3270
3271 static int cnic_cm_abort_req(struct cnic_sock *csk)
3272 {
3273 struct cnic_dev *dev = csk->dev;
3274 struct l4_kwq_reset_req *l4kwqe;
3275 struct kwqe *wqes[1];
3276
3277 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
3278 memset(l4kwqe, 0, sizeof(*l4kwqe));
3279 wqes[0] = (struct kwqe *) l4kwqe;
3280
3281 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
3282 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
3283 l4kwqe->cid = csk->cid;
3284
3285 return dev->submit_kwqes(dev, wqes, 1);
3286 }
3287
3288 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
3289 u32 l5_cid, struct cnic_sock **csk, void *context)
3290 {
3291 struct cnic_local *cp = dev->cnic_priv;
3292 struct cnic_sock *csk1;
3293
3294 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3295 return -EINVAL;
3296
3297 if (cp->ctx_tbl) {
3298 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3299
3300 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3301 return -EAGAIN;
3302 }
3303
3304 csk1 = &cp->csk_tbl[l5_cid];
3305 if (atomic_read(&csk1->ref_count))
3306 return -EAGAIN;
3307
3308 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
3309 return -EBUSY;
3310
3311 csk1->dev = dev;
3312 csk1->cid = cid;
3313 csk1->l5_cid = l5_cid;
3314 csk1->ulp_type = ulp_type;
3315 csk1->context = context;
3316
3317 csk1->ka_timeout = DEF_KA_TIMEOUT;
3318 csk1->ka_interval = DEF_KA_INTERVAL;
3319 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
3320 csk1->tos = DEF_TOS;
3321 csk1->ttl = DEF_TTL;
3322 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
3323 csk1->rcv_buf = DEF_RCV_BUF;
3324 csk1->snd_buf = DEF_SND_BUF;
3325 csk1->seed = DEF_SEED;
3326
3327 *csk = csk1;
3328 return 0;
3329 }
3330
3331 static void cnic_cm_cleanup(struct cnic_sock *csk)
3332 {
3333 if (csk->src_port) {
3334 struct cnic_dev *dev = csk->dev;
3335 struct cnic_local *cp = dev->cnic_priv;
3336
3337 cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
3338 csk->src_port = 0;
3339 }
3340 }
3341
3342 static void cnic_close_conn(struct cnic_sock *csk)
3343 {
3344 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
3345 cnic_cm_upload_pg(csk);
3346 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3347 }
3348 cnic_cm_cleanup(csk);
3349 }
3350
3351 static int cnic_cm_destroy(struct cnic_sock *csk)
3352 {
3353 if (!cnic_in_use(csk))
3354 return -EINVAL;
3355
3356 csk_hold(csk);
3357 clear_bit(SK_F_INUSE, &csk->flags);
3358 smp_mb__after_clear_bit();
3359 while (atomic_read(&csk->ref_count) != 1)
3360 msleep(1);
3361 cnic_cm_cleanup(csk);
3362
3363 csk->flags = 0;
3364 csk_put(csk);
3365 return 0;
3366 }
3367
3368 static inline u16 cnic_get_vlan(struct net_device *dev,
3369 struct net_device **vlan_dev)
3370 {
3371 if (dev->priv_flags & IFF_802_1Q_VLAN) {
3372 *vlan_dev = vlan_dev_real_dev(dev);
3373 return vlan_dev_vlan_id(dev);
3374 }
3375 *vlan_dev = dev;
3376 return 0;
3377 }
3378
3379 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
3380 struct dst_entry **dst)
3381 {
3382 #if defined(CONFIG_INET)
3383 struct flowi fl;
3384 int err;
3385 struct rtable *rt;
3386
3387 memset(&fl, 0, sizeof(fl));
3388 fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
3389
3390 err = ip_route_output_key(&init_net, &rt, &fl);
3391 if (!err)
3392 *dst = &rt->dst;
3393 return err;
3394 #else
3395 return -ENETUNREACH;
3396 #endif
3397 }
3398
3399 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
3400 struct dst_entry **dst)
3401 {
3402 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
3403 struct flowi fl;
3404
3405 memset(&fl, 0, sizeof(fl));
3406 ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
3407 if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
3408 fl.oif = dst_addr->sin6_scope_id;
3409
3410 *dst = ip6_route_output(&init_net, NULL, &fl);
3411 if (*dst)
3412 return 0;
3413 #endif
3414
3415 return -ENETUNREACH;
3416 }
3417
3418 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
3419 int ulp_type)
3420 {
3421 struct cnic_dev *dev = NULL;
3422 struct dst_entry *dst;
3423 struct net_device *netdev = NULL;
3424 int err = -ENETUNREACH;
3425
3426 if (dst_addr->sin_family == AF_INET)
3427 err = cnic_get_v4_route(dst_addr, &dst);
3428 else if (dst_addr->sin_family == AF_INET6) {
3429 struct sockaddr_in6 *dst_addr6 =
3430 (struct sockaddr_in6 *) dst_addr;
3431
3432 err = cnic_get_v6_route(dst_addr6, &dst);
3433 } else
3434 return NULL;
3435
3436 if (err)
3437 return NULL;
3438
3439 if (!dst->dev)
3440 goto done;
3441
3442 cnic_get_vlan(dst->dev, &netdev);
3443
3444 dev = cnic_from_netdev(netdev);
3445
3446 done:
3447 dst_release(dst);
3448 if (dev)
3449 cnic_put(dev);
3450 return dev;
3451 }
3452
3453 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3454 {
3455 struct cnic_dev *dev = csk->dev;
3456 struct cnic_local *cp = dev->cnic_priv;
3457
3458 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
3459 }
3460
3461 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3462 {
3463 struct cnic_dev *dev = csk->dev;
3464 struct cnic_local *cp = dev->cnic_priv;
3465 int is_v6, rc = 0;
3466 struct dst_entry *dst = NULL;
3467 struct net_device *realdev;
3468 __be16 local_port;
3469 u32 port_id;
3470
3471 if (saddr->local.v6.sin6_family == AF_INET6 &&
3472 saddr->remote.v6.sin6_family == AF_INET6)
3473 is_v6 = 1;
3474 else if (saddr->local.v4.sin_family == AF_INET &&
3475 saddr->remote.v4.sin_family == AF_INET)
3476 is_v6 = 0;
3477 else
3478 return -EINVAL;
3479
3480 clear_bit(SK_F_IPV6, &csk->flags);
3481
3482 if (is_v6) {
3483 set_bit(SK_F_IPV6, &csk->flags);
3484 cnic_get_v6_route(&saddr->remote.v6, &dst);
3485
3486 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
3487 sizeof(struct in6_addr));
3488 csk->dst_port = saddr->remote.v6.sin6_port;
3489 local_port = saddr->local.v6.sin6_port;
3490
3491 } else {
3492 cnic_get_v4_route(&saddr->remote.v4, &dst);
3493
3494 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
3495 csk->dst_port = saddr->remote.v4.sin_port;
3496 local_port = saddr->local.v4.sin_port;
3497 }
3498
3499 csk->vlan_id = 0;
3500 csk->mtu = dev->netdev->mtu;
3501 if (dst && dst->dev) {
3502 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3503 if (realdev == dev->netdev) {
3504 csk->vlan_id = vlan;
3505 csk->mtu = dst_mtu(dst);
3506 }
3507 }
3508
3509 port_id = be16_to_cpu(local_port);
3510 if (port_id >= CNIC_LOCAL_PORT_MIN &&
3511 port_id < CNIC_LOCAL_PORT_MAX) {
3512 if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
3513 port_id = 0;
3514 } else
3515 port_id = 0;
3516
3517 if (!port_id) {
3518 port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
3519 if (port_id == -1) {
3520 rc = -ENOMEM;
3521 goto err_out;
3522 }
3523 local_port = cpu_to_be16(port_id);
3524 }
3525 csk->src_port = local_port;
3526
3527 err_out:
3528 dst_release(dst);
3529 return rc;
3530 }
3531
3532 static void cnic_init_csk_state(struct cnic_sock *csk)
3533 {
3534 csk->state = 0;
3535 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3536 clear_bit(SK_F_CLOSING, &csk->flags);
3537 }
3538
3539 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3540 {
3541 int err = 0;
3542
3543 if (!cnic_in_use(csk))
3544 return -EINVAL;
3545
3546 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3547 return -EINVAL;
3548
3549 cnic_init_csk_state(csk);
3550
3551 err = cnic_get_route(csk, saddr);
3552 if (err)
3553 goto err_out;
3554
3555 err = cnic_resolve_addr(csk, saddr);
3556 if (!err)
3557 return 0;
3558
3559 err_out:
3560 clear_bit(SK_F_CONNECT_START, &csk->flags);
3561 return err;
3562 }
3563
3564 static int cnic_cm_abort(struct cnic_sock *csk)
3565 {
3566 struct cnic_local *cp = csk->dev->cnic_priv;
3567 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3568
3569 if (!cnic_in_use(csk))
3570 return -EINVAL;
3571
3572 if (cnic_abort_prep(csk))
3573 return cnic_cm_abort_req(csk);
3574
3575 /* Getting here means that we haven't started connect, or
3576 * connect was not successful.
3577 */
3578
3579 cp->close_conn(csk, opcode);
3580 if (csk->state != opcode)
3581 return -EALREADY;
3582
3583 return 0;
3584 }
3585
3586 static int cnic_cm_close(struct cnic_sock *csk)
3587 {
3588 if (!cnic_in_use(csk))
3589 return -EINVAL;
3590
3591 if (cnic_close_prep(csk)) {
3592 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3593 return cnic_cm_close_req(csk);
3594 } else {
3595 return -EALREADY;
3596 }
3597 return 0;
3598 }
3599
3600 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3601 u8 opcode)
3602 {
3603 struct cnic_ulp_ops *ulp_ops;
3604 int ulp_type = csk->ulp_type;
3605
3606 rcu_read_lock();
3607 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3608 if (ulp_ops) {
3609 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3610 ulp_ops->cm_connect_complete(csk);
3611 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3612 ulp_ops->cm_close_complete(csk);
3613 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3614 ulp_ops->cm_remote_abort(csk);
3615 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3616 ulp_ops->cm_abort_complete(csk);
3617 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3618 ulp_ops->cm_remote_close(csk);
3619 }
3620 rcu_read_unlock();
3621 }
3622
3623 static int cnic_cm_set_pg(struct cnic_sock *csk)
3624 {
3625 if (cnic_offld_prep(csk)) {
3626 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3627 cnic_cm_update_pg(csk);
3628 else
3629 cnic_cm_offload_pg(csk);
3630 }
3631 return 0;
3632 }
3633
3634 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3635 {
3636 struct cnic_local *cp = dev->cnic_priv;
3637 u32 l5_cid = kcqe->pg_host_opaque;
3638 u8 opcode = kcqe->op_code;
3639 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3640
3641 csk_hold(csk);
3642 if (!cnic_in_use(csk))
3643 goto done;
3644
3645 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3646 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3647 goto done;
3648 }
3649 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3650 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3651 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3652 cnic_cm_upcall(cp, csk,
3653 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3654 goto done;
3655 }
3656
3657 csk->pg_cid = kcqe->pg_cid;
3658 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3659 cnic_cm_conn_req(csk);
3660
3661 done:
3662 csk_put(csk);
3663 }
3664
3665 static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
3666 {
3667 struct cnic_local *cp = dev->cnic_priv;
3668 struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
3669 u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
3670 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3671
3672 ctx->timestamp = jiffies;
3673 ctx->wait_cond = 1;
3674 wake_up(&ctx->waitq);
3675 }
3676
3677 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3678 {
3679 struct cnic_local *cp = dev->cnic_priv;
3680 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3681 u8 opcode = l4kcqe->op_code;
3682 u32 l5_cid;
3683 struct cnic_sock *csk;
3684
3685 if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
3686 cnic_process_fcoe_term_conn(dev, kcqe);
3687 return;
3688 }
3689 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3690 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3691 cnic_cm_process_offld_pg(dev, l4kcqe);
3692 return;
3693 }
3694
3695 l5_cid = l4kcqe->conn_id;
3696 if (opcode & 0x80)
3697 l5_cid = l4kcqe->cid;
3698 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3699 return;
3700
3701 csk = &cp->csk_tbl[l5_cid];
3702 csk_hold(csk);
3703
3704 if (!cnic_in_use(csk)) {
3705 csk_put(csk);
3706 return;
3707 }
3708
3709 switch (opcode) {
3710 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3711 if (l4kcqe->status != 0) {
3712 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3713 cnic_cm_upcall(cp, csk,
3714 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3715 }
3716 break;
3717 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3718 if (l4kcqe->status == 0)
3719 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3720
3721 smp_mb__before_clear_bit();
3722 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3723 cnic_cm_upcall(cp, csk, opcode);
3724 break;
3725
3726 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3727 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3728 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3729 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3730 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3731 cp->close_conn(csk, opcode);
3732 break;
3733
3734 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3735 cnic_cm_upcall(cp, csk, opcode);
3736 break;
3737 }
3738 csk_put(csk);
3739 }
3740
3741 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3742 {
3743 struct cnic_dev *dev = data;
3744 int i;
3745
3746 for (i = 0; i < num; i++)
3747 cnic_cm_process_kcqe(dev, kcqe[i]);
3748 }
3749
3750 static struct cnic_ulp_ops cm_ulp_ops = {
3751 .indicate_kcqes = cnic_cm_indicate_kcqe,
3752 };
3753
3754 static void cnic_cm_free_mem(struct cnic_dev *dev)
3755 {
3756 struct cnic_local *cp = dev->cnic_priv;
3757
3758 kfree(cp->csk_tbl);
3759 cp->csk_tbl = NULL;
3760 cnic_free_id_tbl(&cp->csk_port_tbl);
3761 }
3762
3763 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3764 {
3765 struct cnic_local *cp = dev->cnic_priv;
3766
3767 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3768 GFP_KERNEL);
3769 if (!cp->csk_tbl)
3770 return -ENOMEM;
3771
3772 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3773 CNIC_LOCAL_PORT_MIN)) {
3774 cnic_cm_free_mem(dev);
3775 return -ENOMEM;
3776 }
3777 return 0;
3778 }
3779
3780 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3781 {
3782 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
3783 /* Unsolicited RESET_COMP or RESET_RECEIVED */
3784 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3785 csk->state = opcode;
3786 }
3787
3788 /* 1. If event opcode matches the expected event in csk->state
3789 * 2. If the expected event is CLOSE_COMP, we accept any event
3790 * 3. If the expected event is 0, meaning the connection was never
3791 * never established, we accept the opcode from cm_abort.
3792 */
3793 if (opcode == csk->state || csk->state == 0 ||
3794 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
3795 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3796 if (csk->state == 0)
3797 csk->state = opcode;
3798 return 1;
3799 }
3800 }
3801 return 0;
3802 }
3803
3804 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3805 {
3806 struct cnic_dev *dev = csk->dev;
3807 struct cnic_local *cp = dev->cnic_priv;
3808
3809 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
3810 cnic_cm_upcall(cp, csk, opcode);
3811 return;
3812 }
3813
3814 clear_bit(SK_F_CONNECT_START, &csk->flags);
3815 cnic_close_conn(csk);
3816 csk->state = opcode;
3817 cnic_cm_upcall(cp, csk, opcode);
3818 }
3819
3820 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3821 {
3822 }
3823
3824 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3825 {
3826 u32 seed;
3827
3828 get_random_bytes(&seed, 4);
3829 cnic_ctx_wr(dev, 45, 0, seed);
3830 return 0;
3831 }
3832
3833 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3834 {
3835 struct cnic_dev *dev = csk->dev;
3836 struct cnic_local *cp = dev->cnic_priv;
3837 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3838 union l5cm_specific_data l5_data;
3839 u32 cmd = 0;
3840 int close_complete = 0;
3841
3842 switch (opcode) {
3843 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3844 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3845 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3846 if (cnic_ready_to_close(csk, opcode)) {
3847 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3848 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3849 else
3850 close_complete = 1;
3851 }
3852 break;
3853 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3854 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3855 break;
3856 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3857 close_complete = 1;
3858 break;
3859 }
3860 if (cmd) {
3861 memset(&l5_data, 0, sizeof(l5_data));
3862
3863 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3864 &l5_data);
3865 } else if (close_complete) {
3866 ctx->timestamp = jiffies;
3867 cnic_close_conn(csk);
3868 cnic_cm_upcall(cp, csk, csk->state);
3869 }
3870 }
3871
3872 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3873 {
3874 struct cnic_local *cp = dev->cnic_priv;
3875 int i;
3876
3877 if (!cp->ctx_tbl)
3878 return;
3879
3880 if (!netif_running(dev->netdev))
3881 return;
3882
3883 for (i = 0; i < cp->max_cid_space; i++) {
3884 struct cnic_context *ctx = &cp->ctx_tbl[i];
3885
3886 while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3887 msleep(10);
3888
3889 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3890 netdev_warn(dev->netdev, "CID %x not deleted\n",
3891 ctx->cid);
3892 }
3893
3894 cancel_delayed_work(&cp->delete_task);
3895 flush_workqueue(cnic_wq);
3896
3897 if (atomic_read(&cp->iscsi_conn) != 0)
3898 netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
3899 atomic_read(&cp->iscsi_conn));
3900 }
3901
3902 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3903 {
3904 struct cnic_local *cp = dev->cnic_priv;
3905 u32 pfid = cp->pfid;
3906 u32 port = CNIC_PORT(cp);
3907
3908 cnic_init_bnx2x_mac(dev);
3909 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3910
3911 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3912 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
3913
3914 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3915 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
3916 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3917 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
3918 DEF_MAX_DA_COUNT);
3919
3920 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3921 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
3922 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3923 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
3924 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3925 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
3926 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3927 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
3928
3929 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
3930 DEF_MAX_CWND);
3931 return 0;
3932 }
3933
3934 static void cnic_delete_task(struct work_struct *work)
3935 {
3936 struct cnic_local *cp;
3937 struct cnic_dev *dev;
3938 u32 i;
3939 int need_resched = 0;
3940
3941 cp = container_of(work, struct cnic_local, delete_task.work);
3942 dev = cp->dev;
3943
3944 for (i = 0; i < cp->max_cid_space; i++) {
3945 struct cnic_context *ctx = &cp->ctx_tbl[i];
3946
3947 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
3948 !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3949 continue;
3950
3951 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
3952 need_resched = 1;
3953 continue;
3954 }
3955
3956 if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3957 continue;
3958
3959 cnic_bnx2x_destroy_ramrod(dev, i);
3960
3961 cnic_free_bnx2x_conn_resc(dev, i);
3962 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
3963 atomic_dec(&cp->iscsi_conn);
3964
3965 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
3966 }
3967
3968 if (need_resched)
3969 queue_delayed_work(cnic_wq, &cp->delete_task,
3970 msecs_to_jiffies(10));
3971
3972 }
3973
3974 static int cnic_cm_open(struct cnic_dev *dev)
3975 {
3976 struct cnic_local *cp = dev->cnic_priv;
3977 int err;
3978
3979 err = cnic_cm_alloc_mem(dev);
3980 if (err)
3981 return err;
3982
3983 err = cp->start_cm(dev);
3984
3985 if (err)
3986 goto err_out;
3987
3988 INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
3989
3990 dev->cm_create = cnic_cm_create;
3991 dev->cm_destroy = cnic_cm_destroy;
3992 dev->cm_connect = cnic_cm_connect;
3993 dev->cm_abort = cnic_cm_abort;
3994 dev->cm_close = cnic_cm_close;
3995 dev->cm_select_dev = cnic_cm_select_dev;
3996
3997 cp->ulp_handle[CNIC_ULP_L4] = dev;
3998 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
3999 return 0;
4000
4001 err_out:
4002 cnic_cm_free_mem(dev);
4003 return err;
4004 }
4005
4006 static int cnic_cm_shutdown(struct cnic_dev *dev)
4007 {
4008 struct cnic_local *cp = dev->cnic_priv;
4009 int i;
4010
4011 cp->stop_cm(dev);
4012
4013 if (!cp->csk_tbl)
4014 return 0;
4015
4016 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
4017 struct cnic_sock *csk = &cp->csk_tbl[i];
4018
4019 clear_bit(SK_F_INUSE, &csk->flags);
4020 cnic_cm_cleanup(csk);
4021 }
4022 cnic_cm_free_mem(dev);
4023
4024 return 0;
4025 }
4026
4027 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
4028 {
4029 u32 cid_addr;
4030 int i;
4031
4032 cid_addr = GET_CID_ADDR(cid);
4033
4034 for (i = 0; i < CTX_SIZE; i += 4)
4035 cnic_ctx_wr(dev, cid_addr, i, 0);
4036 }
4037
4038 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
4039 {
4040 struct cnic_local *cp = dev->cnic_priv;
4041 int ret = 0, i;
4042 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
4043
4044 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4045 return 0;
4046
4047 for (i = 0; i < cp->ctx_blks; i++) {
4048 int j;
4049 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
4050 u32 val;
4051
4052 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
4053
4054 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
4055 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
4056 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
4057 (u64) cp->ctx_arr[i].mapping >> 32);
4058 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
4059 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4060 for (j = 0; j < 10; j++) {
4061
4062 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
4063 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
4064 break;
4065 udelay(5);
4066 }
4067 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
4068 ret = -EBUSY;
4069 break;
4070 }
4071 }
4072 return ret;
4073 }
4074
4075 static void cnic_free_irq(struct cnic_dev *dev)
4076 {
4077 struct cnic_local *cp = dev->cnic_priv;
4078 struct cnic_eth_dev *ethdev = cp->ethdev;
4079
4080 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4081 cp->disable_int_sync(dev);
4082 tasklet_kill(&cp->cnic_irq_task);
4083 free_irq(ethdev->irq_arr[0].vector, dev);
4084 }
4085 }
4086
4087 static int cnic_request_irq(struct cnic_dev *dev)
4088 {
4089 struct cnic_local *cp = dev->cnic_priv;
4090 struct cnic_eth_dev *ethdev = cp->ethdev;
4091 int err;
4092
4093 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
4094 if (err)
4095 tasklet_disable(&cp->cnic_irq_task);
4096
4097 return err;
4098 }
4099
4100 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
4101 {
4102 struct cnic_local *cp = dev->cnic_priv;
4103 struct cnic_eth_dev *ethdev = cp->ethdev;
4104
4105 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4106 int err, i = 0;
4107 int sblk_num = cp->status_blk_num;
4108 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4109 BNX2_HC_SB_CONFIG_1;
4110
4111 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4112
4113 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
4114 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
4115 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
4116
4117 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
4118 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
4119 (unsigned long) dev);
4120 err = cnic_request_irq(dev);
4121 if (err)
4122 return err;
4123
4124 while (cp->status_blk.bnx2->status_completion_producer_index &&
4125 i < 10) {
4126 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
4127 1 << (11 + sblk_num));
4128 udelay(10);
4129 i++;
4130 barrier();
4131 }
4132 if (cp->status_blk.bnx2->status_completion_producer_index) {
4133 cnic_free_irq(dev);
4134 goto failed;
4135 }
4136
4137 } else {
4138 struct status_block *sblk = cp->status_blk.gen;
4139 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
4140 int i = 0;
4141
4142 while (sblk->status_completion_producer_index && i < 10) {
4143 CNIC_WR(dev, BNX2_HC_COMMAND,
4144 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4145 udelay(10);
4146 i++;
4147 barrier();
4148 }
4149 if (sblk->status_completion_producer_index)
4150 goto failed;
4151
4152 }
4153 return 0;
4154
4155 failed:
4156 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
4157 return -EBUSY;
4158 }
4159
4160 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
4161 {
4162 struct cnic_local *cp = dev->cnic_priv;
4163 struct cnic_eth_dev *ethdev = cp->ethdev;
4164
4165 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4166 return;
4167
4168 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4169 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
4170 }
4171
4172 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
4173 {
4174 struct cnic_local *cp = dev->cnic_priv;
4175 struct cnic_eth_dev *ethdev = cp->ethdev;
4176
4177 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4178 return;
4179
4180 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4181 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4182 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
4183 synchronize_irq(ethdev->irq_arr[0].vector);
4184 }
4185
4186 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
4187 {
4188 struct cnic_local *cp = dev->cnic_priv;
4189 struct cnic_eth_dev *ethdev = cp->ethdev;
4190 struct cnic_uio_dev *udev = cp->udev;
4191 u32 cid_addr, tx_cid, sb_id;
4192 u32 val, offset0, offset1, offset2, offset3;
4193 int i;
4194 struct tx_bd *txbd;
4195 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4196 struct status_block *s_blk = cp->status_blk.gen;
4197
4198 sb_id = cp->status_blk_num;
4199 tx_cid = 20;
4200 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
4201 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4202 struct status_block_msix *sblk = cp->status_blk.bnx2;
4203
4204 tx_cid = TX_TSS_CID + sb_id - 1;
4205 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
4206 (TX_TSS_CID << 7));
4207 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
4208 }
4209 cp->tx_cons = *cp->tx_cons_ptr;
4210
4211 cid_addr = GET_CID_ADDR(tx_cid);
4212 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
4213 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
4214
4215 for (i = 0; i < PHY_CTX_SIZE; i += 4)
4216 cnic_ctx_wr(dev, cid_addr2, i, 0);
4217
4218 offset0 = BNX2_L2CTX_TYPE_XI;
4219 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4220 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4221 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4222 } else {
4223 cnic_init_context(dev, tx_cid);
4224 cnic_init_context(dev, tx_cid + 1);
4225
4226 offset0 = BNX2_L2CTX_TYPE;
4227 offset1 = BNX2_L2CTX_CMD_TYPE;
4228 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4229 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4230 }
4231 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4232 cnic_ctx_wr(dev, cid_addr, offset0, val);
4233
4234 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4235 cnic_ctx_wr(dev, cid_addr, offset1, val);
4236
4237 txbd = (struct tx_bd *) udev->l2_ring;
4238
4239 buf_map = udev->l2_buf_map;
4240 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
4241 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
4242 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4243 }
4244 val = (u64) ring_map >> 32;
4245 cnic_ctx_wr(dev, cid_addr, offset2, val);
4246 txbd->tx_bd_haddr_hi = val;
4247
4248 val = (u64) ring_map & 0xffffffff;
4249 cnic_ctx_wr(dev, cid_addr, offset3, val);
4250 txbd->tx_bd_haddr_lo = val;
4251 }
4252
4253 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
4254 {
4255 struct cnic_local *cp = dev->cnic_priv;
4256 struct cnic_eth_dev *ethdev = cp->ethdev;
4257 struct cnic_uio_dev *udev = cp->udev;
4258 u32 cid_addr, sb_id, val, coal_reg, coal_val;
4259 int i;
4260 struct rx_bd *rxbd;
4261 struct status_block *s_blk = cp->status_blk.gen;
4262 dma_addr_t ring_map = udev->l2_ring_map;
4263
4264 sb_id = cp->status_blk_num;
4265 cnic_init_context(dev, 2);
4266 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
4267 coal_reg = BNX2_HC_COMMAND;
4268 coal_val = CNIC_RD(dev, coal_reg);
4269 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4270 struct status_block_msix *sblk = cp->status_blk.bnx2;
4271
4272 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
4273 coal_reg = BNX2_HC_COALESCE_NOW;
4274 coal_val = 1 << (11 + sb_id);
4275 }
4276 i = 0;
4277 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
4278 CNIC_WR(dev, coal_reg, coal_val);
4279 udelay(10);
4280 i++;
4281 barrier();
4282 }
4283 cp->rx_cons = *cp->rx_cons_ptr;
4284
4285 cid_addr = GET_CID_ADDR(2);
4286 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4287 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4288 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4289
4290 if (sb_id == 0)
4291 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
4292 else
4293 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
4294 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
4295
4296 rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
4297 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
4298 dma_addr_t buf_map;
4299 int n = (i % cp->l2_rx_ring_size) + 1;
4300
4301 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4302 rxbd->rx_bd_len = cp->l2_single_buf_size;
4303 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4304 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
4305 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4306 }
4307 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4308 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4309 rxbd->rx_bd_haddr_hi = val;
4310
4311 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4312 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4313 rxbd->rx_bd_haddr_lo = val;
4314
4315 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
4316 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
4317 }
4318
4319 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
4320 {
4321 struct kwqe *wqes[1], l2kwqe;
4322
4323 memset(&l2kwqe, 0, sizeof(l2kwqe));
4324 wqes[0] = &l2kwqe;
4325 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
4326 (L2_KWQE_OPCODE_VALUE_FLUSH <<
4327 KWQE_OPCODE_SHIFT) | 2;
4328 dev->submit_kwqes(dev, wqes, 1);
4329 }
4330
4331 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
4332 {
4333 struct cnic_local *cp = dev->cnic_priv;
4334 u32 val;
4335
4336 val = cp->func << 2;
4337
4338 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
4339
4340 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4341 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
4342 dev->mac_addr[0] = (u8) (val >> 8);
4343 dev->mac_addr[1] = (u8) val;
4344
4345 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
4346
4347 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4348 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
4349 dev->mac_addr[2] = (u8) (val >> 24);
4350 dev->mac_addr[3] = (u8) (val >> 16);
4351 dev->mac_addr[4] = (u8) (val >> 8);
4352 dev->mac_addr[5] = (u8) val;
4353
4354 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
4355
4356 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
4357 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4358 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
4359
4360 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
4361 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
4362 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
4363 }
4364
4365 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
4366 {
4367 struct cnic_local *cp = dev->cnic_priv;
4368 struct cnic_eth_dev *ethdev = cp->ethdev;
4369 struct status_block *sblk = cp->status_blk.gen;
4370 u32 val, kcq_cid_addr, kwq_cid_addr;
4371 int err;
4372
4373 cnic_set_bnx2_mac(dev);
4374
4375 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
4376 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4377 if (BCM_PAGE_BITS > 12)
4378 val |= (12 - 8) << 4;
4379 else
4380 val |= (BCM_PAGE_BITS - 8) << 4;
4381
4382 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
4383
4384 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
4385 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
4386 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
4387
4388 err = cnic_setup_5709_context(dev, 1);
4389 if (err)
4390 return err;
4391
4392 cnic_init_context(dev, KWQ_CID);
4393 cnic_init_context(dev, KCQ_CID);
4394
4395 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
4396 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
4397
4398 cp->max_kwq_idx = MAX_KWQ_IDX;
4399 cp->kwq_prod_idx = 0;
4400 cp->kwq_con_idx = 0;
4401 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
4402
4403 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
4404 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
4405 else
4406 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
4407
4408 /* Initialize the kernel work queue context. */
4409 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4410 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4411 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
4412
4413 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
4414 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4415
4416 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
4417 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4418
4419 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
4420 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4421
4422 val = (u32) cp->kwq_info.pgtbl_map;
4423 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4424
4425 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
4426 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
4427
4428 cp->kcq1.sw_prod_idx = 0;
4429 cp->kcq1.hw_prod_idx_ptr =
4430 (u16 *) &sblk->status_completion_producer_index;
4431
4432 cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
4433
4434 /* Initialize the kernel complete queue context. */
4435 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4436 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4437 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
4438
4439 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
4440 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4441
4442 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
4443 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4444
4445 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
4446 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4447
4448 val = (u32) cp->kcq1.dma.pgtbl_map;
4449 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4450
4451 cp->int_num = 0;
4452 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4453 struct status_block_msix *msblk = cp->status_blk.bnx2;
4454 u32 sb_id = cp->status_blk_num;
4455 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
4456
4457 cp->kcq1.hw_prod_idx_ptr =
4458 (u16 *) &msblk->status_completion_producer_index;
4459 cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
4460 cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
4461 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
4462 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4463 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4464 }
4465
4466 /* Enable Commnad Scheduler notification when we write to the
4467 * host producer index of the kernel contexts. */
4468 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
4469
4470 /* Enable Command Scheduler notification when we write to either
4471 * the Send Queue or Receive Queue producer indexes of the kernel
4472 * bypass contexts. */
4473 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
4474 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
4475
4476 /* Notify COM when the driver post an application buffer. */
4477 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
4478
4479 /* Set the CP and COM doorbells. These two processors polls the
4480 * doorbell for a non zero value before running. This must be done
4481 * after setting up the kernel queue contexts. */
4482 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
4483 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
4484
4485 cnic_init_bnx2_tx_ring(dev);
4486 cnic_init_bnx2_rx_ring(dev);
4487
4488 err = cnic_init_bnx2_irq(dev);
4489 if (err) {
4490 netdev_err(dev->netdev, "cnic_init_irq failed\n");
4491 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4492 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4493 return err;
4494 }
4495
4496 return 0;
4497 }
4498
4499 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
4500 {
4501 struct cnic_local *cp = dev->cnic_priv;
4502 struct cnic_eth_dev *ethdev = cp->ethdev;
4503 u32 start_offset = ethdev->ctx_tbl_offset;
4504 int i;
4505
4506 for (i = 0; i < cp->ctx_blks; i++) {
4507 struct cnic_ctx *ctx = &cp->ctx_arr[i];
4508 dma_addr_t map = ctx->mapping;
4509
4510 if (cp->ctx_align) {
4511 unsigned long mask = cp->ctx_align - 1;
4512
4513 map = (map + mask) & ~mask;
4514 }
4515
4516 cnic_ctx_tbl_wr(dev, start_offset + i, map);
4517 }
4518 }
4519
4520 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4521 {
4522 struct cnic_local *cp = dev->cnic_priv;
4523 struct cnic_eth_dev *ethdev = cp->ethdev;
4524 int err = 0;
4525
4526 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
4527 (unsigned long) dev);
4528 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4529 err = cnic_request_irq(dev);
4530
4531 return err;
4532 }
4533
4534 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4535 u16 sb_id, u8 sb_index,
4536 u8 disable)
4537 {
4538
4539 u32 addr = BAR_CSTRORM_INTMEM +
4540 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4541 offsetof(struct hc_status_block_data_e1x, index_data) +
4542 sizeof(struct hc_index_data)*sb_index +
4543 offsetof(struct hc_index_data, flags);
4544 u16 flags = CNIC_RD16(dev, addr);
4545 /* clear and set */
4546 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4547 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4548 HC_INDEX_DATA_HC_ENABLED);
4549 CNIC_WR16(dev, addr, flags);
4550 }
4551
4552 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4553 {
4554 struct cnic_local *cp = dev->cnic_priv;
4555 u8 sb_id = cp->status_blk_num;
4556
4557 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4558 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4559 offsetof(struct hc_status_block_data_e1x, index_data) +
4560 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4561 offsetof(struct hc_index_data, timeout), 64 / 12);
4562 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4563 }
4564
4565 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4566 {
4567 }
4568
4569 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4570 struct client_init_ramrod_data *data)
4571 {
4572 struct cnic_local *cp = dev->cnic_priv;
4573 struct cnic_uio_dev *udev = cp->udev;
4574 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4575 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4576 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4577 int port = CNIC_PORT(cp);
4578 int i;
4579 u32 cli = cp->ethdev->iscsi_l2_client_id;
4580 u32 val;
4581
4582 memset(txbd, 0, BCM_PAGE_SIZE);
4583
4584 buf_map = udev->l2_buf_map;
4585 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4586 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4587 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4588
4589 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4590 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4591 reg_bd->addr_hi = start_bd->addr_hi;
4592 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4593 start_bd->nbytes = cpu_to_le16(0x10);
4594 start_bd->nbd = cpu_to_le16(3);
4595 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4596 start_bd->general_data = (UNICAST_ADDRESS <<
4597 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
4598 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4599
4600 }
4601
4602 val = (u64) ring_map >> 32;
4603 txbd->next_bd.addr_hi = cpu_to_le32(val);
4604
4605 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4606
4607 val = (u64) ring_map & 0xffffffff;
4608 txbd->next_bd.addr_lo = cpu_to_le32(val);
4609
4610 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4611
4612 /* Other ramrod params */
4613 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4614 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4615
4616 /* reset xstorm per client statistics */
4617 if (cli < MAX_STAT_COUNTER_ID) {
4618 val = BAR_XSTRORM_INTMEM +
4619 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4620 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
4621 CNIC_WR(dev, val + i * 4, 0);
4622 }
4623
4624 cp->tx_cons_ptr =
4625 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4626 }
4627
4628 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4629 struct client_init_ramrod_data *data)
4630 {
4631 struct cnic_local *cp = dev->cnic_priv;
4632 struct cnic_uio_dev *udev = cp->udev;
4633 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4634 BCM_PAGE_SIZE);
4635 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4636 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
4637 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4638 int i;
4639 int port = CNIC_PORT(cp);
4640 u32 cli = cp->ethdev->iscsi_l2_client_id;
4641 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4642 u32 val;
4643 dma_addr_t ring_map = udev->l2_ring_map;
4644
4645 /* General data */
4646 data->general.client_id = cli;
4647 data->general.statistics_en_flg = 1;
4648 data->general.statistics_counter_id = cli;
4649 data->general.activate_flg = 1;
4650 data->general.sp_client_id = cli;
4651
4652 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
4653 dma_addr_t buf_map;
4654 int n = (i % cp->l2_rx_ring_size) + 1;
4655
4656 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4657 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4658 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4659 }
4660
4661 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4662 rxbd->addr_hi = cpu_to_le32(val);
4663 data->rx.bd_page_base.hi = cpu_to_le32(val);
4664
4665 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4666 rxbd->addr_lo = cpu_to_le32(val);
4667 data->rx.bd_page_base.lo = cpu_to_le32(val);
4668
4669 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
4670 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
4671 rxcqe->addr_hi = cpu_to_le32(val);
4672 data->rx.cqe_page_base.hi = cpu_to_le32(val);
4673
4674 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
4675 rxcqe->addr_lo = cpu_to_le32(val);
4676 data->rx.cqe_page_base.lo = cpu_to_le32(val);
4677
4678 /* Other ramrod params */
4679 data->rx.client_qzone_id = cl_qzone_id;
4680 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
4681 data->rx.status_block_id = BNX2X_DEF_SB_ID;
4682
4683 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
4684 data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
4685
4686 data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4687 data->rx.outer_vlan_removal_enable_flg = 1;
4688
4689 /* reset tstorm and ustorm per client statistics */
4690 if (cli < MAX_STAT_COUNTER_ID) {
4691 val = BAR_TSTRORM_INTMEM +
4692 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4693 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
4694 CNIC_WR(dev, val + i * 4, 0);
4695
4696 val = BAR_USTRORM_INTMEM +
4697 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4698 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4699 CNIC_WR(dev, val + i * 4, 0);
4700 }
4701
4702 cp->rx_cons_ptr =
4703 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
4704 cp->rx_cons = *cp->rx_cons_ptr;
4705 }
4706
4707 static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr,
4708 u32 lower_addr)
4709 {
4710 u32 val;
4711 u8 mac[6];
4712
4713 val = CNIC_RD(dev, upper_addr);
4714
4715 mac[0] = (u8) (val >> 8);
4716 mac[1] = (u8) val;
4717
4718 val = CNIC_RD(dev, lower_addr);
4719
4720 mac[2] = (u8) (val >> 24);
4721 mac[3] = (u8) (val >> 16);
4722 mac[4] = (u8) (val >> 8);
4723 mac[5] = (u8) val;
4724
4725 if (is_valid_ether_addr(mac)) {
4726 memcpy(dev->mac_addr, mac, 6);
4727 return 0;
4728 } else {
4729 return -EINVAL;
4730 }
4731 }
4732
4733 static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4734 {
4735 struct cnic_local *cp = dev->cnic_priv;
4736 u32 base, base2, addr, addr1, val;
4737 int port = CNIC_PORT(cp);
4738
4739 dev->max_iscsi_conn = 0;
4740 base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
4741 if (base == 0)
4742 return;
4743
4744 base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
4745 MISC_REG_GENERIC_CR_0));
4746 addr = BNX2X_SHMEM_ADDR(base,
4747 dev_info.port_hw_config[port].iscsi_mac_upper);
4748
4749 addr1 = BNX2X_SHMEM_ADDR(base,
4750 dev_info.port_hw_config[port].iscsi_mac_lower);
4751
4752 cnic_read_bnx2x_iscsi_mac(dev, addr, addr1);
4753
4754 addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
4755 val = CNIC_RD(dev, addr);
4756
4757 if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
4758 u16 val16;
4759
4760 addr = BNX2X_SHMEM_ADDR(base,
4761 drv_lic_key[port].max_iscsi_init_conn);
4762 val16 = CNIC_RD16(dev, addr);
4763
4764 if (val16)
4765 val16 ^= 0x1e1e;
4766 dev->max_iscsi_conn = val16;
4767 }
4768
4769 if (BNX2X_CHIP_IS_E2(cp->chip_id))
4770 dev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
4771
4772 if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
4773 int func = CNIC_FUNC(cp);
4774 u32 mf_cfg_addr;
4775
4776 if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
4777 mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
4778 mf_cfg_addr));
4779 else
4780 mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
4781
4782 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4783 /* Must determine if the MF is SD vs SI mode */
4784 addr = BNX2X_SHMEM_ADDR(base,
4785 dev_info.shared_feature_config.config);
4786 val = CNIC_RD(dev, addr);
4787 if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) ==
4788 SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) {
4789 int rc;
4790
4791 /* MULTI_FUNCTION_SI mode */
4792 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4793 func_ext_config[func].func_cfg);
4794 val = CNIC_RD(dev, addr);
4795 if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
4796 dev->max_iscsi_conn = 0;
4797
4798 if (!(val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
4799 dev->max_fcoe_conn = 0;
4800
4801 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4802 func_ext_config[func].
4803 iscsi_mac_addr_upper);
4804 addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4805 func_ext_config[func].
4806 iscsi_mac_addr_lower);
4807 rc = cnic_read_bnx2x_iscsi_mac(dev, addr,
4808 addr1);
4809 if (rc && func > 1)
4810 dev->max_iscsi_conn = 0;
4811
4812 return;
4813 }
4814 }
4815
4816 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4817 func_mf_config[func].e1hov_tag);
4818
4819 val = CNIC_RD(dev, addr);
4820 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
4821 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
4822 dev->max_fcoe_conn = 0;
4823 dev->max_iscsi_conn = 0;
4824 }
4825 }
4826 if (!is_valid_ether_addr(dev->mac_addr))
4827 dev->max_iscsi_conn = 0;
4828 }
4829
4830 static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
4831 {
4832 struct cnic_local *cp = dev->cnic_priv;
4833 u32 pfid = cp->pfid;
4834
4835 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
4836 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
4837 cp->kcq1.sw_prod_idx = 0;
4838
4839 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4840 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4841
4842 cp->kcq1.hw_prod_idx_ptr =
4843 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4844 cp->kcq1.status_idx_ptr =
4845 &sb->sb.running_index[SM_RX_ID];
4846 } else {
4847 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
4848
4849 cp->kcq1.hw_prod_idx_ptr =
4850 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4851 cp->kcq1.status_idx_ptr =
4852 &sb->sb.running_index[SM_RX_ID];
4853 }
4854
4855 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4856 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4857
4858 cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
4859 USTORM_FCOE_EQ_PROD_OFFSET(pfid);
4860 cp->kcq2.sw_prod_idx = 0;
4861 cp->kcq2.hw_prod_idx_ptr =
4862 &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
4863 cp->kcq2.status_idx_ptr =
4864 &sb->sb.running_index[SM_RX_ID];
4865 }
4866 }
4867
4868 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4869 {
4870 struct cnic_local *cp = dev->cnic_priv;
4871 struct cnic_eth_dev *ethdev = cp->ethdev;
4872 int func = CNIC_FUNC(cp), ret, i;
4873 u32 pfid;
4874
4875 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4876 u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
4877
4878 if (!(val & 1))
4879 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
4880 else
4881 val = (val >> 1) & 1;
4882
4883 if (val)
4884 cp->pfid = func >> 1;
4885 else
4886 cp->pfid = func & 0x6;
4887 } else {
4888 cp->pfid = func;
4889 }
4890 pfid = cp->pfid;
4891
4892 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4893 cp->iscsi_start_cid);
4894
4895 if (ret)
4896 return -ENOMEM;
4897
4898 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4899 ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
4900 BNX2X_FCOE_NUM_CONNECTIONS,
4901 cp->fcoe_start_cid);
4902
4903 if (ret)
4904 return -ENOMEM;
4905 }
4906
4907 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4908
4909 cnic_init_bnx2x_kcq(dev);
4910
4911 cnic_get_bnx2x_iscsi_info(dev);
4912
4913 /* Only 1 EQ */
4914 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
4915 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4916 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
4917 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4918 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
4919 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
4920 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4921 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
4922 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
4923 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4924 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
4925 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
4926 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4927 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
4928 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
4929 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4930 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
4931 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4932 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
4933 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4934 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
4935 HC_INDEX_ISCSI_EQ_CONS);
4936
4937 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4938 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4939 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
4940 cp->conn_buf_info.pgtbl[2 * i]);
4941 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4942 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
4943 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4944 }
4945
4946 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4947 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
4948 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4949 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4950 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
4951 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4952
4953 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4954 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
4955
4956 cnic_setup_bnx2x_context(dev);
4957
4958 ret = cnic_init_bnx2x_irq(dev);
4959 if (ret)
4960 return ret;
4961
4962 return 0;
4963 }
4964
4965 static void cnic_init_rings(struct cnic_dev *dev)
4966 {
4967 struct cnic_local *cp = dev->cnic_priv;
4968 struct cnic_uio_dev *udev = cp->udev;
4969
4970 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4971 return;
4972
4973 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4974 cnic_init_bnx2_tx_ring(dev);
4975 cnic_init_bnx2_rx_ring(dev);
4976 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4977 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4978 u32 cli = cp->ethdev->iscsi_l2_client_id;
4979 u32 cid = cp->ethdev->iscsi_l2_cid;
4980 u32 cl_qzone_id, type;
4981 struct client_init_ramrod_data *data;
4982 union l5cm_specific_data l5_data;
4983 struct ustorm_eth_rx_producers rx_prods = {0};
4984 u32 off, i;
4985
4986 rx_prods.bd_prod = 0;
4987 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4988 barrier();
4989
4990 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4991
4992 off = BAR_USTRORM_INTMEM +
4993 (BNX2X_CHIP_IS_E2(cp->chip_id) ?
4994 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
4995 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
4996
4997 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4998 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
4999
5000 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
5001
5002 data = udev->l2_buf;
5003
5004 memset(data, 0, sizeof(*data));
5005
5006 cnic_init_bnx2x_tx_ring(dev, data);
5007 cnic_init_bnx2x_rx_ring(dev, data);
5008
5009 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
5010 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
5011
5012 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
5013 & SPE_HDR_CONN_TYPE;
5014 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
5015 SPE_HDR_FUNCTION_ID);
5016
5017 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5018
5019 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
5020 cid, type, &l5_data);
5021
5022 i = 0;
5023 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
5024 ++i < 10)
5025 msleep(1);
5026
5027 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
5028 netdev_err(dev->netdev,
5029 "iSCSI CLIENT_SETUP did not complete\n");
5030 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
5031 cnic_ring_ctl(dev, cid, cli, 1);
5032 }
5033 }
5034
5035 static void cnic_shutdown_rings(struct cnic_dev *dev)
5036 {
5037 struct cnic_local *cp = dev->cnic_priv;
5038
5039 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
5040 return;
5041
5042 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
5043 cnic_shutdown_bnx2_rx_ring(dev);
5044 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
5045 struct cnic_local *cp = dev->cnic_priv;
5046 u32 cli = cp->ethdev->iscsi_l2_client_id;
5047 u32 cid = cp->ethdev->iscsi_l2_cid;
5048 union l5cm_specific_data l5_data;
5049 int i;
5050 u32 type;
5051
5052 cnic_ring_ctl(dev, cid, cli, 0);
5053
5054 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
5055
5056 l5_data.phy_address.lo = cli;
5057 l5_data.phy_address.hi = 0;
5058 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
5059 cid, ETH_CONNECTION_TYPE, &l5_data);
5060 i = 0;
5061 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
5062 ++i < 10)
5063 msleep(1);
5064
5065 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
5066 netdev_err(dev->netdev,
5067 "iSCSI CLIENT_HALT did not complete\n");
5068 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
5069
5070 memset(&l5_data, 0, sizeof(l5_data));
5071 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
5072 & SPE_HDR_CONN_TYPE;
5073 type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
5074 SPE_HDR_FUNCTION_ID);
5075 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
5076 cid, type, &l5_data);
5077 msleep(10);
5078 }
5079 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5080 }
5081
5082 static int cnic_register_netdev(struct cnic_dev *dev)
5083 {
5084 struct cnic_local *cp = dev->cnic_priv;
5085 struct cnic_eth_dev *ethdev = cp->ethdev;
5086 int err;
5087
5088 if (!ethdev)
5089 return -ENODEV;
5090
5091 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
5092 return 0;
5093
5094 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
5095 if (err)
5096 netdev_err(dev->netdev, "register_cnic failed\n");
5097
5098 return err;
5099 }
5100
5101 static void cnic_unregister_netdev(struct cnic_dev *dev)
5102 {
5103 struct cnic_local *cp = dev->cnic_priv;
5104 struct cnic_eth_dev *ethdev = cp->ethdev;
5105
5106 if (!ethdev)
5107 return;
5108
5109 ethdev->drv_unregister_cnic(dev->netdev);
5110 }
5111
5112 static int cnic_start_hw(struct cnic_dev *dev)
5113 {
5114 struct cnic_local *cp = dev->cnic_priv;
5115 struct cnic_eth_dev *ethdev = cp->ethdev;
5116 int err;
5117
5118 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
5119 return -EALREADY;
5120
5121 dev->regview = ethdev->io_base;
5122 pci_dev_get(dev->pcidev);
5123 cp->func = PCI_FUNC(dev->pcidev->devfn);
5124 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
5125 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
5126
5127 err = cp->alloc_resc(dev);
5128 if (err) {
5129 netdev_err(dev->netdev, "allocate resource failure\n");
5130 goto err1;
5131 }
5132
5133 err = cp->start_hw(dev);
5134 if (err)
5135 goto err1;
5136
5137 err = cnic_cm_open(dev);
5138 if (err)
5139 goto err1;
5140
5141 set_bit(CNIC_F_CNIC_UP, &dev->flags);
5142
5143 cp->enable_int(dev);
5144
5145 return 0;
5146
5147 err1:
5148 cp->free_resc(dev);
5149 pci_dev_put(dev->pcidev);
5150 return err;
5151 }
5152
5153 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
5154 {
5155 cnic_disable_bnx2_int_sync(dev);
5156
5157 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
5158 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
5159
5160 cnic_init_context(dev, KWQ_CID);
5161 cnic_init_context(dev, KCQ_CID);
5162
5163 cnic_setup_5709_context(dev, 0);
5164 cnic_free_irq(dev);
5165
5166 cnic_free_resc(dev);
5167 }
5168
5169
5170 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
5171 {
5172 struct cnic_local *cp = dev->cnic_priv;
5173
5174 cnic_free_irq(dev);
5175 *cp->kcq1.hw_prod_idx_ptr = 0;
5176 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5177 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
5178 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
5179 cnic_free_resc(dev);
5180 }
5181
5182 static void cnic_stop_hw(struct cnic_dev *dev)
5183 {
5184 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5185 struct cnic_local *cp = dev->cnic_priv;
5186 int i = 0;
5187
5188 /* Need to wait for the ring shutdown event to complete
5189 * before clearing the CNIC_UP flag.
5190 */
5191 while (cp->udev->uio_dev != -1 && i < 15) {
5192 msleep(100);
5193 i++;
5194 }
5195 cnic_shutdown_rings(dev);
5196 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
5197 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
5198 synchronize_rcu();
5199 cnic_cm_shutdown(dev);
5200 cp->stop_hw(dev);
5201 pci_dev_put(dev->pcidev);
5202 }
5203 }
5204
5205 static void cnic_free_dev(struct cnic_dev *dev)
5206 {
5207 int i = 0;
5208
5209 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
5210 msleep(100);
5211 i++;
5212 }
5213 if (atomic_read(&dev->ref_count) != 0)
5214 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
5215
5216 netdev_info(dev->netdev, "Removed CNIC device\n");
5217 dev_put(dev->netdev);
5218 kfree(dev);
5219 }
5220
5221 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
5222 struct pci_dev *pdev)
5223 {
5224 struct cnic_dev *cdev;
5225 struct cnic_local *cp;
5226 int alloc_size;
5227
5228 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
5229
5230 cdev = kzalloc(alloc_size , GFP_KERNEL);
5231 if (cdev == NULL) {
5232 netdev_err(dev, "allocate dev struct failure\n");
5233 return NULL;
5234 }
5235
5236 cdev->netdev = dev;
5237 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
5238 cdev->register_device = cnic_register_device;
5239 cdev->unregister_device = cnic_unregister_device;
5240 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
5241
5242 cp = cdev->cnic_priv;
5243 cp->dev = cdev;
5244 cp->l2_single_buf_size = 0x400;
5245 cp->l2_rx_ring_size = 3;
5246
5247 spin_lock_init(&cp->cnic_ulp_lock);
5248
5249 netdev_info(dev, "Added CNIC device\n");
5250
5251 return cdev;
5252 }
5253
5254 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
5255 {
5256 struct pci_dev *pdev;
5257 struct cnic_dev *cdev;
5258 struct cnic_local *cp;
5259 struct cnic_eth_dev *ethdev = NULL;
5260 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5261
5262 probe = symbol_get(bnx2_cnic_probe);
5263 if (probe) {
5264 ethdev = (*probe)(dev);
5265 symbol_put(bnx2_cnic_probe);
5266 }
5267 if (!ethdev)
5268 return NULL;
5269
5270 pdev = ethdev->pdev;
5271 if (!pdev)
5272 return NULL;
5273
5274 dev_hold(dev);
5275 pci_dev_get(pdev);
5276 if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
5277 pdev->device == PCI_DEVICE_ID_NX2_5709S) {
5278 u8 rev;
5279
5280 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
5281 if (rev < 0x10) {
5282 pci_dev_put(pdev);
5283 goto cnic_err;
5284 }
5285 }
5286 pci_dev_put(pdev);
5287
5288 cdev = cnic_alloc_dev(dev, pdev);
5289 if (cdev == NULL)
5290 goto cnic_err;
5291
5292 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
5293 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
5294
5295 cp = cdev->cnic_priv;
5296 cp->ethdev = ethdev;
5297 cdev->pcidev = pdev;
5298 cp->chip_id = ethdev->chip_id;
5299
5300 cp->cnic_ops = &cnic_bnx2_ops;
5301 cp->start_hw = cnic_start_bnx2_hw;
5302 cp->stop_hw = cnic_stop_bnx2_hw;
5303 cp->setup_pgtbl = cnic_setup_page_tbl;
5304 cp->alloc_resc = cnic_alloc_bnx2_resc;
5305 cp->free_resc = cnic_free_resc;
5306 cp->start_cm = cnic_cm_init_bnx2_hw;
5307 cp->stop_cm = cnic_cm_stop_bnx2_hw;
5308 cp->enable_int = cnic_enable_bnx2_int;
5309 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
5310 cp->close_conn = cnic_close_bnx2_conn;
5311 cp->next_idx = cnic_bnx2_next_idx;
5312 cp->hw_idx = cnic_bnx2_hw_idx;
5313 return cdev;
5314
5315 cnic_err:
5316 dev_put(dev);
5317 return NULL;
5318 }
5319
5320 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
5321 {
5322 struct pci_dev *pdev;
5323 struct cnic_dev *cdev;
5324 struct cnic_local *cp;
5325 struct cnic_eth_dev *ethdev = NULL;
5326 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5327
5328 probe = symbol_get(bnx2x_cnic_probe);
5329 if (probe) {
5330 ethdev = (*probe)(dev);
5331 symbol_put(bnx2x_cnic_probe);
5332 }
5333 if (!ethdev)
5334 return NULL;
5335
5336 pdev = ethdev->pdev;
5337 if (!pdev)
5338 return NULL;
5339
5340 dev_hold(dev);
5341 cdev = cnic_alloc_dev(dev, pdev);
5342 if (cdev == NULL) {
5343 dev_put(dev);
5344 return NULL;
5345 }
5346
5347 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
5348 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
5349
5350 cp = cdev->cnic_priv;
5351 cp->ethdev = ethdev;
5352 cdev->pcidev = pdev;
5353 cp->chip_id = ethdev->chip_id;
5354
5355 cp->cnic_ops = &cnic_bnx2x_ops;
5356 cp->start_hw = cnic_start_bnx2x_hw;
5357 cp->stop_hw = cnic_stop_bnx2x_hw;
5358 cp->setup_pgtbl = cnic_setup_page_tbl_le;
5359 cp->alloc_resc = cnic_alloc_bnx2x_resc;
5360 cp->free_resc = cnic_free_resc;
5361 cp->start_cm = cnic_cm_init_bnx2x_hw;
5362 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
5363 cp->enable_int = cnic_enable_bnx2x_int;
5364 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
5365 if (BNX2X_CHIP_IS_E2(cp->chip_id))
5366 cp->ack_int = cnic_ack_bnx2x_e2_msix;
5367 else
5368 cp->ack_int = cnic_ack_bnx2x_msix;
5369 cp->close_conn = cnic_close_bnx2x_conn;
5370 cp->next_idx = cnic_bnx2x_next_idx;
5371 cp->hw_idx = cnic_bnx2x_hw_idx;
5372 return cdev;
5373 }
5374
5375 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
5376 {
5377 struct ethtool_drvinfo drvinfo;
5378 struct cnic_dev *cdev = NULL;
5379
5380 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5381 memset(&drvinfo, 0, sizeof(drvinfo));
5382 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5383
5384 if (!strcmp(drvinfo.driver, "bnx2"))
5385 cdev = init_bnx2_cnic(dev);
5386 if (!strcmp(drvinfo.driver, "bnx2x"))
5387 cdev = init_bnx2x_cnic(dev);
5388 if (cdev) {
5389 write_lock(&cnic_dev_lock);
5390 list_add(&cdev->list, &cnic_dev_list);
5391 write_unlock(&cnic_dev_lock);
5392 }
5393 }
5394 return cdev;
5395 }
5396
5397 /**
5398 * netdev event handler
5399 */
5400 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
5401 void *ptr)
5402 {
5403 struct net_device *netdev = ptr;
5404 struct cnic_dev *dev;
5405 int if_type;
5406 int new_dev = 0;
5407
5408 dev = cnic_from_netdev(netdev);
5409
5410 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
5411 /* Check for the hot-plug device */
5412 dev = is_cnic_dev(netdev);
5413 if (dev) {
5414 new_dev = 1;
5415 cnic_hold(dev);
5416 }
5417 }
5418 if (dev) {
5419 struct cnic_local *cp = dev->cnic_priv;
5420
5421 if (new_dev)
5422 cnic_ulp_init(dev);
5423 else if (event == NETDEV_UNREGISTER)
5424 cnic_ulp_exit(dev);
5425
5426 if (event == NETDEV_UP) {
5427 if (cnic_register_netdev(dev) != 0) {
5428 cnic_put(dev);
5429 goto done;
5430 }
5431 if (!cnic_start_hw(dev))
5432 cnic_ulp_start(dev);
5433 }
5434
5435 rcu_read_lock();
5436 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
5437 struct cnic_ulp_ops *ulp_ops;
5438 void *ctx;
5439
5440 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
5441 if (!ulp_ops || !ulp_ops->indicate_netevent)
5442 continue;
5443
5444 ctx = cp->ulp_handle[if_type];
5445
5446 ulp_ops->indicate_netevent(ctx, event);
5447 }
5448 rcu_read_unlock();
5449
5450 if (event == NETDEV_GOING_DOWN) {
5451 cnic_ulp_stop(dev);
5452 cnic_stop_hw(dev);
5453 cnic_unregister_netdev(dev);
5454 } else if (event == NETDEV_UNREGISTER) {
5455 write_lock(&cnic_dev_lock);
5456 list_del_init(&dev->list);
5457 write_unlock(&cnic_dev_lock);
5458
5459 cnic_put(dev);
5460 cnic_free_dev(dev);
5461 goto done;
5462 }
5463 cnic_put(dev);
5464 }
5465 done:
5466 return NOTIFY_DONE;
5467 }
5468
5469 static struct notifier_block cnic_netdev_notifier = {
5470 .notifier_call = cnic_netdev_event
5471 };
5472
5473 static void cnic_release(void)
5474 {
5475 struct cnic_dev *dev;
5476 struct cnic_uio_dev *udev;
5477
5478 while (!list_empty(&cnic_dev_list)) {
5479 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
5480 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5481 cnic_ulp_stop(dev);
5482 cnic_stop_hw(dev);
5483 }
5484
5485 cnic_ulp_exit(dev);
5486 cnic_unregister_netdev(dev);
5487 list_del_init(&dev->list);
5488 cnic_free_dev(dev);
5489 }
5490 while (!list_empty(&cnic_udev_list)) {
5491 udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
5492 list);
5493 cnic_free_uio(udev);
5494 }
5495 }
5496
5497 static int __init cnic_init(void)
5498 {
5499 int rc = 0;
5500
5501 pr_info("%s", version);
5502
5503 rc = register_netdevice_notifier(&cnic_netdev_notifier);
5504 if (rc) {
5505 cnic_release();
5506 return rc;
5507 }
5508
5509 cnic_wq = create_singlethread_workqueue("cnic_wq");
5510 if (!cnic_wq) {
5511 cnic_release();
5512 unregister_netdevice_notifier(&cnic_netdev_notifier);
5513 return -ENOMEM;
5514 }
5515
5516 return 0;
5517 }
5518
5519 static void __exit cnic_exit(void)
5520 {
5521 unregister_netdevice_notifier(&cnic_netdev_notifier);
5522 cnic_release();
5523 destroy_workqueue(cnic_wq);
5524 }
5525
5526 module_init(cnic_init);
5527 module_exit(cnic_exit);
Linux kernel - Deliverables
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