DM9000: Add support for DM9000A and DM9000B chips
[deliverable/linux.git] / drivers / net / dm9000.c
1 /*
2 * Davicom DM9000 Fast Ethernet driver for Linux.
3 * Copyright (C) 1997 Sten Wang
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
16 *
17 * Additional updates, Copyright:
18 * Ben Dooks <ben@simtec.co.uk>
19 * Sascha Hauer <s.hauer@pengutronix.de>
20 */
21
22 #include <linux/module.h>
23 #include <linux/ioport.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/init.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
29 #include <linux/crc32.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/dm9000.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/irq.h>
36
37 #include <asm/delay.h>
38 #include <asm/irq.h>
39 #include <asm/io.h>
40
41 #include "dm9000.h"
42
43 /* Board/System/Debug information/definition ---------------- */
44
45 #define DM9000_PHY 0x40 /* PHY address 0x01 */
46
47 #define CARDNAME "dm9000"
48 #define PFX CARDNAME ": "
49 #define DRV_VERSION "1.30"
50
51 #ifdef CONFIG_BLACKFIN
52 #define readsb insb
53 #define readsw insw
54 #define readsl insl
55 #define writesb outsb
56 #define writesw outsw
57 #define writesl outsl
58 #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH
59 #else
60 #define DEFAULT_TRIGGER (0)
61 #endif
62
63 /*
64 * Transmit timeout, default 5 seconds.
65 */
66 static int watchdog = 5000;
67 module_param(watchdog, int, 0400);
68 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
69
70 /* DM9000 register address locking.
71 *
72 * The DM9000 uses an address register to control where data written
73 * to the data register goes. This means that the address register
74 * must be preserved over interrupts or similar calls.
75 *
76 * During interrupt and other critical calls, a spinlock is used to
77 * protect the system, but the calls themselves save the address
78 * in the address register in case they are interrupting another
79 * access to the device.
80 *
81 * For general accesses a lock is provided so that calls which are
82 * allowed to sleep are serialised so that the address register does
83 * not need to be saved. This lock also serves to serialise access
84 * to the EEPROM and PHY access registers which are shared between
85 * these two devices.
86 */
87
88 /* The driver supports the original DM9000E, and now the two newer
89 * devices, DM9000A and DM9000B.
90 */
91
92 enum dm9000_type {
93 TYPE_DM9000E, /* original DM9000 */
94 TYPE_DM9000A,
95 TYPE_DM9000B
96 };
97
98 /* Structure/enum declaration ------------------------------- */
99 typedef struct board_info {
100
101 void __iomem *io_addr; /* Register I/O base address */
102 void __iomem *io_data; /* Data I/O address */
103 u16 irq; /* IRQ */
104
105 u16 tx_pkt_cnt;
106 u16 queue_pkt_len;
107 u16 queue_start_addr;
108 u16 dbug_cnt;
109 u8 io_mode; /* 0:word, 2:byte */
110 u8 phy_addr;
111 u8 imr_all;
112 unsigned int flags;
113 unsigned int in_suspend :1;
114
115 enum dm9000_type type;
116 int debug_level;
117
118 void (*inblk)(void __iomem *port, void *data, int length);
119 void (*outblk)(void __iomem *port, void *data, int length);
120 void (*dumpblk)(void __iomem *port, int length);
121
122 struct device *dev; /* parent device */
123
124 struct resource *addr_res; /* resources found */
125 struct resource *data_res;
126 struct resource *addr_req; /* resources requested */
127 struct resource *data_req;
128 struct resource *irq_res;
129
130 struct mutex addr_lock; /* phy and eeprom access lock */
131
132 struct delayed_work phy_poll;
133 struct net_device *ndev;
134
135 spinlock_t lock;
136
137 struct mii_if_info mii;
138 u32 msg_enable;
139 } board_info_t;
140
141 /* debug code */
142
143 #define dm9000_dbg(db, lev, msg...) do { \
144 if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \
145 (lev) < db->debug_level) { \
146 dev_dbg(db->dev, msg); \
147 } \
148 } while (0)
149
150 static inline board_info_t *to_dm9000_board(struct net_device *dev)
151 {
152 return dev->priv;
153 }
154
155 /* function declaration ------------------------------------- */
156 static int dm9000_probe(struct platform_device *);
157 static int dm9000_open(struct net_device *);
158 static int dm9000_start_xmit(struct sk_buff *, struct net_device *);
159 static int dm9000_stop(struct net_device *);
160 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd);
161
162 static void dm9000_init_dm9000(struct net_device *);
163
164 static irqreturn_t dm9000_interrupt(int, void *);
165
166 static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg);
167 static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg,
168 int value);
169
170 static void dm9000_read_eeprom(board_info_t *, int addr, u8 *to);
171 static void dm9000_write_eeprom(board_info_t *, int addr, u8 *dp);
172 static void dm9000_rx(struct net_device *);
173 static void dm9000_hash_table(struct net_device *);
174
175 /* DM9000 network board routine ---------------------------- */
176
177 static void
178 dm9000_reset(board_info_t * db)
179 {
180 dev_dbg(db->dev, "resetting device\n");
181
182 /* RESET device */
183 writeb(DM9000_NCR, db->io_addr);
184 udelay(200);
185 writeb(NCR_RST, db->io_data);
186 udelay(200);
187 }
188
189 /*
190 * Read a byte from I/O port
191 */
192 static u8
193 ior(board_info_t * db, int reg)
194 {
195 writeb(reg, db->io_addr);
196 return readb(db->io_data);
197 }
198
199 /*
200 * Write a byte to I/O port
201 */
202
203 static void
204 iow(board_info_t * db, int reg, int value)
205 {
206 writeb(reg, db->io_addr);
207 writeb(value, db->io_data);
208 }
209
210 /* routines for sending block to chip */
211
212 static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
213 {
214 writesb(reg, data, count);
215 }
216
217 static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
218 {
219 writesw(reg, data, (count+1) >> 1);
220 }
221
222 static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
223 {
224 writesl(reg, data, (count+3) >> 2);
225 }
226
227 /* input block from chip to memory */
228
229 static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
230 {
231 readsb(reg, data, count);
232 }
233
234
235 static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
236 {
237 readsw(reg, data, (count+1) >> 1);
238 }
239
240 static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
241 {
242 readsl(reg, data, (count+3) >> 2);
243 }
244
245 /* dump block from chip to null */
246
247 static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
248 {
249 int i;
250 int tmp;
251
252 for (i = 0; i < count; i++)
253 tmp = readb(reg);
254 }
255
256 static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
257 {
258 int i;
259 int tmp;
260
261 count = (count + 1) >> 1;
262
263 for (i = 0; i < count; i++)
264 tmp = readw(reg);
265 }
266
267 static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
268 {
269 int i;
270 int tmp;
271
272 count = (count + 3) >> 2;
273
274 for (i = 0; i < count; i++)
275 tmp = readl(reg);
276 }
277
278 /* dm9000_set_io
279 *
280 * select the specified set of io routines to use with the
281 * device
282 */
283
284 static void dm9000_set_io(struct board_info *db, int byte_width)
285 {
286 /* use the size of the data resource to work out what IO
287 * routines we want to use
288 */
289
290 switch (byte_width) {
291 case 1:
292 db->dumpblk = dm9000_dumpblk_8bit;
293 db->outblk = dm9000_outblk_8bit;
294 db->inblk = dm9000_inblk_8bit;
295 break;
296
297
298 case 3:
299 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
300 case 2:
301 db->dumpblk = dm9000_dumpblk_16bit;
302 db->outblk = dm9000_outblk_16bit;
303 db->inblk = dm9000_inblk_16bit;
304 break;
305
306 case 4:
307 default:
308 db->dumpblk = dm9000_dumpblk_32bit;
309 db->outblk = dm9000_outblk_32bit;
310 db->inblk = dm9000_inblk_32bit;
311 break;
312 }
313 }
314
315 static void dm9000_schedule_poll(board_info_t *db)
316 {
317 if (db->type == TYPE_DM9000E)
318 schedule_delayed_work(&db->phy_poll, HZ * 2);
319 }
320
321 /* Our watchdog timed out. Called by the networking layer */
322 static void dm9000_timeout(struct net_device *dev)
323 {
324 board_info_t *db = (board_info_t *) dev->priv;
325 u8 reg_save;
326 unsigned long flags;
327
328 /* Save previous register address */
329 reg_save = readb(db->io_addr);
330 spin_lock_irqsave(&db->lock,flags);
331
332 netif_stop_queue(dev);
333 dm9000_reset(db);
334 dm9000_init_dm9000(dev);
335 /* We can accept TX packets again */
336 dev->trans_start = jiffies;
337 netif_wake_queue(dev);
338
339 /* Restore previous register address */
340 writeb(reg_save, db->io_addr);
341 spin_unlock_irqrestore(&db->lock,flags);
342 }
343
344 #ifdef CONFIG_NET_POLL_CONTROLLER
345 /*
346 *Used by netconsole
347 */
348 static void dm9000_poll_controller(struct net_device *dev)
349 {
350 disable_irq(dev->irq);
351 dm9000_interrupt(dev->irq,dev);
352 enable_irq(dev->irq);
353 }
354 #endif
355
356 static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
357 {
358 board_info_t *dm = to_dm9000_board(dev);
359
360 if (!netif_running(dev))
361 return -EINVAL;
362
363 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL);
364 }
365
366 /* ethtool ops */
367
368 static void dm9000_get_drvinfo(struct net_device *dev,
369 struct ethtool_drvinfo *info)
370 {
371 board_info_t *dm = to_dm9000_board(dev);
372
373 strcpy(info->driver, CARDNAME);
374 strcpy(info->version, DRV_VERSION);
375 strcpy(info->bus_info, to_platform_device(dm->dev)->name);
376 }
377
378 static u32 dm9000_get_msglevel(struct net_device *dev)
379 {
380 board_info_t *dm = to_dm9000_board(dev);
381
382 return dm->msg_enable;
383 }
384
385 static void dm9000_set_msglevel(struct net_device *dev, u32 value)
386 {
387 board_info_t *dm = to_dm9000_board(dev);
388
389 dm->msg_enable = value;
390 }
391
392 static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
393 {
394 board_info_t *dm = to_dm9000_board(dev);
395
396 mii_ethtool_gset(&dm->mii, cmd);
397 return 0;
398 }
399
400 static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
401 {
402 board_info_t *dm = to_dm9000_board(dev);
403
404 return mii_ethtool_sset(&dm->mii, cmd);
405 }
406
407 static int dm9000_nway_reset(struct net_device *dev)
408 {
409 board_info_t *dm = to_dm9000_board(dev);
410 return mii_nway_restart(&dm->mii);
411 }
412
413 static u32 dm9000_get_link(struct net_device *dev)
414 {
415 board_info_t *dm = to_dm9000_board(dev);
416 return mii_link_ok(&dm->mii);
417 }
418
419 #define DM_EEPROM_MAGIC (0x444D394B)
420
421 static int dm9000_get_eeprom_len(struct net_device *dev)
422 {
423 return 128;
424 }
425
426 static int dm9000_get_eeprom(struct net_device *dev,
427 struct ethtool_eeprom *ee, u8 *data)
428 {
429 board_info_t *dm = to_dm9000_board(dev);
430 int offset = ee->offset;
431 int len = ee->len;
432 int i;
433
434 /* EEPROM access is aligned to two bytes */
435
436 if ((len & 1) != 0 || (offset & 1) != 0)
437 return -EINVAL;
438
439 if (dm->flags & DM9000_PLATF_NO_EEPROM)
440 return -ENOENT;
441
442 ee->magic = DM_EEPROM_MAGIC;
443
444 for (i = 0; i < len; i += 2)
445 dm9000_read_eeprom(dm, (offset + i) / 2, data + i);
446
447 return 0;
448 }
449
450 static int dm9000_set_eeprom(struct net_device *dev,
451 struct ethtool_eeprom *ee, u8 *data)
452 {
453 board_info_t *dm = to_dm9000_board(dev);
454 int offset = ee->offset;
455 int len = ee->len;
456 int i;
457
458 /* EEPROM access is aligned to two bytes */
459
460 if ((len & 1) != 0 || (offset & 1) != 0)
461 return -EINVAL;
462
463 if (dm->flags & DM9000_PLATF_NO_EEPROM)
464 return -ENOENT;
465
466 if (ee->magic != DM_EEPROM_MAGIC)
467 return -EINVAL;
468
469 for (i = 0; i < len; i += 2)
470 dm9000_write_eeprom(dm, (offset + i) / 2, data + i);
471
472 return 0;
473 }
474
475 static const struct ethtool_ops dm9000_ethtool_ops = {
476 .get_drvinfo = dm9000_get_drvinfo,
477 .get_settings = dm9000_get_settings,
478 .set_settings = dm9000_set_settings,
479 .get_msglevel = dm9000_get_msglevel,
480 .set_msglevel = dm9000_set_msglevel,
481 .nway_reset = dm9000_nway_reset,
482 .get_link = dm9000_get_link,
483 .get_eeprom_len = dm9000_get_eeprom_len,
484 .get_eeprom = dm9000_get_eeprom,
485 .set_eeprom = dm9000_set_eeprom,
486 };
487
488 static void
489 dm9000_poll_work(struct work_struct *w)
490 {
491 struct delayed_work *dw = container_of(w, struct delayed_work, work);
492 board_info_t *db = container_of(dw, board_info_t, phy_poll);
493
494 mii_check_media(&db->mii, netif_msg_link(db), 0);
495
496 if (netif_running(db->ndev))
497 dm9000_schedule_poll(db);
498 }
499
500 /* dm9000_release_board
501 *
502 * release a board, and any mapped resources
503 */
504
505 static void
506 dm9000_release_board(struct platform_device *pdev, struct board_info *db)
507 {
508 if (db->data_res == NULL) {
509 if (db->addr_res != NULL)
510 release_mem_region((unsigned long)db->io_addr, 4);
511 return;
512 }
513
514 /* unmap our resources */
515
516 iounmap(db->io_addr);
517 iounmap(db->io_data);
518
519 /* release the resources */
520
521 if (db->data_req != NULL) {
522 release_resource(db->data_req);
523 kfree(db->data_req);
524 }
525
526 if (db->addr_req != NULL) {
527 release_resource(db->addr_req);
528 kfree(db->addr_req);
529 }
530 }
531
532 static unsigned char dm9000_type_to_char(enum dm9000_type type)
533 {
534 switch (type) {
535 case TYPE_DM9000E: return 'e';
536 case TYPE_DM9000A: return 'a';
537 case TYPE_DM9000B: return 'b';
538 }
539
540 return '?';
541 }
542
543 #define res_size(_r) (((_r)->end - (_r)->start) + 1)
544
545 /*
546 * Search DM9000 board, allocate space and register it
547 */
548 static int __devinit
549 dm9000_probe(struct platform_device *pdev)
550 {
551 struct dm9000_plat_data *pdata = pdev->dev.platform_data;
552 struct board_info *db; /* Point a board information structure */
553 struct net_device *ndev;
554 const unsigned char *mac_src;
555 int ret = 0;
556 int iosize;
557 int i;
558 u32 id_val;
559
560 /* Init network device */
561 ndev = alloc_etherdev(sizeof (struct board_info));
562 if (!ndev) {
563 dev_err(&pdev->dev, "could not allocate device.\n");
564 return -ENOMEM;
565 }
566
567 SET_NETDEV_DEV(ndev, &pdev->dev);
568
569 dev_dbg(&pdev->dev, "dm9000_probe()\n");
570
571 /* setup board info structure */
572 db = (struct board_info *) ndev->priv;
573 memset(db, 0, sizeof (*db));
574
575 db->dev = &pdev->dev;
576 db->ndev = ndev;
577
578 spin_lock_init(&db->lock);
579 mutex_init(&db->addr_lock);
580
581 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
582
583
584 if (pdev->num_resources < 3) {
585 ret = -ENODEV;
586 goto out;
587 }
588
589 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
590 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
591 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
592
593 if (db->addr_res == NULL || db->data_res == NULL ||
594 db->irq_res == NULL) {
595 dev_err(db->dev, "insufficient resources\n");
596 ret = -ENOENT;
597 goto out;
598 }
599
600 iosize = res_size(db->addr_res);
601 db->addr_req = request_mem_region(db->addr_res->start, iosize,
602 pdev->name);
603
604 if (db->addr_req == NULL) {
605 dev_err(db->dev, "cannot claim address reg area\n");
606 ret = -EIO;
607 goto out;
608 }
609
610 db->io_addr = ioremap(db->addr_res->start, iosize);
611
612 if (db->io_addr == NULL) {
613 dev_err(db->dev, "failed to ioremap address reg\n");
614 ret = -EINVAL;
615 goto out;
616 }
617
618 iosize = res_size(db->data_res);
619 db->data_req = request_mem_region(db->data_res->start, iosize,
620 pdev->name);
621
622 if (db->data_req == NULL) {
623 dev_err(db->dev, "cannot claim data reg area\n");
624 ret = -EIO;
625 goto out;
626 }
627
628 db->io_data = ioremap(db->data_res->start, iosize);
629
630 if (db->io_data == NULL) {
631 dev_err(db->dev, "failed to ioremap data reg\n");
632 ret = -EINVAL;
633 goto out;
634 }
635
636 /* fill in parameters for net-dev structure */
637 ndev->base_addr = (unsigned long)db->io_addr;
638 ndev->irq = db->irq_res->start;
639
640 /* ensure at least we have a default set of IO routines */
641 dm9000_set_io(db, iosize);
642
643 /* check to see if anything is being over-ridden */
644 if (pdata != NULL) {
645 /* check to see if the driver wants to over-ride the
646 * default IO width */
647
648 if (pdata->flags & DM9000_PLATF_8BITONLY)
649 dm9000_set_io(db, 1);
650
651 if (pdata->flags & DM9000_PLATF_16BITONLY)
652 dm9000_set_io(db, 2);
653
654 if (pdata->flags & DM9000_PLATF_32BITONLY)
655 dm9000_set_io(db, 4);
656
657 /* check to see if there are any IO routine
658 * over-rides */
659
660 if (pdata->inblk != NULL)
661 db->inblk = pdata->inblk;
662
663 if (pdata->outblk != NULL)
664 db->outblk = pdata->outblk;
665
666 if (pdata->dumpblk != NULL)
667 db->dumpblk = pdata->dumpblk;
668
669 db->flags = pdata->flags;
670 }
671
672 dm9000_reset(db);
673
674 /* try two times, DM9000 sometimes gets the first read wrong */
675 for (i = 0; i < 8; i++) {
676 id_val = ior(db, DM9000_VIDL);
677 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
678 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
679 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
680
681 if (id_val == DM9000_ID)
682 break;
683 dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
684 }
685
686 if (id_val != DM9000_ID) {
687 dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
688 ret = -ENODEV;
689 goto out;
690 }
691
692 /* Identify what type of DM9000 we are working on */
693
694 id_val = ior(db, DM9000_CHIPR);
695 dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val);
696
697 switch (id_val) {
698 case CHIPR_DM9000A:
699 db->type = TYPE_DM9000A;
700 break;
701 case CHIPR_DM9000B:
702 db->type = TYPE_DM9000B;
703 break;
704 default:
705 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val);
706 db->type = TYPE_DM9000E;
707 }
708
709 /* from this point we assume that we have found a DM9000 */
710
711 /* driver system function */
712 ether_setup(ndev);
713
714 ndev->open = &dm9000_open;
715 ndev->hard_start_xmit = &dm9000_start_xmit;
716 ndev->tx_timeout = &dm9000_timeout;
717 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
718 ndev->stop = &dm9000_stop;
719 ndev->set_multicast_list = &dm9000_hash_table;
720 ndev->ethtool_ops = &dm9000_ethtool_ops;
721 ndev->do_ioctl = &dm9000_ioctl;
722
723 #ifdef CONFIG_NET_POLL_CONTROLLER
724 ndev->poll_controller = &dm9000_poll_controller;
725 #endif
726
727 db->msg_enable = NETIF_MSG_LINK;
728 db->mii.phy_id_mask = 0x1f;
729 db->mii.reg_num_mask = 0x1f;
730 db->mii.force_media = 0;
731 db->mii.full_duplex = 0;
732 db->mii.dev = ndev;
733 db->mii.mdio_read = dm9000_phy_read;
734 db->mii.mdio_write = dm9000_phy_write;
735
736 mac_src = "eeprom";
737
738 /* try reading the node address from the attached EEPROM */
739 for (i = 0; i < 6; i += 2)
740 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
741
742 if (!is_valid_ether_addr(ndev->dev_addr)) {
743 /* try reading from mac */
744
745 mac_src = "chip";
746 for (i = 0; i < 6; i++)
747 ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
748 }
749
750 if (!is_valid_ether_addr(ndev->dev_addr))
751 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
752 "set using ifconfig\n", ndev->name);
753
754 platform_set_drvdata(pdev, ndev);
755 ret = register_netdev(ndev);
756
757 if (ret == 0) {
758 DECLARE_MAC_BUF(mac);
759 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n",
760 ndev->name, dm9000_type_to_char(db->type),
761 db->io_addr, db->io_data, ndev->irq,
762 print_mac(mac, ndev->dev_addr), mac_src);
763 }
764 return 0;
765
766 out:
767 dev_err(db->dev, "not found (%d).\n", ret);
768
769 dm9000_release_board(pdev, db);
770 free_netdev(ndev);
771
772 return ret;
773 }
774
775 /*
776 * Open the interface.
777 * The interface is opened whenever "ifconfig" actives it.
778 */
779 static int
780 dm9000_open(struct net_device *dev)
781 {
782 board_info_t *db = (board_info_t *) dev->priv;
783 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
784
785 if (netif_msg_ifup(db))
786 dev_dbg(db->dev, "enabling %s\n", dev->name);
787
788 /* If there is no IRQ type specified, default to something that
789 * may work, and tell the user that this is a problem */
790
791 if (irqflags == IRQF_TRIGGER_NONE) {
792 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
793 irqflags = DEFAULT_TRIGGER;
794 }
795
796 irqflags |= IRQF_SHARED;
797
798 if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev))
799 return -EAGAIN;
800
801 /* Initialize DM9000 board */
802 dm9000_reset(db);
803 dm9000_init_dm9000(dev);
804
805 /* Init driver variable */
806 db->dbug_cnt = 0;
807
808 mii_check_media(&db->mii, netif_msg_link(db), 1);
809 netif_start_queue(dev);
810
811 dm9000_schedule_poll(db);
812
813 return 0;
814 }
815
816 /*
817 * Initilize dm9000 board
818 */
819 static void
820 dm9000_init_dm9000(struct net_device *dev)
821 {
822 board_info_t *db = (board_info_t *) dev->priv;
823 unsigned int imr;
824
825 dm9000_dbg(db, 1, "entering %s\n", __func__);
826
827 /* I/O mode */
828 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
829
830 /* GPIO0 on pre-activate PHY */
831 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
832 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
833 iow(db, DM9000_GPR, 0); /* Enable PHY */
834
835 if (db->flags & DM9000_PLATF_EXT_PHY)
836 iow(db, DM9000_NCR, NCR_EXT_PHY);
837
838 /* Program operating register */
839 iow(db, DM9000_TCR, 0); /* TX Polling clear */
840 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
841 iow(db, DM9000_FCR, 0xff); /* Flow Control */
842 iow(db, DM9000_SMCR, 0); /* Special Mode */
843 /* clear TX status */
844 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
845 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
846
847 /* Set address filter table */
848 dm9000_hash_table(dev);
849
850 imr = IMR_PAR | IMR_PTM | IMR_PRM;
851 if (db->type != TYPE_DM9000E)
852 imr |= IMR_LNKCHNG;
853
854 db->imr_all = imr;
855
856 /* Enable TX/RX interrupt mask */
857 iow(db, DM9000_IMR, imr);
858
859 /* Init Driver variable */
860 db->tx_pkt_cnt = 0;
861 db->queue_pkt_len = 0;
862 dev->trans_start = 0;
863 }
864
865 /*
866 * Hardware start transmission.
867 * Send a packet to media from the upper layer.
868 */
869 static int
870 dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
871 {
872 unsigned long flags;
873 board_info_t *db = (board_info_t *) dev->priv;
874
875 dm9000_dbg(db, 3, "%s:\n", __func__);
876
877 if (db->tx_pkt_cnt > 1)
878 return 1;
879
880 spin_lock_irqsave(&db->lock, flags);
881
882 /* Move data to DM9000 TX RAM */
883 writeb(DM9000_MWCMD, db->io_addr);
884
885 (db->outblk)(db->io_data, skb->data, skb->len);
886 dev->stats.tx_bytes += skb->len;
887
888 db->tx_pkt_cnt++;
889 /* TX control: First packet immediately send, second packet queue */
890 if (db->tx_pkt_cnt == 1) {
891 /* Set TX length to DM9000 */
892 iow(db, DM9000_TXPLL, skb->len);
893 iow(db, DM9000_TXPLH, skb->len >> 8);
894
895 /* Issue TX polling command */
896 iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
897
898 dev->trans_start = jiffies; /* save the time stamp */
899 } else {
900 /* Second packet */
901 db->queue_pkt_len = skb->len;
902 netif_stop_queue(dev);
903 }
904
905 spin_unlock_irqrestore(&db->lock, flags);
906
907 /* free this SKB */
908 dev_kfree_skb(skb);
909
910 return 0;
911 }
912
913 static void
914 dm9000_shutdown(struct net_device *dev)
915 {
916 board_info_t *db = (board_info_t *) dev->priv;
917
918 /* RESET device */
919 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
920 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
921 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
922 iow(db, DM9000_RCR, 0x00); /* Disable RX */
923 }
924
925 /*
926 * Stop the interface.
927 * The interface is stopped when it is brought.
928 */
929 static int
930 dm9000_stop(struct net_device *ndev)
931 {
932 board_info_t *db = (board_info_t *) ndev->priv;
933
934 if (netif_msg_ifdown(db))
935 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
936
937 cancel_delayed_work_sync(&db->phy_poll);
938
939 netif_stop_queue(ndev);
940 netif_carrier_off(ndev);
941
942 /* free interrupt */
943 free_irq(ndev->irq, ndev);
944
945 dm9000_shutdown(ndev);
946
947 return 0;
948 }
949
950 /*
951 * DM9000 interrupt handler
952 * receive the packet to upper layer, free the transmitted packet
953 */
954
955 static void
956 dm9000_tx_done(struct net_device *dev, board_info_t * db)
957 {
958 int tx_status = ior(db, DM9000_NSR); /* Got TX status */
959
960 if (tx_status & (NSR_TX2END | NSR_TX1END)) {
961 /* One packet sent complete */
962 db->tx_pkt_cnt--;
963 dev->stats.tx_packets++;
964
965 if (netif_msg_tx_done(db))
966 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
967
968 /* Queue packet check & send */
969 if (db->tx_pkt_cnt > 0) {
970 iow(db, DM9000_TXPLL, db->queue_pkt_len);
971 iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8);
972 iow(db, DM9000_TCR, TCR_TXREQ);
973 dev->trans_start = jiffies;
974 }
975 netif_wake_queue(dev);
976 }
977 }
978
979 static irqreturn_t
980 dm9000_interrupt(int irq, void *dev_id)
981 {
982 struct net_device *dev = dev_id;
983 board_info_t *db = (board_info_t *) dev->priv;
984 int int_status;
985 u8 reg_save;
986
987 dm9000_dbg(db, 3, "entering %s\n", __func__);
988
989 /* A real interrupt coming */
990
991 spin_lock(&db->lock);
992
993 /* Save previous register address */
994 reg_save = readb(db->io_addr);
995
996 /* Disable all interrupts */
997 iow(db, DM9000_IMR, IMR_PAR);
998
999 /* Got DM9000 interrupt status */
1000 int_status = ior(db, DM9000_ISR); /* Got ISR */
1001 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
1002
1003 if (netif_msg_intr(db))
1004 dev_dbg(db->dev, "interrupt status %02x\n", int_status);
1005
1006 /* Received the coming packet */
1007 if (int_status & ISR_PRS)
1008 dm9000_rx(dev);
1009
1010 /* Trnasmit Interrupt check */
1011 if (int_status & ISR_PTS)
1012 dm9000_tx_done(dev, db);
1013
1014 if (db->type != TYPE_DM9000E) {
1015 if (int_status & ISR_LNKCHNG) {
1016 /* fire a link-change request */
1017 schedule_delayed_work(&db->phy_poll, 1);
1018 }
1019 }
1020
1021 /* Re-enable interrupt mask */
1022 iow(db, DM9000_IMR, db->imr_all);
1023
1024 /* Restore previous register address */
1025 writeb(reg_save, db->io_addr);
1026
1027 spin_unlock(&db->lock);
1028
1029 return IRQ_HANDLED;
1030 }
1031
1032 struct dm9000_rxhdr {
1033 u8 RxPktReady;
1034 u8 RxStatus;
1035 __le16 RxLen;
1036 } __attribute__((__packed__));
1037
1038 /*
1039 * Received a packet and pass to upper layer
1040 */
1041 static void
1042 dm9000_rx(struct net_device *dev)
1043 {
1044 board_info_t *db = (board_info_t *) dev->priv;
1045 struct dm9000_rxhdr rxhdr;
1046 struct sk_buff *skb;
1047 u8 rxbyte, *rdptr;
1048 bool GoodPacket;
1049 int RxLen;
1050
1051 /* Check packet ready or not */
1052 do {
1053 ior(db, DM9000_MRCMDX); /* Dummy read */
1054
1055 /* Get most updated data */
1056 rxbyte = readb(db->io_data);
1057
1058 /* Status check: this byte must be 0 or 1 */
1059 if (rxbyte > DM9000_PKT_RDY) {
1060 dev_warn(db->dev, "status check fail: %d\n", rxbyte);
1061 iow(db, DM9000_RCR, 0x00); /* Stop Device */
1062 iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
1063 return;
1064 }
1065
1066 if (rxbyte != DM9000_PKT_RDY)
1067 return;
1068
1069 /* A packet ready now & Get status/length */
1070 GoodPacket = true;
1071 writeb(DM9000_MRCMD, db->io_addr);
1072
1073 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
1074
1075 RxLen = le16_to_cpu(rxhdr.RxLen);
1076
1077 if (netif_msg_rx_status(db))
1078 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
1079 rxhdr.RxStatus, RxLen);
1080
1081 /* Packet Status check */
1082 if (RxLen < 0x40) {
1083 GoodPacket = false;
1084 if (netif_msg_rx_err(db))
1085 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
1086 }
1087
1088 if (RxLen > DM9000_PKT_MAX) {
1089 dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
1090 }
1091
1092 if (rxhdr.RxStatus & 0xbf) {
1093 GoodPacket = false;
1094 if (rxhdr.RxStatus & 0x01) {
1095 if (netif_msg_rx_err(db))
1096 dev_dbg(db->dev, "fifo error\n");
1097 dev->stats.rx_fifo_errors++;
1098 }
1099 if (rxhdr.RxStatus & 0x02) {
1100 if (netif_msg_rx_err(db))
1101 dev_dbg(db->dev, "crc error\n");
1102 dev->stats.rx_crc_errors++;
1103 }
1104 if (rxhdr.RxStatus & 0x80) {
1105 if (netif_msg_rx_err(db))
1106 dev_dbg(db->dev, "length error\n");
1107 dev->stats.rx_length_errors++;
1108 }
1109 }
1110
1111 /* Move data from DM9000 */
1112 if (GoodPacket
1113 && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
1114 skb_reserve(skb, 2);
1115 rdptr = (u8 *) skb_put(skb, RxLen - 4);
1116
1117 /* Read received packet from RX SRAM */
1118
1119 (db->inblk)(db->io_data, rdptr, RxLen);
1120 dev->stats.rx_bytes += RxLen;
1121
1122 /* Pass to upper layer */
1123 skb->protocol = eth_type_trans(skb, dev);
1124 netif_rx(skb);
1125 dev->stats.rx_packets++;
1126
1127 } else {
1128 /* need to dump the packet's data */
1129
1130 (db->dumpblk)(db->io_data, RxLen);
1131 }
1132 } while (rxbyte == DM9000_PKT_RDY);
1133 }
1134
1135 static unsigned int
1136 dm9000_read_locked(board_info_t *db, int reg)
1137 {
1138 unsigned long flags;
1139 unsigned int ret;
1140
1141 spin_lock_irqsave(&db->lock, flags);
1142 ret = ior(db, reg);
1143 spin_unlock_irqrestore(&db->lock, flags);
1144
1145 return ret;
1146 }
1147
1148 static int dm9000_wait_eeprom(board_info_t *db)
1149 {
1150 unsigned int status;
1151 int timeout = 8; /* wait max 8msec */
1152
1153 /* The DM9000 data sheets say we should be able to
1154 * poll the ERRE bit in EPCR to wait for the EEPROM
1155 * operation. From testing several chips, this bit
1156 * does not seem to work.
1157 *
1158 * We attempt to use the bit, but fall back to the
1159 * timeout (which is why we do not return an error
1160 * on expiry) to say that the EEPROM operation has
1161 * completed.
1162 */
1163
1164 while (1) {
1165 status = dm9000_read_locked(db, DM9000_EPCR);
1166
1167 if ((status & EPCR_ERRE) == 0)
1168 break;
1169
1170 if (timeout-- < 0) {
1171 dev_dbg(db->dev, "timeout waiting EEPROM\n");
1172 break;
1173 }
1174 }
1175
1176 return 0;
1177 }
1178
1179 /*
1180 * Read a word data from EEPROM
1181 */
1182 static void
1183 dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
1184 {
1185 unsigned long flags;
1186
1187 if (db->flags & DM9000_PLATF_NO_EEPROM) {
1188 to[0] = 0xff;
1189 to[1] = 0xff;
1190 return;
1191 }
1192
1193 mutex_lock(&db->addr_lock);
1194
1195 spin_lock_irqsave(&db->lock, flags);
1196
1197 iow(db, DM9000_EPAR, offset);
1198 iow(db, DM9000_EPCR, EPCR_ERPRR);
1199
1200 spin_unlock_irqrestore(&db->lock, flags);
1201
1202 dm9000_wait_eeprom(db);
1203
1204 /* delay for at-least 150uS */
1205 msleep(1);
1206
1207 spin_lock_irqsave(&db->lock, flags);
1208
1209 iow(db, DM9000_EPCR, 0x0);
1210
1211 to[0] = ior(db, DM9000_EPDRL);
1212 to[1] = ior(db, DM9000_EPDRH);
1213
1214 spin_unlock_irqrestore(&db->lock, flags);
1215
1216 mutex_unlock(&db->addr_lock);
1217 }
1218
1219 /*
1220 * Write a word data to SROM
1221 */
1222 static void
1223 dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
1224 {
1225 unsigned long flags;
1226
1227 if (db->flags & DM9000_PLATF_NO_EEPROM)
1228 return;
1229
1230 mutex_lock(&db->addr_lock);
1231
1232 spin_lock_irqsave(&db->lock, flags);
1233 iow(db, DM9000_EPAR, offset);
1234 iow(db, DM9000_EPDRH, data[1]);
1235 iow(db, DM9000_EPDRL, data[0]);
1236 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
1237 spin_unlock_irqrestore(&db->lock, flags);
1238
1239 dm9000_wait_eeprom(db);
1240
1241 mdelay(1); /* wait at least 150uS to clear */
1242
1243 spin_lock_irqsave(&db->lock, flags);
1244 iow(db, DM9000_EPCR, 0);
1245 spin_unlock_irqrestore(&db->lock, flags);
1246
1247 mutex_unlock(&db->addr_lock);
1248 }
1249
1250 /*
1251 * Set DM9000 multicast address
1252 */
1253 static void
1254 dm9000_hash_table(struct net_device *dev)
1255 {
1256 board_info_t *db = (board_info_t *) dev->priv;
1257 struct dev_mc_list *mcptr = dev->mc_list;
1258 int mc_cnt = dev->mc_count;
1259 int i, oft;
1260 u32 hash_val;
1261 u16 hash_table[4];
1262 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
1263 unsigned long flags;
1264
1265 dm9000_dbg(db, 1, "entering %s\n", __func__);
1266
1267 spin_lock_irqsave(&db->lock, flags);
1268
1269 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
1270 iow(db, oft, dev->dev_addr[i]);
1271
1272 /* Clear Hash Table */
1273 for (i = 0; i < 4; i++)
1274 hash_table[i] = 0x0;
1275
1276 /* broadcast address */
1277 hash_table[3] = 0x8000;
1278
1279 if (dev->flags & IFF_PROMISC)
1280 rcr |= RCR_PRMSC;
1281
1282 if (dev->flags & IFF_ALLMULTI)
1283 rcr |= RCR_ALL;
1284
1285 /* the multicast address in Hash Table : 64 bits */
1286 for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1287 hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f;
1288 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1289 }
1290
1291 /* Write the hash table to MAC MD table */
1292 for (i = 0, oft = DM9000_MAR; i < 4; i++) {
1293 iow(db, oft++, hash_table[i]);
1294 iow(db, oft++, hash_table[i] >> 8);
1295 }
1296
1297 iow(db, DM9000_RCR, rcr);
1298 spin_unlock_irqrestore(&db->lock, flags);
1299 }
1300
1301
1302 /*
1303 * Sleep, either by using msleep() or if we are suspending, then
1304 * use mdelay() to sleep.
1305 */
1306 static void dm9000_msleep(board_info_t *db, unsigned int ms)
1307 {
1308 if (db->in_suspend)
1309 mdelay(ms);
1310 else
1311 msleep(ms);
1312 }
1313
1314 /*
1315 * Read a word from phyxcer
1316 */
1317 static int
1318 dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
1319 {
1320 board_info_t *db = (board_info_t *) dev->priv;
1321 unsigned long flags;
1322 unsigned int reg_save;
1323 int ret;
1324
1325 mutex_lock(&db->addr_lock);
1326
1327 spin_lock_irqsave(&db->lock,flags);
1328
1329 /* Save previous register address */
1330 reg_save = readb(db->io_addr);
1331
1332 /* Fill the phyxcer register into REG_0C */
1333 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1334
1335 iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
1336
1337 writeb(reg_save, db->io_addr);
1338 spin_unlock_irqrestore(&db->lock,flags);
1339
1340 dm9000_msleep(db, 1); /* Wait read complete */
1341
1342 spin_lock_irqsave(&db->lock,flags);
1343 reg_save = readb(db->io_addr);
1344
1345 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
1346
1347 /* The read data keeps on REG_0D & REG_0E */
1348 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
1349
1350 /* restore the previous address */
1351 writeb(reg_save, db->io_addr);
1352 spin_unlock_irqrestore(&db->lock,flags);
1353
1354 mutex_unlock(&db->addr_lock);
1355
1356 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
1357 return ret;
1358 }
1359
1360 /*
1361 * Write a word to phyxcer
1362 */
1363 static void
1364 dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
1365 {
1366 board_info_t *db = (board_info_t *) dev->priv;
1367 unsigned long flags;
1368 unsigned long reg_save;
1369
1370 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
1371 mutex_lock(&db->addr_lock);
1372
1373 spin_lock_irqsave(&db->lock,flags);
1374
1375 /* Save previous register address */
1376 reg_save = readb(db->io_addr);
1377
1378 /* Fill the phyxcer register into REG_0C */
1379 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1380
1381 /* Fill the written data into REG_0D & REG_0E */
1382 iow(db, DM9000_EPDRL, value);
1383 iow(db, DM9000_EPDRH, value >> 8);
1384
1385 iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
1386
1387 writeb(reg_save, db->io_addr);
1388 spin_unlock_irqrestore(&db->lock, flags);
1389
1390 dm9000_msleep(db, 1); /* Wait write complete */
1391
1392 spin_lock_irqsave(&db->lock,flags);
1393 reg_save = readb(db->io_addr);
1394
1395 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
1396
1397 /* restore the previous address */
1398 writeb(reg_save, db->io_addr);
1399
1400 spin_unlock_irqrestore(&db->lock, flags);
1401 mutex_unlock(&db->addr_lock);
1402 }
1403
1404 static int
1405 dm9000_drv_suspend(struct platform_device *dev, pm_message_t state)
1406 {
1407 struct net_device *ndev = platform_get_drvdata(dev);
1408 board_info_t *db;
1409
1410 if (ndev) {
1411 db = (board_info_t *) ndev->priv;
1412 db->in_suspend = 1;
1413
1414 if (netif_running(ndev)) {
1415 netif_device_detach(ndev);
1416 dm9000_shutdown(ndev);
1417 }
1418 }
1419 return 0;
1420 }
1421
1422 static int
1423 dm9000_drv_resume(struct platform_device *dev)
1424 {
1425 struct net_device *ndev = platform_get_drvdata(dev);
1426 board_info_t *db = (board_info_t *) ndev->priv;
1427
1428 if (ndev) {
1429
1430 if (netif_running(ndev)) {
1431 dm9000_reset(db);
1432 dm9000_init_dm9000(ndev);
1433
1434 netif_device_attach(ndev);
1435 }
1436
1437 db->in_suspend = 0;
1438 }
1439 return 0;
1440 }
1441
1442 static int __devexit
1443 dm9000_drv_remove(struct platform_device *pdev)
1444 {
1445 struct net_device *ndev = platform_get_drvdata(pdev);
1446
1447 platform_set_drvdata(pdev, NULL);
1448
1449 unregister_netdev(ndev);
1450 dm9000_release_board(pdev, (board_info_t *) ndev->priv);
1451 free_netdev(ndev); /* free device structure */
1452
1453 dev_dbg(&pdev->dev, "released and freed device\n");
1454 return 0;
1455 }
1456
1457 static struct platform_driver dm9000_driver = {
1458 .driver = {
1459 .name = "dm9000",
1460 .owner = THIS_MODULE,
1461 },
1462 .probe = dm9000_probe,
1463 .remove = __devexit_p(dm9000_drv_remove),
1464 .suspend = dm9000_drv_suspend,
1465 .resume = dm9000_drv_resume,
1466 };
1467
1468 static int __init
1469 dm9000_init(void)
1470 {
1471 printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
1472
1473 return platform_driver_register(&dm9000_driver); /* search board and register */
1474 }
1475
1476 static void __exit
1477 dm9000_cleanup(void)
1478 {
1479 platform_driver_unregister(&dm9000_driver);
1480 }
1481
1482 module_init(dm9000_init);
1483 module_exit(dm9000_cleanup);
1484
1485 MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
1486 MODULE_DESCRIPTION("Davicom DM9000 network driver");
1487 MODULE_LICENSE("GPL");
1488 MODULE_ALIAS("platform:dm9000");
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