drivers/net/dsa/mv88e6131.c

   1 /*
   2  * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
   3  * Copyright (c) 2008-2009 Marvell Semiconductor
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/jiffies.h>
  13 #include <linux/list.h>
  14 #include <linux/module.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/phy.h>
  17 #include <net/dsa.h>
  18 #include "mv88e6xxx.h"
  19
  20 static char *mv88e6131_probe(struct device *host_dev, int sw_addr)
  21 {
  22         struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  23         int ret;
  24
  25         if (bus == NULL)
  26                 return NULL;
  27
  28         ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
  29         if (ret >= 0) {
  30                 int ret_masked = ret & 0xfff0;
  31
  32                 if (ret_masked == PORT_SWITCH_ID_6085)
  33                         return "Marvell 88E6085";
  34                 if (ret_masked == PORT_SWITCH_ID_6095)
  35                         return "Marvell 88E6095/88E6095F";
  36                 if (ret == PORT_SWITCH_ID_6131_B2)
  37                         return "Marvell 88E6131 (B2)";
  38                 if (ret_masked == PORT_SWITCH_ID_6131)
  39                         return "Marvell 88E6131";
  40         }
  41
  42         return NULL;
  43 }
  44
  45 static int mv88e6131_setup_global(struct dsa_switch *ds)
  46 {
  47         int ret;
  48
  49         ret = mv88e6xxx_setup_global(ds);
  50         if (ret)
  51                 return ret;
  52
  53         /* Enable the PHY polling unit, don't discard packets with
  54          * excessive collisions, use a weighted fair queueing scheme
  55          * to arbitrate between packet queues, set the maximum frame
  56          * size to 1632, and mask all interrupt sources.
  57          */
  58         REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
  59
  60         /* Set the VLAN ethertype to 0x8100. */
  61         REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
  62
  63         /* Disable ARP mirroring, and configure the upstream port as
  64          * the port to which ingress and egress monitor frames are to
  65          * be sent.
  66          */
  67         REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
  68
  69         /* Disable cascade port functionality unless this device
  70          * is used in a cascade configuration, and set the switch's
  71          * DSA device number.
  72          */
  73         if (ds->dst->pd->nr_chips > 1)
  74                 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
  75         else
  76                 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
  77
  78         /* Force the priority of IGMP/MLD snoop frames and ARP frames
  79          * to the highest setting.
  80          */
  81         REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6131_setup(struct dsa_switch *ds)
  87 {
  88         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  89         int ret;
  90
  91         ret = mv88e6xxx_setup_common(ds);
  92         if (ret < 0)
  93                 return ret;
  94
  95         mv88e6xxx_ppu_state_init(ds);
  96
  97         switch (ps->id) {
  98         case PORT_SWITCH_ID_6085:
  99                 ps->num_ports = 10;
 100                 break;
 101         case PORT_SWITCH_ID_6095:
 102                 ps->num_ports = 11;
 103                 break;
 104         case PORT_SWITCH_ID_6131:
 105         case PORT_SWITCH_ID_6131_B2:
 106                 ps->num_ports = 8;
 107                 break;
 108         default:
 109                 return -ENODEV;
 110         }
 111
 112         ret = mv88e6xxx_switch_reset(ds, false);
 113         if (ret < 0)
 114                 return ret;
 115
 116         ret = mv88e6131_setup_global(ds);
 117         if (ret < 0)
 118                 return ret;
 119
 120         return mv88e6xxx_setup_ports(ds);
 121 }
 122
 123 static int mv88e6131_port_to_phy_addr(struct dsa_switch *ds, int port)
 124 {
 125         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 126
 127         if (port >= 0 && port < ps->num_ports)
 128                 return port;
 129
 130         return -EINVAL;
 131 }
 132
 133 static int
 134 mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
 135 {
 136         int addr = mv88e6131_port_to_phy_addr(ds, port);
 137
 138         if (addr < 0)
 139                 return addr;
 140
 141         return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
 142 }
 143
 144 static int
 145 mv88e6131_phy_write(struct dsa_switch *ds,
 146                               int port, int regnum, u16 val)
 147 {
 148         int addr = mv88e6131_port_to_phy_addr(ds, port);
 149
 150         if (addr < 0)
 151                 return addr;
 152
 153         return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
 154 }
 155
 156 struct dsa_switch_driver mv88e6131_switch_driver = {
 157         .tag_protocol           = DSA_TAG_PROTO_DSA,
 158         .priv_size              = sizeof(struct mv88e6xxx_priv_state),
 159         .probe                  = mv88e6131_probe,
 160         .setup                  = mv88e6131_setup,
 161         .set_addr               = mv88e6xxx_set_addr_direct,
 162         .phy_read               = mv88e6131_phy_read,
 163         .phy_write              = mv88e6131_phy_write,
 164         .poll_link              = mv88e6xxx_poll_link,
 165         .get_strings            = mv88e6xxx_get_strings,
 166         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
 167         .get_sset_count         = mv88e6xxx_get_sset_count,
 168 };
 169
 170 MODULE_ALIAS("platform:mv88e6085");
 171 MODULE_ALIAS("platform:mv88e6095");
 172 MODULE_ALIAS("platform:mv88e6095f");
 173 MODULE_ALIAS("platform:mv88e6131");