2 * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
4 * Copyright (c) 2014 Guenter Roeck
6 * Derived from mv88e6123_61_65.c
7 * Copyright (c) 2008-2009 Marvell Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/delay.h>
16 #include <linux/jiffies.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/netdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/phy.h>
23 #include "mv88e6xxx.h"
25 static char *mv88e6352_probe(struct device
*host_dev
, int sw_addr
)
27 struct mii_bus
*bus
= dsa_host_dev_to_mii_bus(host_dev
);
33 ret
= __mv88e6xxx_reg_read(bus
, sw_addr
, REG_PORT(0), 0x03);
35 if ((ret
& 0xfff0) == 0x1760)
36 return "Marvell 88E6176";
38 return "Marvell 88E6352 (A0)";
40 return "Marvell 88E6352 (A1)";
41 if ((ret
& 0xfff0) == 0x3520)
42 return "Marvell 88E6352";
48 static int mv88e6352_switch_reset(struct dsa_switch
*ds
)
50 unsigned long timeout
;
54 /* Set all ports to the disabled state. */
55 for (i
= 0; i
< 7; i
++) {
56 ret
= REG_READ(REG_PORT(i
), 0x04);
57 REG_WRITE(REG_PORT(i
), 0x04, ret
& 0xfffc);
60 /* Wait for transmit queues to drain. */
61 usleep_range(2000, 4000);
63 /* Reset the switch. Keep PPU active (bit 14, undocumented).
64 * The PPU needs to be active to support indirect phy register
65 * accesses through global registers 0x18 and 0x19.
67 REG_WRITE(REG_GLOBAL
, 0x04, 0xc000);
69 /* Wait up to one second for reset to complete. */
70 timeout
= jiffies
+ 1 * HZ
;
71 while (time_before(jiffies
, timeout
)) {
72 ret
= REG_READ(REG_GLOBAL
, 0x00);
73 if ((ret
& 0x8800) == 0x8800)
75 usleep_range(1000, 2000);
77 if (time_after(jiffies
, timeout
))
83 static int mv88e6352_setup_global(struct dsa_switch
*ds
)
88 /* Discard packets with excessive collisions,
89 * mask all interrupt sources, enable PPU (bit 14, undocumented).
91 REG_WRITE(REG_GLOBAL
, 0x04, 0x6000);
93 /* Set the default address aging time to 5 minutes, and
94 * enable address learn messages to be sent to all message
97 REG_WRITE(REG_GLOBAL
, 0x0a, 0x0148);
99 /* Configure the priority mapping registers. */
100 ret
= mv88e6xxx_config_prio(ds
);
104 /* Configure the upstream port, and configure the upstream
105 * port as the port to which ingress and egress monitor frames
108 REG_WRITE(REG_GLOBAL
, 0x1a, (dsa_upstream_port(ds
) * 0x1110));
110 /* Disable remote management for now, and set the switch's
113 REG_WRITE(REG_GLOBAL
, 0x1c, ds
->index
& 0x1f);
115 /* Send all frames with destination addresses matching
116 * 01:80:c2:00:00:2x to the CPU port.
118 REG_WRITE(REG_GLOBAL2
, 0x02, 0xffff);
120 /* Send all frames with destination addresses matching
121 * 01:80:c2:00:00:0x to the CPU port.
123 REG_WRITE(REG_GLOBAL2
, 0x03, 0xffff);
125 /* Disable the loopback filter, disable flow control
126 * messages, disable flood broadcast override, disable
127 * removing of provider tags, disable ATU age violation
128 * interrupts, disable tag flow control, force flow
129 * control priority to the highest, and send all special
130 * multicast frames to the CPU at the highest priority.
132 REG_WRITE(REG_GLOBAL2
, 0x05, 0x00ff);
134 /* Program the DSA routing table. */
135 for (i
= 0; i
< 32; i
++) {
138 if (i
!= ds
->index
&& i
< ds
->dst
->pd
->nr_chips
)
139 nexthop
= ds
->pd
->rtable
[i
] & 0x1f;
141 REG_WRITE(REG_GLOBAL2
, 0x06, 0x8000 | (i
<< 8) | nexthop
);
144 /* Clear all trunk masks. */
145 for (i
= 0; i
< 8; i
++)
146 REG_WRITE(REG_GLOBAL2
, 0x07, 0x8000 | (i
<< 12) | 0x7f);
148 /* Clear all trunk mappings. */
149 for (i
= 0; i
< 16; i
++)
150 REG_WRITE(REG_GLOBAL2
, 0x08, 0x8000 | (i
<< 11));
152 /* Disable ingress rate limiting by resetting all ingress
153 * rate limit registers to their initial state.
155 for (i
= 0; i
< 7; i
++)
156 REG_WRITE(REG_GLOBAL2
, 0x09, 0x9000 | (i
<< 8));
158 /* Initialise cross-chip port VLAN table to reset defaults. */
159 REG_WRITE(REG_GLOBAL2
, 0x0b, 0x9000);
161 /* Clear the priority override table. */
162 for (i
= 0; i
< 16; i
++)
163 REG_WRITE(REG_GLOBAL2
, 0x0f, 0x8000 | (i
<< 8));
165 /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
170 static int mv88e6352_setup_port(struct dsa_switch
*ds
, int p
)
172 int addr
= REG_PORT(p
);
175 /* MAC Forcing register: don't force link, speed, duplex
176 * or flow control state to any particular values on physical
177 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
180 if (dsa_is_cpu_port(ds
, p
) || ds
->dsa_port_mask
& (1 << p
))
181 REG_WRITE(addr
, 0x01, 0x003e);
183 REG_WRITE(addr
, 0x01, 0x0003);
185 /* Do not limit the period of time that this port can be
186 * paused for by the remote end or the period of time that
187 * this port can pause the remote end.
189 REG_WRITE(addr
, 0x02, 0x0000);
191 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
192 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
193 * tunneling, determine priority by looking at 802.1p and IP
194 * priority fields (IP prio has precedence), and set STP state
197 * If this is the CPU link, use DSA or EDSA tagging depending
198 * on which tagging mode was configured.
200 * If this is a link to another switch, use DSA tagging mode.
202 * If this is the upstream port for this switch, enable
203 * forwarding of unknown unicasts and multicasts.
206 if (dsa_is_cpu_port(ds
, p
)) {
207 if (ds
->dst
->tag_protocol
== DSA_TAG_PROTO_EDSA
)
212 if (ds
->dsa_port_mask
& (1 << p
))
214 if (p
== dsa_upstream_port(ds
))
216 REG_WRITE(addr
, 0x04, val
);
218 /* Port Control 1: disable trunking. Also, if this is the
219 * CPU port, enable learn messages to be sent to this port.
221 REG_WRITE(addr
, 0x05, dsa_is_cpu_port(ds
, p
) ? 0x8000 : 0x0000);
223 /* Port based VLAN map: give each port its own address
224 * database, allow the CPU port to talk to each of the 'real'
225 * ports, and allow each of the 'real' ports to only talk to
228 val
= (p
& 0xf) << 12;
229 if (dsa_is_cpu_port(ds
, p
))
230 val
|= ds
->phys_port_mask
;
232 val
|= 1 << dsa_upstream_port(ds
);
233 REG_WRITE(addr
, 0x06, val
);
235 /* Default VLAN ID and priority: don't set a default VLAN
236 * ID, and set the default packet priority to zero.
238 REG_WRITE(addr
, 0x07, 0x0000);
240 /* Port Control 2: don't force a good FCS, set the maximum
241 * frame size to 10240 bytes, don't let the switch add or
242 * strip 802.1q tags, don't discard tagged or untagged frames
243 * on this port, do a destination address lookup on all
244 * received packets as usual, disable ARP mirroring and don't
245 * send a copy of all transmitted/received frames on this port
248 REG_WRITE(addr
, 0x08, 0x2080);
250 /* Egress rate control: disable egress rate control. */
251 REG_WRITE(addr
, 0x09, 0x0001);
253 /* Egress rate control 2: disable egress rate control. */
254 REG_WRITE(addr
, 0x0a, 0x0000);
256 /* Port Association Vector: when learning source addresses
257 * of packets, add the address to the address database using
258 * a port bitmap that has only the bit for this port set and
259 * the other bits clear.
261 REG_WRITE(addr
, 0x0b, 1 << p
);
263 /* Port ATU control: disable limiting the number of address
264 * database entries that this port is allowed to use.
266 REG_WRITE(addr
, 0x0c, 0x0000);
268 /* Priority Override: disable DA, SA and VTU priority override. */
269 REG_WRITE(addr
, 0x0d, 0x0000);
271 /* Port Ethertype: use the Ethertype DSA Ethertype value. */
272 REG_WRITE(addr
, 0x0f, ETH_P_EDSA
);
274 /* Tag Remap: use an identity 802.1p prio -> switch prio
277 REG_WRITE(addr
, 0x18, 0x3210);
279 /* Tag Remap 2: use an identity 802.1p prio -> switch prio
282 REG_WRITE(addr
, 0x19, 0x7654);
287 #ifdef CONFIG_NET_DSA_HWMON
289 static int mv88e6352_phy_page_read(struct dsa_switch
*ds
,
290 int port
, int page
, int reg
)
292 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
295 mutex_lock(&ps
->phy_mutex
);
296 ret
= mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, page
);
299 ret
= mv88e6xxx_phy_read_indirect(ds
, port
, reg
);
301 mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, 0x0);
302 mutex_unlock(&ps
->phy_mutex
);
306 static int mv88e6352_phy_page_write(struct dsa_switch
*ds
,
307 int port
, int page
, int reg
, int val
)
309 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
312 mutex_lock(&ps
->phy_mutex
);
313 ret
= mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, page
);
317 ret
= mv88e6xxx_phy_write_indirect(ds
, port
, reg
, val
);
319 mv88e6xxx_phy_write_indirect(ds
, port
, 0x16, 0x0);
320 mutex_unlock(&ps
->phy_mutex
);
324 static int mv88e6352_get_temp(struct dsa_switch
*ds
, int *temp
)
330 ret
= mv88e6352_phy_page_read(ds
, 0, 6, 27);
334 *temp
= (ret
& 0xff) - 25;
339 static int mv88e6352_get_temp_limit(struct dsa_switch
*ds
, int *temp
)
345 ret
= mv88e6352_phy_page_read(ds
, 0, 6, 26);
349 *temp
= (((ret
>> 8) & 0x1f) * 5) - 25;
354 static int mv88e6352_set_temp_limit(struct dsa_switch
*ds
, int temp
)
358 ret
= mv88e6352_phy_page_read(ds
, 0, 6, 26);
361 temp
= clamp_val(DIV_ROUND_CLOSEST(temp
, 5) + 5, 0, 0x1f);
362 return mv88e6352_phy_page_write(ds
, 0, 6, 26,
363 (ret
& 0xe0ff) | (temp
<< 8));
366 static int mv88e6352_get_temp_alarm(struct dsa_switch
*ds
, bool *alarm
)
372 ret
= mv88e6352_phy_page_read(ds
, 0, 6, 26);
376 *alarm
= !!(ret
& 0x40);
380 #endif /* CONFIG_NET_DSA_HWMON */
382 static int mv88e6352_setup(struct dsa_switch
*ds
)
384 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
388 mutex_init(&ps
->smi_mutex
);
389 mutex_init(&ps
->stats_mutex
);
390 mutex_init(&ps
->phy_mutex
);
391 mutex_init(&ps
->eeprom_mutex
);
393 ps
->id
= REG_READ(REG_PORT(0), 0x03) & 0xfff0;
395 ret
= mv88e6352_switch_reset(ds
);
399 /* @@@ initialise vtu and atu */
401 ret
= mv88e6352_setup_global(ds
);
405 for (i
= 0; i
< 7; i
++) {
406 ret
= mv88e6352_setup_port(ds
, i
);
414 static int mv88e6352_port_to_phy_addr(int port
)
416 if (port
>= 0 && port
<= 4)
422 mv88e6352_phy_read(struct dsa_switch
*ds
, int port
, int regnum
)
424 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
425 int addr
= mv88e6352_port_to_phy_addr(port
);
431 mutex_lock(&ps
->phy_mutex
);
432 ret
= mv88e6xxx_phy_read_indirect(ds
, addr
, regnum
);
433 mutex_unlock(&ps
->phy_mutex
);
439 mv88e6352_phy_write(struct dsa_switch
*ds
, int port
, int regnum
, u16 val
)
441 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
442 int addr
= mv88e6352_port_to_phy_addr(port
);
448 mutex_lock(&ps
->phy_mutex
);
449 ret
= mv88e6xxx_phy_write_indirect(ds
, addr
, regnum
, val
);
450 mutex_unlock(&ps
->phy_mutex
);
455 static struct mv88e6xxx_hw_stat mv88e6352_hw_stats
[] = {
456 { "in_good_octets", 8, 0x00, },
457 { "in_bad_octets", 4, 0x02, },
458 { "in_unicast", 4, 0x04, },
459 { "in_broadcasts", 4, 0x06, },
460 { "in_multicasts", 4, 0x07, },
461 { "in_pause", 4, 0x16, },
462 { "in_undersize", 4, 0x18, },
463 { "in_fragments", 4, 0x19, },
464 { "in_oversize", 4, 0x1a, },
465 { "in_jabber", 4, 0x1b, },
466 { "in_rx_error", 4, 0x1c, },
467 { "in_fcs_error", 4, 0x1d, },
468 { "out_octets", 8, 0x0e, },
469 { "out_unicast", 4, 0x10, },
470 { "out_broadcasts", 4, 0x13, },
471 { "out_multicasts", 4, 0x12, },
472 { "out_pause", 4, 0x15, },
473 { "excessive", 4, 0x11, },
474 { "collisions", 4, 0x1e, },
475 { "deferred", 4, 0x05, },
476 { "single", 4, 0x14, },
477 { "multiple", 4, 0x17, },
478 { "out_fcs_error", 4, 0x03, },
479 { "late", 4, 0x1f, },
480 { "hist_64bytes", 4, 0x08, },
481 { "hist_65_127bytes", 4, 0x09, },
482 { "hist_128_255bytes", 4, 0x0a, },
483 { "hist_256_511bytes", 4, 0x0b, },
484 { "hist_512_1023bytes", 4, 0x0c, },
485 { "hist_1024_max_bytes", 4, 0x0d, },
486 { "sw_in_discards", 4, 0x110, },
487 { "sw_in_filtered", 2, 0x112, },
488 { "sw_out_filtered", 2, 0x113, },
491 static int mv88e6352_read_eeprom_word(struct dsa_switch
*ds
, int addr
)
493 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
496 mutex_lock(&ps
->eeprom_mutex
);
498 ret
= mv88e6xxx_reg_write(ds
, REG_GLOBAL2
, 0x14,
499 0xc000 | (addr
& 0xff));
503 ret
= mv88e6xxx_eeprom_busy_wait(ds
);
507 ret
= mv88e6xxx_reg_read(ds
, REG_GLOBAL2
, 0x15);
509 mutex_unlock(&ps
->eeprom_mutex
);
513 static int mv88e6352_get_eeprom(struct dsa_switch
*ds
,
514 struct ethtool_eeprom
*eeprom
, u8
*data
)
520 offset
= eeprom
->offset
;
524 eeprom
->magic
= 0xc3ec4951;
526 ret
= mv88e6xxx_eeprom_load_wait(ds
);
533 word
= mv88e6352_read_eeprom_word(ds
, offset
>> 1);
537 *data
++ = (word
>> 8) & 0xff;
547 word
= mv88e6352_read_eeprom_word(ds
, offset
>> 1);
551 *data
++ = word
& 0xff;
552 *data
++ = (word
>> 8) & 0xff;
562 word
= mv88e6352_read_eeprom_word(ds
, offset
>> 1);
566 *data
++ = word
& 0xff;
576 static int mv88e6352_eeprom_is_readonly(struct dsa_switch
*ds
)
580 ret
= mv88e6xxx_reg_read(ds
, REG_GLOBAL2
, 0x14);
590 static int mv88e6352_write_eeprom_word(struct dsa_switch
*ds
, int addr
,
593 struct mv88e6xxx_priv_state
*ps
= ds_to_priv(ds
);
596 mutex_lock(&ps
->eeprom_mutex
);
598 ret
= mv88e6xxx_reg_write(ds
, REG_GLOBAL2
, 0x15, data
);
602 ret
= mv88e6xxx_reg_write(ds
, REG_GLOBAL2
, 0x14,
603 0xb000 | (addr
& 0xff));
607 ret
= mv88e6xxx_eeprom_busy_wait(ds
);
609 mutex_unlock(&ps
->eeprom_mutex
);
613 static int mv88e6352_set_eeprom(struct dsa_switch
*ds
,
614 struct ethtool_eeprom
*eeprom
, u8
*data
)
620 if (eeprom
->magic
!= 0xc3ec4951)
623 ret
= mv88e6352_eeprom_is_readonly(ds
);
627 offset
= eeprom
->offset
;
631 ret
= mv88e6xxx_eeprom_load_wait(ds
);
638 word
= mv88e6352_read_eeprom_word(ds
, offset
>> 1);
642 word
= (*data
++ << 8) | (word
& 0xff);
644 ret
= mv88e6352_write_eeprom_word(ds
, offset
>> 1, word
);
657 word
|= *data
++ << 8;
659 ret
= mv88e6352_write_eeprom_word(ds
, offset
>> 1, word
);
671 word
= mv88e6352_read_eeprom_word(ds
, offset
>> 1);
675 word
= (word
& 0xff00) | *data
++;
677 ret
= mv88e6352_write_eeprom_word(ds
, offset
>> 1, word
);
690 mv88e6352_get_strings(struct dsa_switch
*ds
, int port
, uint8_t *data
)
692 mv88e6xxx_get_strings(ds
, ARRAY_SIZE(mv88e6352_hw_stats
),
693 mv88e6352_hw_stats
, port
, data
);
697 mv88e6352_get_ethtool_stats(struct dsa_switch
*ds
, int port
, uint64_t *data
)
699 mv88e6xxx_get_ethtool_stats(ds
, ARRAY_SIZE(mv88e6352_hw_stats
),
700 mv88e6352_hw_stats
, port
, data
);
703 static int mv88e6352_get_sset_count(struct dsa_switch
*ds
)
705 return ARRAY_SIZE(mv88e6352_hw_stats
);
708 struct dsa_switch_driver mv88e6352_switch_driver
= {
709 .tag_protocol
= DSA_TAG_PROTO_EDSA
,
710 .priv_size
= sizeof(struct mv88e6xxx_priv_state
),
711 .probe
= mv88e6352_probe
,
712 .setup
= mv88e6352_setup
,
713 .set_addr
= mv88e6xxx_set_addr_indirect
,
714 .phy_read
= mv88e6352_phy_read
,
715 .phy_write
= mv88e6352_phy_write
,
716 .poll_link
= mv88e6xxx_poll_link
,
717 .get_strings
= mv88e6352_get_strings
,
718 .get_ethtool_stats
= mv88e6352_get_ethtool_stats
,
719 .get_sset_count
= mv88e6352_get_sset_count
,
720 #ifdef CONFIG_NET_DSA_HWMON
721 .get_temp
= mv88e6352_get_temp
,
722 .get_temp_limit
= mv88e6352_get_temp_limit
,
723 .set_temp_limit
= mv88e6352_set_temp_limit
,
724 .get_temp_alarm
= mv88e6352_get_temp_alarm
,
726 .get_eeprom
= mv88e6352_get_eeprom
,
727 .set_eeprom
= mv88e6352_set_eeprom
,
728 .get_regs_len
= mv88e6xxx_get_regs_len
,
729 .get_regs
= mv88e6xxx_get_regs
,
732 MODULE_ALIAS("platform:mv88e6352");