1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
58 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
);
59 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
);
60 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
);
61 static s32
e1000_check_for_serdes_link_82571(struct e1000_hw
*hw
);
62 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
63 u16 words
, u16
*data
);
64 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
);
65 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
);
66 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
);
68 static void e1000_clear_vfta_82571(struct e1000_hw
*hw
);
69 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
);
70 static s32
e1000_led_on_82574(struct e1000_hw
*hw
);
71 static void e1000_put_hw_semaphore_82571(struct e1000_hw
*hw
);
72 static void e1000_power_down_phy_copper_82571(struct e1000_hw
*hw
);
75 * e1000_init_phy_params_82571 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
78 static s32
e1000_init_phy_params_82571(struct e1000_hw
*hw
)
80 struct e1000_phy_info
*phy
= &hw
->phy
;
83 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
84 phy
->type
= e1000_phy_none
;
89 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
90 phy
->reset_delay_us
= 100;
92 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
93 phy
->ops
.power_down
= e1000_power_down_phy_copper_82571
;
95 switch (hw
->mac
.type
) {
98 phy
->type
= e1000_phy_igp_2
;
101 phy
->type
= e1000_phy_m88
;
105 phy
->type
= e1000_phy_bm
;
108 return -E1000_ERR_PHY
;
112 /* This can only be done after all function pointers are setup. */
113 ret_val
= e1000_get_phy_id_82571(hw
);
116 switch (hw
->mac
.type
) {
119 if (phy
->id
!= IGP01E1000_I_PHY_ID
)
120 return -E1000_ERR_PHY
;
123 if (phy
->id
!= M88E1111_I_PHY_ID
)
124 return -E1000_ERR_PHY
;
128 if (phy
->id
!= BME1000_E_PHY_ID_R2
)
129 return -E1000_ERR_PHY
;
132 return -E1000_ERR_PHY
;
140 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
141 * @hw: pointer to the HW structure
143 static s32
e1000_init_nvm_params_82571(struct e1000_hw
*hw
)
145 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
146 u32 eecd
= er32(EECD
);
149 nvm
->opcode_bits
= 8;
151 switch (nvm
->override
) {
152 case e1000_nvm_override_spi_large
:
154 nvm
->address_bits
= 16;
156 case e1000_nvm_override_spi_small
:
158 nvm
->address_bits
= 8;
161 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
162 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
166 switch (hw
->mac
.type
) {
170 if (((eecd
>> 15) & 0x3) == 0x3) {
171 nvm
->type
= e1000_nvm_flash_hw
;
172 nvm
->word_size
= 2048;
174 * Autonomous Flash update bit must be cleared due
175 * to Flash update issue.
177 eecd
&= ~E1000_EECD_AUPDEN
;
183 nvm
->type
= e1000_nvm_eeprom_spi
;
184 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
185 E1000_EECD_SIZE_EX_SHIFT
);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
192 /* EEPROM access above 16k is unsupported */
195 nvm
->word_size
= 1 << size
;
203 * e1000_init_mac_params_82571 - Init MAC func ptrs.
204 * @hw: pointer to the HW structure
206 static s32
e1000_init_mac_params_82571(struct e1000_adapter
*adapter
)
208 struct e1000_hw
*hw
= &adapter
->hw
;
209 struct e1000_mac_info
*mac
= &hw
->mac
;
210 struct e1000_mac_operations
*func
= &mac
->ops
;
213 bool force_clear_smbi
= false;
216 switch (adapter
->pdev
->device
) {
217 case E1000_DEV_ID_82571EB_FIBER
:
218 case E1000_DEV_ID_82572EI_FIBER
:
219 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
220 hw
->phy
.media_type
= e1000_media_type_fiber
;
222 case E1000_DEV_ID_82571EB_SERDES
:
223 case E1000_DEV_ID_82572EI_SERDES
:
224 case E1000_DEV_ID_82571EB_SERDES_DUAL
:
225 case E1000_DEV_ID_82571EB_SERDES_QUAD
:
226 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
229 hw
->phy
.media_type
= e1000_media_type_copper
;
233 /* Set mta register count */
234 mac
->mta_reg_count
= 128;
235 /* Set rar entry count */
236 mac
->rar_entry_count
= E1000_RAR_ENTRIES
;
237 /* Adaptive IFS supported */
238 mac
->adaptive_ifs
= true;
241 switch (hw
->phy
.media_type
) {
242 case e1000_media_type_copper
:
243 func
->setup_physical_interface
= e1000_setup_copper_link_82571
;
244 func
->check_for_link
= e1000e_check_for_copper_link
;
245 func
->get_link_up_info
= e1000e_get_speed_and_duplex_copper
;
247 case e1000_media_type_fiber
:
248 func
->setup_physical_interface
=
249 e1000_setup_fiber_serdes_link_82571
;
250 func
->check_for_link
= e1000e_check_for_fiber_link
;
251 func
->get_link_up_info
=
252 e1000e_get_speed_and_duplex_fiber_serdes
;
254 case e1000_media_type_internal_serdes
:
255 func
->setup_physical_interface
=
256 e1000_setup_fiber_serdes_link_82571
;
257 func
->check_for_link
= e1000_check_for_serdes_link_82571
;
258 func
->get_link_up_info
=
259 e1000e_get_speed_and_duplex_fiber_serdes
;
262 return -E1000_ERR_CONFIG
;
266 switch (hw
->mac
.type
) {
268 func
->set_lan_id
= e1000_set_lan_id_single_port
;
269 func
->check_mng_mode
= e1000e_check_mng_mode_generic
;
270 func
->led_on
= e1000e_led_on_generic
;
273 mac
->has_fwsm
= true;
275 * ARC supported; valid only if manageability features are
278 mac
->arc_subsystem_valid
=
279 (er32(FWSM
) & E1000_FWSM_MODE_MASK
)
284 func
->set_lan_id
= e1000_set_lan_id_single_port
;
285 func
->check_mng_mode
= e1000_check_mng_mode_82574
;
286 func
->led_on
= e1000_led_on_82574
;
289 func
->check_mng_mode
= e1000e_check_mng_mode_generic
;
290 func
->led_on
= e1000e_led_on_generic
;
293 mac
->has_fwsm
= true;
298 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
299 * first NVM or PHY acess. This should be done for single-port
300 * devices, and for one port only on dual-port devices so that
301 * for those devices we can still use the SMBI lock to synchronize
302 * inter-port accesses to the PHY & NVM.
304 switch (hw
->mac
.type
) {
309 if (!(swsm2
& E1000_SWSM2_LOCK
)) {
310 /* Only do this for the first interface on this card */
312 swsm2
| E1000_SWSM2_LOCK
);
313 force_clear_smbi
= true;
315 force_clear_smbi
= false;
318 force_clear_smbi
= true;
322 if (force_clear_smbi
) {
323 /* Make sure SWSM.SMBI is clear */
325 if (swsm
& E1000_SWSM_SMBI
) {
326 /* This bit should not be set on a first interface, and
327 * indicates that the bootagent or EFI code has
328 * improperly left this bit enabled
330 e_dbg("Please update your 82571 Bootagent\n");
332 ew32(SWSM
, swsm
& ~E1000_SWSM_SMBI
);
336 * Initialize device specific counter of SMBI acquisition
339 hw
->dev_spec
.e82571
.smb_counter
= 0;
344 static s32
e1000_get_variants_82571(struct e1000_adapter
*adapter
)
346 struct e1000_hw
*hw
= &adapter
->hw
;
347 static int global_quad_port_a
; /* global port a indication */
348 struct pci_dev
*pdev
= adapter
->pdev
;
349 int is_port_b
= er32(STATUS
) & E1000_STATUS_FUNC_1
;
352 rc
= e1000_init_mac_params_82571(adapter
);
356 rc
= e1000_init_nvm_params_82571(hw
);
360 rc
= e1000_init_phy_params_82571(hw
);
364 /* tag quad port adapters first, it's used below */
365 switch (pdev
->device
) {
366 case E1000_DEV_ID_82571EB_QUAD_COPPER
:
367 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
368 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP
:
369 case E1000_DEV_ID_82571PT_QUAD_COPPER
:
370 adapter
->flags
|= FLAG_IS_QUAD_PORT
;
371 /* mark the first port */
372 if (global_quad_port_a
== 0)
373 adapter
->flags
|= FLAG_IS_QUAD_PORT_A
;
374 /* Reset for multiple quad port adapters */
375 global_quad_port_a
++;
376 if (global_quad_port_a
== 4)
377 global_quad_port_a
= 0;
383 switch (adapter
->hw
.mac
.type
) {
385 /* these dual ports don't have WoL on port B at all */
386 if (((pdev
->device
== E1000_DEV_ID_82571EB_FIBER
) ||
387 (pdev
->device
== E1000_DEV_ID_82571EB_SERDES
) ||
388 (pdev
->device
== E1000_DEV_ID_82571EB_COPPER
)) &&
390 adapter
->flags
&= ~FLAG_HAS_WOL
;
391 /* quad ports only support WoL on port A */
392 if (adapter
->flags
& FLAG_IS_QUAD_PORT
&&
393 (!(adapter
->flags
& FLAG_IS_QUAD_PORT_A
)))
394 adapter
->flags
&= ~FLAG_HAS_WOL
;
395 /* Does not support WoL on any port */
396 if (pdev
->device
== E1000_DEV_ID_82571EB_SERDES_QUAD
)
397 adapter
->flags
&= ~FLAG_HAS_WOL
;
402 /* Disable ASPM L0s due to hardware errata */
403 e1000e_disable_aspm(adapter
->pdev
, PCIE_LINK_STATE_L0S
);
405 if (pdev
->device
== E1000_DEV_ID_82573L
) {
406 adapter
->flags
|= FLAG_HAS_JUMBO_FRAMES
;
407 adapter
->max_hw_frame_size
= DEFAULT_JUMBO
;
418 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
419 * @hw: pointer to the HW structure
421 * Reads the PHY registers and stores the PHY ID and possibly the PHY
422 * revision in the hardware structure.
424 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
)
426 struct e1000_phy_info
*phy
= &hw
->phy
;
430 switch (hw
->mac
.type
) {
434 * The 82571 firmware may still be configuring the PHY.
435 * In this case, we cannot access the PHY until the
436 * configuration is done. So we explicitly set the
439 phy
->id
= IGP01E1000_I_PHY_ID
;
442 return e1000e_get_phy_id(hw
);
446 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
450 phy
->id
= (u32
)(phy_id
<< 16);
452 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
456 phy
->id
|= (u32
)(phy_id
);
457 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
460 return -E1000_ERR_PHY
;
468 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
469 * @hw: pointer to the HW structure
471 * Acquire the HW semaphore to access the PHY or NVM
473 static s32
e1000_get_hw_semaphore_82571(struct e1000_hw
*hw
)
476 s32 sw_timeout
= hw
->nvm
.word_size
+ 1;
477 s32 fw_timeout
= hw
->nvm
.word_size
+ 1;
481 * If we have timedout 3 times on trying to acquire
482 * the inter-port SMBI semaphore, there is old code
483 * operating on the other port, and it is not
484 * releasing SMBI. Modify the number of times that
485 * we try for the semaphore to interwork with this
488 if (hw
->dev_spec
.e82571
.smb_counter
> 2)
491 /* Get the SW semaphore */
492 while (i
< sw_timeout
) {
494 if (!(swsm
& E1000_SWSM_SMBI
))
501 if (i
== sw_timeout
) {
502 e_dbg("Driver can't access device - SMBI bit is set.\n");
503 hw
->dev_spec
.e82571
.smb_counter
++;
505 /* Get the FW semaphore. */
506 for (i
= 0; i
< fw_timeout
; i
++) {
508 ew32(SWSM
, swsm
| E1000_SWSM_SWESMBI
);
510 /* Semaphore acquired if bit latched */
511 if (er32(SWSM
) & E1000_SWSM_SWESMBI
)
517 if (i
== fw_timeout
) {
518 /* Release semaphores */
519 e1000_put_hw_semaphore_82571(hw
);
520 e_dbg("Driver can't access the NVM\n");
521 return -E1000_ERR_NVM
;
528 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
529 * @hw: pointer to the HW structure
531 * Release hardware semaphore used to access the PHY or NVM
533 static void e1000_put_hw_semaphore_82571(struct e1000_hw
*hw
)
538 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
543 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
544 * @hw: pointer to the HW structure
546 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
547 * Then for non-82573 hardware, set the EEPROM access request bit and wait
548 * for EEPROM access grant bit. If the access grant bit is not set, release
549 * hardware semaphore.
551 static s32
e1000_acquire_nvm_82571(struct e1000_hw
*hw
)
555 ret_val
= e1000_get_hw_semaphore_82571(hw
);
559 switch (hw
->mac
.type
) {
565 ret_val
= e1000e_acquire_nvm(hw
);
570 e1000_put_hw_semaphore_82571(hw
);
576 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
577 * @hw: pointer to the HW structure
579 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
581 static void e1000_release_nvm_82571(struct e1000_hw
*hw
)
583 e1000e_release_nvm(hw
);
584 e1000_put_hw_semaphore_82571(hw
);
588 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
589 * @hw: pointer to the HW structure
590 * @offset: offset within the EEPROM to be written to
591 * @words: number of words to write
592 * @data: 16 bit word(s) to be written to the EEPROM
594 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
596 * If e1000e_update_nvm_checksum is not called after this function, the
597 * EEPROM will most likely contain an invalid checksum.
599 static s32
e1000_write_nvm_82571(struct e1000_hw
*hw
, u16 offset
, u16 words
,
604 switch (hw
->mac
.type
) {
608 ret_val
= e1000_write_nvm_eewr_82571(hw
, offset
, words
, data
);
612 ret_val
= e1000e_write_nvm_spi(hw
, offset
, words
, data
);
615 ret_val
= -E1000_ERR_NVM
;
623 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
624 * @hw: pointer to the HW structure
626 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
627 * up to the checksum. Then calculates the EEPROM checksum and writes the
628 * value to the EEPROM.
630 static s32
e1000_update_nvm_checksum_82571(struct e1000_hw
*hw
)
636 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
641 * If our nvm is an EEPROM, then we're done
642 * otherwise, commit the checksum to the flash NVM.
644 if (hw
->nvm
.type
!= e1000_nvm_flash_hw
)
647 /* Check for pending operations. */
648 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
650 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
654 if (i
== E1000_FLASH_UPDATES
)
655 return -E1000_ERR_NVM
;
657 /* Reset the firmware if using STM opcode. */
658 if ((er32(FLOP
) & 0xFF00) == E1000_STM_OPCODE
) {
660 * The enabling of and the actual reset must be done
661 * in two write cycles.
663 ew32(HICR
, E1000_HICR_FW_RESET_ENABLE
);
665 ew32(HICR
, E1000_HICR_FW_RESET
);
668 /* Commit the write to flash */
669 eecd
= er32(EECD
) | E1000_EECD_FLUPD
;
672 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
674 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
678 if (i
== E1000_FLASH_UPDATES
)
679 return -E1000_ERR_NVM
;
685 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
686 * @hw: pointer to the HW structure
688 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
689 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
691 static s32
e1000_validate_nvm_checksum_82571(struct e1000_hw
*hw
)
693 if (hw
->nvm
.type
== e1000_nvm_flash_hw
)
694 e1000_fix_nvm_checksum_82571(hw
);
696 return e1000e_validate_nvm_checksum_generic(hw
);
700 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
701 * @hw: pointer to the HW structure
702 * @offset: offset within the EEPROM to be written to
703 * @words: number of words to write
704 * @data: 16 bit word(s) to be written to the EEPROM
706 * After checking for invalid values, poll the EEPROM to ensure the previous
707 * command has completed before trying to write the next word. After write
708 * poll for completion.
710 * If e1000e_update_nvm_checksum is not called after this function, the
711 * EEPROM will most likely contain an invalid checksum.
713 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
714 u16 words
, u16
*data
)
716 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
721 * A check for invalid values: offset too large, too many words,
722 * and not enough words.
724 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
726 e_dbg("nvm parameter(s) out of bounds\n");
727 return -E1000_ERR_NVM
;
730 for (i
= 0; i
< words
; i
++) {
731 eewr
= (data
[i
] << E1000_NVM_RW_REG_DATA
) |
732 ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
733 E1000_NVM_RW_REG_START
;
735 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
741 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
750 * e1000_get_cfg_done_82571 - Poll for configuration done
751 * @hw: pointer to the HW structure
753 * Reads the management control register for the config done bit to be set.
755 static s32
e1000_get_cfg_done_82571(struct e1000_hw
*hw
)
757 s32 timeout
= PHY_CFG_TIMEOUT
;
761 E1000_NVM_CFG_DONE_PORT_0
)
767 e_dbg("MNG configuration cycle has not completed.\n");
768 return -E1000_ERR_RESET
;
775 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
776 * @hw: pointer to the HW structure
777 * @active: true to enable LPLU, false to disable
779 * Sets the LPLU D0 state according to the active flag. When activating LPLU
780 * this function also disables smart speed and vice versa. LPLU will not be
781 * activated unless the device autonegotiation advertisement meets standards
782 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
783 * pointer entry point only called by PHY setup routines.
785 static s32
e1000_set_d0_lplu_state_82571(struct e1000_hw
*hw
, bool active
)
787 struct e1000_phy_info
*phy
= &hw
->phy
;
791 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
796 data
|= IGP02E1000_PM_D0_LPLU
;
797 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
801 /* When LPLU is enabled, we should disable SmartSpeed */
802 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
803 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
804 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
808 data
&= ~IGP02E1000_PM_D0_LPLU
;
809 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
811 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
812 * during Dx states where the power conservation is most
813 * important. During driver activity we should enable
814 * SmartSpeed, so performance is maintained.
816 if (phy
->smart_speed
== e1000_smart_speed_on
) {
817 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
822 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
823 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
827 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
828 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
833 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
834 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
845 * e1000_reset_hw_82571 - Reset hardware
846 * @hw: pointer to the HW structure
848 * This resets the hardware into a known state.
850 static s32
e1000_reset_hw_82571(struct e1000_hw
*hw
)
852 u32 ctrl
, extcnf_ctrl
, ctrl_ext
, icr
;
857 * Prevent the PCI-E bus from sticking if there is no TLP connection
858 * on the last TLP read/write transaction when MAC is reset.
860 ret_val
= e1000e_disable_pcie_master(hw
);
862 e_dbg("PCI-E Master disable polling has failed.\n");
864 e_dbg("Masking off all interrupts\n");
865 ew32(IMC
, 0xffffffff);
868 ew32(TCTL
, E1000_TCTL_PSP
);
874 * Must acquire the MDIO ownership before MAC reset.
875 * Ownership defaults to firmware after a reset.
877 switch (hw
->mac
.type
) {
881 extcnf_ctrl
= er32(EXTCNF_CTRL
);
882 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
885 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
886 extcnf_ctrl
= er32(EXTCNF_CTRL
);
888 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
891 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
895 } while (i
< MDIO_OWNERSHIP_TIMEOUT
);
903 e_dbg("Issuing a global reset to MAC\n");
904 ew32(CTRL
, ctrl
| E1000_CTRL_RST
);
906 if (hw
->nvm
.type
== e1000_nvm_flash_hw
) {
908 ctrl_ext
= er32(CTRL_EXT
);
909 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
910 ew32(CTRL_EXT
, ctrl_ext
);
914 ret_val
= e1000e_get_auto_rd_done(hw
);
916 /* We don't want to continue accessing MAC registers. */
920 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
921 * Need to wait for Phy configuration completion before accessing
925 switch (hw
->mac
.type
) {
935 /* Clear any pending interrupt events. */
936 ew32(IMC
, 0xffffffff);
939 /* Install any alternate MAC address into RAR0 */
940 ret_val
= e1000_check_alt_mac_addr_generic(hw
);
944 e1000e_set_laa_state_82571(hw
, true);
946 /* Reinitialize the 82571 serdes link state machine */
947 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
948 hw
->mac
.serdes_link_state
= e1000_serdes_link_down
;
954 * e1000_init_hw_82571 - Initialize hardware
955 * @hw: pointer to the HW structure
957 * This inits the hardware readying it for operation.
959 static s32
e1000_init_hw_82571(struct e1000_hw
*hw
)
961 struct e1000_mac_info
*mac
= &hw
->mac
;
964 u16 i
, rar_count
= mac
->rar_entry_count
;
966 e1000_initialize_hw_bits_82571(hw
);
968 /* Initialize identification LED */
969 ret_val
= e1000e_id_led_init(hw
);
971 e_dbg("Error initializing identification LED\n");
972 /* This is not fatal and we should not stop init due to this */
974 /* Disabling VLAN filtering */
975 e_dbg("Initializing the IEEE VLAN\n");
976 mac
->ops
.clear_vfta(hw
);
978 /* Setup the receive address. */
980 * If, however, a locally administered address was assigned to the
981 * 82571, we must reserve a RAR for it to work around an issue where
982 * resetting one port will reload the MAC on the other port.
984 if (e1000e_get_laa_state_82571(hw
))
986 e1000e_init_rx_addrs(hw
, rar_count
);
988 /* Zero out the Multicast HASH table */
989 e_dbg("Zeroing the MTA\n");
990 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
991 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
993 /* Setup link and flow control */
994 ret_val
= e1000_setup_link_82571(hw
);
996 /* Set the transmit descriptor write-back policy */
997 reg_data
= er32(TXDCTL(0));
998 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
999 E1000_TXDCTL_FULL_TX_DESC_WB
|
1000 E1000_TXDCTL_COUNT_DESC
;
1001 ew32(TXDCTL(0), reg_data
);
1003 /* ...for both queues. */
1004 switch (mac
->type
) {
1006 e1000e_enable_tx_pkt_filtering(hw
);
1010 reg_data
= er32(GCR
);
1011 reg_data
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
1012 ew32(GCR
, reg_data
);
1015 reg_data
= er32(TXDCTL(1));
1016 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
1017 E1000_TXDCTL_FULL_TX_DESC_WB
|
1018 E1000_TXDCTL_COUNT_DESC
;
1019 ew32(TXDCTL(1), reg_data
);
1024 * Clear all of the statistics registers (clear on read). It is
1025 * important that we do this after we have tried to establish link
1026 * because the symbol error count will increment wildly if there
1029 e1000_clear_hw_cntrs_82571(hw
);
1035 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1036 * @hw: pointer to the HW structure
1038 * Initializes required hardware-dependent bits needed for normal operation.
1040 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
)
1044 /* Transmit Descriptor Control 0 */
1045 reg
= er32(TXDCTL(0));
1047 ew32(TXDCTL(0), reg
);
1049 /* Transmit Descriptor Control 1 */
1050 reg
= er32(TXDCTL(1));
1052 ew32(TXDCTL(1), reg
);
1054 /* Transmit Arbitration Control 0 */
1055 reg
= er32(TARC(0));
1056 reg
&= ~(0xF << 27); /* 30:27 */
1057 switch (hw
->mac
.type
) {
1060 reg
|= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1067 /* Transmit Arbitration Control 1 */
1068 reg
= er32(TARC(1));
1069 switch (hw
->mac
.type
) {
1072 reg
&= ~((1 << 29) | (1 << 30));
1073 reg
|= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1074 if (er32(TCTL
) & E1000_TCTL_MULR
)
1084 /* Device Control */
1085 switch (hw
->mac
.type
) {
1097 /* Extended Device Control */
1098 switch (hw
->mac
.type
) {
1102 reg
= er32(CTRL_EXT
);
1105 ew32(CTRL_EXT
, reg
);
1111 if (hw
->mac
.type
== e1000_82571
) {
1112 reg
= er32(PBA_ECC
);
1113 reg
|= E1000_PBA_ECC_CORR_EN
;
1117 * Workaround for hardware errata.
1118 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1121 if ((hw
->mac
.type
== e1000_82571
) ||
1122 (hw
->mac
.type
== e1000_82572
)) {
1123 reg
= er32(CTRL_EXT
);
1124 reg
&= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN
;
1125 ew32(CTRL_EXT
, reg
);
1129 /* PCI-Ex Control Registers */
1130 switch (hw
->mac
.type
) {
1138 * Workaround for hardware errata.
1139 * apply workaround for hardware errata documented in errata
1140 * docs Fixes issue where some error prone or unreliable PCIe
1141 * completions are occurring, particularly with ASPM enabled.
1142 * Without fix, issue can cause tx timeouts.
1154 * e1000_clear_vfta_82571 - Clear VLAN filter table
1155 * @hw: pointer to the HW structure
1157 * Clears the register array which contains the VLAN filter table by
1158 * setting all the values to 0.
1160 static void e1000_clear_vfta_82571(struct e1000_hw
*hw
)
1164 u32 vfta_offset
= 0;
1165 u32 vfta_bit_in_reg
= 0;
1167 switch (hw
->mac
.type
) {
1171 if (hw
->mng_cookie
.vlan_id
!= 0) {
1173 * The VFTA is a 4096b bit-field, each identifying
1174 * a single VLAN ID. The following operations
1175 * determine which 32b entry (i.e. offset) into the
1176 * array we want to set the VLAN ID (i.e. bit) of
1177 * the manageability unit.
1179 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
1180 E1000_VFTA_ENTRY_SHIFT
) &
1181 E1000_VFTA_ENTRY_MASK
;
1182 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
1183 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
1189 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
1191 * If the offset we want to clear is the same offset of the
1192 * manageability VLAN ID, then clear all bits except that of
1193 * the manageability unit.
1195 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
1196 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, vfta_value
);
1202 * e1000_check_mng_mode_82574 - Check manageability is enabled
1203 * @hw: pointer to the HW structure
1205 * Reads the NVM Initialization Control Word 2 and returns true
1206 * (>0) if any manageability is enabled, else false (0).
1208 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
)
1212 e1000_read_nvm(hw
, NVM_INIT_CONTROL2_REG
, 1, &data
);
1213 return (data
& E1000_NVM_INIT_CTRL2_MNGM
) != 0;
1217 * e1000_led_on_82574 - Turn LED on
1218 * @hw: pointer to the HW structure
1222 static s32
e1000_led_on_82574(struct e1000_hw
*hw
)
1227 ctrl
= hw
->mac
.ledctl_mode2
;
1228 if (!(E1000_STATUS_LU
& er32(STATUS
))) {
1230 * If no link, then turn LED on by setting the invert bit
1231 * for each LED that's "on" (0x0E) in ledctl_mode2.
1233 for (i
= 0; i
< 4; i
++)
1234 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1235 E1000_LEDCTL_MODE_LED_ON
)
1236 ctrl
|= (E1000_LEDCTL_LED0_IVRT
<< (i
* 8));
1244 * e1000_setup_link_82571 - Setup flow control and link settings
1245 * @hw: pointer to the HW structure
1247 * Determines which flow control settings to use, then configures flow
1248 * control. Calls the appropriate media-specific link configuration
1249 * function. Assuming the adapter has a valid link partner, a valid link
1250 * should be established. Assumes the hardware has previously been reset
1251 * and the transmitter and receiver are not enabled.
1253 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
)
1256 * 82573 does not have a word in the NVM to determine
1257 * the default flow control setting, so we explicitly
1260 switch (hw
->mac
.type
) {
1264 if (hw
->fc
.requested_mode
== e1000_fc_default
)
1265 hw
->fc
.requested_mode
= e1000_fc_full
;
1271 return e1000e_setup_link(hw
);
1275 * e1000_setup_copper_link_82571 - Configure copper link settings
1276 * @hw: pointer to the HW structure
1278 * Configures the link for auto-neg or forced speed and duplex. Then we check
1279 * for link, once link is established calls to configure collision distance
1280 * and flow control are called.
1282 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
)
1288 ctrl
|= E1000_CTRL_SLU
;
1289 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1292 switch (hw
->phy
.type
) {
1295 ret_val
= e1000e_copper_link_setup_m88(hw
);
1297 case e1000_phy_igp_2
:
1298 ret_val
= e1000e_copper_link_setup_igp(hw
);
1301 return -E1000_ERR_PHY
;
1308 ret_val
= e1000e_setup_copper_link(hw
);
1314 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1315 * @hw: pointer to the HW structure
1317 * Configures collision distance and flow control for fiber and serdes links.
1318 * Upon successful setup, poll for link.
1320 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
)
1322 switch (hw
->mac
.type
) {
1326 * If SerDes loopback mode is entered, there is no form
1327 * of reset to take the adapter out of that mode. So we
1328 * have to explicitly take the adapter out of loopback
1329 * mode. This prevents drivers from twiddling their thumbs
1330 * if another tool failed to take it out of loopback mode.
1332 ew32(SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1338 return e1000e_setup_fiber_serdes_link(hw
);
1342 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1343 * @hw: pointer to the HW structure
1345 * Reports the link state as up or down.
1347 * If autonegotiation is supported by the link partner, the link state is
1348 * determined by the result of autonegotiation. This is the most likely case.
1349 * If autonegotiation is not supported by the link partner, and the link
1350 * has a valid signal, force the link up.
1352 * The link state is represented internally here by 4 states:
1355 * 2) autoneg_progress
1356 * 3) autoneg_complete (the link successfully autonegotiated)
1357 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1360 static s32
e1000_check_for_serdes_link_82571(struct e1000_hw
*hw
)
1362 struct e1000_mac_info
*mac
= &hw
->mac
;
1369 status
= er32(STATUS
);
1372 if ((rxcw
& E1000_RXCW_SYNCH
) && !(rxcw
& E1000_RXCW_IV
)) {
1374 /* Receiver is synchronized with no invalid bits. */
1375 switch (mac
->serdes_link_state
) {
1376 case e1000_serdes_link_autoneg_complete
:
1377 if (!(status
& E1000_STATUS_LU
)) {
1379 * We have lost link, retry autoneg before
1380 * reporting link failure
1382 mac
->serdes_link_state
=
1383 e1000_serdes_link_autoneg_progress
;
1384 mac
->serdes_has_link
= false;
1385 e_dbg("AN_UP -> AN_PROG\n");
1389 case e1000_serdes_link_forced_up
:
1391 * If we are receiving /C/ ordered sets, re-enable
1392 * auto-negotiation in the TXCW register and disable
1393 * forced link in the Device Control register in an
1394 * attempt to auto-negotiate with our link partner.
1396 if (rxcw
& E1000_RXCW_C
) {
1397 /* Enable autoneg, and unforce link up */
1398 ew32(TXCW
, mac
->txcw
);
1399 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
1400 mac
->serdes_link_state
=
1401 e1000_serdes_link_autoneg_progress
;
1402 mac
->serdes_has_link
= false;
1403 e_dbg("FORCED_UP -> AN_PROG\n");
1407 case e1000_serdes_link_autoneg_progress
:
1408 if (rxcw
& E1000_RXCW_C
) {
1410 * We received /C/ ordered sets, meaning the
1411 * link partner has autonegotiated, and we can
1412 * trust the Link Up (LU) status bit.
1414 if (status
& E1000_STATUS_LU
) {
1415 mac
->serdes_link_state
=
1416 e1000_serdes_link_autoneg_complete
;
1417 e_dbg("AN_PROG -> AN_UP\n");
1418 mac
->serdes_has_link
= true;
1420 /* Autoneg completed, but failed. */
1421 mac
->serdes_link_state
=
1422 e1000_serdes_link_down
;
1423 e_dbg("AN_PROG -> DOWN\n");
1427 * The link partner did not autoneg.
1428 * Force link up and full duplex, and change
1431 ew32(TXCW
, (mac
->txcw
& ~E1000_TXCW_ANE
));
1432 ctrl
|= (E1000_CTRL_SLU
| E1000_CTRL_FD
);
1435 /* Configure Flow Control after link up. */
1436 ret_val
= e1000e_config_fc_after_link_up(hw
);
1438 e_dbg("Error config flow control\n");
1441 mac
->serdes_link_state
=
1442 e1000_serdes_link_forced_up
;
1443 mac
->serdes_has_link
= true;
1444 e_dbg("AN_PROG -> FORCED_UP\n");
1448 case e1000_serdes_link_down
:
1451 * The link was down but the receiver has now gained
1452 * valid sync, so lets see if we can bring the link
1455 ew32(TXCW
, mac
->txcw
);
1456 ew32(CTRL
, (ctrl
& ~E1000_CTRL_SLU
));
1457 mac
->serdes_link_state
=
1458 e1000_serdes_link_autoneg_progress
;
1459 e_dbg("DOWN -> AN_PROG\n");
1463 if (!(rxcw
& E1000_RXCW_SYNCH
)) {
1464 mac
->serdes_has_link
= false;
1465 mac
->serdes_link_state
= e1000_serdes_link_down
;
1466 e_dbg("ANYSTATE -> DOWN\n");
1469 * We have sync, and can tolerate one invalid (IV)
1470 * codeword before declaring link down, so reread
1475 if (rxcw
& E1000_RXCW_IV
) {
1476 mac
->serdes_link_state
= e1000_serdes_link_down
;
1477 mac
->serdes_has_link
= false;
1478 e_dbg("ANYSTATE -> DOWN\n");
1487 * e1000_valid_led_default_82571 - Verify a valid default LED config
1488 * @hw: pointer to the HW structure
1489 * @data: pointer to the NVM (EEPROM)
1491 * Read the EEPROM for the current default LED configuration. If the
1492 * LED configuration is not valid, set to a valid LED configuration.
1494 static s32
e1000_valid_led_default_82571(struct e1000_hw
*hw
, u16
*data
)
1498 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1500 e_dbg("NVM Read Error\n");
1504 switch (hw
->mac
.type
) {
1508 if (*data
== ID_LED_RESERVED_F746
)
1509 *data
= ID_LED_DEFAULT_82573
;
1512 if (*data
== ID_LED_RESERVED_0000
||
1513 *data
== ID_LED_RESERVED_FFFF
)
1514 *data
= ID_LED_DEFAULT
;
1522 * e1000e_get_laa_state_82571 - Get locally administered address state
1523 * @hw: pointer to the HW structure
1525 * Retrieve and return the current locally administered address state.
1527 bool e1000e_get_laa_state_82571(struct e1000_hw
*hw
)
1529 if (hw
->mac
.type
!= e1000_82571
)
1532 return hw
->dev_spec
.e82571
.laa_is_present
;
1536 * e1000e_set_laa_state_82571 - Set locally administered address state
1537 * @hw: pointer to the HW structure
1538 * @state: enable/disable locally administered address
1540 * Enable/Disable the current locally administered address state.
1542 void e1000e_set_laa_state_82571(struct e1000_hw
*hw
, bool state
)
1544 if (hw
->mac
.type
!= e1000_82571
)
1547 hw
->dev_spec
.e82571
.laa_is_present
= state
;
1549 /* If workaround is activated... */
1552 * Hold a copy of the LAA in RAR[14] This is done so that
1553 * between the time RAR[0] gets clobbered and the time it
1554 * gets fixed, the actual LAA is in one of the RARs and no
1555 * incoming packets directed to this port are dropped.
1556 * Eventually the LAA will be in RAR[0] and RAR[14].
1558 e1000e_rar_set(hw
, hw
->mac
.addr
, hw
->mac
.rar_entry_count
- 1);
1562 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1563 * @hw: pointer to the HW structure
1565 * Verifies that the EEPROM has completed the update. After updating the
1566 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1567 * the checksum fix is not implemented, we need to set the bit and update
1568 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1569 * we need to return bad checksum.
1571 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
)
1573 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1577 if (nvm
->type
!= e1000_nvm_flash_hw
)
1581 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1582 * 10h-12h. Checksum may need to be fixed.
1584 ret_val
= e1000_read_nvm(hw
, 0x10, 1, &data
);
1588 if (!(data
& 0x10)) {
1590 * Read 0x23 and check bit 15. This bit is a 1
1591 * when the checksum has already been fixed. If
1592 * the checksum is still wrong and this bit is a
1593 * 1, we need to return bad checksum. Otherwise,
1594 * we need to set this bit to a 1 and update the
1597 ret_val
= e1000_read_nvm(hw
, 0x23, 1, &data
);
1601 if (!(data
& 0x8000)) {
1603 ret_val
= e1000_write_nvm(hw
, 0x23, 1, &data
);
1606 ret_val
= e1000e_update_nvm_checksum(hw
);
1614 * e1000_read_mac_addr_82571 - Read device MAC address
1615 * @hw: pointer to the HW structure
1617 static s32
e1000_read_mac_addr_82571(struct e1000_hw
*hw
)
1622 * If there's an alternate MAC address place it in RAR0
1623 * so that it will override the Si installed default perm
1626 ret_val
= e1000_check_alt_mac_addr_generic(hw
);
1630 ret_val
= e1000_read_mac_addr_generic(hw
);
1637 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1638 * @hw: pointer to the HW structure
1640 * In the case of a PHY power down to save power, or to turn off link during a
1641 * driver unload, or wake on lan is not enabled, remove the link.
1643 static void e1000_power_down_phy_copper_82571(struct e1000_hw
*hw
)
1645 struct e1000_phy_info
*phy
= &hw
->phy
;
1646 struct e1000_mac_info
*mac
= &hw
->mac
;
1648 if (!(phy
->ops
.check_reset_block
))
1651 /* If the management interface is not enabled, then power down */
1652 if (!(mac
->ops
.check_mng_mode(hw
) || phy
->ops
.check_reset_block(hw
)))
1653 e1000_power_down_phy_copper(hw
);
1657 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1658 * @hw: pointer to the HW structure
1660 * Clears the hardware counters by reading the counter registers.
1662 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
)
1664 e1000e_clear_hw_cntrs_base(hw
);
1702 static struct e1000_mac_operations e82571_mac_ops
= {
1703 /* .check_mng_mode: mac type dependent */
1704 /* .check_for_link: media type dependent */
1705 .id_led_init
= e1000e_id_led_init
,
1706 .cleanup_led
= e1000e_cleanup_led_generic
,
1707 .clear_hw_cntrs
= e1000_clear_hw_cntrs_82571
,
1708 .get_bus_info
= e1000e_get_bus_info_pcie
,
1709 .set_lan_id
= e1000_set_lan_id_multi_port_pcie
,
1710 /* .get_link_up_info: media type dependent */
1711 /* .led_on: mac type dependent */
1712 .led_off
= e1000e_led_off_generic
,
1713 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
1714 .write_vfta
= e1000_write_vfta_generic
,
1715 .clear_vfta
= e1000_clear_vfta_82571
,
1716 .reset_hw
= e1000_reset_hw_82571
,
1717 .init_hw
= e1000_init_hw_82571
,
1718 .setup_link
= e1000_setup_link_82571
,
1719 /* .setup_physical_interface: media type dependent */
1720 .setup_led
= e1000e_setup_led_generic
,
1721 .read_mac_addr
= e1000_read_mac_addr_82571
,
1724 static struct e1000_phy_operations e82_phy_ops_igp
= {
1725 .acquire
= e1000_get_hw_semaphore_82571
,
1726 .check_polarity
= e1000_check_polarity_igp
,
1727 .check_reset_block
= e1000e_check_reset_block_generic
,
1729 .force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
,
1730 .get_cfg_done
= e1000_get_cfg_done_82571
,
1731 .get_cable_length
= e1000e_get_cable_length_igp_2
,
1732 .get_info
= e1000e_get_phy_info_igp
,
1733 .read_reg
= e1000e_read_phy_reg_igp
,
1734 .release
= e1000_put_hw_semaphore_82571
,
1735 .reset
= e1000e_phy_hw_reset_generic
,
1736 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1737 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1738 .write_reg
= e1000e_write_phy_reg_igp
,
1739 .cfg_on_link_up
= NULL
,
1742 static struct e1000_phy_operations e82_phy_ops_m88
= {
1743 .acquire
= e1000_get_hw_semaphore_82571
,
1744 .check_polarity
= e1000_check_polarity_m88
,
1745 .check_reset_block
= e1000e_check_reset_block_generic
,
1746 .commit
= e1000e_phy_sw_reset
,
1747 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1748 .get_cfg_done
= e1000e_get_cfg_done
,
1749 .get_cable_length
= e1000e_get_cable_length_m88
,
1750 .get_info
= e1000e_get_phy_info_m88
,
1751 .read_reg
= e1000e_read_phy_reg_m88
,
1752 .release
= e1000_put_hw_semaphore_82571
,
1753 .reset
= e1000e_phy_hw_reset_generic
,
1754 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1755 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1756 .write_reg
= e1000e_write_phy_reg_m88
,
1757 .cfg_on_link_up
= NULL
,
1760 static struct e1000_phy_operations e82_phy_ops_bm
= {
1761 .acquire
= e1000_get_hw_semaphore_82571
,
1762 .check_polarity
= e1000_check_polarity_m88
,
1763 .check_reset_block
= e1000e_check_reset_block_generic
,
1764 .commit
= e1000e_phy_sw_reset
,
1765 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1766 .get_cfg_done
= e1000e_get_cfg_done
,
1767 .get_cable_length
= e1000e_get_cable_length_m88
,
1768 .get_info
= e1000e_get_phy_info_m88
,
1769 .read_reg
= e1000e_read_phy_reg_bm2
,
1770 .release
= e1000_put_hw_semaphore_82571
,
1771 .reset
= e1000e_phy_hw_reset_generic
,
1772 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1773 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1774 .write_reg
= e1000e_write_phy_reg_bm2
,
1775 .cfg_on_link_up
= NULL
,
1778 static struct e1000_nvm_operations e82571_nvm_ops
= {
1779 .acquire
= e1000_acquire_nvm_82571
,
1780 .read
= e1000e_read_nvm_eerd
,
1781 .release
= e1000_release_nvm_82571
,
1782 .update
= e1000_update_nvm_checksum_82571
,
1783 .valid_led_default
= e1000_valid_led_default_82571
,
1784 .validate
= e1000_validate_nvm_checksum_82571
,
1785 .write
= e1000_write_nvm_82571
,
1788 struct e1000_info e1000_82571_info
= {
1790 .flags
= FLAG_HAS_HW_VLAN_FILTER
1791 | FLAG_HAS_JUMBO_FRAMES
1793 | FLAG_APME_IN_CTRL3
1794 | FLAG_RX_CSUM_ENABLED
1795 | FLAG_HAS_CTRLEXT_ON_LOAD
1796 | FLAG_HAS_SMART_POWER_DOWN
1797 | FLAG_RESET_OVERWRITES_LAA
/* errata */
1798 | FLAG_TARC_SPEED_MODE_BIT
/* errata */
1799 | FLAG_APME_CHECK_PORT_B
,
1800 .flags2
= FLAG2_DISABLE_ASPM_L1
, /* errata 13 */
1802 .max_hw_frame_size
= DEFAULT_JUMBO
,
1803 .get_variants
= e1000_get_variants_82571
,
1804 .mac_ops
= &e82571_mac_ops
,
1805 .phy_ops
= &e82_phy_ops_igp
,
1806 .nvm_ops
= &e82571_nvm_ops
,
1809 struct e1000_info e1000_82572_info
= {
1811 .flags
= FLAG_HAS_HW_VLAN_FILTER
1812 | FLAG_HAS_JUMBO_FRAMES
1814 | FLAG_APME_IN_CTRL3
1815 | FLAG_RX_CSUM_ENABLED
1816 | FLAG_HAS_CTRLEXT_ON_LOAD
1817 | FLAG_TARC_SPEED_MODE_BIT
, /* errata */
1818 .flags2
= FLAG2_DISABLE_ASPM_L1
, /* errata 13 */
1820 .max_hw_frame_size
= DEFAULT_JUMBO
,
1821 .get_variants
= e1000_get_variants_82571
,
1822 .mac_ops
= &e82571_mac_ops
,
1823 .phy_ops
= &e82_phy_ops_igp
,
1824 .nvm_ops
= &e82571_nvm_ops
,
1827 struct e1000_info e1000_82573_info
= {
1829 .flags
= FLAG_HAS_HW_VLAN_FILTER
1831 | FLAG_APME_IN_CTRL3
1832 | FLAG_RX_CSUM_ENABLED
1833 | FLAG_HAS_SMART_POWER_DOWN
1835 | FLAG_HAS_SWSM_ON_LOAD
,
1837 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
1838 .get_variants
= e1000_get_variants_82571
,
1839 .mac_ops
= &e82571_mac_ops
,
1840 .phy_ops
= &e82_phy_ops_m88
,
1841 .nvm_ops
= &e82571_nvm_ops
,
1844 struct e1000_info e1000_82574_info
= {
1846 .flags
= FLAG_HAS_HW_VLAN_FILTER
1848 | FLAG_HAS_JUMBO_FRAMES
1850 | FLAG_APME_IN_CTRL3
1851 | FLAG_RX_CSUM_ENABLED
1852 | FLAG_HAS_SMART_POWER_DOWN
1854 | FLAG_HAS_CTRLEXT_ON_LOAD
,
1856 .max_hw_frame_size
= DEFAULT_JUMBO
,
1857 .get_variants
= e1000_get_variants_82571
,
1858 .mac_ops
= &e82571_mac_ops
,
1859 .phy_ops
= &e82_phy_ops_bm
,
1860 .nvm_ops
= &e82571_nvm_ops
,
1863 struct e1000_info e1000_82583_info
= {
1865 .flags
= FLAG_HAS_HW_VLAN_FILTER
1867 | FLAG_APME_IN_CTRL3
1868 | FLAG_RX_CSUM_ENABLED
1869 | FLAG_HAS_SMART_POWER_DOWN
1871 | FLAG_HAS_CTRLEXT_ON_LOAD
,
1873 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
1874 .get_variants
= e1000_get_variants_82571
,
1875 .mac_ops
= &e82571_mac_ops
,
1876 .phy_ops
= &e82_phy_ops_bm
,
1877 .nvm_ops
= &e82571_nvm_ops
,