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e1000e: use alternate MAC address on ESB2 if available
[deliverable/linux.git] / drivers / net / e1000e / es2lan.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
32 */
33
34 #include "e1000.h"
35
36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
40
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
44
45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
48
49 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
51
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
54
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
57
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
64
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
67 /* 1=Reverse Auto-Negotiation */
68
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
75
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
77
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
80 1 = 50-80M
81 2 = 80-110M
82 3 = 110-140M
83 4 = >140M */
84
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
87
88 /* Max number of times Kumeran read/write should be validated */
89 #define GG82563_MAX_KMRN_RETRY 0x5
90
91 /* Power Management Control Register (Page 193, Register 20) */
92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
94
95 /* In-Band Control Register (Page 194, Register 18) */
96 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
97
98 /*
99 * A table for the GG82563 cable length where the range is defined
100 * with a lower bound at "index" and the upper bound at
101 * "index + 5".
102 */
103 static const u16 e1000_gg82563_cable_length_table[] =
104 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
106 ARRAY_SIZE(e1000_gg82563_cable_length_table)
107
108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
116 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
117 u16 *data);
118 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
119 u16 data);
120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
121
122 /**
123 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
124 * @hw: pointer to the HW structure
125 **/
126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
127 {
128 struct e1000_phy_info *phy = &hw->phy;
129 s32 ret_val;
130
131 if (hw->phy.media_type != e1000_media_type_copper) {
132 phy->type = e1000_phy_none;
133 return 0;
134 } else {
135 phy->ops.power_up = e1000_power_up_phy_copper;
136 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
137 }
138
139 phy->addr = 1;
140 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
141 phy->reset_delay_us = 100;
142 phy->type = e1000_phy_gg82563;
143
144 /* This can only be done after all function pointers are setup. */
145 ret_val = e1000e_get_phy_id(hw);
146
147 /* Verify phy id */
148 if (phy->id != GG82563_E_PHY_ID)
149 return -E1000_ERR_PHY;
150
151 return ret_val;
152 }
153
154 /**
155 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
156 * @hw: pointer to the HW structure
157 **/
158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
159 {
160 struct e1000_nvm_info *nvm = &hw->nvm;
161 u32 eecd = er32(EECD);
162 u16 size;
163
164 nvm->opcode_bits = 8;
165 nvm->delay_usec = 1;
166 switch (nvm->override) {
167 case e1000_nvm_override_spi_large:
168 nvm->page_size = 32;
169 nvm->address_bits = 16;
170 break;
171 case e1000_nvm_override_spi_small:
172 nvm->page_size = 8;
173 nvm->address_bits = 8;
174 break;
175 default:
176 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
177 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
178 break;
179 }
180
181 nvm->type = e1000_nvm_eeprom_spi;
182
183 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
184 E1000_EECD_SIZE_EX_SHIFT);
185
186 /*
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
189 */
190 size += NVM_WORD_SIZE_BASE_SHIFT;
191
192 /* EEPROM access above 16k is unsupported */
193 if (size > 14)
194 size = 14;
195 nvm->word_size = 1 << size;
196
197 return 0;
198 }
199
200 /**
201 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
202 * @hw: pointer to the HW structure
203 **/
204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
205 {
206 struct e1000_hw *hw = &adapter->hw;
207 struct e1000_mac_info *mac = &hw->mac;
208 struct e1000_mac_operations *func = &mac->ops;
209
210 /* Set media type */
211 switch (adapter->pdev->device) {
212 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
213 hw->phy.media_type = e1000_media_type_internal_serdes;
214 break;
215 default:
216 hw->phy.media_type = e1000_media_type_copper;
217 break;
218 }
219
220 /* Set mta register count */
221 mac->mta_reg_count = 128;
222 /* Set rar entry count */
223 mac->rar_entry_count = E1000_RAR_ENTRIES;
224 /* Set if manageability features are enabled. */
225 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
226 ? true : false;
227 /* Adaptive IFS not supported */
228 mac->adaptive_ifs = false;
229
230 /* check for link */
231 switch (hw->phy.media_type) {
232 case e1000_media_type_copper:
233 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
234 func->check_for_link = e1000e_check_for_copper_link;
235 break;
236 case e1000_media_type_fiber:
237 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
238 func->check_for_link = e1000e_check_for_fiber_link;
239 break;
240 case e1000_media_type_internal_serdes:
241 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
242 func->check_for_link = e1000e_check_for_serdes_link;
243 break;
244 default:
245 return -E1000_ERR_CONFIG;
246 break;
247 }
248
249 return 0;
250 }
251
252 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
253 {
254 struct e1000_hw *hw = &adapter->hw;
255 s32 rc;
256
257 rc = e1000_init_mac_params_80003es2lan(adapter);
258 if (rc)
259 return rc;
260
261 rc = e1000_init_nvm_params_80003es2lan(hw);
262 if (rc)
263 return rc;
264
265 rc = e1000_init_phy_params_80003es2lan(hw);
266 if (rc)
267 return rc;
268
269 return 0;
270 }
271
272 /**
273 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
274 * @hw: pointer to the HW structure
275 *
276 * A wrapper to acquire access rights to the correct PHY.
277 **/
278 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
279 {
280 u16 mask;
281
282 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
283 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
284 }
285
286 /**
287 * e1000_release_phy_80003es2lan - Release rights to access PHY
288 * @hw: pointer to the HW structure
289 *
290 * A wrapper to release access rights to the correct PHY.
291 **/
292 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
293 {
294 u16 mask;
295
296 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
297 e1000_release_swfw_sync_80003es2lan(hw, mask);
298 }
299
300 /**
301 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
302 * @hw: pointer to the HW structure
303 *
304 * Acquire the semaphore to access the Kumeran interface.
305 *
306 **/
307 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
308 {
309 u16 mask;
310
311 mask = E1000_SWFW_CSR_SM;
312
313 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
314 }
315
316 /**
317 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
318 * @hw: pointer to the HW structure
319 *
320 * Release the semaphore used to access the Kumeran interface
321 **/
322 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
323 {
324 u16 mask;
325
326 mask = E1000_SWFW_CSR_SM;
327
328 e1000_release_swfw_sync_80003es2lan(hw, mask);
329 }
330
331 /**
332 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
333 * @hw: pointer to the HW structure
334 *
335 * Acquire the semaphore to access the EEPROM.
336 **/
337 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
338 {
339 s32 ret_val;
340
341 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
342 if (ret_val)
343 return ret_val;
344
345 ret_val = e1000e_acquire_nvm(hw);
346
347 if (ret_val)
348 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
349
350 return ret_val;
351 }
352
353 /**
354 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
355 * @hw: pointer to the HW structure
356 *
357 * Release the semaphore used to access the EEPROM.
358 **/
359 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
360 {
361 e1000e_release_nvm(hw);
362 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
363 }
364
365 /**
366 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
367 * @hw: pointer to the HW structure
368 * @mask: specifies which semaphore to acquire
369 *
370 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
371 * will also specify which port we're acquiring the lock for.
372 **/
373 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
374 {
375 u32 swfw_sync;
376 u32 swmask = mask;
377 u32 fwmask = mask << 16;
378 s32 i = 0;
379 s32 timeout = 50;
380
381 while (i < timeout) {
382 if (e1000e_get_hw_semaphore(hw))
383 return -E1000_ERR_SWFW_SYNC;
384
385 swfw_sync = er32(SW_FW_SYNC);
386 if (!(swfw_sync & (fwmask | swmask)))
387 break;
388
389 /*
390 * Firmware currently using resource (fwmask)
391 * or other software thread using resource (swmask)
392 */
393 e1000e_put_hw_semaphore(hw);
394 mdelay(5);
395 i++;
396 }
397
398 if (i == timeout) {
399 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
400 return -E1000_ERR_SWFW_SYNC;
401 }
402
403 swfw_sync |= swmask;
404 ew32(SW_FW_SYNC, swfw_sync);
405
406 e1000e_put_hw_semaphore(hw);
407
408 return 0;
409 }
410
411 /**
412 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
413 * @hw: pointer to the HW structure
414 * @mask: specifies which semaphore to acquire
415 *
416 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
417 * will also specify which port we're releasing the lock for.
418 **/
419 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
420 {
421 u32 swfw_sync;
422
423 while (e1000e_get_hw_semaphore(hw) != 0);
424 /* Empty */
425
426 swfw_sync = er32(SW_FW_SYNC);
427 swfw_sync &= ~mask;
428 ew32(SW_FW_SYNC, swfw_sync);
429
430 e1000e_put_hw_semaphore(hw);
431 }
432
433 /**
434 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
435 * @hw: pointer to the HW structure
436 * @offset: offset of the register to read
437 * @data: pointer to the data returned from the operation
438 *
439 * Read the GG82563 PHY register.
440 **/
441 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
442 u32 offset, u16 *data)
443 {
444 s32 ret_val;
445 u32 page_select;
446 u16 temp;
447
448 ret_val = e1000_acquire_phy_80003es2lan(hw);
449 if (ret_val)
450 return ret_val;
451
452 /* Select Configuration Page */
453 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
454 page_select = GG82563_PHY_PAGE_SELECT;
455 } else {
456 /*
457 * Use Alternative Page Select register to access
458 * registers 30 and 31
459 */
460 page_select = GG82563_PHY_PAGE_SELECT_ALT;
461 }
462
463 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
464 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
465 if (ret_val) {
466 e1000_release_phy_80003es2lan(hw);
467 return ret_val;
468 }
469
470 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
471 /*
472 * The "ready" bit in the MDIC register may be incorrectly set
473 * before the device has completed the "Page Select" MDI
474 * transaction. So we wait 200us after each MDI command...
475 */
476 udelay(200);
477
478 /* ...and verify the command was successful. */
479 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
480
481 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
482 ret_val = -E1000_ERR_PHY;
483 e1000_release_phy_80003es2lan(hw);
484 return ret_val;
485 }
486
487 udelay(200);
488
489 ret_val = e1000e_read_phy_reg_mdic(hw,
490 MAX_PHY_REG_ADDRESS & offset,
491 data);
492
493 udelay(200);
494 } else {
495 ret_val = e1000e_read_phy_reg_mdic(hw,
496 MAX_PHY_REG_ADDRESS & offset,
497 data);
498 }
499
500 e1000_release_phy_80003es2lan(hw);
501
502 return ret_val;
503 }
504
505 /**
506 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
507 * @hw: pointer to the HW structure
508 * @offset: offset of the register to read
509 * @data: value to write to the register
510 *
511 * Write to the GG82563 PHY register.
512 **/
513 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
514 u32 offset, u16 data)
515 {
516 s32 ret_val;
517 u32 page_select;
518 u16 temp;
519
520 ret_val = e1000_acquire_phy_80003es2lan(hw);
521 if (ret_val)
522 return ret_val;
523
524 /* Select Configuration Page */
525 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
526 page_select = GG82563_PHY_PAGE_SELECT;
527 } else {
528 /*
529 * Use Alternative Page Select register to access
530 * registers 30 and 31
531 */
532 page_select = GG82563_PHY_PAGE_SELECT_ALT;
533 }
534
535 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
536 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
537 if (ret_val) {
538 e1000_release_phy_80003es2lan(hw);
539 return ret_val;
540 }
541
542 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
543 /*
544 * The "ready" bit in the MDIC register may be incorrectly set
545 * before the device has completed the "Page Select" MDI
546 * transaction. So we wait 200us after each MDI command...
547 */
548 udelay(200);
549
550 /* ...and verify the command was successful. */
551 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
552
553 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
554 e1000_release_phy_80003es2lan(hw);
555 return -E1000_ERR_PHY;
556 }
557
558 udelay(200);
559
560 ret_val = e1000e_write_phy_reg_mdic(hw,
561 MAX_PHY_REG_ADDRESS & offset,
562 data);
563
564 udelay(200);
565 } else {
566 ret_val = e1000e_write_phy_reg_mdic(hw,
567 MAX_PHY_REG_ADDRESS & offset,
568 data);
569 }
570
571 e1000_release_phy_80003es2lan(hw);
572
573 return ret_val;
574 }
575
576 /**
577 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
578 * @hw: pointer to the HW structure
579 * @offset: offset of the register to read
580 * @words: number of words to write
581 * @data: buffer of data to write to the NVM
582 *
583 * Write "words" of data to the ESB2 NVM.
584 **/
585 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
586 u16 words, u16 *data)
587 {
588 return e1000e_write_nvm_spi(hw, offset, words, data);
589 }
590
591 /**
592 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
593 * @hw: pointer to the HW structure
594 *
595 * Wait a specific amount of time for manageability processes to complete.
596 * This is a function pointer entry point called by the phy module.
597 **/
598 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
599 {
600 s32 timeout = PHY_CFG_TIMEOUT;
601 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
602
603 if (hw->bus.func == 1)
604 mask = E1000_NVM_CFG_DONE_PORT_1;
605
606 while (timeout) {
607 if (er32(EEMNGCTL) & mask)
608 break;
609 msleep(1);
610 timeout--;
611 }
612 if (!timeout) {
613 e_dbg("MNG configuration cycle has not completed.\n");
614 return -E1000_ERR_RESET;
615 }
616
617 return 0;
618 }
619
620 /**
621 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
622 * @hw: pointer to the HW structure
623 *
624 * Force the speed and duplex settings onto the PHY. This is a
625 * function pointer entry point called by the phy module.
626 **/
627 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
628 {
629 s32 ret_val;
630 u16 phy_data;
631 bool link;
632
633 /*
634 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
635 * forced whenever speed and duplex are forced.
636 */
637 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
638 if (ret_val)
639 return ret_val;
640
641 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
642 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
643 if (ret_val)
644 return ret_val;
645
646 e_dbg("GG82563 PSCR: %X\n", phy_data);
647
648 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
649 if (ret_val)
650 return ret_val;
651
652 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
653
654 /* Reset the phy to commit changes. */
655 phy_data |= MII_CR_RESET;
656
657 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
658 if (ret_val)
659 return ret_val;
660
661 udelay(1);
662
663 if (hw->phy.autoneg_wait_to_complete) {
664 e_dbg("Waiting for forced speed/duplex link "
665 "on GG82563 phy.\n");
666
667 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
668 100000, &link);
669 if (ret_val)
670 return ret_val;
671
672 if (!link) {
673 /*
674 * We didn't get link.
675 * Reset the DSP and cross our fingers.
676 */
677 ret_val = e1000e_phy_reset_dsp(hw);
678 if (ret_val)
679 return ret_val;
680 }
681
682 /* Try once more */
683 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
684 100000, &link);
685 if (ret_val)
686 return ret_val;
687 }
688
689 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
690 if (ret_val)
691 return ret_val;
692
693 /*
694 * Resetting the phy means we need to verify the TX_CLK corresponds
695 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
696 */
697 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
698 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
699 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
700 else
701 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
702
703 /*
704 * In addition, we must re-enable CRS on Tx for both half and full
705 * duplex.
706 */
707 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
708 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
709
710 return ret_val;
711 }
712
713 /**
714 * e1000_get_cable_length_80003es2lan - Set approximate cable length
715 * @hw: pointer to the HW structure
716 *
717 * Find the approximate cable length as measured by the GG82563 PHY.
718 * This is a function pointer entry point called by the phy module.
719 **/
720 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
721 {
722 struct e1000_phy_info *phy = &hw->phy;
723 s32 ret_val = 0;
724 u16 phy_data, index;
725
726 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
727 if (ret_val)
728 goto out;
729
730 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
731
732 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
733 ret_val = -E1000_ERR_PHY;
734 goto out;
735 }
736
737 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
738 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
739
740 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
741
742 out:
743 return ret_val;
744 }
745
746 /**
747 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
748 * @hw: pointer to the HW structure
749 * @speed: pointer to speed buffer
750 * @duplex: pointer to duplex buffer
751 *
752 * Retrieve the current speed and duplex configuration.
753 **/
754 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
755 u16 *duplex)
756 {
757 s32 ret_val;
758
759 if (hw->phy.media_type == e1000_media_type_copper) {
760 ret_val = e1000e_get_speed_and_duplex_copper(hw,
761 speed,
762 duplex);
763 hw->phy.ops.cfg_on_link_up(hw);
764 } else {
765 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
766 speed,
767 duplex);
768 }
769
770 return ret_val;
771 }
772
773 /**
774 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
775 * @hw: pointer to the HW structure
776 *
777 * Perform a global reset to the ESB2 controller.
778 **/
779 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
780 {
781 u32 ctrl, icr;
782 s32 ret_val;
783
784 /*
785 * Prevent the PCI-E bus from sticking if there is no TLP connection
786 * on the last TLP read/write transaction when MAC is reset.
787 */
788 ret_val = e1000e_disable_pcie_master(hw);
789 if (ret_val)
790 e_dbg("PCI-E Master disable polling has failed.\n");
791
792 e_dbg("Masking off all interrupts\n");
793 ew32(IMC, 0xffffffff);
794
795 ew32(RCTL, 0);
796 ew32(TCTL, E1000_TCTL_PSP);
797 e1e_flush();
798
799 msleep(10);
800
801 ctrl = er32(CTRL);
802
803 ret_val = e1000_acquire_phy_80003es2lan(hw);
804 e_dbg("Issuing a global reset to MAC\n");
805 ew32(CTRL, ctrl | E1000_CTRL_RST);
806 e1000_release_phy_80003es2lan(hw);
807
808 ret_val = e1000e_get_auto_rd_done(hw);
809 if (ret_val)
810 /* We don't want to continue accessing MAC registers. */
811 return ret_val;
812
813 /* Clear any pending interrupt events. */
814 ew32(IMC, 0xffffffff);
815 icr = er32(ICR);
816
817 ret_val = e1000_check_alt_mac_addr_generic(hw);
818
819 return ret_val;
820 }
821
822 /**
823 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
824 * @hw: pointer to the HW structure
825 *
826 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
827 **/
828 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
829 {
830 struct e1000_mac_info *mac = &hw->mac;
831 u32 reg_data;
832 s32 ret_val;
833 u16 i;
834
835 e1000_initialize_hw_bits_80003es2lan(hw);
836
837 /* Initialize identification LED */
838 ret_val = e1000e_id_led_init(hw);
839 if (ret_val)
840 e_dbg("Error initializing identification LED\n");
841 /* This is not fatal and we should not stop init due to this */
842
843 /* Disabling VLAN filtering */
844 e_dbg("Initializing the IEEE VLAN\n");
845 mac->ops.clear_vfta(hw);
846
847 /* Setup the receive address. */
848 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
849
850 /* Zero out the Multicast HASH table */
851 e_dbg("Zeroing the MTA\n");
852 for (i = 0; i < mac->mta_reg_count; i++)
853 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
854
855 /* Setup link and flow control */
856 ret_val = e1000e_setup_link(hw);
857
858 /* Set the transmit descriptor write-back policy */
859 reg_data = er32(TXDCTL(0));
860 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
861 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
862 ew32(TXDCTL(0), reg_data);
863
864 /* ...for both queues. */
865 reg_data = er32(TXDCTL(1));
866 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
867 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
868 ew32(TXDCTL(1), reg_data);
869
870 /* Enable retransmit on late collisions */
871 reg_data = er32(TCTL);
872 reg_data |= E1000_TCTL_RTLC;
873 ew32(TCTL, reg_data);
874
875 /* Configure Gigabit Carry Extend Padding */
876 reg_data = er32(TCTL_EXT);
877 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
878 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
879 ew32(TCTL_EXT, reg_data);
880
881 /* Configure Transmit Inter-Packet Gap */
882 reg_data = er32(TIPG);
883 reg_data &= ~E1000_TIPG_IPGT_MASK;
884 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
885 ew32(TIPG, reg_data);
886
887 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
888 reg_data &= ~0x00100000;
889 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
890
891 /* default to true to enable the MDIC W/A */
892 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
893
894 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
895 E1000_KMRNCTRLSTA_OFFSET >>
896 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
897 &i);
898 if (!ret_val) {
899 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
900 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
901 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
902 }
903
904 /*
905 * Clear all of the statistics registers (clear on read). It is
906 * important that we do this after we have tried to establish link
907 * because the symbol error count will increment wildly if there
908 * is no link.
909 */
910 e1000_clear_hw_cntrs_80003es2lan(hw);
911
912 return ret_val;
913 }
914
915 /**
916 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
917 * @hw: pointer to the HW structure
918 *
919 * Initializes required hardware-dependent bits needed for normal operation.
920 **/
921 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
922 {
923 u32 reg;
924
925 /* Transmit Descriptor Control 0 */
926 reg = er32(TXDCTL(0));
927 reg |= (1 << 22);
928 ew32(TXDCTL(0), reg);
929
930 /* Transmit Descriptor Control 1 */
931 reg = er32(TXDCTL(1));
932 reg |= (1 << 22);
933 ew32(TXDCTL(1), reg);
934
935 /* Transmit Arbitration Control 0 */
936 reg = er32(TARC(0));
937 reg &= ~(0xF << 27); /* 30:27 */
938 if (hw->phy.media_type != e1000_media_type_copper)
939 reg &= ~(1 << 20);
940 ew32(TARC(0), reg);
941
942 /* Transmit Arbitration Control 1 */
943 reg = er32(TARC(1));
944 if (er32(TCTL) & E1000_TCTL_MULR)
945 reg &= ~(1 << 28);
946 else
947 reg |= (1 << 28);
948 ew32(TARC(1), reg);
949 }
950
951 /**
952 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
953 * @hw: pointer to the HW structure
954 *
955 * Setup some GG82563 PHY registers for obtaining link
956 **/
957 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
958 {
959 struct e1000_phy_info *phy = &hw->phy;
960 s32 ret_val;
961 u32 ctrl_ext;
962 u16 data;
963
964 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
965 if (ret_val)
966 return ret_val;
967
968 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
969 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
970 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
971
972 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
973 if (ret_val)
974 return ret_val;
975
976 /*
977 * Options:
978 * MDI/MDI-X = 0 (default)
979 * 0 - Auto for all speeds
980 * 1 - MDI mode
981 * 2 - MDI-X mode
982 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
983 */
984 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
985 if (ret_val)
986 return ret_val;
987
988 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
989
990 switch (phy->mdix) {
991 case 1:
992 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
993 break;
994 case 2:
995 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
996 break;
997 case 0:
998 default:
999 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1000 break;
1001 }
1002
1003 /*
1004 * Options:
1005 * disable_polarity_correction = 0 (default)
1006 * Automatic Correction for Reversed Cable Polarity
1007 * 0 - Disabled
1008 * 1 - Enabled
1009 */
1010 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1011 if (phy->disable_polarity_correction)
1012 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1013
1014 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1015 if (ret_val)
1016 return ret_val;
1017
1018 /* SW Reset the PHY so all changes take effect */
1019 ret_val = e1000e_commit_phy(hw);
1020 if (ret_val) {
1021 e_dbg("Error Resetting the PHY\n");
1022 return ret_val;
1023 }
1024
1025 /* Bypass Rx and Tx FIFO's */
1026 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1027 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1028 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1029 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1030 if (ret_val)
1031 return ret_val;
1032
1033 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1034 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1035 &data);
1036 if (ret_val)
1037 return ret_val;
1038 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1039 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1040 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1041 data);
1042 if (ret_val)
1043 return ret_val;
1044
1045 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1046 if (ret_val)
1047 return ret_val;
1048
1049 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1050 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1051 if (ret_val)
1052 return ret_val;
1053
1054 ctrl_ext = er32(CTRL_EXT);
1055 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1056 ew32(CTRL_EXT, ctrl_ext);
1057
1058 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1059 if (ret_val)
1060 return ret_val;
1061
1062 /*
1063 * Do not init these registers when the HW is in IAMT mode, since the
1064 * firmware will have already initialized them. We only initialize
1065 * them if the HW is not in IAMT mode.
1066 */
1067 if (!e1000e_check_mng_mode(hw)) {
1068 /* Enable Electrical Idle on the PHY */
1069 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1070 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1071 if (ret_val)
1072 return ret_val;
1073
1074 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1075 if (ret_val)
1076 return ret_val;
1077
1078 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1079 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1080 if (ret_val)
1081 return ret_val;
1082 }
1083
1084 /*
1085 * Workaround: Disable padding in Kumeran interface in the MAC
1086 * and in the PHY to avoid CRC errors.
1087 */
1088 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1089 if (ret_val)
1090 return ret_val;
1091
1092 data |= GG82563_ICR_DIS_PADDING;
1093 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1094 if (ret_val)
1095 return ret_val;
1096
1097 return 0;
1098 }
1099
1100 /**
1101 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1102 * @hw: pointer to the HW structure
1103 *
1104 * Essentially a wrapper for setting up all things "copper" related.
1105 * This is a function pointer entry point called by the mac module.
1106 **/
1107 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1108 {
1109 u32 ctrl;
1110 s32 ret_val;
1111 u16 reg_data;
1112
1113 ctrl = er32(CTRL);
1114 ctrl |= E1000_CTRL_SLU;
1115 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1116 ew32(CTRL, ctrl);
1117
1118 /*
1119 * Set the mac to wait the maximum time between each
1120 * iteration and increase the max iterations when
1121 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1122 */
1123 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1124 0xFFFF);
1125 if (ret_val)
1126 return ret_val;
1127 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1128 &reg_data);
1129 if (ret_val)
1130 return ret_val;
1131 reg_data |= 0x3F;
1132 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1133 reg_data);
1134 if (ret_val)
1135 return ret_val;
1136 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1137 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1138 &reg_data);
1139 if (ret_val)
1140 return ret_val;
1141 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1142 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1143 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1144 reg_data);
1145 if (ret_val)
1146 return ret_val;
1147
1148 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1149 if (ret_val)
1150 return ret_val;
1151
1152 ret_val = e1000e_setup_copper_link(hw);
1153
1154 return 0;
1155 }
1156
1157 /**
1158 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1159 * @hw: pointer to the HW structure
1160 * @duplex: current duplex setting
1161 *
1162 * Configure the KMRN interface by applying last minute quirks for
1163 * 10/100 operation.
1164 **/
1165 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1166 {
1167 s32 ret_val = 0;
1168 u16 speed;
1169 u16 duplex;
1170
1171 if (hw->phy.media_type == e1000_media_type_copper) {
1172 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1173 &duplex);
1174 if (ret_val)
1175 return ret_val;
1176
1177 if (speed == SPEED_1000)
1178 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1179 else
1180 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1181 }
1182
1183 return ret_val;
1184 }
1185
1186 /**
1187 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1188 * @hw: pointer to the HW structure
1189 * @duplex: current duplex setting
1190 *
1191 * Configure the KMRN interface by applying last minute quirks for
1192 * 10/100 operation.
1193 **/
1194 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1195 {
1196 s32 ret_val;
1197 u32 tipg;
1198 u32 i = 0;
1199 u16 reg_data, reg_data2;
1200
1201 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1202 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1203 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1204 reg_data);
1205 if (ret_val)
1206 return ret_val;
1207
1208 /* Configure Transmit Inter-Packet Gap */
1209 tipg = er32(TIPG);
1210 tipg &= ~E1000_TIPG_IPGT_MASK;
1211 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1212 ew32(TIPG, tipg);
1213
1214 do {
1215 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1216 if (ret_val)
1217 return ret_val;
1218
1219 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1220 if (ret_val)
1221 return ret_val;
1222 i++;
1223 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1224
1225 if (duplex == HALF_DUPLEX)
1226 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1227 else
1228 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1229
1230 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1231
1232 return 0;
1233 }
1234
1235 /**
1236 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1237 * @hw: pointer to the HW structure
1238 *
1239 * Configure the KMRN interface by applying last minute quirks for
1240 * gigabit operation.
1241 **/
1242 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1243 {
1244 s32 ret_val;
1245 u16 reg_data, reg_data2;
1246 u32 tipg;
1247 u32 i = 0;
1248
1249 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1250 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1251 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1252 reg_data);
1253 if (ret_val)
1254 return ret_val;
1255
1256 /* Configure Transmit Inter-Packet Gap */
1257 tipg = er32(TIPG);
1258 tipg &= ~E1000_TIPG_IPGT_MASK;
1259 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1260 ew32(TIPG, tipg);
1261
1262 do {
1263 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1264 if (ret_val)
1265 return ret_val;
1266
1267 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1268 if (ret_val)
1269 return ret_val;
1270 i++;
1271 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1272
1273 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1274 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1275
1276 return ret_val;
1277 }
1278
1279 /**
1280 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1281 * @hw: pointer to the HW structure
1282 * @offset: register offset to be read
1283 * @data: pointer to the read data
1284 *
1285 * Acquire semaphore, then read the PHY register at offset
1286 * using the kumeran interface. The information retrieved is stored in data.
1287 * Release the semaphore before exiting.
1288 **/
1289 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1290 u16 *data)
1291 {
1292 u32 kmrnctrlsta;
1293 s32 ret_val = 0;
1294
1295 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1296 if (ret_val)
1297 return ret_val;
1298
1299 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1300 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1301 ew32(KMRNCTRLSTA, kmrnctrlsta);
1302
1303 udelay(2);
1304
1305 kmrnctrlsta = er32(KMRNCTRLSTA);
1306 *data = (u16)kmrnctrlsta;
1307
1308 e1000_release_mac_csr_80003es2lan(hw);
1309
1310 return ret_val;
1311 }
1312
1313 /**
1314 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1315 * @hw: pointer to the HW structure
1316 * @offset: register offset to write to
1317 * @data: data to write at register offset
1318 *
1319 * Acquire semaphore, then write the data to PHY register
1320 * at the offset using the kumeran interface. Release semaphore
1321 * before exiting.
1322 **/
1323 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1324 u16 data)
1325 {
1326 u32 kmrnctrlsta;
1327 s32 ret_val = 0;
1328
1329 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1330 if (ret_val)
1331 return ret_val;
1332
1333 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1334 E1000_KMRNCTRLSTA_OFFSET) | data;
1335 ew32(KMRNCTRLSTA, kmrnctrlsta);
1336
1337 udelay(2);
1338
1339 e1000_release_mac_csr_80003es2lan(hw);
1340
1341 return ret_val;
1342 }
1343
1344 /**
1345 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1346 * @hw: pointer to the HW structure
1347 **/
1348 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1349 {
1350 s32 ret_val = 0;
1351
1352 /*
1353 * If there's an alternate MAC address place it in RAR0
1354 * so that it will override the Si installed default perm
1355 * address.
1356 */
1357 ret_val = e1000_check_alt_mac_addr_generic(hw);
1358 if (ret_val)
1359 goto out;
1360
1361 ret_val = e1000_read_mac_addr_generic(hw);
1362
1363 out:
1364 return ret_val;
1365 }
1366
1367 /**
1368 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1369 * @hw: pointer to the HW structure
1370 *
1371 * In the case of a PHY power down to save power, or to turn off link during a
1372 * driver unload, or wake on lan is not enabled, remove the link.
1373 **/
1374 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1375 {
1376 /* If the management interface is not enabled, then power down */
1377 if (!(hw->mac.ops.check_mng_mode(hw) ||
1378 hw->phy.ops.check_reset_block(hw)))
1379 e1000_power_down_phy_copper(hw);
1380
1381 return;
1382 }
1383
1384 /**
1385 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1386 * @hw: pointer to the HW structure
1387 *
1388 * Clears the hardware counters by reading the counter registers.
1389 **/
1390 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1391 {
1392 e1000e_clear_hw_cntrs_base(hw);
1393
1394 er32(PRC64);
1395 er32(PRC127);
1396 er32(PRC255);
1397 er32(PRC511);
1398 er32(PRC1023);
1399 er32(PRC1522);
1400 er32(PTC64);
1401 er32(PTC127);
1402 er32(PTC255);
1403 er32(PTC511);
1404 er32(PTC1023);
1405 er32(PTC1522);
1406
1407 er32(ALGNERRC);
1408 er32(RXERRC);
1409 er32(TNCRS);
1410 er32(CEXTERR);
1411 er32(TSCTC);
1412 er32(TSCTFC);
1413
1414 er32(MGTPRC);
1415 er32(MGTPDC);
1416 er32(MGTPTC);
1417
1418 er32(IAC);
1419 er32(ICRXOC);
1420
1421 er32(ICRXPTC);
1422 er32(ICRXATC);
1423 er32(ICTXPTC);
1424 er32(ICTXATC);
1425 er32(ICTXQEC);
1426 er32(ICTXQMTC);
1427 er32(ICRXDMTC);
1428 }
1429
1430 static struct e1000_mac_operations es2_mac_ops = {
1431 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1432 .id_led_init = e1000e_id_led_init,
1433 .check_mng_mode = e1000e_check_mng_mode_generic,
1434 /* check_for_link dependent on media type */
1435 .cleanup_led = e1000e_cleanup_led_generic,
1436 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1437 .get_bus_info = e1000e_get_bus_info_pcie,
1438 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1439 .led_on = e1000e_led_on_generic,
1440 .led_off = e1000e_led_off_generic,
1441 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1442 .write_vfta = e1000_write_vfta_generic,
1443 .clear_vfta = e1000_clear_vfta_generic,
1444 .reset_hw = e1000_reset_hw_80003es2lan,
1445 .init_hw = e1000_init_hw_80003es2lan,
1446 .setup_link = e1000e_setup_link,
1447 /* setup_physical_interface dependent on media type */
1448 .setup_led = e1000e_setup_led_generic,
1449 };
1450
1451 static struct e1000_phy_operations es2_phy_ops = {
1452 .acquire = e1000_acquire_phy_80003es2lan,
1453 .check_polarity = e1000_check_polarity_m88,
1454 .check_reset_block = e1000e_check_reset_block_generic,
1455 .commit = e1000e_phy_sw_reset,
1456 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1457 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1458 .get_cable_length = e1000_get_cable_length_80003es2lan,
1459 .get_info = e1000e_get_phy_info_m88,
1460 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1461 .release = e1000_release_phy_80003es2lan,
1462 .reset = e1000e_phy_hw_reset_generic,
1463 .set_d0_lplu_state = NULL,
1464 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1465 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1466 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1467 };
1468
1469 static struct e1000_nvm_operations es2_nvm_ops = {
1470 .acquire = e1000_acquire_nvm_80003es2lan,
1471 .read = e1000e_read_nvm_eerd,
1472 .release = e1000_release_nvm_80003es2lan,
1473 .update = e1000e_update_nvm_checksum_generic,
1474 .valid_led_default = e1000e_valid_led_default,
1475 .validate = e1000e_validate_nvm_checksum_generic,
1476 .write = e1000_write_nvm_80003es2lan,
1477 };
1478
1479 struct e1000_info e1000_es2_info = {
1480 .mac = e1000_80003es2lan,
1481 .flags = FLAG_HAS_HW_VLAN_FILTER
1482 | FLAG_HAS_JUMBO_FRAMES
1483 | FLAG_HAS_WOL
1484 | FLAG_APME_IN_CTRL3
1485 | FLAG_RX_CSUM_ENABLED
1486 | FLAG_HAS_CTRLEXT_ON_LOAD
1487 | FLAG_RX_NEEDS_RESTART /* errata */
1488 | FLAG_TARC_SET_BIT_ZERO /* errata */
1489 | FLAG_APME_CHECK_PORT_B
1490 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1491 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1492 .pba = 38,
1493 .max_hw_frame_size = DEFAULT_JUMBO,
1494 .get_variants = e1000_get_variants_80003es2lan,
1495 .mac_ops = &es2_mac_ops,
1496 .phy_ops = &es2_phy_ops,
1497 .nvm_ops = &es2_nvm_ops,
1498 };
1499
Linux kernel - Deliverables
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