drivers/net/e1000e/hw.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_HW_H_
  30 #define _E1000_HW_H_
  31
  32 #include <linux/types.h>
  33
  34 struct e1000_hw;
  35 struct e1000_adapter;
  36
  37 #include "defines.h"
  38
  39 #define er32(reg)       __er32(hw, E1000_##reg)
  40 #define ew32(reg,val)   __ew32(hw, E1000_##reg, (val))
  41 #define e1e_flush()     er32(STATUS)
  42
  43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
  44         (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
  45
  46 #define E1000_READ_REG_ARRAY(a, reg, offset) \
  47         (readl((a)->hw_addr + reg + ((offset) << 2)))
  48
  49 enum e1e_registers {
  50         E1000_CTRL     = 0x00000, /* Device Control - RW */
  51         E1000_STATUS   = 0x00008, /* Device Status - RO */
  52         E1000_EECD     = 0x00010, /* EEPROM/Flash Control - RW */
  53         E1000_EERD     = 0x00014, /* EEPROM Read - RW */
  54         E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
  55         E1000_FLA      = 0x0001C, /* Flash Access - RW */
  56         E1000_MDIC     = 0x00020, /* MDI Control - RW */
  57         E1000_SCTL     = 0x00024, /* SerDes Control - RW */
  58         E1000_FCAL     = 0x00028, /* Flow Control Address Low - RW */
  59         E1000_FCAH     = 0x0002C, /* Flow Control Address High -RW */
  60         E1000_FEXTNVM  = 0x00028, /* Future Extended NVM - RW */
  61         E1000_FCT      = 0x00030, /* Flow Control Type - RW */
  62         E1000_VET      = 0x00038, /* VLAN Ether Type - RW */
  63         E1000_ICR      = 0x000C0, /* Interrupt Cause Read - R/clr */
  64         E1000_ITR      = 0x000C4, /* Interrupt Throttling Rate - RW */
  65         E1000_ICS      = 0x000C8, /* Interrupt Cause Set - WO */
  66         E1000_IMS      = 0x000D0, /* Interrupt Mask Set - RW */
  67         E1000_IMC      = 0x000D8, /* Interrupt Mask Clear - WO */
  68         E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
  69         E1000_IAM      = 0x000E0, /* Interrupt Acknowledge Auto Mask */
  70         E1000_IVAR     = 0x000E4, /* Interrupt Vector Allocation - RW */
  71         E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
  72 #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
  73         E1000_RCTL     = 0x00100, /* Rx Control - RW */
  74         E1000_FCTTV    = 0x00170, /* Flow Control Transmit Timer Value - RW */
  75         E1000_TXCW     = 0x00178, /* Tx Configuration Word - RW */
  76         E1000_RXCW     = 0x00180, /* Rx Configuration Word - RO */
  77         E1000_TCTL     = 0x00400, /* Tx Control - RW */
  78         E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
  79         E1000_TIPG     = 0x00410, /* Tx Inter-packet gap -RW */
  80         E1000_AIT      = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
  81         E1000_LEDCTL   = 0x00E00, /* LED Control - RW */
  82         E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
  83         E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
  84         E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
  85         E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
  86         E1000_PBS      = 0x01008, /* Packet Buffer Size */
  87         E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
  88         E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
  89         E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
  90         E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */
  91         E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
  92         E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
  93         E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
  94         E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
  95         E1000_RDBAL    = 0x02800, /* Rx Descriptor Base Address Low - RW */
  96         E1000_RDBAH    = 0x02804, /* Rx Descriptor Base Address High - RW */
  97         E1000_RDLEN    = 0x02808, /* Rx Descriptor Length - RW */
  98         E1000_RDH      = 0x02810, /* Rx Descriptor Head - RW */
  99         E1000_RDT      = 0x02818, /* Rx Descriptor Tail - RW */
 100         E1000_RDTR     = 0x02820, /* Rx Delay Timer - RW */
 101         E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
 102 #define E1000_RXDCTL(_n)   (E1000_RXDCTL_BASE + (_n << 8))
 103         E1000_RADV     = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
 104
 105 /* Convenience macros
 106  *
 107  * Note: "_n" is the queue number of the register to be written to.
 108  *
 109  * Example usage:
 110  * E1000_RDBAL_REG(current_rx_queue)
 111  *
 112  */
 113 #define E1000_RDBAL_REG(_n)   (E1000_RDBAL + (_n << 8))
 114         E1000_KABGTXD  = 0x03004, /* AFE Band Gap Transmit Ref Data */
 115         E1000_TDBAL    = 0x03800, /* Tx Descriptor Base Address Low - RW */
 116         E1000_TDBAH    = 0x03804, /* Tx Descriptor Base Address High - RW */
 117         E1000_TDLEN    = 0x03808, /* Tx Descriptor Length - RW */
 118         E1000_TDH      = 0x03810, /* Tx Descriptor Head - RW */
 119         E1000_TDT      = 0x03818, /* Tx Descriptor Tail - RW */
 120         E1000_TIDV     = 0x03820, /* Tx Interrupt Delay Value - RW */
 121         E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
 122 #define E1000_TXDCTL(_n)   (E1000_TXDCTL_BASE + (_n << 8))
 123         E1000_TADV     = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
 124         E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
 125 #define E1000_TARC(_n)   (E1000_TARC_BASE + (_n << 8))
 126         E1000_CRCERRS  = 0x04000, /* CRC Error Count - R/clr */
 127         E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
 128         E1000_SYMERRS  = 0x04008, /* Symbol Error Count - R/clr */
 129         E1000_RXERRC   = 0x0400C, /* Receive Error Count - R/clr */
 130         E1000_MPC      = 0x04010, /* Missed Packet Count - R/clr */
 131         E1000_SCC      = 0x04014, /* Single Collision Count - R/clr */
 132         E1000_ECOL     = 0x04018, /* Excessive Collision Count - R/clr */
 133         E1000_MCC      = 0x0401C, /* Multiple Collision Count - R/clr */
 134         E1000_LATECOL  = 0x04020, /* Late Collision Count - R/clr */
 135         E1000_COLC     = 0x04028, /* Collision Count - R/clr */
 136         E1000_DC       = 0x04030, /* Defer Count - R/clr */
 137         E1000_TNCRS    = 0x04034, /* Tx-No CRS - R/clr */
 138         E1000_SEC      = 0x04038, /* Sequence Error Count - R/clr */
 139         E1000_CEXTERR  = 0x0403C, /* Carrier Extension Error Count - R/clr */
 140         E1000_RLEC     = 0x04040, /* Receive Length Error Count - R/clr */
 141         E1000_XONRXC   = 0x04048, /* XON Rx Count - R/clr */
 142         E1000_XONTXC   = 0x0404C, /* XON Tx Count - R/clr */
 143         E1000_XOFFRXC  = 0x04050, /* XOFF Rx Count - R/clr */
 144         E1000_XOFFTXC  = 0x04054, /* XOFF Tx Count - R/clr */
 145         E1000_FCRUC    = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
 146         E1000_PRC64    = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
 147         E1000_PRC127   = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
 148         E1000_PRC255   = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
 149         E1000_PRC511   = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
 150         E1000_PRC1023  = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
 151         E1000_PRC1522  = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
 152         E1000_GPRC     = 0x04074, /* Good Packets Rx Count - R/clr */
 153         E1000_BPRC     = 0x04078, /* Broadcast Packets Rx Count - R/clr */
 154         E1000_MPRC     = 0x0407C, /* Multicast Packets Rx Count - R/clr */
 155         E1000_GPTC     = 0x04080, /* Good Packets Tx Count - R/clr */
 156         E1000_GORCL    = 0x04088, /* Good Octets Rx Count Low - R/clr */
 157         E1000_GORCH    = 0x0408C, /* Good Octets Rx Count High - R/clr */
 158         E1000_GOTCL    = 0x04090, /* Good Octets Tx Count Low - R/clr */
 159         E1000_GOTCH    = 0x04094, /* Good Octets Tx Count High - R/clr */
 160         E1000_RNBC     = 0x040A0, /* Rx No Buffers Count - R/clr */
 161         E1000_RUC      = 0x040A4, /* Rx Undersize Count - R/clr */
 162         E1000_RFC      = 0x040A8, /* Rx Fragment Count - R/clr */
 163         E1000_ROC      = 0x040AC, /* Rx Oversize Count - R/clr */
 164         E1000_RJC      = 0x040B0, /* Rx Jabber Count - R/clr */
 165         E1000_MGTPRC   = 0x040B4, /* Management Packets Rx Count - R/clr */
 166         E1000_MGTPDC   = 0x040B8, /* Management Packets Dropped Count - R/clr */
 167         E1000_MGTPTC   = 0x040BC, /* Management Packets Tx Count - R/clr */
 168         E1000_TORL     = 0x040C0, /* Total Octets Rx Low - R/clr */
 169         E1000_TORH     = 0x040C4, /* Total Octets Rx High - R/clr */
 170         E1000_TOTL     = 0x040C8, /* Total Octets Tx Low - R/clr */
 171         E1000_TOTH     = 0x040CC, /* Total Octets Tx High - R/clr */
 172         E1000_TPR      = 0x040D0, /* Total Packets Rx - R/clr */
 173         E1000_TPT      = 0x040D4, /* Total Packets Tx - R/clr */
 174         E1000_PTC64    = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
 175         E1000_PTC127   = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
 176         E1000_PTC255   = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
 177         E1000_PTC511   = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
 178         E1000_PTC1023  = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
 179         E1000_PTC1522  = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
 180         E1000_MPTC     = 0x040F0, /* Multicast Packets Tx Count - R/clr */
 181         E1000_BPTC     = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
 182         E1000_TSCTC    = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
 183         E1000_TSCTFC   = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
 184         E1000_IAC      = 0x04100, /* Interrupt Assertion Count */
 185         E1000_ICRXPTC  = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
 186         E1000_ICRXATC  = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
 187         E1000_ICTXPTC  = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
 188         E1000_ICTXATC  = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
 189         E1000_ICTXQEC  = 0x04118, /* Irq Cause Tx Queue Empty Count */
 190         E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
 191         E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
 192         E1000_ICRXOC   = 0x04124, /* Irq Cause Receiver Overrun Count */
 193         E1000_RXCSUM   = 0x05000, /* Rx Checksum Control - RW */
 194         E1000_RFCTL    = 0x05008, /* Receive Filter Control */
 195         E1000_MTA      = 0x05200, /* Multicast Table Array - RW Array */
 196         E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
 197 #define E1000_RAL(_n)   (E1000_RAL_BASE + ((_n) * 8))
 198 #define E1000_RA        (E1000_RAL(0))
 199         E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
 200 #define E1000_RAH(_n)   (E1000_RAH_BASE + ((_n) * 8))
 201         E1000_VFTA     = 0x05600, /* VLAN Filter Table Array - RW Array */
 202         E1000_WUC      = 0x05800, /* Wakeup Control - RW */
 203         E1000_WUFC     = 0x05808, /* Wakeup Filter Control - RW */
 204         E1000_WUS      = 0x05810, /* Wakeup Status - RO */
 205         E1000_MANC     = 0x05820, /* Management Control - RW */
 206         E1000_FFLT     = 0x05F00, /* Flexible Filter Length Table - RW Array */
 207         E1000_HOST_IF  = 0x08800, /* Host Interface */
 208
 209         E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
 210         E1000_MANC2H    = 0x05860, /* Management Control To Host - RW */
 211         E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
 212         E1000_GCR       = 0x05B00, /* PCI-Ex Control */
 213         E1000_GCR2      = 0x05B64, /* PCI-Ex Control #2 */
 214         E1000_FACTPS    = 0x05B30, /* Function Active and Power State to MNG */
 215         E1000_SWSM      = 0x05B50, /* SW Semaphore */
 216         E1000_FWSM      = 0x05B54, /* FW Semaphore */
 217         E1000_SWSM2     = 0x05B58, /* Driver-only SW semaphore */
 218         E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
 219         E1000_HICR      = 0x08F00, /* Host Interface Control */
 220 };
 221
 222 #define E1000_MAX_PHY_ADDR              4
 223
 224 /* IGP01E1000 Specific Registers */
 225 #define IGP01E1000_PHY_PORT_CONFIG      0x10 /* Port Config */
 226 #define IGP01E1000_PHY_PORT_STATUS      0x11 /* Status */
 227 #define IGP01E1000_PHY_PORT_CTRL        0x12 /* Control */
 228 #define IGP01E1000_PHY_LINK_HEALTH      0x13 /* PHY Link Health */
 229 #define IGP02E1000_PHY_POWER_MGMT       0x19 /* Power Management */
 230 #define IGP01E1000_PHY_PAGE_SELECT      0x1F /* Page Select */
 231 #define BM_PHY_PAGE_SELECT              22   /* Page Select for BM */
 232 #define IGP_PAGE_SHIFT                  5
 233 #define PHY_REG_MASK                    0x1F
 234
 235 #define BM_WUC_PAGE                     800
 236 #define BM_WUC_ADDRESS_OPCODE           0x11
 237 #define BM_WUC_DATA_OPCODE              0x12
 238 #define BM_WUC_ENABLE_PAGE              769
 239 #define BM_WUC_ENABLE_REG               17
 240 #define BM_WUC_ENABLE_BIT               (1 << 2)
 241 #define BM_WUC_HOST_WU_BIT              (1 << 4)
 242
 243 #define BM_WUC  PHY_REG(BM_WUC_PAGE, 1)
 244 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
 245 #define BM_WUS  PHY_REG(BM_WUC_PAGE, 3)
 246
 247 #define IGP01E1000_PHY_PCS_INIT_REG     0x00B4
 248 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 249
 250 #define IGP01E1000_PSCR_AUTO_MDIX       0x1000
 251 #define IGP01E1000_PSCR_FORCE_MDI_MDIX  0x2000 /* 0=MDI, 1=MDIX */
 252
 253 #define IGP01E1000_PSCFR_SMART_SPEED    0x0080
 254
 255 #define IGP02E1000_PM_SPD               0x0001 /* Smart Power Down */
 256 #define IGP02E1000_PM_D0_LPLU           0x0002 /* For D0a states */
 257 #define IGP02E1000_PM_D3_LPLU           0x0004 /* For all other states */
 258
 259 #define IGP01E1000_PLHR_SS_DOWNGRADE    0x8000
 260
 261 #define IGP01E1000_PSSR_POLARITY_REVERSED       0x0002
 262 #define IGP01E1000_PSSR_MDIX                    0x0800
 263 #define IGP01E1000_PSSR_SPEED_MASK              0xC000
 264 #define IGP01E1000_PSSR_SPEED_1000MBPS          0xC000
 265
 266 #define IGP02E1000_PHY_CHANNEL_NUM              4
 267 #define IGP02E1000_PHY_AGC_A                    0x11B1
 268 #define IGP02E1000_PHY_AGC_B                    0x12B1
 269 #define IGP02E1000_PHY_AGC_C                    0x14B1
 270 #define IGP02E1000_PHY_AGC_D                    0x18B1
 271
 272 #define IGP02E1000_AGC_LENGTH_SHIFT     9 /* Course - 15:13, Fine - 12:9 */
 273 #define IGP02E1000_AGC_LENGTH_MASK      0x7F
 274 #define IGP02E1000_AGC_RANGE            15
 275
 276 /* manage.c */
 277 #define E1000_VFTA_ENTRY_SHIFT          5
 278 #define E1000_VFTA_ENTRY_MASK           0x7F
 279 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
 280
 281 #define E1000_HICR_EN                   0x01  /* Enable bit - RO */
 282 /* Driver sets this bit when done to put command in RAM */
 283 #define E1000_HICR_C                    0x02
 284 #define E1000_HICR_FW_RESET_ENABLE      0x40
 285 #define E1000_HICR_FW_RESET             0x80
 286
 287 #define E1000_FWSM_MODE_MASK            0xE
 288 #define E1000_FWSM_MODE_SHIFT           1
 289
 290 #define E1000_MNG_IAMT_MODE             0x3
 291 #define E1000_MNG_DHCP_COOKIE_LENGTH    0x10
 292 #define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0
 293 #define E1000_MNG_DHCP_COMMAND_TIMEOUT  10
 294 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64
 295 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING    0x1
 296 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN       0x2
 297
 298 /* nvm.c */
 299 #define E1000_STM_OPCODE  0xDB00
 300
 301 #define E1000_KMRNCTRLSTA_OFFSET        0x001F0000
 302 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT  16
 303 #define E1000_KMRNCTRLSTA_REN           0x00200000
 304 #define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3    /* Kumeran Diagnostic */
 305 #define E1000_KMRNCTRLSTA_TIMEOUTS      0x4    /* Kumeran Timeouts */
 306 #define E1000_KMRNCTRLSTA_INBAND_PARAM  0x9    /* Kumeran InBand Parameters */
 307 #define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000 /* Nearend Loopback mode */
 308 #define E1000_KMRNCTRLSTA_K1_CONFIG     0x7
 309 #define E1000_KMRNCTRLSTA_K1_ENABLE     0x140E
 310 #define E1000_KMRNCTRLSTA_K1_DISABLE    0x1400
 311
 312 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
 313 #define IFE_PHY_SPECIAL_CONTROL         0x11 /* 100BaseTx PHY Special Control */
 314 #define IFE_PHY_SPECIAL_CONTROL_LED     0x1B /* PHY Special and LED Control */
 315 #define IFE_PHY_MDIX_CONTROL            0x1C /* MDI/MDI-X Control */
 316
 317 /* IFE PHY Extended Status Control */
 318 #define IFE_PESC_POLARITY_REVERSED      0x0100
 319
 320 /* IFE PHY Special Control */
 321 #define IFE_PSC_AUTO_POLARITY_DISABLE           0x0010
 322 #define IFE_PSC_FORCE_POLARITY                  0x0020
 323
 324 /* IFE PHY Special Control and LED Control */
 325 #define IFE_PSCL_PROBE_MODE             0x0020
 326 #define IFE_PSCL_PROBE_LEDS_OFF         0x0006 /* Force LEDs 0 and 2 off */
 327 #define IFE_PSCL_PROBE_LEDS_ON          0x0007 /* Force LEDs 0 and 2 on */
 328
 329 /* IFE PHY MDIX Control */
 330 #define IFE_PMC_MDIX_STATUS     0x0020 /* 1=MDI-X, 0=MDI */
 331 #define IFE_PMC_FORCE_MDIX      0x0040 /* 1=force MDI-X, 0=force MDI */
 332 #define IFE_PMC_AUTO_MDIX       0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
 333
 334 #define E1000_CABLE_LENGTH_UNDEFINED    0xFF
 335
 336 #define E1000_DEV_ID_82571EB_COPPER             0x105E
 337 #define E1000_DEV_ID_82571EB_FIBER              0x105F
 338 #define E1000_DEV_ID_82571EB_SERDES             0x1060
 339 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
 340 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
 341 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
 342 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
 343 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
 344 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
 345 #define E1000_DEV_ID_82572EI_COPPER             0x107D
 346 #define E1000_DEV_ID_82572EI_FIBER              0x107E
 347 #define E1000_DEV_ID_82572EI_SERDES             0x107F
 348 #define E1000_DEV_ID_82572EI                    0x10B9
 349 #define E1000_DEV_ID_82573E                     0x108B
 350 #define E1000_DEV_ID_82573E_IAMT                0x108C
 351 #define E1000_DEV_ID_82573L                     0x109A
 352 #define E1000_DEV_ID_82574L                     0x10D3
 353 #define E1000_DEV_ID_82574LA                    0x10F6
 354 #define E1000_DEV_ID_82583V                     0x150C
 355
 356 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 357 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 358 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 359 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 360
 361 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 362 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 363 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 364 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 365 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 366 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 367 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 368 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 369 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 370 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 371 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 372 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 373 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 374 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 375 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 376 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 377 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 378 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 379 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 380 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 381 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 382 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 383 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 384 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 385 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 386 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 387
 388 #define E1000_REVISION_4 4
 389
 390 #define E1000_FUNC_1 1
 391
 392 enum e1000_mac_type {
 393         e1000_82571,
 394         e1000_82572,
 395         e1000_82573,
 396         e1000_82574,
 397         e1000_82583,
 398         e1000_80003es2lan,
 399         e1000_ich8lan,
 400         e1000_ich9lan,
 401         e1000_ich10lan,
 402         e1000_pchlan,
 403 };
 404
 405 enum e1000_media_type {
 406         e1000_media_type_unknown = 0,
 407         e1000_media_type_copper = 1,
 408         e1000_media_type_fiber = 2,
 409         e1000_media_type_internal_serdes = 3,
 410         e1000_num_media_types
 411 };
 412
 413 enum e1000_nvm_type {
 414         e1000_nvm_unknown = 0,
 415         e1000_nvm_none,
 416         e1000_nvm_eeprom_spi,
 417         e1000_nvm_flash_hw,
 418         e1000_nvm_flash_sw
 419 };
 420
 421 enum e1000_nvm_override {
 422         e1000_nvm_override_none = 0,
 423         e1000_nvm_override_spi_small,
 424         e1000_nvm_override_spi_large
 425 };
 426
 427 enum e1000_phy_type {
 428         e1000_phy_unknown = 0,
 429         e1000_phy_none,
 430         e1000_phy_m88,
 431         e1000_phy_igp,
 432         e1000_phy_igp_2,
 433         e1000_phy_gg82563,
 434         e1000_phy_igp_3,
 435         e1000_phy_ife,
 436         e1000_phy_bm,
 437         e1000_phy_82578,
 438         e1000_phy_82577,
 439 };
 440
 441 enum e1000_bus_width {
 442         e1000_bus_width_unknown = 0,
 443         e1000_bus_width_pcie_x1,
 444         e1000_bus_width_pcie_x2,
 445         e1000_bus_width_pcie_x4 = 4,
 446         e1000_bus_width_32,
 447         e1000_bus_width_64,
 448         e1000_bus_width_reserved
 449 };
 450
 451 enum e1000_1000t_rx_status {
 452         e1000_1000t_rx_status_not_ok = 0,
 453         e1000_1000t_rx_status_ok,
 454         e1000_1000t_rx_status_undefined = 0xFF
 455 };
 456
 457 enum e1000_rev_polarity{
 458         e1000_rev_polarity_normal = 0,
 459         e1000_rev_polarity_reversed,
 460         e1000_rev_polarity_undefined = 0xFF
 461 };
 462
 463 enum e1000_fc_mode {
 464         e1000_fc_none = 0,
 465         e1000_fc_rx_pause,
 466         e1000_fc_tx_pause,
 467         e1000_fc_full,
 468         e1000_fc_default = 0xFF
 469 };
 470
 471 enum e1000_ms_type {
 472         e1000_ms_hw_default = 0,
 473         e1000_ms_force_master,
 474         e1000_ms_force_slave,
 475         e1000_ms_auto
 476 };
 477
 478 enum e1000_smart_speed {
 479         e1000_smart_speed_default = 0,
 480         e1000_smart_speed_on,
 481         e1000_smart_speed_off
 482 };
 483
 484 enum e1000_serdes_link_state {
 485         e1000_serdes_link_down = 0,
 486         e1000_serdes_link_autoneg_progress,
 487         e1000_serdes_link_autoneg_complete,
 488         e1000_serdes_link_forced_up
 489 };
 490
 491 /* Receive Descriptor */
 492 struct e1000_rx_desc {
 493         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 494         __le16 length;      /* Length of data DMAed into data buffer */
 495         __le16 csum;    /* Packet checksum */
 496         u8  status;      /* Descriptor status */
 497         u8  errors;      /* Descriptor Errors */
 498         __le16 special;
 499 };
 500
 501 /* Receive Descriptor - Extended */
 502 union e1000_rx_desc_extended {
 503         struct {
 504                 __le64 buffer_addr;
 505                 __le64 reserved;
 506         } read;
 507         struct {
 508                 struct {
 509                         __le32 mrq;           /* Multiple Rx Queues */
 510                         union {
 511                                 __le32 rss;         /* RSS Hash */
 512                                 struct {
 513                                         __le16 ip_id;  /* IP id */
 514                                         __le16 csum;   /* Packet Checksum */
 515                                 } csum_ip;
 516                         } hi_dword;
 517                 } lower;
 518                 struct {
 519                         __le32 status_error;     /* ext status/error */
 520                         __le16 length;
 521                         __le16 vlan;         /* VLAN tag */
 522                 } upper;
 523         } wb;  /* writeback */
 524 };
 525
 526 #define MAX_PS_BUFFERS 4
 527 /* Receive Descriptor - Packet Split */
 528 union e1000_rx_desc_packet_split {
 529         struct {
 530                 /* one buffer for protocol header(s), three data buffers */
 531                 __le64 buffer_addr[MAX_PS_BUFFERS];
 532         } read;
 533         struct {
 534                 struct {
 535                         __le32 mrq;           /* Multiple Rx Queues */
 536                         union {
 537                                 __le32 rss;           /* RSS Hash */
 538                                 struct {
 539                                         __le16 ip_id;    /* IP id */
 540                                         __le16 csum;     /* Packet Checksum */
 541                                 } csum_ip;
 542                         } hi_dword;
 543                 } lower;
 544                 struct {
 545                         __le32 status_error;     /* ext status/error */
 546                         __le16 length0;   /* length of buffer 0 */
 547                         __le16 vlan;         /* VLAN tag */
 548                 } middle;
 549                 struct {
 550                         __le16 header_status;
 551                         __le16 length[3];       /* length of buffers 1-3 */
 552                 } upper;
 553                 __le64 reserved;
 554         } wb; /* writeback */
 555 };
 556
 557 /* Transmit Descriptor */
 558 struct e1000_tx_desc {
 559         __le64 buffer_addr;      /* Address of the descriptor's data buffer */
 560         union {
 561                 __le32 data;
 562                 struct {
 563                         __le16 length;    /* Data buffer length */
 564                         u8 cso; /* Checksum offset */
 565                         u8 cmd; /* Descriptor control */
 566                 } flags;
 567         } lower;
 568         union {
 569                 __le32 data;
 570                 struct {
 571                         u8 status;     /* Descriptor status */
 572                         u8 css; /* Checksum start */
 573                         __le16 special;
 574                 } fields;
 575         } upper;
 576 };
 577
 578 /* Offload Context Descriptor */
 579 struct e1000_context_desc {
 580         union {
 581                 __le32 ip_config;
 582                 struct {
 583                         u8 ipcss;      /* IP checksum start */
 584                         u8 ipcso;      /* IP checksum offset */
 585                         __le16 ipcse;     /* IP checksum end */
 586                 } ip_fields;
 587         } lower_setup;
 588         union {
 589                 __le32 tcp_config;
 590                 struct {
 591                         u8 tucss;      /* TCP checksum start */
 592                         u8 tucso;      /* TCP checksum offset */
 593                         __le16 tucse;     /* TCP checksum end */
 594                 } tcp_fields;
 595         } upper_setup;
 596         __le32 cmd_and_length;
 597         union {
 598                 __le32 data;
 599                 struct {
 600                         u8 status;     /* Descriptor status */
 601                         u8 hdr_len;    /* Header length */
 602                         __le16 mss;       /* Maximum segment size */
 603                 } fields;
 604         } tcp_seg_setup;
 605 };
 606
 607 /* Offload data descriptor */
 608 struct e1000_data_desc {
 609         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 610         union {
 611                 __le32 data;
 612                 struct {
 613                         __le16 length;    /* Data buffer length */
 614                         u8 typ_len_ext;
 615                         u8 cmd;
 616                 } flags;
 617         } lower;
 618         union {
 619                 __le32 data;
 620                 struct {
 621                         u8 status;     /* Descriptor status */
 622                         u8 popts;      /* Packet Options */
 623                         __le16 special;   /* */
 624                 } fields;
 625         } upper;
 626 };
 627
 628 /* Statistics counters collected by the MAC */
 629 struct e1000_hw_stats {
 630         u64 crcerrs;
 631         u64 algnerrc;
 632         u64 symerrs;
 633         u64 rxerrc;
 634         u64 mpc;
 635         u64 scc;
 636         u64 ecol;
 637         u64 mcc;
 638         u64 latecol;
 639         u64 colc;
 640         u64 dc;
 641         u64 tncrs;
 642         u64 sec;
 643         u64 cexterr;
 644         u64 rlec;
 645         u64 xonrxc;
 646         u64 xontxc;
 647         u64 xoffrxc;
 648         u64 xofftxc;
 649         u64 fcruc;
 650         u64 prc64;
 651         u64 prc127;
 652         u64 prc255;
 653         u64 prc511;
 654         u64 prc1023;
 655         u64 prc1522;
 656         u64 gprc;
 657         u64 bprc;
 658         u64 mprc;
 659         u64 gptc;
 660         u64 gorc;
 661         u64 gotc;
 662         u64 rnbc;
 663         u64 ruc;
 664         u64 rfc;
 665         u64 roc;
 666         u64 rjc;
 667         u64 mgprc;
 668         u64 mgpdc;
 669         u64 mgptc;
 670         u64 tor;
 671         u64 tot;
 672         u64 tpr;
 673         u64 tpt;
 674         u64 ptc64;
 675         u64 ptc127;
 676         u64 ptc255;
 677         u64 ptc511;
 678         u64 ptc1023;
 679         u64 ptc1522;
 680         u64 mptc;
 681         u64 bptc;
 682         u64 tsctc;
 683         u64 tsctfc;
 684         u64 iac;
 685         u64 icrxptc;
 686         u64 icrxatc;
 687         u64 ictxptc;
 688         u64 ictxatc;
 689         u64 ictxqec;
 690         u64 ictxqmtc;
 691         u64 icrxdmtc;
 692         u64 icrxoc;
 693 };
 694
 695 struct e1000_phy_stats {
 696         u32 idle_errors;
 697         u32 receive_errors;
 698 };
 699
 700 struct e1000_host_mng_dhcp_cookie {
 701         u32 signature;
 702         u8  status;
 703         u8  reserved0;
 704         u16 vlan_id;
 705         u32 reserved1;
 706         u16 reserved2;
 707         u8  reserved3;
 708         u8  checksum;
 709 };
 710
 711 /* Host Interface "Rev 1" */
 712 struct e1000_host_command_header {
 713         u8 command_id;
 714         u8 command_length;
 715         u8 command_options;
 716         u8 checksum;
 717 };
 718
 719 #define E1000_HI_MAX_DATA_LENGTH     252
 720 struct e1000_host_command_info {
 721         struct e1000_host_command_header command_header;
 722         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 723 };
 724
 725 /* Host Interface "Rev 2" */
 726 struct e1000_host_mng_command_header {
 727         u8  command_id;
 728         u8  checksum;
 729         u16 reserved1;
 730         u16 reserved2;
 731         u16 command_length;
 732 };
 733
 734 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 735 struct e1000_host_mng_command_info {
 736         struct e1000_host_mng_command_header command_header;
 737         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 738 };
 739
 740 /* Function pointers and static data for the MAC. */
 741 struct e1000_mac_operations {
 742         s32  (*id_led_init)(struct e1000_hw *);
 743         bool (*check_mng_mode)(struct e1000_hw *);
 744         s32  (*check_for_link)(struct e1000_hw *);
 745         s32  (*cleanup_led)(struct e1000_hw *);
 746         void (*clear_hw_cntrs)(struct e1000_hw *);
 747         void (*clear_vfta)(struct e1000_hw *);
 748         s32  (*get_bus_info)(struct e1000_hw *);
 749         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 750         s32  (*led_on)(struct e1000_hw *);
 751         s32  (*led_off)(struct e1000_hw *);
 752         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
 753         s32  (*reset_hw)(struct e1000_hw *);
 754         s32  (*init_hw)(struct e1000_hw *);
 755         s32  (*setup_link)(struct e1000_hw *);
 756         s32  (*setup_physical_interface)(struct e1000_hw *);
 757         s32  (*setup_led)(struct e1000_hw *);
 758         void (*write_vfta)(struct e1000_hw *, u32, u32);
 759 };
 760
 761 /* Function pointers for the PHY. */
 762 struct e1000_phy_operations {
 763         s32  (*acquire)(struct e1000_hw *);
 764         s32  (*cfg_on_link_up)(struct e1000_hw *);
 765         s32  (*check_polarity)(struct e1000_hw *);
 766         s32  (*check_reset_block)(struct e1000_hw *);
 767         s32  (*commit)(struct e1000_hw *);
 768         s32  (*force_speed_duplex)(struct e1000_hw *);
 769         s32  (*get_cfg_done)(struct e1000_hw *hw);
 770         s32  (*get_cable_length)(struct e1000_hw *);
 771         s32  (*get_info)(struct e1000_hw *);
 772         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 773         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 774         void (*release)(struct e1000_hw *);
 775         s32  (*reset)(struct e1000_hw *);
 776         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 777         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 778         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 779         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 780         void (*power_up)(struct e1000_hw *);
 781         void (*power_down)(struct e1000_hw *);
 782 };
 783
 784 /* Function pointers for the NVM. */
 785 struct e1000_nvm_operations {
 786         s32  (*acquire)(struct e1000_hw *);
 787         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 788         void (*release)(struct e1000_hw *);
 789         s32  (*update)(struct e1000_hw *);
 790         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 791         s32  (*validate)(struct e1000_hw *);
 792         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 793 };
 794
 795 struct e1000_mac_info {
 796         struct e1000_mac_operations ops;
 797
 798         u8 addr[6];
 799         u8 perm_addr[6];
 800
 801         enum e1000_mac_type type;
 802
 803         u32 collision_delta;
 804         u32 ledctl_default;
 805         u32 ledctl_mode1;
 806         u32 ledctl_mode2;
 807         u32 mc_filter_type;
 808         u32 tx_packet_delta;
 809         u32 txcw;
 810
 811         u16 current_ifs_val;
 812         u16 ifs_max_val;
 813         u16 ifs_min_val;
 814         u16 ifs_ratio;
 815         u16 ifs_step_size;
 816         u16 mta_reg_count;
 817         u16 rar_entry_count;
 818
 819         u8  forced_speed_duplex;
 820
 821         bool arc_subsystem_valid;
 822         bool autoneg;
 823         bool autoneg_failed;
 824         bool get_link_status;
 825         bool in_ifs_mode;
 826         bool serdes_has_link;
 827         bool tx_pkt_filtering;
 828         enum e1000_serdes_link_state serdes_link_state;
 829 };
 830
 831 struct e1000_phy_info {
 832         struct e1000_phy_operations ops;
 833
 834         enum e1000_phy_type type;
 835
 836         enum e1000_1000t_rx_status local_rx;
 837         enum e1000_1000t_rx_status remote_rx;
 838         enum e1000_ms_type ms_type;
 839         enum e1000_ms_type original_ms_type;
 840         enum e1000_rev_polarity cable_polarity;
 841         enum e1000_smart_speed smart_speed;
 842
 843         u32 addr;
 844         u32 id;
 845         u32 reset_delay_us; /* in usec */
 846         u32 revision;
 847
 848         enum e1000_media_type media_type;
 849
 850         u16 autoneg_advertised;
 851         u16 autoneg_mask;
 852         u16 cable_length;
 853         u16 max_cable_length;
 854         u16 min_cable_length;
 855
 856         u8 mdix;
 857
 858         bool disable_polarity_correction;
 859         bool is_mdix;
 860         bool polarity_correction;
 861         bool speed_downgraded;
 862         bool autoneg_wait_to_complete;
 863 };
 864
 865 struct e1000_nvm_info {
 866         struct e1000_nvm_operations ops;
 867
 868         enum e1000_nvm_type type;
 869         enum e1000_nvm_override override;
 870
 871         u32 flash_bank_size;
 872         u32 flash_base_addr;
 873
 874         u16 word_size;
 875         u16 delay_usec;
 876         u16 address_bits;
 877         u16 opcode_bits;
 878         u16 page_size;
 879 };
 880
 881 struct e1000_bus_info {
 882         enum e1000_bus_width width;
 883
 884         u16 func;
 885 };
 886
 887 struct e1000_fc_info {
 888         u32 high_water;          /* Flow control high-water mark */
 889         u32 low_water;           /* Flow control low-water mark */
 890         u16 pause_time;          /* Flow control pause timer */
 891         bool send_xon;           /* Flow control send XON */
 892         bool strict_ieee;        /* Strict IEEE mode */
 893         enum e1000_fc_mode current_mode; /* FC mode in effect */
 894         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 895 };
 896
 897 struct e1000_dev_spec_82571 {
 898         bool laa_is_present;
 899         bool alt_mac_addr_is_present;
 900         u32 smb_counter;
 901 };
 902
 903 struct e1000_dev_spec_80003es2lan {
 904         bool  mdic_wa_enable;
 905 };
 906
 907 struct e1000_shadow_ram {
 908         u16  value;
 909         bool modified;
 910 };
 911
 912 #define E1000_ICH8_SHADOW_RAM_WORDS             2048
 913
 914 struct e1000_dev_spec_ich8lan {
 915         bool kmrn_lock_loss_workaround_enabled;
 916         struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
 917         bool nvm_k1_enabled;
 918 };
 919
 920 struct e1000_hw {
 921         struct e1000_adapter *adapter;
 922
 923         u8 __iomem *hw_addr;
 924         u8 __iomem *flash_address;
 925
 926         struct e1000_mac_info  mac;
 927         struct e1000_fc_info   fc;
 928         struct e1000_phy_info  phy;
 929         struct e1000_nvm_info  nvm;
 930         struct e1000_bus_info  bus;
 931         struct e1000_host_mng_dhcp_cookie mng_cookie;
 932
 933         union {
 934                 struct e1000_dev_spec_82571     e82571;
 935                 struct e1000_dev_spec_80003es2lan e80003es2lan;
 936                 struct e1000_dev_spec_ich8lan   ich8lan;
 937         } dev_spec;
 938 };
 939
 940 #endif