1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
34 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
35 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
);
36 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
);
37 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
);
38 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
39 u16
*data
, bool read
);
40 static u32
e1000_get_phy_addr_for_hv_page(u32 page
);
41 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
42 u16
*data
, bool read
);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table
[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
50 static const u16 e1000_igp_2_cable_length_table
[] =
51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 ARRAY_SIZE(e1000_igp_2_cable_length_table)
62 #define BM_PHY_REG_PAGE(offset) \
63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
64 #define BM_PHY_REG_NUM(offset) \
65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
67 ~MAX_PHY_REG_ADDRESS)))
69 #define HV_INTC_FC_PAGE_START 768
70 #define I82578_ADDR_REG 29
71 #define I82577_ADDR_REG 16
72 #define I82577_CFG_REG 22
73 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
74 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
75 #define I82577_CTRL_REG 23
77 /* 82577 specific PHY registers */
78 #define I82577_PHY_CTRL_2 18
79 #define I82577_PHY_STATUS_2 26
80 #define I82577_PHY_DIAG_STATUS 31
82 /* I82577 PHY Status 2 */
83 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
84 #define I82577_PHY_STATUS2_MDIX 0x0800
85 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
86 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
88 /* I82577 PHY Control 2 */
89 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
90 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
92 /* I82577 PHY Diagnostics Status */
93 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
94 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
96 /* BM PHY Copper Specific Control 1 */
97 #define BM_CS_CTRL1 16
99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
101 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
105 * @hw: pointer to the HW structure
107 * Read the PHY management control register and check whether a PHY reset
108 * is blocked. If a reset is not blocked return 0, otherwise
109 * return E1000_BLK_PHY_RESET (12).
111 s32
e1000e_check_reset_block_generic(struct e1000_hw
*hw
)
117 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
118 E1000_BLK_PHY_RESET
: 0;
122 * e1000e_get_phy_id - Retrieve the PHY ID and revision
123 * @hw: pointer to the HW structure
125 * Reads the PHY registers and stores the PHY ID and possibly the PHY
126 * revision in the hardware structure.
128 s32
e1000e_get_phy_id(struct e1000_hw
*hw
)
130 struct e1000_phy_info
*phy
= &hw
->phy
;
135 if (!(phy
->ops
.read_reg
))
138 while (retry_count
< 2) {
139 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
143 phy
->id
= (u32
)(phy_id
<< 16);
145 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
149 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
150 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
152 if (phy
->id
!= 0 && phy
->id
!= PHY_REVISION_MASK
)
156 * If the PHY ID is still unknown, we may have an 82577i
157 * without link. We will try again after setting Slow
158 * MDIC mode. No harm in trying again in this case since
159 * the PHY ID is unknown at this point anyway
161 ret_val
= phy
->ops
.acquire(hw
);
164 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
167 phy
->ops
.release(hw
);
172 /* Revert to MDIO fast mode, if applicable */
174 ret_val
= phy
->ops
.acquire(hw
);
177 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, false);
178 phy
->ops
.release(hw
);
185 * e1000e_phy_reset_dsp - Reset PHY DSP
186 * @hw: pointer to the HW structure
188 * Reset the digital signal processor.
190 s32
e1000e_phy_reset_dsp(struct e1000_hw
*hw
)
194 ret_val
= e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
198 return e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
202 * e1000e_read_phy_reg_mdic - Read MDI control register
203 * @hw: pointer to the HW structure
204 * @offset: register offset to be read
205 * @data: pointer to the read data
207 * Reads the MDI control register in the PHY at offset and stores the
208 * information read to data.
210 s32
e1000e_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
212 struct e1000_phy_info
*phy
= &hw
->phy
;
215 if (offset
> MAX_PHY_REG_ADDRESS
) {
216 e_dbg("PHY Address %d is out of range\n", offset
);
217 return -E1000_ERR_PARAM
;
221 * Set up Op-code, Phy Address, and register offset in the MDI
222 * Control register. The MAC will take care of interfacing with the
223 * PHY to retrieve the desired data.
225 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
226 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
227 (E1000_MDIC_OP_READ
));
232 * Poll the ready bit to see if the MDI read completed
233 * Increasing the time out as testing showed failures with
236 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
239 if (mdic
& E1000_MDIC_READY
)
242 if (!(mdic
& E1000_MDIC_READY
)) {
243 e_dbg("MDI Read did not complete\n");
244 return -E1000_ERR_PHY
;
246 if (mdic
& E1000_MDIC_ERROR
) {
247 e_dbg("MDI Error\n");
248 return -E1000_ERR_PHY
;
256 * e1000e_write_phy_reg_mdic - Write MDI control register
257 * @hw: pointer to the HW structure
258 * @offset: register offset to write to
259 * @data: data to write to register at offset
261 * Writes data to MDI control register in the PHY at offset.
263 s32
e1000e_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
265 struct e1000_phy_info
*phy
= &hw
->phy
;
268 if (offset
> MAX_PHY_REG_ADDRESS
) {
269 e_dbg("PHY Address %d is out of range\n", offset
);
270 return -E1000_ERR_PARAM
;
274 * Set up Op-code, Phy Address, and register offset in the MDI
275 * Control register. The MAC will take care of interfacing with the
276 * PHY to retrieve the desired data.
278 mdic
= (((u32
)data
) |
279 (offset
<< E1000_MDIC_REG_SHIFT
) |
280 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
281 (E1000_MDIC_OP_WRITE
));
286 * Poll the ready bit to see if the MDI read completed
287 * Increasing the time out as testing showed failures with
290 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
293 if (mdic
& E1000_MDIC_READY
)
296 if (!(mdic
& E1000_MDIC_READY
)) {
297 e_dbg("MDI Write did not complete\n");
298 return -E1000_ERR_PHY
;
300 if (mdic
& E1000_MDIC_ERROR
) {
301 e_dbg("MDI Error\n");
302 return -E1000_ERR_PHY
;
309 * e1000e_read_phy_reg_m88 - Read m88 PHY register
310 * @hw: pointer to the HW structure
311 * @offset: register offset to be read
312 * @data: pointer to the read data
314 * Acquires semaphore, if necessary, then reads the PHY register at offset
315 * and storing the retrieved information in data. Release any acquired
316 * semaphores before exiting.
318 s32
e1000e_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
322 ret_val
= hw
->phy
.ops
.acquire(hw
);
326 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
329 hw
->phy
.ops
.release(hw
);
335 * e1000e_write_phy_reg_m88 - Write m88 PHY register
336 * @hw: pointer to the HW structure
337 * @offset: register offset to write to
338 * @data: data to write at register offset
340 * Acquires semaphore, if necessary, then writes the data to PHY register
341 * at the offset. Release any acquired semaphores before exiting.
343 s32
e1000e_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
347 ret_val
= hw
->phy
.ops
.acquire(hw
);
351 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
354 hw
->phy
.ops
.release(hw
);
360 * __e1000e_read_phy_reg_igp - Read igp PHY register
361 * @hw: pointer to the HW structure
362 * @offset: register offset to be read
363 * @data: pointer to the read data
364 * @locked: semaphore has already been acquired or not
366 * Acquires semaphore, if necessary, then reads the PHY register at offset
367 * and stores the retrieved information in data. Release any acquired
368 * semaphores before exiting.
370 static s32
__e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
376 if (!(hw
->phy
.ops
.acquire
))
379 ret_val
= hw
->phy
.ops
.acquire(hw
);
384 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
385 ret_val
= e1000e_write_phy_reg_mdic(hw
,
386 IGP01E1000_PHY_PAGE_SELECT
,
392 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
397 hw
->phy
.ops
.release(hw
);
403 * e1000e_read_phy_reg_igp - Read igp PHY register
404 * @hw: pointer to the HW structure
405 * @offset: register offset to be read
406 * @data: pointer to the read data
408 * Acquires semaphore then reads the PHY register at offset and stores the
409 * retrieved information in data.
410 * Release the acquired semaphore before exiting.
412 s32
e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
414 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, false);
418 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
419 * @hw: pointer to the HW structure
420 * @offset: register offset to be read
421 * @data: pointer to the read data
423 * Reads the PHY register at offset and stores the retrieved information
424 * in data. Assumes semaphore already acquired.
426 s32
e1000e_read_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
428 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, true);
432 * e1000e_write_phy_reg_igp - Write igp PHY register
433 * @hw: pointer to the HW structure
434 * @offset: register offset to write to
435 * @data: data to write at register offset
436 * @locked: semaphore has already been acquired or not
438 * Acquires semaphore, if necessary, then writes the data to PHY register
439 * at the offset. Release any acquired semaphores before exiting.
441 static s32
__e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
,
447 if (!(hw
->phy
.ops
.acquire
))
450 ret_val
= hw
->phy
.ops
.acquire(hw
);
455 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
456 ret_val
= e1000e_write_phy_reg_mdic(hw
,
457 IGP01E1000_PHY_PAGE_SELECT
,
463 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
468 hw
->phy
.ops
.release(hw
);
475 * e1000e_write_phy_reg_igp - Write igp PHY register
476 * @hw: pointer to the HW structure
477 * @offset: register offset to write to
478 * @data: data to write at register offset
480 * Acquires semaphore then writes the data to PHY register
481 * at the offset. Release any acquired semaphores before exiting.
483 s32
e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
485 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, false);
489 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
490 * @hw: pointer to the HW structure
491 * @offset: register offset to write to
492 * @data: data to write at register offset
494 * Writes the data to PHY register at the offset.
495 * Assumes semaphore already acquired.
497 s32
e1000e_write_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
499 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, true);
503 * __e1000_read_kmrn_reg - Read kumeran register
504 * @hw: pointer to the HW structure
505 * @offset: register offset to be read
506 * @data: pointer to the read data
507 * @locked: semaphore has already been acquired or not
509 * Acquires semaphore, if necessary. Then reads the PHY register at offset
510 * using the kumeran interface. The information retrieved is stored in data.
511 * Release any acquired semaphores before exiting.
513 static s32
__e1000_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
520 if (!(hw
->phy
.ops
.acquire
))
523 ret_val
= hw
->phy
.ops
.acquire(hw
);
528 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
529 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
530 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
534 kmrnctrlsta
= er32(KMRNCTRLSTA
);
535 *data
= (u16
)kmrnctrlsta
;
538 hw
->phy
.ops
.release(hw
);
545 * e1000e_read_kmrn_reg - Read kumeran register
546 * @hw: pointer to the HW structure
547 * @offset: register offset to be read
548 * @data: pointer to the read data
550 * Acquires semaphore then reads the PHY register at offset using the
551 * kumeran interface. The information retrieved is stored in data.
552 * Release the acquired semaphore before exiting.
554 s32
e1000e_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
556 return __e1000_read_kmrn_reg(hw
, offset
, data
, false);
560 * e1000e_read_kmrn_reg_locked - Read kumeran register
561 * @hw: pointer to the HW structure
562 * @offset: register offset to be read
563 * @data: pointer to the read data
565 * Reads the PHY register at offset using the kumeran interface. The
566 * information retrieved is stored in data.
567 * Assumes semaphore already acquired.
569 s32
e1000e_read_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
571 return __e1000_read_kmrn_reg(hw
, offset
, data
, true);
575 * __e1000_write_kmrn_reg - Write kumeran register
576 * @hw: pointer to the HW structure
577 * @offset: register offset to write to
578 * @data: data to write at register offset
579 * @locked: semaphore has already been acquired or not
581 * Acquires semaphore, if necessary. Then write the data to PHY register
582 * at the offset using the kumeran interface. Release any acquired semaphores
585 static s32
__e1000_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
,
592 if (!(hw
->phy
.ops
.acquire
))
595 ret_val
= hw
->phy
.ops
.acquire(hw
);
600 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
601 E1000_KMRNCTRLSTA_OFFSET
) | data
;
602 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
607 hw
->phy
.ops
.release(hw
);
614 * e1000e_write_kmrn_reg - Write kumeran register
615 * @hw: pointer to the HW structure
616 * @offset: register offset to write to
617 * @data: data to write at register offset
619 * Acquires semaphore then writes the data to the PHY register at the offset
620 * using the kumeran interface. Release the acquired semaphore before exiting.
622 s32
e1000e_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
624 return __e1000_write_kmrn_reg(hw
, offset
, data
, false);
628 * e1000e_write_kmrn_reg_locked - Write kumeran register
629 * @hw: pointer to the HW structure
630 * @offset: register offset to write to
631 * @data: data to write at register offset
633 * Write the data to PHY register at the offset using the kumeran interface.
634 * Assumes semaphore already acquired.
636 s32
e1000e_write_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
638 return __e1000_write_kmrn_reg(hw
, offset
, data
, true);
642 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
643 * @hw: pointer to the HW structure
645 * Sets up Carrier-sense on Transmit and downshift values.
647 s32
e1000_copper_link_setup_82577(struct e1000_hw
*hw
)
649 struct e1000_phy_info
*phy
= &hw
->phy
;
653 /* Enable CRS on TX. This must be set for half-duplex operation. */
654 ret_val
= phy
->ops
.read_reg(hw
, I82577_CFG_REG
, &phy_data
);
658 phy_data
|= I82577_CFG_ASSERT_CRS_ON_TX
;
660 /* Enable downshift */
661 phy_data
|= I82577_CFG_ENABLE_DOWNSHIFT
;
663 ret_val
= phy
->ops
.write_reg(hw
, I82577_CFG_REG
, phy_data
);
670 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
671 * @hw: pointer to the HW structure
673 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
674 * and downshift values are set also.
676 s32
e1000e_copper_link_setup_m88(struct e1000_hw
*hw
)
678 struct e1000_phy_info
*phy
= &hw
->phy
;
682 /* Enable CRS on Tx. This must be set for half-duplex operation. */
683 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
687 /* For BM PHY this bit is downshift enable */
688 if (phy
->type
!= e1000_phy_bm
)
689 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
693 * MDI/MDI-X = 0 (default)
694 * 0 - Auto for all speeds
697 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
699 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
703 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
706 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
709 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
713 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
719 * disable_polarity_correction = 0 (default)
720 * Automatic Correction for Reversed Cable Polarity
724 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
725 if (phy
->disable_polarity_correction
== 1)
726 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
728 /* Enable downshift on BM (disabled by default) */
729 if (phy
->type
== e1000_phy_bm
)
730 phy_data
|= BME1000_PSCR_ENABLE_DOWNSHIFT
;
732 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
736 if ((phy
->type
== e1000_phy_m88
) &&
737 (phy
->revision
< E1000_REVISION_4
) &&
738 (phy
->id
!= BME1000_E_PHY_ID_R2
)) {
740 * Force TX_CLK in the Extended PHY Specific Control Register
743 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
747 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
749 if ((phy
->revision
== 2) &&
750 (phy
->id
== M88E1111_I_PHY_ID
)) {
751 /* 82573L PHY - set the downshift counter to 5x. */
752 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
753 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
755 /* Configure Master and Slave downshift values */
756 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
757 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
758 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
759 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
761 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
766 if ((phy
->type
== e1000_phy_bm
) && (phy
->id
== BME1000_E_PHY_ID_R2
)) {
767 /* Set PHY page 0, register 29 to 0x0003 */
768 ret_val
= e1e_wphy(hw
, 29, 0x0003);
772 /* Set PHY page 0, register 30 to 0x0000 */
773 ret_val
= e1e_wphy(hw
, 30, 0x0000);
778 /* Commit the changes. */
779 ret_val
= e1000e_commit_phy(hw
);
781 e_dbg("Error committing the PHY changes\n");
785 if (phy
->type
== e1000_phy_82578
) {
786 ret_val
= phy
->ops
.read_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
791 /* 82578 PHY - set the downshift count to 1x. */
792 phy_data
|= I82578_EPSCR_DOWNSHIFT_ENABLE
;
793 phy_data
&= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK
;
794 ret_val
= phy
->ops
.write_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
804 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
805 * @hw: pointer to the HW structure
807 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
810 s32
e1000e_copper_link_setup_igp(struct e1000_hw
*hw
)
812 struct e1000_phy_info
*phy
= &hw
->phy
;
816 ret_val
= e1000_phy_hw_reset(hw
);
818 e_dbg("Error resetting the PHY.\n");
823 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
824 * timeout issues when LFS is enabled.
828 /* disable lplu d0 during driver init */
829 ret_val
= e1000_set_d0_lplu_state(hw
, false);
831 e_dbg("Error Disabling LPLU D0\n");
834 /* Configure mdi-mdix settings */
835 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
839 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
843 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
846 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
850 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
853 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
857 /* set auto-master slave resolution settings */
858 if (hw
->mac
.autoneg
) {
860 * when autonegotiation advertisement is only 1000Mbps then we
861 * should disable SmartSpeed and enable Auto MasterSlave
862 * resolution as hardware default.
864 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
865 /* Disable SmartSpeed */
866 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
871 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
872 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
877 /* Set auto Master/Slave resolution process */
878 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
882 data
&= ~CR_1000T_MS_ENABLE
;
883 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
888 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
892 /* load defaults for future use */
893 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
894 ((data
& CR_1000T_MS_VALUE
) ?
895 e1000_ms_force_master
:
896 e1000_ms_force_slave
) :
899 switch (phy
->ms_type
) {
900 case e1000_ms_force_master
:
901 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
903 case e1000_ms_force_slave
:
904 data
|= CR_1000T_MS_ENABLE
;
905 data
&= ~(CR_1000T_MS_VALUE
);
908 data
&= ~CR_1000T_MS_ENABLE
;
912 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
919 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
920 * @hw: pointer to the HW structure
922 * Reads the MII auto-neg advertisement register and/or the 1000T control
923 * register and if the PHY is already setup for auto-negotiation, then
924 * return successful. Otherwise, setup advertisement and flow control to
925 * the appropriate values for the wanted auto-negotiation.
927 static s32
e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
929 struct e1000_phy_info
*phy
= &hw
->phy
;
931 u16 mii_autoneg_adv_reg
;
932 u16 mii_1000t_ctrl_reg
= 0;
934 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
936 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
937 ret_val
= e1e_rphy(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
941 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
942 /* Read the MII 1000Base-T Control Register (Address 9). */
943 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
949 * Need to parse both autoneg_advertised and fc and set up
950 * the appropriate PHY registers. First we will parse for
951 * autoneg_advertised software override. Since we can advertise
952 * a plethora of combinations, we need to check each bit
957 * First we clear all the 10/100 mb speed bits in the Auto-Neg
958 * Advertisement Register (Address 4) and the 1000 mb speed bits in
959 * the 1000Base-T Control Register (Address 9).
961 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
962 NWAY_AR_100TX_HD_CAPS
|
963 NWAY_AR_10T_FD_CAPS
|
964 NWAY_AR_10T_HD_CAPS
);
965 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
967 e_dbg("autoneg_advertised %x\n", phy
->autoneg_advertised
);
969 /* Do we want to advertise 10 Mb Half Duplex? */
970 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
971 e_dbg("Advertise 10mb Half duplex\n");
972 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
975 /* Do we want to advertise 10 Mb Full Duplex? */
976 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
977 e_dbg("Advertise 10mb Full duplex\n");
978 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
981 /* Do we want to advertise 100 Mb Half Duplex? */
982 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
983 e_dbg("Advertise 100mb Half duplex\n");
984 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
987 /* Do we want to advertise 100 Mb Full Duplex? */
988 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
989 e_dbg("Advertise 100mb Full duplex\n");
990 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
993 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
994 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
995 e_dbg("Advertise 1000mb Half duplex request denied!\n");
997 /* Do we want to advertise 1000 Mb Full Duplex? */
998 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
999 e_dbg("Advertise 1000mb Full duplex\n");
1000 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
1004 * Check for a software override of the flow control settings, and
1005 * setup the PHY advertisement registers accordingly. If
1006 * auto-negotiation is enabled, then software will have to set the
1007 * "PAUSE" bits to the correct value in the Auto-Negotiation
1008 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1011 * The possible values of the "fc" parameter are:
1012 * 0: Flow control is completely disabled
1013 * 1: Rx flow control is enabled (we can receive pause frames
1014 * but not send pause frames).
1015 * 2: Tx flow control is enabled (we can send pause frames
1016 * but we do not support receiving pause frames).
1017 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1018 * other: No software override. The flow control configuration
1019 * in the EEPROM is used.
1021 switch (hw
->fc
.current_mode
) {
1024 * Flow control (Rx & Tx) is completely disabled by a
1025 * software over-ride.
1027 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1029 case e1000_fc_rx_pause
:
1031 * Rx Flow control is enabled, and Tx Flow control is
1032 * disabled, by a software over-ride.
1034 * Since there really isn't a way to advertise that we are
1035 * capable of Rx Pause ONLY, we will advertise that we
1036 * support both symmetric and asymmetric Rx PAUSE. Later
1037 * (in e1000e_config_fc_after_link_up) we will disable the
1038 * hw's ability to send PAUSE frames.
1040 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1042 case e1000_fc_tx_pause
:
1044 * Tx Flow control is enabled, and Rx Flow control is
1045 * disabled, by a software over-ride.
1047 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1048 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1052 * Flow control (both Rx and Tx) is enabled by a software
1055 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1058 e_dbg("Flow control param set incorrectly\n");
1059 ret_val
= -E1000_ERR_CONFIG
;
1063 ret_val
= e1e_wphy(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1067 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1069 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
1070 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1077 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1078 * @hw: pointer to the HW structure
1080 * Performs initial bounds checking on autoneg advertisement parameter, then
1081 * configure to advertise the full capability. Setup the PHY to autoneg
1082 * and restart the negotiation process between the link partner. If
1083 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1085 static s32
e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1087 struct e1000_phy_info
*phy
= &hw
->phy
;
1092 * Perform some bounds checking on the autoneg advertisement
1095 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1098 * If autoneg_advertised is zero, we assume it was not defaulted
1099 * by the calling code so we set to advertise full capability.
1101 if (phy
->autoneg_advertised
== 0)
1102 phy
->autoneg_advertised
= phy
->autoneg_mask
;
1104 e_dbg("Reconfiguring auto-neg advertisement params\n");
1105 ret_val
= e1000_phy_setup_autoneg(hw
);
1107 e_dbg("Error Setting up Auto-Negotiation\n");
1110 e_dbg("Restarting Auto-Neg\n");
1113 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1114 * the Auto Neg Restart bit in the PHY control register.
1116 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
1120 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1121 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
1126 * Does the user want to wait for Auto-Neg to complete here, or
1127 * check at a later time (for example, callback routine).
1129 if (phy
->autoneg_wait_to_complete
) {
1130 ret_val
= e1000_wait_autoneg(hw
);
1132 e_dbg("Error while waiting for "
1133 "autoneg to complete\n");
1138 hw
->mac
.get_link_status
= 1;
1144 * e1000e_setup_copper_link - Configure copper link settings
1145 * @hw: pointer to the HW structure
1147 * Calls the appropriate function to configure the link for auto-neg or forced
1148 * speed and duplex. Then we check for link, once link is established calls
1149 * to configure collision distance and flow control are called. If link is
1150 * not established, we return -E1000_ERR_PHY (-2).
1152 s32
e1000e_setup_copper_link(struct e1000_hw
*hw
)
1157 if (hw
->mac
.autoneg
) {
1159 * Setup autoneg and flow control advertisement and perform
1162 ret_val
= e1000_copper_link_autoneg(hw
);
1167 * PHY will be set to 10H, 10F, 100H or 100F
1168 * depending on user settings.
1170 e_dbg("Forcing Speed and Duplex\n");
1171 ret_val
= e1000_phy_force_speed_duplex(hw
);
1173 e_dbg("Error Forcing Speed and Duplex\n");
1179 * Check link status. Wait up to 100 microseconds for link to become
1182 ret_val
= e1000e_phy_has_link_generic(hw
,
1183 COPPER_LINK_UP_LIMIT
,
1190 e_dbg("Valid link established!!!\n");
1191 e1000e_config_collision_dist(hw
);
1192 ret_val
= e1000e_config_fc_after_link_up(hw
);
1194 e_dbg("Unable to establish link!!!\n");
1201 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1202 * @hw: pointer to the HW structure
1204 * Calls the PHY setup function to force speed and duplex. Clears the
1205 * auto-crossover to force MDI manually. Waits for link and returns
1206 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1208 s32
e1000e_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
1210 struct e1000_phy_info
*phy
= &hw
->phy
;
1215 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1219 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1221 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1226 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1227 * forced whenever speed and duplex are forced.
1229 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1233 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1234 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1236 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1240 e_dbg("IGP PSCR: %X\n", phy_data
);
1244 if (phy
->autoneg_wait_to_complete
) {
1245 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1247 ret_val
= e1000e_phy_has_link_generic(hw
,
1255 e_dbg("Link taking longer than expected.\n");
1258 ret_val
= e1000e_phy_has_link_generic(hw
,
1270 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1271 * @hw: pointer to the HW structure
1273 * Calls the PHY setup function to force speed and duplex. Clears the
1274 * auto-crossover to force MDI manually. Resets the PHY to commit the
1275 * changes. If time expires while waiting for link up, we reset the DSP.
1276 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1277 * successful completion, else return corresponding error code.
1279 s32
e1000e_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
1281 struct e1000_phy_info
*phy
= &hw
->phy
;
1287 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1288 * forced whenever speed and duplex are forced.
1290 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1294 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1295 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1299 e_dbg("M88E1000 PSCR: %X\n", phy_data
);
1301 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1305 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1307 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1311 /* Reset the phy to commit changes. */
1312 ret_val
= e1000e_commit_phy(hw
);
1316 if (phy
->autoneg_wait_to_complete
) {
1317 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1319 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1326 * We didn't get link.
1327 * Reset the DSP and cross our fingers.
1329 ret_val
= e1e_wphy(hw
, M88E1000_PHY_PAGE_SELECT
,
1333 ret_val
= e1000e_phy_reset_dsp(hw
);
1339 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1345 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1350 * Resetting the phy means we need to re-force TX_CLK in the
1351 * Extended PHY Specific Control Register to 25MHz clock from
1352 * the reset value of 2.5MHz.
1354 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1355 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1360 * In addition, we must re-enable CRS on Tx for both half and full
1363 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1367 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1368 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1374 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1375 * @hw: pointer to the HW structure
1376 * @phy_ctrl: pointer to current value of PHY_CONTROL
1378 * Forces speed and duplex on the PHY by doing the following: disable flow
1379 * control, force speed/duplex on the MAC, disable auto speed detection,
1380 * disable auto-negotiation, configure duplex, configure speed, configure
1381 * the collision distance, write configuration to CTRL register. The
1382 * caller must write to the PHY_CONTROL register for these settings to
1385 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1387 struct e1000_mac_info
*mac
= &hw
->mac
;
1390 /* Turn off flow control when forcing speed/duplex */
1391 hw
->fc
.current_mode
= e1000_fc_none
;
1393 /* Force speed/duplex on the mac */
1395 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1396 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1398 /* Disable Auto Speed Detection */
1399 ctrl
&= ~E1000_CTRL_ASDE
;
1401 /* Disable autoneg on the phy */
1402 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1404 /* Forcing Full or Half Duplex? */
1405 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1406 ctrl
&= ~E1000_CTRL_FD
;
1407 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1408 e_dbg("Half Duplex\n");
1410 ctrl
|= E1000_CTRL_FD
;
1411 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1412 e_dbg("Full Duplex\n");
1415 /* Forcing 10mb or 100mb? */
1416 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1417 ctrl
|= E1000_CTRL_SPD_100
;
1418 *phy_ctrl
|= MII_CR_SPEED_100
;
1419 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1420 e_dbg("Forcing 100mb\n");
1422 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1423 *phy_ctrl
|= MII_CR_SPEED_10
;
1424 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1425 e_dbg("Forcing 10mb\n");
1428 e1000e_config_collision_dist(hw
);
1434 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1435 * @hw: pointer to the HW structure
1436 * @active: boolean used to enable/disable lplu
1438 * Success returns 0, Failure returns 1
1440 * The low power link up (lplu) state is set to the power management level D3
1441 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1442 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1443 * is used during Dx states where the power conservation is most important.
1444 * During driver activity, SmartSpeed should be enabled so performance is
1447 s32
e1000e_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
1449 struct e1000_phy_info
*phy
= &hw
->phy
;
1453 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1458 data
&= ~IGP02E1000_PM_D3_LPLU
;
1459 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1463 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1464 * during Dx states where the power conservation is most
1465 * important. During driver activity we should enable
1466 * SmartSpeed, so performance is maintained.
1468 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1469 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1474 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1475 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1479 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1480 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1485 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1486 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1491 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1492 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1493 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1494 data
|= IGP02E1000_PM_D3_LPLU
;
1495 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1499 /* When LPLU is enabled, we should disable SmartSpeed */
1500 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1504 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1505 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1512 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1513 * @hw: pointer to the HW structure
1515 * Success returns 0, Failure returns 1
1517 * A downshift is detected by querying the PHY link health.
1519 s32
e1000e_check_downshift(struct e1000_hw
*hw
)
1521 struct e1000_phy_info
*phy
= &hw
->phy
;
1523 u16 phy_data
, offset
, mask
;
1525 switch (phy
->type
) {
1527 case e1000_phy_gg82563
:
1528 case e1000_phy_82578
:
1529 case e1000_phy_82577
:
1530 offset
= M88E1000_PHY_SPEC_STATUS
;
1531 mask
= M88E1000_PSSR_DOWNSHIFT
;
1533 case e1000_phy_igp_2
:
1534 case e1000_phy_igp_3
:
1535 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1536 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1539 /* speed downshift not supported */
1540 phy
->speed_downgraded
= false;
1544 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1547 phy
->speed_downgraded
= (phy_data
& mask
);
1553 * e1000_check_polarity_m88 - Checks the polarity.
1554 * @hw: pointer to the HW structure
1556 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1558 * Polarity is determined based on the PHY specific status register.
1560 static s32
e1000_check_polarity_m88(struct e1000_hw
*hw
)
1562 struct e1000_phy_info
*phy
= &hw
->phy
;
1566 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1569 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1570 ? e1000_rev_polarity_reversed
1571 : e1000_rev_polarity_normal
;
1577 * e1000_check_polarity_igp - Checks the polarity.
1578 * @hw: pointer to the HW structure
1580 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1582 * Polarity is determined based on the PHY port status register, and the
1583 * current speed (since there is no polarity at 100Mbps).
1585 static s32
e1000_check_polarity_igp(struct e1000_hw
*hw
)
1587 struct e1000_phy_info
*phy
= &hw
->phy
;
1589 u16 data
, offset
, mask
;
1592 * Polarity is determined based on the speed of
1595 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1599 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1600 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1601 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1602 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1605 * This really only applies to 10Mbps since
1606 * there is no polarity for 100Mbps (always 0).
1608 offset
= IGP01E1000_PHY_PORT_STATUS
;
1609 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1612 ret_val
= e1e_rphy(hw
, offset
, &data
);
1615 phy
->cable_polarity
= (data
& mask
)
1616 ? e1000_rev_polarity_reversed
1617 : e1000_rev_polarity_normal
;
1623 * e1000_wait_autoneg - Wait for auto-neg completion
1624 * @hw: pointer to the HW structure
1626 * Waits for auto-negotiation to complete or for the auto-negotiation time
1627 * limit to expire, which ever happens first.
1629 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
)
1634 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1635 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1636 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1639 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1642 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1648 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1655 * e1000e_phy_has_link_generic - Polls PHY for link
1656 * @hw: pointer to the HW structure
1657 * @iterations: number of times to poll for link
1658 * @usec_interval: delay between polling attempts
1659 * @success: pointer to whether polling was successful or not
1661 * Polls the PHY status register for link, 'iterations' number of times.
1663 s32
e1000e_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
1664 u32 usec_interval
, bool *success
)
1669 for (i
= 0; i
< iterations
; i
++) {
1671 * Some PHYs require the PHY_STATUS register to be read
1672 * twice due to the link bit being sticky. No harm doing
1673 * it across the board.
1675 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1678 * If the first read fails, another entity may have
1679 * ownership of the resources, wait and try again to
1680 * see if they have relinquished the resources yet.
1682 udelay(usec_interval
);
1683 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1686 if (phy_status
& MII_SR_LINK_STATUS
)
1688 if (usec_interval
>= 1000)
1689 mdelay(usec_interval
/1000);
1691 udelay(usec_interval
);
1694 *success
= (i
< iterations
);
1700 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1701 * @hw: pointer to the HW structure
1703 * Reads the PHY specific status register to retrieve the cable length
1704 * information. The cable length is determined by averaging the minimum and
1705 * maximum values to get the "average" cable length. The m88 PHY has four
1706 * possible cable length values, which are:
1707 * Register Value Cable Length
1711 * 3 110 - 140 meters
1714 s32
e1000e_get_cable_length_m88(struct e1000_hw
*hw
)
1716 struct e1000_phy_info
*phy
= &hw
->phy
;
1718 u16 phy_data
, index
;
1720 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1724 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
1725 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
1726 if (index
>= M88E1000_CABLE_LENGTH_TABLE_SIZE
- 1) {
1727 ret_val
= -E1000_ERR_PHY
;
1731 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
1732 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+ 1];
1734 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1741 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1742 * @hw: pointer to the HW structure
1744 * The automatic gain control (agc) normalizes the amplitude of the
1745 * received signal, adjusting for the attenuation produced by the
1746 * cable. By reading the AGC registers, which represent the
1747 * combination of course and fine gain value, the value can be put
1748 * into a lookup table to obtain the approximate cable length
1751 s32
e1000e_get_cable_length_igp_2(struct e1000_hw
*hw
)
1753 struct e1000_phy_info
*phy
= &hw
->phy
;
1755 u16 phy_data
, i
, agc_value
= 0;
1756 u16 cur_agc_index
, max_agc_index
= 0;
1757 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
1758 u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
1759 {IGP02E1000_PHY_AGC_A
,
1760 IGP02E1000_PHY_AGC_B
,
1761 IGP02E1000_PHY_AGC_C
,
1762 IGP02E1000_PHY_AGC_D
};
1764 /* Read the AGC registers for all channels */
1765 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
1766 ret_val
= e1e_rphy(hw
, agc_reg_array
[i
], &phy_data
);
1771 * Getting bits 15:9, which represent the combination of
1772 * course and fine gain values. The result is a number
1773 * that can be put into the lookup table to obtain the
1774 * approximate cable length.
1776 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
1777 IGP02E1000_AGC_LENGTH_MASK
;
1779 /* Array index bound check. */
1780 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
1781 (cur_agc_index
== 0))
1782 return -E1000_ERR_PHY
;
1784 /* Remove min & max AGC values from calculation. */
1785 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
1786 e1000_igp_2_cable_length_table
[cur_agc_index
])
1787 min_agc_index
= cur_agc_index
;
1788 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
1789 e1000_igp_2_cable_length_table
[cur_agc_index
])
1790 max_agc_index
= cur_agc_index
;
1792 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
1795 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
1796 e1000_igp_2_cable_length_table
[max_agc_index
]);
1797 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
1799 /* Calculate cable length with the error range of +/- 10 meters. */
1800 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
1801 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
1802 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
1804 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1810 * e1000e_get_phy_info_m88 - Retrieve PHY information
1811 * @hw: pointer to the HW structure
1813 * Valid for only copper links. Read the PHY status register (sticky read)
1814 * to verify that link is up. Read the PHY special control register to
1815 * determine the polarity and 10base-T extended distance. Read the PHY
1816 * special status register to determine MDI/MDIx and current speed. If
1817 * speed is 1000, then determine cable length, local and remote receiver.
1819 s32
e1000e_get_phy_info_m88(struct e1000_hw
*hw
)
1821 struct e1000_phy_info
*phy
= &hw
->phy
;
1826 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1827 e_dbg("Phy info is only valid for copper media\n");
1828 return -E1000_ERR_CONFIG
;
1831 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1836 e_dbg("Phy info is only valid if link is up\n");
1837 return -E1000_ERR_CONFIG
;
1840 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1844 phy
->polarity_correction
= (phy_data
&
1845 M88E1000_PSCR_POLARITY_REVERSAL
);
1847 ret_val
= e1000_check_polarity_m88(hw
);
1851 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1855 phy
->is_mdix
= (phy_data
& M88E1000_PSSR_MDIX
);
1857 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
1858 ret_val
= e1000_get_cable_length(hw
);
1862 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &phy_data
);
1866 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
1867 ? e1000_1000t_rx_status_ok
1868 : e1000_1000t_rx_status_not_ok
;
1870 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
1871 ? e1000_1000t_rx_status_ok
1872 : e1000_1000t_rx_status_not_ok
;
1874 /* Set values to "undefined" */
1875 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1876 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1877 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1884 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1885 * @hw: pointer to the HW structure
1887 * Read PHY status to determine if link is up. If link is up, then
1888 * set/determine 10base-T extended distance and polarity correction. Read
1889 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1890 * determine on the cable length, local and remote receiver.
1892 s32
e1000e_get_phy_info_igp(struct e1000_hw
*hw
)
1894 struct e1000_phy_info
*phy
= &hw
->phy
;
1899 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1904 e_dbg("Phy info is only valid if link is up\n");
1905 return -E1000_ERR_CONFIG
;
1908 phy
->polarity_correction
= true;
1910 ret_val
= e1000_check_polarity_igp(hw
);
1914 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1918 phy
->is_mdix
= (data
& IGP01E1000_PSSR_MDIX
);
1920 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1921 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1922 ret_val
= e1000_get_cable_length(hw
);
1926 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &data
);
1930 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
1931 ? e1000_1000t_rx_status_ok
1932 : e1000_1000t_rx_status_not_ok
;
1934 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
1935 ? e1000_1000t_rx_status_ok
1936 : e1000_1000t_rx_status_not_ok
;
1938 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1939 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1940 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1947 * e1000e_phy_sw_reset - PHY software reset
1948 * @hw: pointer to the HW structure
1950 * Does a software reset of the PHY by reading the PHY control register and
1951 * setting/write the control register reset bit to the PHY.
1953 s32
e1000e_phy_sw_reset(struct e1000_hw
*hw
)
1958 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
1962 phy_ctrl
|= MII_CR_RESET
;
1963 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
1973 * e1000e_phy_hw_reset_generic - PHY hardware reset
1974 * @hw: pointer to the HW structure
1976 * Verify the reset block is not blocking us from resetting. Acquire
1977 * semaphore (if necessary) and read/set/write the device control reset
1978 * bit in the PHY. Wait the appropriate delay time for the device to
1979 * reset and release the semaphore (if necessary).
1981 s32
e1000e_phy_hw_reset_generic(struct e1000_hw
*hw
)
1983 struct e1000_phy_info
*phy
= &hw
->phy
;
1987 ret_val
= e1000_check_reset_block(hw
);
1991 ret_val
= phy
->ops
.acquire(hw
);
1996 ew32(CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
1999 udelay(phy
->reset_delay_us
);
2006 phy
->ops
.release(hw
);
2008 return e1000_get_phy_cfg_done(hw
);
2012 * e1000e_get_cfg_done - Generic configuration done
2013 * @hw: pointer to the HW structure
2015 * Generic function to wait 10 milli-seconds for configuration to complete
2016 * and return success.
2018 s32
e1000e_get_cfg_done(struct e1000_hw
*hw
)
2025 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2026 * @hw: pointer to the HW structure
2028 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2030 s32
e1000e_phy_init_script_igp3(struct e1000_hw
*hw
)
2032 e_dbg("Running IGP 3 PHY init script\n");
2034 /* PHY init IGP 3 */
2035 /* Enable rise/fall, 10-mode work in class-A */
2036 e1e_wphy(hw
, 0x2F5B, 0x9018);
2037 /* Remove all caps from Replica path filter */
2038 e1e_wphy(hw
, 0x2F52, 0x0000);
2039 /* Bias trimming for ADC, AFE and Driver (Default) */
2040 e1e_wphy(hw
, 0x2FB1, 0x8B24);
2041 /* Increase Hybrid poly bias */
2042 e1e_wphy(hw
, 0x2FB2, 0xF8F0);
2043 /* Add 4% to Tx amplitude in Gig mode */
2044 e1e_wphy(hw
, 0x2010, 0x10B0);
2045 /* Disable trimming (TTT) */
2046 e1e_wphy(hw
, 0x2011, 0x0000);
2047 /* Poly DC correction to 94.6% + 2% for all channels */
2048 e1e_wphy(hw
, 0x20DD, 0x249A);
2049 /* ABS DC correction to 95.9% */
2050 e1e_wphy(hw
, 0x20DE, 0x00D3);
2051 /* BG temp curve trim */
2052 e1e_wphy(hw
, 0x28B4, 0x04CE);
2053 /* Increasing ADC OPAMP stage 1 currents to max */
2054 e1e_wphy(hw
, 0x2F70, 0x29E4);
2055 /* Force 1000 ( required for enabling PHY regs configuration) */
2056 e1e_wphy(hw
, 0x0000, 0x0140);
2057 /* Set upd_freq to 6 */
2058 e1e_wphy(hw
, 0x1F30, 0x1606);
2060 e1e_wphy(hw
, 0x1F31, 0xB814);
2061 /* Disable adaptive fixed FFE (Default) */
2062 e1e_wphy(hw
, 0x1F35, 0x002A);
2063 /* Enable FFE hysteresis */
2064 e1e_wphy(hw
, 0x1F3E, 0x0067);
2065 /* Fixed FFE for short cable lengths */
2066 e1e_wphy(hw
, 0x1F54, 0x0065);
2067 /* Fixed FFE for medium cable lengths */
2068 e1e_wphy(hw
, 0x1F55, 0x002A);
2069 /* Fixed FFE for long cable lengths */
2070 e1e_wphy(hw
, 0x1F56, 0x002A);
2071 /* Enable Adaptive Clip Threshold */
2072 e1e_wphy(hw
, 0x1F72, 0x3FB0);
2073 /* AHT reset limit to 1 */
2074 e1e_wphy(hw
, 0x1F76, 0xC0FF);
2075 /* Set AHT master delay to 127 msec */
2076 e1e_wphy(hw
, 0x1F77, 0x1DEC);
2077 /* Set scan bits for AHT */
2078 e1e_wphy(hw
, 0x1F78, 0xF9EF);
2079 /* Set AHT Preset bits */
2080 e1e_wphy(hw
, 0x1F79, 0x0210);
2081 /* Change integ_factor of channel A to 3 */
2082 e1e_wphy(hw
, 0x1895, 0x0003);
2083 /* Change prop_factor of channels BCD to 8 */
2084 e1e_wphy(hw
, 0x1796, 0x0008);
2085 /* Change cg_icount + enable integbp for channels BCD */
2086 e1e_wphy(hw
, 0x1798, 0xD008);
2088 * Change cg_icount + enable integbp + change prop_factor_master
2089 * to 8 for channel A
2091 e1e_wphy(hw
, 0x1898, 0xD918);
2092 /* Disable AHT in Slave mode on channel A */
2093 e1e_wphy(hw
, 0x187A, 0x0800);
2095 * Enable LPLU and disable AN to 1000 in non-D0a states,
2098 e1e_wphy(hw
, 0x0019, 0x008D);
2099 /* Enable restart AN on an1000_dis change */
2100 e1e_wphy(hw
, 0x001B, 0x2080);
2101 /* Enable wh_fifo read clock in 10/100 modes */
2102 e1e_wphy(hw
, 0x0014, 0x0045);
2103 /* Restart AN, Speed selection is 1000 */
2104 e1e_wphy(hw
, 0x0000, 0x1340);
2109 /* Internal function pointers */
2112 * e1000_get_phy_cfg_done - Generic PHY configuration done
2113 * @hw: pointer to the HW structure
2115 * Return success if silicon family did not implement a family specific
2116 * get_cfg_done function.
2118 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
2120 if (hw
->phy
.ops
.get_cfg_done
)
2121 return hw
->phy
.ops
.get_cfg_done(hw
);
2127 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2128 * @hw: pointer to the HW structure
2130 * When the silicon family has not implemented a forced speed/duplex
2131 * function for the PHY, simply return 0.
2133 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
2135 if (hw
->phy
.ops
.force_speed_duplex
)
2136 return hw
->phy
.ops
.force_speed_duplex(hw
);
2142 * e1000e_get_phy_type_from_id - Get PHY type from id
2143 * @phy_id: phy_id read from the phy
2145 * Returns the phy type from the id.
2147 enum e1000_phy_type
e1000e_get_phy_type_from_id(u32 phy_id
)
2149 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2152 case M88E1000_I_PHY_ID
:
2153 case M88E1000_E_PHY_ID
:
2154 case M88E1111_I_PHY_ID
:
2155 case M88E1011_I_PHY_ID
:
2156 phy_type
= e1000_phy_m88
;
2158 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
2159 phy_type
= e1000_phy_igp_2
;
2161 case GG82563_E_PHY_ID
:
2162 phy_type
= e1000_phy_gg82563
;
2164 case IGP03E1000_E_PHY_ID
:
2165 phy_type
= e1000_phy_igp_3
;
2168 case IFE_PLUS_E_PHY_ID
:
2169 case IFE_C_E_PHY_ID
:
2170 phy_type
= e1000_phy_ife
;
2172 case BME1000_E_PHY_ID
:
2173 case BME1000_E_PHY_ID_R2
:
2174 phy_type
= e1000_phy_bm
;
2176 case I82578_E_PHY_ID
:
2177 phy_type
= e1000_phy_82578
;
2179 case I82577_E_PHY_ID
:
2180 phy_type
= e1000_phy_82577
;
2183 phy_type
= e1000_phy_unknown
;
2190 * e1000e_determine_phy_address - Determines PHY address.
2191 * @hw: pointer to the HW structure
2193 * This uses a trial and error method to loop through possible PHY
2194 * addresses. It tests each by reading the PHY ID registers and
2195 * checking for a match.
2197 s32
e1000e_determine_phy_address(struct e1000_hw
*hw
)
2199 s32 ret_val
= -E1000_ERR_PHY_TYPE
;
2202 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2205 for (phy_addr
= 0; phy_addr
< 4; phy_addr
++) {
2206 hw
->phy
.addr
= phy_addr
;
2207 e1000e_get_phy_id(hw
);
2208 phy_type
= e1000e_get_phy_type_from_id(hw
->phy
.id
);
2211 * If phy_type is valid, break - we found our
2214 if (phy_type
!= e1000_phy_unknown
) {
2220 } while ((ret_val
!= 0) && (i
< 100));
2226 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2227 * @page: page to access
2229 * Returns the phy address for the page requested.
2231 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
)
2235 if ((page
>= 768) || (page
== 0 && reg
== 25) || (reg
== 31))
2242 * e1000e_write_phy_reg_bm - Write BM PHY register
2243 * @hw: pointer to the HW structure
2244 * @offset: register offset to write to
2245 * @data: data to write at register offset
2247 * Acquires semaphore, if necessary, then writes the data to PHY register
2248 * at the offset. Release any acquired semaphores before exiting.
2250 s32
e1000e_write_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2253 u32 page_select
= 0;
2254 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2257 ret_val
= hw
->phy
.ops
.acquire(hw
);
2261 /* Page 800 works differently than the rest so it has its own func */
2262 if (page
== BM_WUC_PAGE
) {
2263 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2268 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2270 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2272 * Page select is register 31 for phy address 1 and 22 for
2273 * phy address 2 and 3. Page select is shifted only for
2276 if (hw
->phy
.addr
== 1) {
2277 page_shift
= IGP_PAGE_SHIFT
;
2278 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2281 page_select
= BM_PHY_PAGE_SELECT
;
2284 /* Page is shifted left, PHY expects (page x 32) */
2285 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2286 (page
<< page_shift
));
2291 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2295 hw
->phy
.ops
.release(hw
);
2300 * e1000e_read_phy_reg_bm - Read BM PHY register
2301 * @hw: pointer to the HW structure
2302 * @offset: register offset to be read
2303 * @data: pointer to the read data
2305 * Acquires semaphore, if necessary, then reads the PHY register at offset
2306 * and storing the retrieved information in data. Release any acquired
2307 * semaphores before exiting.
2309 s32
e1000e_read_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2312 u32 page_select
= 0;
2313 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2316 ret_val
= hw
->phy
.ops
.acquire(hw
);
2320 /* Page 800 works differently than the rest so it has its own func */
2321 if (page
== BM_WUC_PAGE
) {
2322 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2327 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2329 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2331 * Page select is register 31 for phy address 1 and 22 for
2332 * phy address 2 and 3. Page select is shifted only for
2335 if (hw
->phy
.addr
== 1) {
2336 page_shift
= IGP_PAGE_SHIFT
;
2337 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2340 page_select
= BM_PHY_PAGE_SELECT
;
2343 /* Page is shifted left, PHY expects (page x 32) */
2344 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2345 (page
<< page_shift
));
2350 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2353 hw
->phy
.ops
.release(hw
);
2358 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2359 * @hw: pointer to the HW structure
2360 * @offset: register offset to be read
2361 * @data: pointer to the read data
2363 * Acquires semaphore, if necessary, then reads the PHY register at offset
2364 * and storing the retrieved information in data. Release any acquired
2365 * semaphores before exiting.
2367 s32
e1000e_read_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2370 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2372 ret_val
= hw
->phy
.ops
.acquire(hw
);
2376 /* Page 800 works differently than the rest so it has its own func */
2377 if (page
== BM_WUC_PAGE
) {
2378 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2385 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2387 /* Page is shifted left, PHY expects (page x 32) */
2388 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2395 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2398 hw
->phy
.ops
.release(hw
);
2403 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2404 * @hw: pointer to the HW structure
2405 * @offset: register offset to write to
2406 * @data: data to write at register offset
2408 * Acquires semaphore, if necessary, then writes the data to PHY register
2409 * at the offset. Release any acquired semaphores before exiting.
2411 s32
e1000e_write_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2414 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2416 ret_val
= hw
->phy
.ops
.acquire(hw
);
2420 /* Page 800 works differently than the rest so it has its own func */
2421 if (page
== BM_WUC_PAGE
) {
2422 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2429 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2430 /* Page is shifted left, PHY expects (page x 32) */
2431 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2438 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2442 hw
->phy
.ops
.release(hw
);
2447 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2448 * @hw: pointer to the HW structure
2449 * @offset: register offset to be read or written
2450 * @data: pointer to the data to read or write
2451 * @read: determines if operation is read or write
2453 * Acquires semaphore, if necessary, then reads the PHY register at offset
2454 * and storing the retrieved information in data. Release any acquired
2455 * semaphores before exiting. Note that procedure to read the wakeup
2456 * registers are different. It works as such:
2457 * 1) Set page 769, register 17, bit 2 = 1
2458 * 2) Set page to 800 for host (801 if we were manageability)
2459 * 3) Write the address using the address opcode (0x11)
2460 * 4) Read or write the data using the data opcode (0x12)
2461 * 5) Restore 769_17.2 to its original value
2463 * Assumes semaphore already acquired.
2465 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
2466 u16
*data
, bool read
)
2469 u16 reg
= BM_PHY_REG_NUM(offset
);
2472 /* Gig must be disabled for MDIO accesses to page 800 */
2473 if ((hw
->mac
.type
== e1000_pchlan
) &&
2474 (!(er32(PHY_CTRL
) & E1000_PHY_CTRL_GBE_DISABLE
)))
2475 e_dbg("Attempting to access page 800 while gig enabled\n");
2477 /* All operations in this function are phy address 1 */
2481 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2482 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2484 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, &phy_reg
);
2488 /* First clear bit 4 to avoid a power state change */
2489 phy_reg
&= ~(BM_WUC_HOST_WU_BIT
);
2490 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2494 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2495 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
,
2496 phy_reg
| BM_WUC_ENABLE_BIT
);
2500 /* Select page 800 */
2501 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2502 (BM_WUC_PAGE
<< IGP_PAGE_SHIFT
));
2504 /* Write the page 800 offset value using opcode 0x11 */
2505 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ADDRESS_OPCODE
, reg
);
2510 /* Read the page 800 value using opcode 0x12 */
2511 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2514 /* Read the page 800 value using opcode 0x12 */
2515 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2523 * Restore 769_17.2 to its original value
2526 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2527 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2529 /* Clear 769_17.2 */
2530 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2537 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2538 * @hw: pointer to the HW structure
2540 * In the case of a PHY power down to save power, or to turn off link during a
2541 * driver unload, or wake on lan is not enabled, restore the link to previous
2544 void e1000_power_up_phy_copper(struct e1000_hw
*hw
)
2548 /* The PHY will retain its settings across a power down/up cycle */
2549 e1e_rphy(hw
, PHY_CONTROL
, &mii_reg
);
2550 mii_reg
&= ~MII_CR_POWER_DOWN
;
2551 e1e_wphy(hw
, PHY_CONTROL
, mii_reg
);
2555 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2556 * @hw: pointer to the HW structure
2558 * In the case of a PHY power down to save power, or to turn off link during a
2559 * driver unload, or wake on lan is not enabled, restore the link to previous
2562 void e1000_power_down_phy_copper(struct e1000_hw
*hw
)
2566 /* The PHY will retain its settings across a power down/up cycle */
2567 e1e_rphy(hw
, PHY_CONTROL
, &mii_reg
);
2568 mii_reg
|= MII_CR_POWER_DOWN
;
2569 e1e_wphy(hw
, PHY_CONTROL
, mii_reg
);
2574 * e1000e_commit_phy - Soft PHY reset
2575 * @hw: pointer to the HW structure
2577 * Performs a soft PHY reset on those that apply. This is a function pointer
2578 * entry point called by drivers.
2580 s32
e1000e_commit_phy(struct e1000_hw
*hw
)
2582 if (hw
->phy
.ops
.commit
)
2583 return hw
->phy
.ops
.commit(hw
);
2589 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2590 * @hw: pointer to the HW structure
2591 * @active: boolean used to enable/disable lplu
2593 * Success returns 0, Failure returns 1
2595 * The low power link up (lplu) state is set to the power management level D0
2596 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2597 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2598 * is used during Dx states where the power conservation is most important.
2599 * During driver activity, SmartSpeed should be enabled so performance is
2600 * maintained. This is a function pointer entry point called by drivers.
2602 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
)
2604 if (hw
->phy
.ops
.set_d0_lplu_state
)
2605 return hw
->phy
.ops
.set_d0_lplu_state(hw
, active
);
2611 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2612 * @hw: pointer to the HW structure
2613 * @slow: true for slow mode, false for normal mode
2615 * Assumes semaphore already acquired.
2617 s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
, bool slow
)
2622 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2624 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2625 (BM_PORT_CTRL_PAGE
<< IGP_PAGE_SHIFT
));
2629 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_CS_CTRL1
,
2630 (0x2180 | (slow
<< 10)));
2634 /* dummy read when reverting to fast mode - throw away result */
2636 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_CS_CTRL1
, &data
);
2643 * __e1000_read_phy_reg_hv - Read HV PHY register
2644 * @hw: pointer to the HW structure
2645 * @offset: register offset to be read
2646 * @data: pointer to the read data
2647 * @locked: semaphore has already been acquired or not
2649 * Acquires semaphore, if necessary, then reads the PHY register at offset
2650 * and stores the retrieved information in data. Release any acquired
2651 * semaphore before exiting.
2653 static s32
__e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
2657 u16 page
= BM_PHY_REG_PAGE(offset
);
2658 u16 reg
= BM_PHY_REG_NUM(offset
);
2659 bool in_slow_mode
= false;
2662 ret_val
= hw
->phy
.ops
.acquire(hw
);
2667 /* Workaround failure in MDIO access while cable is disconnected */
2668 if ((hw
->phy
.type
== e1000_phy_82577
) &&
2669 !(er32(STATUS
) & E1000_STATUS_LU
)) {
2670 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
2674 in_slow_mode
= true;
2677 /* Page 800 works differently than the rest so it has its own func */
2678 if (page
== BM_WUC_PAGE
) {
2679 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
2684 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2685 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2690 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2692 if (page
== HV_INTC_FC_PAGE_START
)
2695 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2696 u32 phy_addr
= hw
->phy
.addr
;
2700 /* Page is shifted left, PHY expects (page x 32) */
2701 ret_val
= e1000e_write_phy_reg_mdic(hw
,
2702 IGP01E1000_PHY_PAGE_SELECT
,
2703 (page
<< IGP_PAGE_SHIFT
));
2704 hw
->phy
.addr
= phy_addr
;
2710 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2713 /* Revert to MDIO fast mode, if applicable */
2714 if ((hw
->phy
.type
== e1000_phy_82577
) && in_slow_mode
)
2715 ret_val
|= e1000_set_mdio_slow_mode_hv(hw
, false);
2718 hw
->phy
.ops
.release(hw
);
2724 * e1000_read_phy_reg_hv - Read HV PHY register
2725 * @hw: pointer to the HW structure
2726 * @offset: register offset to be read
2727 * @data: pointer to the read data
2729 * Acquires semaphore then reads the PHY register at offset and stores
2730 * the retrieved information in data. Release the acquired semaphore
2733 s32
e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2735 return __e1000_read_phy_reg_hv(hw
, offset
, data
, false);
2739 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2740 * @hw: pointer to the HW structure
2741 * @offset: register offset to be read
2742 * @data: pointer to the read data
2744 * Reads the PHY register at offset and stores the retrieved information
2745 * in data. Assumes semaphore already acquired.
2747 s32
e1000_read_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2749 return __e1000_read_phy_reg_hv(hw
, offset
, data
, true);
2753 * __e1000_write_phy_reg_hv - Write HV PHY register
2754 * @hw: pointer to the HW structure
2755 * @offset: register offset to write to
2756 * @data: data to write at register offset
2757 * @locked: semaphore has already been acquired or not
2759 * Acquires semaphore, if necessary, then writes the data to PHY register
2760 * at the offset. Release any acquired semaphores before exiting.
2762 static s32
__e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
,
2766 u16 page
= BM_PHY_REG_PAGE(offset
);
2767 u16 reg
= BM_PHY_REG_NUM(offset
);
2768 bool in_slow_mode
= false;
2771 ret_val
= hw
->phy
.ops
.acquire(hw
);
2776 /* Workaround failure in MDIO access while cable is disconnected */
2777 if ((hw
->phy
.type
== e1000_phy_82577
) &&
2778 !(er32(STATUS
) & E1000_STATUS_LU
)) {
2779 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
2783 in_slow_mode
= true;
2786 /* Page 800 works differently than the rest so it has its own func */
2787 if (page
== BM_WUC_PAGE
) {
2788 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
2793 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2794 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2799 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2801 if (page
== HV_INTC_FC_PAGE_START
)
2805 * Workaround MDIO accesses being disabled after entering IEEE Power
2806 * Down (whenever bit 11 of the PHY Control register is set)
2808 if ((hw
->phy
.type
== e1000_phy_82578
) &&
2809 (hw
->phy
.revision
>= 1) &&
2810 (hw
->phy
.addr
== 2) &&
2811 ((MAX_PHY_REG_ADDRESS
& reg
) == 0) &&
2812 (data
& (1 << 11))) {
2814 ret_val
= e1000_access_phy_debug_regs_hv(hw
, (1 << 6) | 0x3,
2820 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2821 u32 phy_addr
= hw
->phy
.addr
;
2825 /* Page is shifted left, PHY expects (page x 32) */
2826 ret_val
= e1000e_write_phy_reg_mdic(hw
,
2827 IGP01E1000_PHY_PAGE_SELECT
,
2828 (page
<< IGP_PAGE_SHIFT
));
2829 hw
->phy
.addr
= phy_addr
;
2835 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2839 /* Revert to MDIO fast mode, if applicable */
2840 if ((hw
->phy
.type
== e1000_phy_82577
) && in_slow_mode
)
2841 ret_val
|= e1000_set_mdio_slow_mode_hv(hw
, false);
2844 hw
->phy
.ops
.release(hw
);
2850 * e1000_write_phy_reg_hv - Write HV PHY register
2851 * @hw: pointer to the HW structure
2852 * @offset: register offset to write to
2853 * @data: data to write at register offset
2855 * Acquires semaphore then writes the data to PHY register at the offset.
2856 * Release the acquired semaphores before exiting.
2858 s32
e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2860 return __e1000_write_phy_reg_hv(hw
, offset
, data
, false);
2864 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2865 * @hw: pointer to the HW structure
2866 * @offset: register offset to write to
2867 * @data: data to write at register offset
2869 * Writes the data to PHY register at the offset. Assumes semaphore
2872 s32
e1000_write_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2874 return __e1000_write_phy_reg_hv(hw
, offset
, data
, true);
2878 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
2879 * @page: page to be accessed
2881 static u32
e1000_get_phy_addr_for_hv_page(u32 page
)
2885 if (page
>= HV_INTC_FC_PAGE_START
)
2892 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2893 * @hw: pointer to the HW structure
2894 * @offset: register offset to be read or written
2895 * @data: pointer to the data to be read or written
2896 * @read: determines if operation is read or written
2898 * Reads the PHY register at offset and stores the retreived information
2899 * in data. Assumes semaphore already acquired. Note that the procedure
2900 * to read these regs uses the address port and data port to read/write.
2902 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
2903 u16
*data
, bool read
)
2909 /* This takes care of the difference with desktop vs mobile phy */
2910 addr_reg
= (hw
->phy
.type
== e1000_phy_82578
) ?
2911 I82578_ADDR_REG
: I82577_ADDR_REG
;
2912 data_reg
= addr_reg
+ 1;
2914 /* All operations in this function are phy address 2 */
2917 /* masking with 0x3F to remove the page from offset */
2918 ret_val
= e1000e_write_phy_reg_mdic(hw
, addr_reg
, (u16
)offset
& 0x3F);
2920 e_dbg("Could not write PHY the HV address register\n");
2924 /* Read or write the data value next */
2926 ret_val
= e1000e_read_phy_reg_mdic(hw
, data_reg
, data
);
2928 ret_val
= e1000e_write_phy_reg_mdic(hw
, data_reg
, *data
);
2931 e_dbg("Could not read data value from HV data register\n");
2940 * e1000_link_stall_workaround_hv - Si workaround
2941 * @hw: pointer to the HW structure
2943 * This function works around a Si bug where the link partner can get
2944 * a link up indication before the PHY does. If small packets are sent
2945 * by the link partner they can be placed in the packet buffer without
2946 * being properly accounted for by the PHY and will stall preventing
2947 * further packets from being received. The workaround is to clear the
2948 * packet buffer after the PHY detects link up.
2950 s32
e1000_link_stall_workaround_hv(struct e1000_hw
*hw
)
2955 if (hw
->phy
.type
!= e1000_phy_82578
)
2958 /* Do not apply workaround if in PHY loopback bit 14 set */
2959 hw
->phy
.ops
.read_reg(hw
, PHY_CONTROL
, &data
);
2960 if (data
& PHY_CONTROL_LB
)
2963 /* check if link is up and at 1Gbps */
2964 ret_val
= hw
->phy
.ops
.read_reg(hw
, BM_CS_STATUS
, &data
);
2968 data
&= BM_CS_STATUS_LINK_UP
|
2969 BM_CS_STATUS_RESOLVED
|
2970 BM_CS_STATUS_SPEED_MASK
;
2972 if (data
!= (BM_CS_STATUS_LINK_UP
|
2973 BM_CS_STATUS_RESOLVED
|
2974 BM_CS_STATUS_SPEED_1000
))
2979 /* flush the packets in the fifo buffer */
2980 ret_val
= hw
->phy
.ops
.write_reg(hw
, HV_MUX_DATA_CTRL
,
2981 HV_MUX_DATA_CTRL_GEN_TO_MAC
|
2982 HV_MUX_DATA_CTRL_FORCE_SPEED
);
2986 ret_val
= hw
->phy
.ops
.write_reg(hw
, HV_MUX_DATA_CTRL
,
2987 HV_MUX_DATA_CTRL_GEN_TO_MAC
);
2994 * e1000_check_polarity_82577 - Checks the polarity.
2995 * @hw: pointer to the HW structure
2997 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2999 * Polarity is determined based on the PHY specific status register.
3001 s32
e1000_check_polarity_82577(struct e1000_hw
*hw
)
3003 struct e1000_phy_info
*phy
= &hw
->phy
;
3007 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_STATUS_2
, &data
);
3010 phy
->cable_polarity
= (data
& I82577_PHY_STATUS2_REV_POLARITY
)
3011 ? e1000_rev_polarity_reversed
3012 : e1000_rev_polarity_normal
;
3018 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3019 * @hw: pointer to the HW structure
3021 * Calls the PHY setup function to force speed and duplex. Clears the
3022 * auto-crossover to force MDI manually. Waits for link and returns
3023 * successful if link up is successful, else -E1000_ERR_PHY (-2).
3025 s32
e1000_phy_force_speed_duplex_82577(struct e1000_hw
*hw
)
3027 struct e1000_phy_info
*phy
= &hw
->phy
;
3032 ret_val
= phy
->ops
.read_reg(hw
, PHY_CONTROL
, &phy_data
);
3036 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
3038 ret_val
= phy
->ops
.write_reg(hw
, PHY_CONTROL
, phy_data
);
3043 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
3044 * forced whenever speed and duplex are forced.
3046 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_CTRL_2
, &phy_data
);
3050 phy_data
&= ~I82577_PHY_CTRL2_AUTO_MDIX
;
3051 phy_data
&= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX
;
3053 ret_val
= phy
->ops
.write_reg(hw
, I82577_PHY_CTRL_2
, phy_data
);
3057 e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data
);
3061 if (phy
->autoneg_wait_to_complete
) {
3062 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3064 ret_val
= e1000e_phy_has_link_generic(hw
,
3072 e_dbg("Link taking longer than expected.\n");
3075 ret_val
= e1000e_phy_has_link_generic(hw
,
3088 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3089 * @hw: pointer to the HW structure
3091 * Read PHY status to determine if link is up. If link is up, then
3092 * set/determine 10base-T extended distance and polarity correction. Read
3093 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3094 * determine on the cable length, local and remote receiver.
3096 s32
e1000_get_phy_info_82577(struct e1000_hw
*hw
)
3098 struct e1000_phy_info
*phy
= &hw
->phy
;
3103 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
3108 e_dbg("Phy info is only valid if link is up\n");
3109 ret_val
= -E1000_ERR_CONFIG
;
3113 phy
->polarity_correction
= true;
3115 ret_val
= e1000_check_polarity_82577(hw
);
3119 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_STATUS_2
, &data
);
3123 phy
->is_mdix
= (data
& I82577_PHY_STATUS2_MDIX
) ? true : false;
3125 if ((data
& I82577_PHY_STATUS2_SPEED_MASK
) ==
3126 I82577_PHY_STATUS2_SPEED_1000MBPS
) {
3127 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
3131 ret_val
= phy
->ops
.read_reg(hw
, PHY_1000T_STATUS
, &data
);
3135 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
3136 ? e1000_1000t_rx_status_ok
3137 : e1000_1000t_rx_status_not_ok
;
3139 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
3140 ? e1000_1000t_rx_status_ok
3141 : e1000_1000t_rx_status_not_ok
;
3143 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
3144 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
3145 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
3153 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3154 * @hw: pointer to the HW structure
3156 * Reads the diagnostic status register and verifies result is valid before
3157 * placing it in the phy_cable_length field.
3159 s32
e1000_get_cable_length_82577(struct e1000_hw
*hw
)
3161 struct e1000_phy_info
*phy
= &hw
->phy
;
3163 u16 phy_data
, length
;
3165 ret_val
= phy
->ops
.read_reg(hw
, I82577_PHY_DIAG_STATUS
, &phy_data
);
3169 length
= (phy_data
& I82577_DSTATUS_CABLE_LENGTH
) >>
3170 I82577_DSTATUS_CABLE_LENGTH_SHIFT
;
3172 if (length
== E1000_CABLE_LENGTH_UNDEFINED
)
3173 ret_val
= -E1000_ERR_PHY
;
3175 phy
->cable_length
= length
;